Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
OPA2810 Dual-Channel, 27-V, Rail-to-Rail Input/Output FET-Input Operational Amplifier
1 Features
3 Description
•
•
•
•
•
The OPA2810 is a dual-channel, FET-input, voltagefeedback operational amplifier with low input bias
current. The OPA2810 is unity-gain stable with a
small-signal unity-gain bandwidth of 105 MHz, and
offers excellent DC precision and dynamic AC
performance at a low quiescent current (IQ) of 3.6 mA
per channel (typical). The OPA2810 is fabricated on
Texas Instrument's proprietary, high-speed SiGe
BiCMOS
process
and
achieves
significant
performance improvements over comparable FETinput amplifiers at similar levels of quiescent power.
With a gain-bandwidth product (GBWP) of 70 MHz,
slew-rate of 192 V/µs, and voltage low noise of
6 nV/√Hz, the OPA2810 is well suited for use in a
wide range of high fidelity data acquisition and signal
processing applications.
1
•
•
•
•
•
•
Gain-bandwidth product: 70 MHz
Small-signal bandwidth: 105 MHz
Slew rate: 192 V/µs
Wide supply range: 4.75 V to 27 V
Low noise:
– Input voltage noise: 6 nV/√Hz (f = 500 kHz)
– Input current noise: 5 fA/√Hz (f = 10 kHz)
Rail-to-rail input and output:
– FET input stage: 2-pA input bias current
(typical)
– High linear output current: 75 mA
Input offset: ±1.5 mV (maximum)
Offset drift: ±2 µV/°C (typical)
Low power: 3.6 mA/channel
Extended temperature operation:
–40°C to +125°C
Single-channel version: OPA810
2 Applications
•
•
•
•
•
•
•
Wideband photodiode transimpedance amplifiers
High-Z front-ends
Impedance measurements
Power analyzers
Multichannel sensor interface
Level shifting and buffering
Optoelectronic drivers
The OPA2810 is characterized to operate over a wide
supply range of 4.75 V to 27 V, and features rail-torail inputs and outputs. The OPA2810 amplifier
delivers 75 mA of linear output current, suitable for
driving optoelectronics components and analog-todigital converter (ADC) inputs or buffering DAC
outputs into heavy loads.
The OPA2810 is available in 8-pin SOIC, SOT23, and
VSSOP packages and is rated to work over the
extended industrial temperature range of –40°C to
+125°C. The OPA810 is a single-channel variant of
this device, available in 8-pin SOIC and 5-pin SOT-23
and SC70 packages.
Device Information(1)
PART NUMBER
OPA2810
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (8)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Multichannel Sensor Interface
Harmonic Distortion vs Frequency
-50
-60
ADC
MUX
+
Harmonic Distortion (dBc)
OPA2810
-70
-80
-90
-100
-110
HD2, RL = 1 k:
HD3, RL = 1 k:
HD2, RL = 500 :
HD3, RL = 500 :
-120
-130
-140
100k
1M
Frequency (Hz)
D048
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: 10 V ................................. 5
Electrical Characteristics: 24 V ................................. 8
Electrical Characteristics: 5 V ................................. 11
Typical Characteristics: VS = 10 V .......................... 14
Typical Characteristics: VS = 24 V .......................... 17
Typical Characteristics: VS = 5 V .......................... 20
Typical Characteristics: ±2.375 V to ±12 V Split
Supply ...................................................................... 22
Detailed Description ............................................ 25
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
25
25
26
27
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Applications ................................................ 33
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 38
12 Device and Documentation Support ................. 39
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
39
39
13 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
Changes from Revision B (December 2018) to Revision C
Page
•
Added OPA810 single-channel version information to front page.......................................................................................... 1
•
Added OPA810 to Device Comparison Table ........................................................................................................................ 3
•
Changed Functional Block Diagram and Feature Description sections to meet format requirements................................. 25
Changes from Revision A (June 2018) to Revision B
Page
•
Added D (SOIC) package to document ................................................................................................................................. 1
•
Changed value of minimum linear output drive at TA = –40℃ to 125℃ in 10 V, 24 V and 5 V Electrical
Characteristics tables ............................................................................................................................................................. 6
•
Changed test condition for linear output drive at TA = –40℃ to +125℃ in 10 V, 24 V and 5 V Electrical
Characteristics tables. ............................................................................................................................................................ 6
•
Deleted specification for minimum output short-circuit current in 10 V, 24 V and 5 V Electrical Characteristics tables........ 6
•
Deleted '±' sign from the test condition for PSRR at 25℃ in 10 V, 24 V and 5 V Electrical Characteristics tables............... 7
•
Changed footnote for PSRR in 10 V, 24 V and 5 V Electrical Characteristics tables. ........................................................... 7
•
Added VCM = 0.5 V to the test condition for PSRR at 25℃ in 5 V Electrical Characteristics table. ..................................... 12
•
Changed changed test condition for open-loop voltage gain in auxiliary CMOS input stage section in 5 V Electrical
Characteristics table. ............................................................................................................................................................ 13
Changes from Original (August 2017) to Revision A
•
2
Page
Changed device status from Advance Information to Production Data ................................................................................. 1
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
5 Device Comparison Table
DEVICE
VS± (V)
IQ / Channel
(mA)
GBWP
(MHz)
SLEW RATE
(V/μs)
VOLTAGE NOISE
(nV/√Hz)
AMPLIFIER DESCRIPTION
OPA2810
±12
3.6
70
192
6
Unity-gain stable FET input (dual-ch)
OPA810
±12
3.7
70
200
6.3
Unity-gain stable FET input (single-ch)
THS4631
±15
13
210
900
7
Unity-gain stable FET input
OPA656
±6
14
230
290
7
Unity-gain stable FET input
OPA657
±6
14
1600
700
4.8
Gain of 7 stable FET input
OPA659
±6
32
350
2550
8.9
Unity-gain stable FET input
6 Pin Configuration and Functions
D, DCN, and DGK Packages
8-Pin SOIC, SOT-23, and VSSOP
Top View
VO1
1
8
VS+
VIN1-
2
7
VO2
VIN1+
3
6
VIN2-
VS-
4
5
VIN2+
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
VO1
1
O
Amplifier 1 output pin
VIN1-
2
I
Amplifier 1 inverting input pin
VIN1+
3
I
Amplifier 1 noninverting input pin
VS-
4
P
Negative power supply pin
VIN2+
5
I
Amplifier 2 noninverting input pin
VIN2-
6
I
Amplifier 2 inverting input pin
VO2
7
O
Amplifier 2 output pin
VS+
8
P
Positive power supply pin
(1)
I = input, O = output, and P = power.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
3
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Supply voltage (total bipolar supplies) (2)
VIN
Input voltage
VIN,Diff
Differential input voltage (3)
II
Continuous input current
IO
Continuous output current (4)
PD
Continuous power dissipation
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
VS– – 0.5
MAX
UNIT
±14
V
VS+ + 0.5
V
±7
V
±10
mA
TA = –40℃ to +85℃
±40
mA
TA = 125℃
±12
mA
See Thermal Information
–65
150
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VS is the total supply voltage given by VS = VS+ – VS– .
Equal to the lower of ±7 V or total supply voltage.
Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Total supply voltage
4.75
TA
Ambient temperature
–40
NOM
25
MAX
UNIT
27
V
125
°C
7.4 Thermal Information
OPA2810
THERMAL METRIC (1)
D (SOIC)
DCN (SOT-23)
DGK (VSSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
123.9
130.9
177.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.3
86.6
64.6
°C/W
RθJB
Junction-to-board thermal resistance
69.4
42.3
99.0
°C/W
ψJT
Junction-to-top characterization parameter
13.5
25.9
9.7
°C/W
ψJB
Junction-to-board characterization parameter
68.1
42.3
97.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
7.5 Electrical Characteristics: 10 V
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to
midsupply (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test
Level (2)
AC PERFORMANCE
SSBW
Small-signal bandwidth
G = 1, Vo = 20 mVPP, RF = 0 Ω
75
MHz
C
G = 1, Vo = 20 mVPP, RF = 0 Ω,
CL= 33 pF
105
MHz
C
G = –1, Vo = 20 mVPP
50
MHz
C
G = 2, Vo = 20 mVPP
49
MHz
C
G = 5, Vo = 20 mVPP
15
MHz
C
G = 2, Vo = 2 VPP
38
MHz
C
G = 2, Vo = 4 VPP
26
MHz
C
70
MHz
C
LSBW
Large-signal bandwidth
GBWP
Gain-bandwidth product
G = 11, Vo = 20 mVPP
Bandwdith for 0.1dB flatness
G = 2, Vo = 20 mVPP
Slew rate (20%-80%) (3)
SR
C
V/µs
C
G = –1, Vo = –2-V to 2-V step
187
V/µs
C
G = 2, Vo = –4.5-V to 3.5-V step
193
V/µs
C
Vo = 200-mV step
4
ns
C
Fall time
Vo = 200-mV step
5
ns
C
G = 2, Vo = 2-V step
73
ns
C
G = 2, Vo = 8-V step
97
ns
C
G = –1, Vo = 8-V step
96
ns
C
G = 2, Vo = 2-V step
374
ns
C
G = 2, Vo = 8-V step
213
ns
C
G = –1, Vo = 8-V step
163
ns
C
G = +1, RF = 0 Ω, Vo = 200 mVPP
9/10
%
C
G = +1, RF = 0 Ω, Vo = 2 VPP
4/5
%
C
Input overdrive recovery
G = 1, RF = 0 Ω, (VS– – 0.5 V) to
(VS+ + 0.5 V) input (see Figure 14)
44
ns
C
Output overdrive recovery
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input (see Figure 15)
55
ns
C
Settling time to 0.001%
Overshoot/undershoot
HD3
MHz
192
Rise time
Settling time to 0.1%
HD2
13
G = 2, Vo = –2-V to 2-V step
Second-order harmonic
distortion
Third-order harmonic
distortion
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
–118
dBc
C
f = 100 kHz, RL =1 kΩ, Vo = 8 VPP
–101
dBc
C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
–99
dBc
C
f = 1 MHz, RL =1 kΩ, Vo = 8 VPP
–82
dBc
C
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
–134
dBc
C
f = 100 kHz, RL = 1 kΩ, Vo = 8 VPP
–105
dBc
C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
–104
dBc
C
f = 1 MHz, RL = 1 kΩ, Vo = 8 VPP
–92
dBc
C
f = 500 kHz, flatband
en
Input-referred voltage noise
ei
Input-referred current noise
zO
Close-loop output impedance f = 100 kHz
(1)
(2)
(3)
f = 0.1-10 Hz integrated
f = 10 kHz
6
nV/√Hz
C
0.42
µVrms
C
5
fA/√Hz
C
Ω
C
0.007
For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
Lower of the measured positive and negative slew rate.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
5
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Electrical Characteristics: 10 V (continued)
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to
midsupply(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
f = DC, Vo = ±2.5 V
108
120
TA = –40°C to +125°C
108
MAX
UNIT
Test
Level (2)
dB
A
DC PERFORMANCE
AOL
Open-loop voltage gain
VOS
Input offset voltage
TA = 25°C
Input offset voltage drift
1.5
mV
A
TA = –40°C to +85°C
0.1
2.4
mV
B
TA = –40°C to +125°C
2.8
mV
B
µV/°C
B
T = 25°C
1.5
TA = –40°C to +125°C
TA = 25°C
Input bias current
TA = –40°C to +85°C (4)
TA = –40°C to +125°C
Input offset current
(4)
CMRR
13
µV/°C
B
2
20
pA
A
20
60
pA
B
100
350
pA
B
TA = 25°C
1
20
pA
A
TA = –40°C to +85°C
5
pA
B
50
pA
B
100
dB
A
dB
B
V
C
GΩ||pF
C
0.5
pF
C
VS+ + 0.3
V
A
V
B
V
A
TA = –40°C to +125°C
Common-mode rejection
ratio
B
f = DC, TA = 25°C, VCM = –3 V to +1 V
85
TA = –40°C to +125°C
85
INPUT
Allowable input differential
voltage
See Figure 57
Common-mode input
impedance
In closed-loop configuration
±7
12 || 2.5
Differential input capacitance In open-loop configuration
Most positive input voltage
Most negative input voltage
Most positive input voltage
for main-JFET stage
ΔVOS < 5 mV (5)
VS+ + 0.2
TA = –40°C to +125°C
VS+ + 0.2
ΔVOS < 5 mV
(5)
VS– – 0.2
TA = –40°C to +125°C
VS– – 0.2
T = 25°C (see Figure 18)
VS+ – 2.9
TA = –40°C to +125°C
VS– – 0.3
VS+ – 2.5
VS+ – 3
V
B
V
C
V
C
V
A
V
B
V
A
V
B
mA
A
mA
B
OUTPUT
VOCRH
VOCRL
IO(max)
Output voltage range high
Output voltage range low
Linear output drive (sourcing
and sinking)
TA = 25°C, RL = 667 Ω
TA = –40°C to +125°C, RL = 667 Ω
TA = 25°C, RL = 667 Ω
VS+ – 0.18 VS+ – 0.11
VS+ – 0.2
VS– + 0.15 VS– + 0.08
TA = –40°C to +125°C, RL = 667 Ω
VS– + 0.2
TA = 25°C, VO = 2.65 V, RL = 51 Ω,
VOS < 2 mV
52
TA = –40°C to +125°C, VO = 1.4 V,
VOS < 2 mV
28
75
ISC
Output short-circuit current
TA = 25°C, TDelay = 5 ms
100
mA
B
CL
Capacitive load drive
< 1 dB peaking, RS = 0 Ω
35
pF
C
(4)
(5)
6
Maximum bias current specification is set using ±5σ limits (corresponding to 0.58 DPPM) obtained using the statistical distribution from
electrical characterization over temperature of a sample set of 70 units. Maximum specification is not specified by final automated test
equipment (ATE) nor by QA sample testing.
Change in input offset from its value when input is biased to midsupply.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Electrical Characteristics: 10 V (continued)
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to
midsupply(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test
Level (2)
POWER SUPPLY
VS
Operating voltage
IQ
Quiescent current per
channel
PSRR
Power supply rejection ratio
TA = 25°C
4.75
27
V
A
TA = –40°C to +125°C
4.75
27
V
B
4.05
mA
A
4.4
mA
B
dB
A
dB
B
35
MHz
C
100
dB
A
TA = 25°C
3.125
TA = –40°C to +125°C
2.9
ΔVS = 2 V (6)
82
TA = –40°C to +125°C
82
3.6
100
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product
VCM = (VS+) – 1 V
Open-loop voltage gain
VCM = (VS+) – 1 V, f = DC, Vo = 2 V to
4V
Input-referred voltage noise
VCM = VS+ – 1V, f = 1 MHz
80
nV/√Hz
C
VCM = VS+ – 1.5 V, no-load
4
mV
A
VCM = VS+ – 0.5 V, no-load
4.8
mV
A
VCM = VS+ – 0.5 V, TA = –40°C to
+125°C, no-load
6.4
mV
B
2
20
pA
A
VCM = VS+ – 1.5 V, TA = -40°C to
+125°C
0.15
0.5
nA
B
Common-mode rejection
ratio
VCM = VS+ - 1.5 V to VS+ – 0.5 V
75
dB
B
Power supply rejection ratio
VCM = VS+ – 1.5 V, ΔVS = ±2 V (6)
75
dB
B
3
%
C
dBc
C
mV
A
Input offset voltage
VCM = VS+ – 1.5 V
Input bias current
21
CHANNEL MATCHING
Channel-to-channel GBWP
mismatch
(6)
TA = 25°C
Channel-to-channel crosstalk f = 100 kHz
–93
Input offset voltage mismatch TA = 25°C
0.1
2.5
The supply voltages are VS+ = 5 V ± 1 V and VS– = –5 V for +PSRR, and VS+ = 5 V and VS– = –5 V ± 1 V for –PSRR.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
7
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
7.6 Electrical Characteristics: 24 V
Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to
midsupply (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test
Level (2)
AC PERFORMANCE
SSBW
Small-signal bandwidth
G = 1, Vo = 20 mVPP, RF = 0 Ω
75
MHz
C
G = 1, Vo = 20 mVPP, RF = 0 Ω,
CL= 33 pF
105
MHz
C
G = –1, Vo = 20 mVPP
51
MHz
C
G = 2, Vo = 20 mVPP
49
MHz
C
G = 5, Vo = 20 mVPP
15
MHz
C
G = 2 Vo = 2 VPP
38
MHz
C
G = 2 Vo = 10 VPP
14
MHz
C
70
MHz
C
LSBW
Large-signal bandwidth
GBWP
Gain-bandwidth product
G = 11, Vo = 20 mVPP
Bandwdith for 0.1dB flatness
G = 2, Vo = 20 mVPP
Slew rate (20%-80%) (3)
SR
C
V/µs
C
G = –1, Vo = –2-V to 2-V step
218
V/µs
C
G = 2, Vo = –4.5-V to 3.5-V step
243
V/µs
C
Vo = 200-mV step
4
ns
C
Fall time
Vo = 200-mV step
5
ns
C
G = 2, Vo = 2-V step
72
ns
C
G = 2, Vo = 10-V step
90
ns
C
G = –1, Vo = 10-V step
89
ns
C
G = 2, Vo = 2-V step
370
ns
C
G = 2, Vo = 10-V step
210
ns
C
G = –1, Vo = 10-V step
150
ns
C
7.5/9
%
C
G = 1, RF = 0 Ω, Vo = 2 VPP
4/5
%
C
Input overdrive recovery
G = 1, RF = 0 Ω, (VS– – 0.5 V) to
(VS+ + 0.5 V) input (see Figure 31)
66
ns
C
Output overdrive recovery
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input (see Figure 32)
30
ns
C
Settling time to 0.001%
Overshoot/undershoot
HD3
MHz
226
Rise time
Settling time to 0.1%
HD2
12
G = 2, Vo = –2-V to 2-V step
Second-order harmonic
distortion
Third-order harmonic
distortion
G = 1, RF = 0 Ω, Vo = 200 mVPP
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
–123
dBc
C
f = 100 kHz, RL =1 kΩ, Vo = 10 VPP
–113
dBc
C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
–105
dBc
C
f = 1 MHz, RL=1 kΩ, Vo = 10 VPP
–92
dBc
C
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
–134
dBc
C
f = 100 kHz, RL =1 kΩ, Vo = 10 VPP
–130
dBc
C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
–103
dBc
C
f = 1 MHz, RL =1 kΩ, Vo = 10 VPP
–86
dBc
C
f = 500 kHz, flatband
en
Input-referred voltage noise
ei
Input-referred current noise
zO
Close-loop output impedance f = 100 kHz
(1)
(2)
(3)
8
f = 0.1-10 Hz integrated
f = 10 kHz
6
nV/√Hz
C
0.36
µVrms
C
5
fA/√Hz
C
Ω
C
0.007
For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
Lower of the measured positive and negative slew rate.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Electrical Characteristics: 24 V (continued)
Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to
midsupply(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
f = DC, Vo = ±8 V
108
120
TA = –40°C to +125°C
108
MAX
UNIT
Test
Level (2)
dB
A
dB
B
DC PERFORMANCE
AOL
Open-loop voltage gain
VOS
Input offset voltage
TA = 25°C
Input offset voltage drift
1.5
mV
A
TA = –40°C to +85°C
0.1
2.4
mV
B
TA = –40°C to +125°C
2.8
mV
B
µV/°C
B
TA = 25°C
1.5
TA = –40°C to +125°C
TA = 25°C
Input bias current
TA = –40°C to +85°C (4)
TA = –40°C to +125°C
Input offset current
(4)
CMRR
µV/°C
B
20
pA
A
20
60
pA
B
100
460
pA
B
TA = 25°C
1
20
pA
A
TA = –40°C to +85°C
5
pA
B
50
pA
B
105
dB
A
dB
B
V
C
GΩ||pF
C
0.5
pF
C
VS+ + 0.3
V
A
V
B
V
A
TA = –40°C to +125°C
Common-mode rejection
ratio
13
2
f = DC, TA = 25°C, VCM = ±5 V
90
TA = –40°C to +125°C
90
INPUT
Allowable input differential
voltage
see Figure 57
Common-mode input
impedance
In closed-loop configuration
±7
12 || 2.5
Differential input capacitance In open-loop configuration
Most positive input voltage
Most negative input voltage
Most positive input voltage
for main-JFET stage
ΔVOS < 5 mV (5)
VS+ + 0.2
TA = –40°C to +125°C
VS+ + 0.1
ΔVOS < 5 mV
(5)
VS– – 0.2
TA = –40°C to +125°C
VS– – 0.2
TA = 25°C (see Figure 35)
VS+ – 2.9
VS– – 0.3
V
B
V
C
V
C
VS+ – 0.33 VS+ – 0.22
V
A
TA = –40°C to +125°C, RL = 667 Ω
VS+ – 0.36
V
B
TA = 25°C, RL = 667 Ω
VS– + 0.23 VS– + 0.15
V
A
TA = –40°C to +125°C, RL = 667 Ω
VS– + 0.33
V
B
mA
A
mA
B
TA = –40°C to +125°C
VS+ – 2.5
VS+ – 3
OUTPUT
VOCRH
VOCRL
IO(max)
Output voltage range high
Output voltage range low
Linear output drive (sourcing
and sinking)
TA = 25°C, RL = 667 Ω
TA = 25°C, Vo = 7.25 V, RL = 151 Ω,
VOS < 2 mV
48
TA = –40°C to +90°C, Vo = 4.35 V, VOS
< 2 mV
29
64
ISC
Output short-circuit current
TA = 25°C, TDelay = 5 ms
108
mA
B
CL
Capacitive load drive
< 1 dB peaking, RS = 0 Ω
35
pF
C
(4)
(5)
Maximum bias current specification is set using ±5σ limits (corresponding to 0.58 DPPM) obtained using the statistical distribution from
electrical characterization over temperature of a sample set of 70 units. Maximum specification is not specified by final automated test
equipment (ATE) nor by QA sample testing.
Change in input offset from its value when input is biased to midsupply.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
9
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Electrical Characteristics: 24 V (continued)
Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to
midsupply(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test
Level (2)
POWER SUPPLY
VS
Operating voltage
IQ
Quiescent current per
channel
PSRR
Power supply rejection ratio
TA = 25°C
4.75
27
V
A
TA = –40°C to +125°C
4.75
27
V
B
4.1
mA
A
4.5
mA
B
dB
A
dB
B
35
MHz
C
95
dB
A
TA = 25°C
3.2
TA = –40°C to +125°C
3.0
ΔVS = 2 V (6)
90
TA = –40°C to +125°C
90
3.7
105
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product
VCM = VS+ – 1 V
Open-loop voltage gain
VCM = VS+ – 1 V, f = DC, Vo = 7 V to
–7 V
Input-referred voltage noise
VCM = VS+ – 1 V, f = 1 MHz
80
nV/√Hz
C
VCM = VS+ – 1.5 V, no-load
4
mV
A
VCM = VS+ – 0.5 V, no-load
4.8
mV
A
VCM = VS+ – 0.5 V, TA = –40°C to
+125°C, no-load
6.4
mV
B
2
24
pA
A
VCM = VS+ – 1.5 V, TA = –40°C to
+125°C
0.15
1
nA
B
Common-mode rejection
ratio
VCM = VS+ – 1.5 V to VS+ – 0.5 V
75
dB
B
Power supply rejection ratio
VCM = VS+ – 1.5 V, ΔVS = ±2 V (6)
70
dB
B
3
%
C
dBc
C
mV
A
Input offset voltage
VCM = VS+ – 1.5 V
Input bias current
21
CHANNEL MATCHING
Channel-to-channel GBWP
mismatch
(6)
10
TA = 25°C
Channel-to-channel crosstalk f = 100 kHz
-93
Input offset voltage mismatch TA = 25°C
0.1
2.5
The supply voltages are VS+ = 12 V ± 1 V and VS– = –12 V for +PSRR, and VS+ = 12 V and VS– = –12 V ± 1 V for –PSRR.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
7.7 Electrical Characteristics: 5 V
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ, and output is biased to
midsupply (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test
Level (2)
AC PERFORMANCE
SSBW
Small-signal bandwidth
G = 1, Vo = 20 mVPP, RF = 0 Ω
74
MHz
C
G = 1, Vo = 20 mVPP, RF= 0 Ω,
CL= 33 pF
103
MHz
C
G = –1, Vo = 20 mVPP
51
MHz
C
G = 2, Vo = 20 mVPP
49
MHz
C
G = 5, Vo = 20 mVPP
15
MHz
C
LSBW
Large-signal bandwidth
G = 2 Vo = 2 VPP
33
MHz
C
GBWP
Gain-bandwidth product
G = 11, Vo = 20 mVPP
70
MHz
C
Bandwdith for 0.1dB flatness
G = 2, Vo = 20 mVPP
11
MHz
C
SR
G = 2, Vo = –1-V to 1-V step
119
V/µs
C
Slew rate (20%-80%) (3)
G = 2, Vo = –2-V to 2-V step,
VS = ±2.5 V
88
V/µs
C
Rise time
Vo = 200-mV step
4
ns
C
Fall time
Vo = 200-mV step
5
ns
C
Settling time to 0.1%
G = 2, Vo = –2-V to 0-V step,
VS = ±2.5 V
108
ns
C
Settling time to 0.001%
G = 2, Vo = –2-V to 0-V step,
VS = ±2.5 V
197
ns
C
10/11
%
C
G = 1, Vo = –1.25-V to 0.75-V step
1/7
%
C
Input overdrive recovery
G = 1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input, VS = ±2.5 V (see Figure 39)
71
ns
C
Output overdrive recovery
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input, VS = ±2.5 V (see Figure 40)
91
ns
C
–102
dBc
C
–85
dBc
C
–113
dBc
C
Overshoot/undershoot
HD2
HD3
G = 1, Vo = 200 mVPP
Second-order harmonic
distortion
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
Third-order harmonic
distortion
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
–97
f = 500 kHz, latband
en
Input-referred voltage noise
ei
Input-referred current noise
zO
Close-loop output impedance f = 100 kHz
f = 0.1-10 Hz integrated
f = 10 kHz
dBc
C
6
nV/√Hz
C
0.42
µVrms
C
5
fA/√Hz
C
0.007
Ω
C
118
dB
A
dB
B
1.5
mV
A
2.4
mV
B
DC PERFORMANCE
AOL
Open-loop voltage gain
f = DC, Vo = 1.25 V to 3.25 V
104
TA = –40°C to +125°C
104
TA = 25°C, no-load
VOS
Input offset voltage
0.1
TA = –40°C to +85°C
TA = –40°C to +125°C
Input offset voltage drift
(1)
(2)
(3)
TA = 25°C, no-load
TA = –40°C to +125°C
2.8
1.5
13
mV
B
µV/°C
B
µV/°C
B
For AC specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, input and output are biased to 0 V (unless
otherwise noted).
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
Lower of the measured positive and negative slew rate.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
11
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Electrical Characteristics: 5 V (continued)
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ, and output is biased to
midsupply(1).
PARAMETER
TEST CONDITIONS
MIN
TA = 25°C
Input bias current
Input offset current
Common-mode rejection
ratio
CMRR
TYP
MAX
UNIT
Test
Level (2)
2
20
pA
A
TA = –40°C to +85°C (4)
20
50
pA
B
TA = –40°C to +125°C (4)
100
340
pA
B
TA = 25°C
1
20
pA
A
TA = –40°C to +85°C
5
pA
B
TA = –40°C to +125°C
50
pA
B
92
dB
A
dB
B
V
C
GΩ||pF
C
0.5
pF
C
VS+ + 0.3
V
A
V
B
V
A
f = DC, TA = 25°C, VCM = 0.75 V to
1.75 V
78
TA = –40°C to +125°C
75
INPUT
Allowable input differential
voltage
See Figure 57
Common-mode input
impedance
In closed-loop configuration
±5
12 || 2.5
Differential input capacitance In open-loop configuration
Most positive input voltage
Most negative input voltage
Most positive input voltage
for main-JFET stage
ΔVOS < 5 mV (5)
VS+ + 0.2
TA = –40°C to +125°C
VS+ + 0.2
ΔVOS < 5 mV
(5)
VS- – 0.2
TA = –40°C to +125°C
VS- – 0.2
T = 25°C (see Figure 43)
VS+ – 2.9
TA = –40°C to +125°C
VS- – 0.3
VS+ – 2.5
VS+ – 3
V
B
V
C
V
C
OUTPUT
VOCRH
Output voltage range high
VOCRL
Output voltage range low
IO(max)
Linear output drive (sourcing
and sinking)
TA = 25°C, RL = 667 Ω
VS+ – 0.12 VS+ – 0.09
V
A
TA = –40°C to +125°C, RLOAD = 667 Ω
VS+ – 0.15
V
B
V
A
V
B
mA
A
mA
B
TA = 25°C, RL = 667 Ω
TA = –40°C to +125°C, RL = 667 Ω
VS– + 0.1
VS–+ 0.06
VS– + 0.15
TA = 25°C, VO = 1.4 V, RL = 27.5 Ω,
VOS < 2 mV, VS+ = 3 V and VS– = –2 V
50
TA = -40°C to 125°C, VO = 0.6 V, VOS
< 2 mV, VS+ = 3 V and VS– = –2 V
22
64
ISC
Output short-circuit current
TA = 25°C, TDelay = 5 ms
96
mA
B
CL
Capacitive load drive
< 1 dB peaking, RS = 0 Ω
35
pF
C
V
A
27
V
B
4
mA
A
4.4
mA
B
dB
A
dB
B
POWER SUPPLY
VS
Operating voltage
IQ
Quiescent current per
channel
PSRR
(4)
(5)
(6)
12
Power supply rejection ratio
TA = 25°C
4.75
TA = –40°C to +125°C
4.75
TA = 25°C
3.05
TA = –40°C to +125°C
2.8
ΔVS = 0.5 V, VCM = 0.5 V (6)
80
TA = –40°C to +125°C
80
27
3.6
100
Maximum bias current specification is set using ±5σ limits (corresponding to 0.58 DPPM) obtained using the statistical distribution from
electrical characterization over temperature of a sample set of 70 units. Maximum specification is not specified by final automated test
equipment (ATE) nor by QA sample testing.
Change in input offset from its value when input is biased to 0 V.
The supply voltages are VS+ = 5 V ± 0.25 V and VS– = 0 V for +PSRR, and VS+ = 5 V and VS– = 0 V ± 0.25 V for –PSRR.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Electrical Characteristics: 5 V (continued)
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ, and output is biased to
midsupply(1).
PARAMETER
TEST CONDITIONS
MIN
UNIT
Test
Level (2)
35
MHz
C
100
dB
A
TYP
MAX
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product
VCM = VS+ – 1 V
Open-loop voltage gain
VCM = VS+ – 1 V, f = DC, Vo = 1.5 V to
2.5 V
Input-referred voltage noise
VCM = VS+ – 1 V, f = 1 MHz
80
nV/√Hz
C
VCM = VS+ – 1.5 V, no-load
4
mV
A
VCM = VS+ – 0.5 V, no-load
4.8
mV
A
VCM = VS+ – 0.5 V, TA = –40°C to
+125°C, no-load
6.4
mV
B
2
20
pA
A
VCM = VS+ – 1.5 V, TA = –40°C to
+125°C
0.15
0.5
nA
B
Common-mode rejection
ratio
VCM = VS+ – 1.5 V to VS+ – 0.5 V
75
dB
B
Power supply rejection ratio
VCM = VS+ – 1.5 V, ΔVS = ±0.5 V (6)
75
dB
B
3
%
C
dBc
C
mV
A
Input offset voltage
VCM = VS+ – 1.5 V
Input bias current
21
CHANNEL MATCHING
Channel-to-channel GBWP
mismatch
TA = 25°C
Channel-to-channel crosstalk f = 100 kHz
-93
Input offset voltage mismatch TA = 25°C
0.1
2.5
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
13
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
7.8 Typical Characteristics: VS = 10 V
at VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2
VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
3
3
0
-3
Normalized Gain (dB)
Normalized Gain (dB)
0
-6
-9
-12
Gain = -1 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
Gain = 100 V/V
-15
-18
-21
100k
1M
-3
-6
-9
RL = 500 :
RL = 1 k:
RL = 100 k:
-12
10M
Frequency (MHz)
-15
100k
100M
1M
D041
See Figure 64 and Figure 65, VO = 20 mVPP
10M
Frequency (Hz)
100M
D042
See Figure 64, VO = 20 mVPP, Gain = 1 V/V, RF = 0 Ω
Figure 1. Small-Signal Frequency Response vs Gain
Figure 2. Small-Signal Frequency Response vs Output Load
3
3
0
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
-6
-9
RL = 500 :
RL = 1 k:
RL = 100 k:
-12
-15
100k
1M
-3
-6
-9
-12
RS = 0 :, CL = 2.2 pF
RS = 0 :, CL = 33 pF
RS = 24 :, CL = 47 pF
RS = 24 :, CL = 100 pF
RS = 17.4 :, CL = 200 pF
-15
-18
10M
Frequency (Hz)
-21
100k
100M
D043
1M
10M
Frequency (Hz)
100M
D044
See Figure 64 and Figure 62,
VO = 20 mVPP, Gain = 1 V/V, RF = 0 Ω
See Figure 64, VO = 20 mVPP, Gain = 2 V/V
Figure 4. Small-Signal Frequency Response vs CL
Figure 3. Small-Signal Frequency Response vs Output Load
3
3
0
0
-3
Normalized Gain (dB)
Normalized Gain (dB)
-3
-6
-9
-12
RS = 0 :, CL = 2.2pF
RS = 0 :, CL = 33pF
RS = 30 :, CL = 47pF
RS = 30 :, CL = 100 pF
RS = 23 :, CL = 200 pF
-15
-18
-21
100k
1M
10M
Frequency (Hz)
-6
-9
-12
-15
-18
-21
-24
-27
-30
100k
100M
D045
See Figure 64and Figure 62, VO = 20 mVPP, Gain = 2 V/V
Figure 5. Small-Signal Frequency Response vs CL
14
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
1M
10M
Frequency (Hz)
100M
D046
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 6. Large-Signal Frequency Response vs Output
Voltage
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Typical Characteristics: VS = 10 V (continued)
3
1
0
0.8
-3
0.6
Normalized Gain (dB)
Normalized Gain (dB)
at VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2
VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
-6
-9
-12
-15
-18
-21
-24
-27
-30
100k
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
1M
Gain = -1 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
10M
Frequency (Hz)
-1
100k
100M
See Figure 64, Gain = 2 V/V
-60
-60
-70
-70
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-80
-90
-100
-110
HD2, RL = 1 k:
HD3, RL = 1 k:
HD2, RL = 500 :
HD3, RL = 500 :
-140
100k
-80
-90
-100
-110
-120
-130
-140
100k
1M
Frequency (Hz)
1M
Frequency (Hz)
D048
Figure 10. Harmonic Distortion vs Frequency
0.15
-50
HD2, Gain = 1
HD3, Gain = 1
HD2, Gain = 2
HD3, Gain = 2
HD2, Gain = -1
HD3, Gain = -1
0.1
Output Voltage (V)
Harmonic Distortion (dBc)
-80
D049
See Figure 65, Gain = –1 V/V
Figure 9. Harmonic Distortion vs Frequency
-70
D051
HD2, RL = 1 k:
HD3, RL = 1 k:
HD2, RL = 500 :
HD3, RL = 500 :
See Figure 64, Gain = 2 V/V
-60
100M
Figure 8. Small-Signal Response Flatness vs Gain
-50
-130
10M
Frequency (MHz)
See Figure 64 and Figure 65, VO = 20 mVPP
Figure 7. Large-Signal Frequency Response vs Output
Voltage
-120
1M
D047
-90
-100
-110
0.05
0
-0.05
-120
-0.1
-130
-140
100k
-0.15
1M
Frequency (Hz)
Time (200 nsec/div)
D052
D050
See Figure 64 and Figure 65, RF = 0 Ω for Gain = 1 V/V
Figure 11. Harmonic Distortion vs Gain
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 12. Small-Signal Transient Response
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
15
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2
VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
6
Overshoot, VO = 200 mVPP
Undershoot, VO = 200 mVPP
Overshoot, VO = 2 VPP
Undershoot, VO = 2 VPP
40
VIN
VO
5
Input and Output Voltage (V)
Overshoot/Undershoot (%)
50
30
20
10
4
3
2
1
0
-1
-2
-3
-4
-5
0
-6
10
0
100
Load Capacitance (pF)
150
300
D053
See Figure 64, Gain = 1 V/V, RF = 0 Ω
450
600 750 900 1050 1200 1350 1500
Time (ns)
D054
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 13. Overshoot and Undershoot vs CL
Figure 14. Input Overdrive Recovery
6
6
4
3
Output Voltage (V)
Input and Output Voltage (V)
5
4
2
0
-2
2
1
Sourcing
Sinking
0
-1
-2
-3
-4
-4
VIN x -1 Gain
VO
-5
-6
-6
0
150
300
450
600 750 900 1050 1200 1350 1500
Time (ns)
D055
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Output Current (mA)
D056
See Figure 65, Gain = -1 V/V
Figure 16. Output Voltage vs Load Current
1200
800
Input Offset Voltage (PV)
Output Short-Circuit Current (mA)
Figure 15. Output Overdrive Recovery
130
125
120
115
110
105
100
95
90
85
80
75
70
65
60
55
50
-50
400
0
-400
-800
-1200
-30
-10
10
30
50
70
Ambient Temperature (oC)
90
110
130
-6
D057
Output saturated and then short-circuited, Io measured after
TDelay = 5 msec
Figure 17. Output Short-Circuit Current vs Ambient
Temperature
16
-4
-2
0
2
Input Common-Mode Voltage (V)
4
6
D058
Measured for 34 units
Figure 18. Input Offset Voltage vs Input Common-Mode
Voltage
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
7.9 Typical Characteristics: VS = 24 V
3
1.5
0
-1.5
-3
-4.5
-6
-7.5
-9
-10.5
-12
-13.5
-15
-16.5
-18
-19.5
-21
100k
6
3
0
Normalized Gain (dB)
Normalized Gain (dB)
at VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2
VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
Gain = -1 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
1M
-6
-9
-12
VCM = -11 V
VCM = -9 V
VCM = 0 V
VCM = 9 V
VCM = 11 V
-15
-18
10M
Frequency (Hz)
-21
100k
100M
10M
Frequency (Hz)
100M
D072
See Figure 64, VO = 20 mVPP, Gain = 1 V/V, CL = 33 pF, RF = 0 Ω
Figure 19. Noninverting Small-Signal Frequency Response
vs Gain
Figure 20. Small-Signal Frequency Response vs Output
Common-Mode Voltage
6
3
0
3
-3
Normalized Gain (dB)
0
-3
-6
-9
-12
VCM = -11 V
VCM = -9 V
VCM = 0 V
VCM = 9 V
VCM = 11 V
-15
-18
-21
100k
1M
-6
-9
-12
-15
-18
-21
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
-24
-27
10M
Frequency (Hz)
-30
100k
100M
D073
See Figure 64, VO = 20 mVPP, Gain = 1 V/V, CL = 47 pF, RF = 0 Ω
-40
-3
-50
Harmonic Distortion (dBc)
-30
0
-9
-12
-15
-18
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
VO = 10 VPP
-21
-24
-27
-30
100k
1M
10M
Frequency (Hz)
100M
D074
Figure 22. Large-Signal Frequency Response vs Output
Voltage
3
-6
1M
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 21. Small-Signal Frequency Response vs Output
Common-Mode Voltage
Normalized Gain (dB)
1M
D071
See Figure 64 and Figure 65, VO = 20 mVPP
Normalized Gain (dB)
-3
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, VO = 10 VPP
HD3, VO = 10 VPP
HD2, VO = 20 VPP
HD3, VO = 20 VPP
-60
-70
-80
-90
-100
-110
-120
-130
10M
Frequency (Hz)
-140
100k
100M
D075
See Figure 64, Gain = 2 V/V
1M
Frequency
D076
See Figure 64, Gain = 2 V/V
Figure 23. Large-Signal Frequency Response vs Vo
Figure 24. Harmonic Distortion vs Frequency vs Vo
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
17
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Typical Characteristics: VS = 24 V (continued)
at VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2
VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
-30
0.15
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, VO = 10 VPP
HD3, VO = 10 VPP
HD2, VO = 20 VPP
HD3, VO = 20 VPP
-50
-60
-70
0.1
Output Voltage (V)
Harmonic Distortion (dBc)
-40
-80
-90
-100
-110
-120
0.05
0
-0.05
-0.1
-130
-140
100k
-0.15
500
1M
Frequency (Hz)
700
900
D077
See Figure 65, Gain = –1 V/V
1100
1300
1500
Time (200 nsec/div)
1700
1900
D078
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 25. Harmonic Distortion vs Frequency vs Vo
Figure 26. Small-Signal Transient Response
12
6
VO = 2 VPP
VO = 10 VPP
4
VO = 2 VPP
VO = 10 VPP
VO = 20 VPP
10
8
Output Voltage (V)
Output Voltage (V)
6
2
0
-2
4
2
0
-2
-4
-6
-8
-4
-10
-6
300
-12
500
700
900
Time (200 ns/div)
1100
1300
Time (200 ns/div)
D080
D079
See Figure 64, Gain = 1 V/V, RF = 0 Ω
See Figure 64, Gain = 2 V/V
Figure 27. Large-Signal Transient Response
Figure 28. Large-Signal Transient Response
6
50
Overshoot/Undershoot (%)
4
Output Voltage (V)
Overshoot, VO = 200 mVPP
Undershoot, VO = 200 mVPP
Overshoot, VO = 2 VPP
Undershoot, VO = 2 VPP
VO = 2 VPP
VO = 10 VPP
2
0
-2
-4
-6
40
30
20
10
0
10
Time (200 ns/div)
See Figure 65, Gain = –1 V/V
D082
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 29. Large-Signal Transient Response
18
100
Load Capacitance (pF)
D081
Figure 30. Overshoot and Undershoot vs CL
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Typical Characteristics: VS = 24 V (continued)
15
15
12
12
Input and Output Voltage (V)
Input and Output Voltage (V)
at VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2
VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
9
6
3
0
-3
-6
-9
VIN
VO
-12
VIN x -1 Gain
VO
9
6
3
0
-3
-6
-9
-12
-15
-15
0
150
300
450
600 750 900 1050 1200 1350 1500
Time (ns)
D083
0
150
300
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Output Short-Circuit Current (mA)
Output Voltage (V)
Figure 32. Output Overdrive Recovery
Sourcing
Sinking
0
600 750 900 1050 1200 1350 1500
Time (ns)
D084
See Figure 65, Gain = –1 V/V
Figure 31. Input Overdrive Recovery
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
450
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Output Current (mA)
D085
130
125
120
115
110
105
100
95
90
85
80
75
70
65
60
55
50
-50
-30
-10
10
30
50
70
Ambient Temperature (oC)
90
110
130
D086
Output saturated and then short-circuited, Io measured after
TDelay = 5 msec
Figure 33. Output Voltage Range vs Load Current
Figure 34. Output Short-Circuit Current vs Ambient
Temperature
1500
Input Offset Voltage (PV)
1000
500
0
-500
-1000
-1500
-12.5 -10
-7.5 -5 -2.5
0
2.5
5
7.5
Input Common-Mode Voltage (V)
10
12.5
D087
Measured for 34 units
Figure 35. Input Offset Voltage vs Input Common-Mode Voltage
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
19
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
7.10 Typical Characteristics: VS = 5 V
0.15
3
1.5
0
-1.5
-3
-4.5
-6
-7.5
-9
-10.5
-12
-13.5
-15
-16.5
-18
-19.5
-21
100k
0.1
Output Voltage (V)
Normalized Gain (dB)
at VS+ = 5 V, VS– = 0 V, VCM= 1.25 V, RL = 1 kΩ, output is biased to midsupply, and TA ≈ 25°C. For AC specifications, VS+ =
3.5 V, VS– = –1.5 V, VCM= 0 V, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
Gain = -1 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
0.05
0
-0.05
-0.1
-0.15
1M
10M
Frequency (Hz)
100M
Time (200 nsec/div)
D011
D010
See Figure 64 and Figure 65, VO = 20 mVPP
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 36. Small-Signal Response vs Gain
Figure 37. Small-Signal Transient Response
4
Overshoot, VO = 200 mVPP
Undershoot, VO = 200 mVPP
Overshoot, VO = 2 VPP
Undershoot, VO = 2 VPP
40
VIN
VO
3
Input and Output Voltage (V)
Overshoot/Undershoot (%)
50
30
20
10
2
1
0
-1
-2
-3
0
-4
10
0
100
Load Capacitance (pF)
150
See Figure 64, Gain = 1 V/V, RF = 0 Ω
450
600 750 900 1050 1200 1350 1500
Time (ns)
D013
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 38. Overshoot and Undershoot vs CL
Figure 39. Input Overdrive Recovery
4
3
3
2
2
Output Voltage (V)
Input and Output Voltage (V)
300
D012
1
0
-1
1
Sourcing
Sinking
0
-1
-2
-3
VIN x -1 Gain
VO
-4
-2
-3
0
150
300
450
600 750 900 1050 1200 1350 1500
Time (ns)
D014
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Output Current (mA)
D015
See Figure 65, Gain = –1 V/V
Figure 40. Output Overdrive Recovery
20
Figure 41. Output Voltage Range vs Output Current
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Typical Characteristics: VS = 5 V (continued)
at VS+ = 5 V, VS– = 0 V, VCM= 1.25 V, RL = 1 kΩ, output is biased to midsupply, and TA ≈ 25°C. For AC specifications, VS+ =
3.5 V, VS– = –1.5 V, VCM= 0 V, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)
1000
120
Input Offset Voltage (PV)
Output Short-Circuit Current (mA)
130
110
100
90
80
70
500
0
-500
60
50
-50
-30
-10
10
30
50
70
Ambient Temperature (oC)
90
110
130
-1000
-3
D016
Output saturated and then short-circuited, Io measured after
TDelay = 5 ms
Figure 42. Output Short-Circuit Current vs Ambient
Temperature
-2
-1
0
1
Input Common-Mode Voltage (V)
2
3
D017
Measured for 34 units
Figure 43. Input Offset Voltage vs Input Common-Mode
Voltage
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
21
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
7.11 Typical Characteristics: ±2.375 V to ±12 V Split Supply
at VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted)
90
140
70
120
50
100
30
80
10
60
-10
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
3
0
Normalized Gain (dB)
110
180
Magnitude
Phase
160
Open-Loop Phase (o)
Open-Loop Gain Magnitude (dB)
130
-3
-6
-9
-12
-15
VS = 5 V
VS = 10 V
VS = 24 V
-18
40
100M
-21
100k
Simulated with no output load
0
-50
-3
-6
-9
-12
-15
VS = 5 V
VS = 10 V
VS = 24 V
-60
-70
-80
-90
-100
-110
-120
-130
1M
10M
Frequency (Hz)
-140
100k
100M
Figure 47. Harmonic Distortion vs Frequency vs Supply
Voltage
1000
HD2, VS = 5 V
HD3, VS = 5 V
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 24 V
HD3, VS = 24 V
Input Voltage Noise (nV/—Hz)
Harmonic Distortion (dBc)
-80
D103
See Figure 64, Gain = 2 V/V
-40
-70
1M
Frequency (Hz)
D102
Figure 46. Large-Signal Response vs Supply Voltage
-60
D101
HD2, VS = 5 V
HD3, VS = 5 V
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 24 V
HD3, VS = 24 V
See Figure 64, Gain = 2 V/V
-50
100M
Figure 45. Large-Signal Response vs Supply Voltage
-40
Harmonic Distortion (dBc)
Normalized Gain (dB)
Figure 44. Open-Loop Gain and Phase vs Frequency
-21
100k
10M
Frequency (Hz)
See Figure 64, Gain = 1 V/V, RF = 0 Ω
3
-18
1M
D109
-90
-100
-110
-120
100
10
-130
-140
100k
1M
Frequency (Hz)
1
10
D104
See Figure 65, Gain = –1 V/V
1k
10k
100k
Frequency (Hz)
1M
10M
D105
Measured then fit to ideal 1/f model
Figure 48. Harmonic Distortion vs Frequency vs Supply
Voltage
22
100
Figure 49. Input Voltage Noise Density vs Frequency
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Typical Characteristics: ±2.375 V to ±12 V Split Supply (continued)
at VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted)
-40
Aux Input Voltage Noise (nV/—Hz)
10000
-60
Crosstalk (dBc)
1000
100
-80
-100
-120
Ch-A to Ch-B
Ch-B to Ch-A
10
10
100
1k
10k
100k
Frequency (Hz)
1M
-140
100k
10M
Measured then fit to ideal 1/f model
D107
120
Common-Mode Rejection Ratio (dB)
10
1
0.1
0.01
0.001
Gain = 1 V/V
Gain = 2 V/V
0.0001
1k
10k
100k
1M
Frequency (Hz)
10M
100
90
80
70
60
50
40
30
20
100
100M
VS = 5 V
VS = 10 V
VS = 24 V
110
1k
10k
D108
See Figure 64 (simulation)
100k
1M
Frequency (Hz)
10M
100M
D110
Simulated curves
Figure 52. Closed-Loop Output Impedance vs Frequency
Figure 53. Common-Mode Rejection Ratio vs Frequency
120
120
PSRR VS+
PSRR VS-
100
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
100M
Figure 51. Crosstalk vs Frequency
100
80
60
40
20
0
100
10M
Frequency (Hz)
See Figure 64, Gain = 1 V/V, RF = 0 Ω
Figure 50. Auxiliary Input Stage Voltage Noise Density vs
Frequency
Output Impedance (ohms)
1M
D106
1k
10k
100k
1M
Frequency (Hz)
10M
100M
PSRR VS+
PSRR VS-
100
80
60
40
20
0
100
D111
Simulated Curves, VS = 5 V and 10 V
1k
10k
100k
1M
Frequency (Hz)
10M
100M
D112
Simulated curves, VS = 24 V
Figure 54. Power Supply Rejection Ratio vs Frequency
Figure 55. Power Supply Rejection Ratio vs Frequency
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
23
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Typical Characteristics: ±2.375 V to ±12 V Split Supply (continued)
at VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted)
300
Non-Inverting Input Bias Current (PA)
10
Inverting Input Bias Current (pA)
8
6
4
2
0
-2
-4
-6
-8
-10
-12 -10
-8
-6 -4 -2
0
2
4
6
Input Common-Mode Voltage (V)
8
10
200
100
0
-100
-200
TA = 25oC
TA = 125oC
-300
-7.5
12
-6
-4.5
-3 -1.5
0
1.5
3
Differential Input Voltage (V)
D118
VS = ±12-V
4.5
6
7.5
D115
Abs (VIN,Diff (max)) = VS when VS < 7 V
Figure 56. Input Bias Current vs Input Common-Mode
Voltage
Figure 57. Input Bias Current vs Differential Input Voltage
3.85
600
Input Offset Voltage (PV)
Quiescent Current (mA)
400
3.75
3.65
3.55
200
0
-200
-400
3.45
-40
-20
0
20
40
60
80
Ambient Temperature (oC)
100
-600
-40
120
-20
0
D117
70 units, DGK package
20
40
60
80
Ambient Temperature (oC)
100
120
D116
70 units, DGK package
Figure 58. Quiescent Current vs Ambient Temperature
Figure 59. Input Offset Voltage vs Ambient Temperature
18
300
16
No. of Units in Each Bin
No. of Units in Each Bin
250
200
150
100
14
12
10
8
6
4
50
2
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-7
400
350
300
250
200
150
100
0
50
-50
-100
-150
-200
-250
-300
-350
-400
D114
D113
Input offset voltage drift (µV/°C), –40°C to +125°C fit, 70 units
Input offset voltage (µV), 1246 units
Figure 60. Input Offset Voltage Distribution
24
-6
0
0
Figure 61. Input Offset Voltage Drift Distribution
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
8 Detailed Description
8.1 Overview
The OPA2810 is a dual-channel, FET-input, unity-gain stable voltage-feedback operational amplifier with
extremely low input bias current across its common-mode input voltage range. The OPA2810, characterized to
operate over a wide supply range of 4.75 V to 27 V, has a small-signal unity-gain bandwidth of 105 MHz and
offers both excellent DC precision and dynamic AC performance at low quiescent power. The OPA2810 is
fabricated on Texas Instrument's proprietary, high-speed SiGe BiCMOS process and achieves significant
performance improvements over comparable FET-input amplifiers at similar levels of quiescent power. With a
gain-bandwidth product (GBWP) of 70MHz, extremely high slew-rate (192 V/µs), and low-noise (6 nV/√Hz) the
OPA2810 is ideal in a wide range of data acquisition and signal processing applications. The OPA2810 includes
input clamps to allow maximum input differential voltage of up to 7 V, making it suitable for use with multiplexers
and processing of signals with fast transients. It achieves these benchmark levels of performance while
consuming a typical quiescent current (IQ) of 3.6 mA /channel.
The OPA2810 can source and sink large amounts of current without degradation in its linearity performance. The
wide-bandwidth of the OPA2810 implies that the device has low output-impedance across a wide frequency
range, thereby allowing the amplifier to drive capacitive loads up to 35 pF without requiring output isolation. This
device is suitable for a wide range of data acquisition, test and measurement front-end buffer, impedance
measurement, power analyzer, wideband photodiode transimpedance and signal processing applications.
8.2 Functional Block Diagram
VS+
OPA2810
VIN(1,2)+
+
±
+
±
Aux-Stage
EN
CC
JFET-Stage
VO(1,2)
EN
±
±
+
VIN(1,2)-
VS+ ± 2.5 V
VS-
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
25
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
8.3 Feature Description
8.3.1 OPA2810 Architecture
The OPA2810 features a true high-impedance input stage including a JFET differential-input pair main stage and
a CMOS differential-input auxiliary (Aux) stage operational within 2.5 V of the positive supply voltage. The bias
current is limited to a maximum of 20 pA throughout the common-mode input range of the amplifier. The
Functional Block Diagram section shows a block diagram representation for the input stage of the OPA2810.
The amplifier exhibits superior performance for high-speed signals (distortion, noise and input offset voltage)
while the Aux stage enables rail-to-rail inputs and prevents phase reversal. The OPA2810 also includes input
clamps which enable maximum input differential voltage of upto 7 V (lower of 7 V and total supply voltage). This
architecture offers significantly greater differential input voltage capability as compared to one to two times the
diode forward voltage drop maximum rating in standard amplifiers, and makes this device suitable for use with
multiplexers and processing of signals with fast transients. The input bias currents are also clamped to maximum
300 µA, as Figure 57 shows, which does not load the previous driver stage or require current-limiting resistors
(except limiting current through the input ESD diodes when input common-mode voltages are greater than the
supply voltages). This also enables the use of one of the channels as a comparator in systems which require an
amplifier and a comparator for signal-gain and fault-detection, respectively. For the lowest offset, distortion and
noise performance, limit the common-mode input voltage to the main JFET-input stage (greater than 2.5 V away
from the positive supply).
The OPA2810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in
Figure 16 for 10-V supply operation. This is particularly useful for inputs biased near the rails or when the
amplifier is configured in a closed-loop gain such that the output approaches the supply voltage. When the output
saturates, it recovers with 55 ns when inputs exceed the supply voltages by 0.5 V in an G = –1 V/V inverting gain
with a 10–V supply. The outputs are short-circuit protected with the limits of Figure 17.
An amplifier phase margin reduces and it becomes unstable when driving a capacitive load (CL) at the output, as
Figure 62 shows. Use of a series resistor (RS) between the amplifier output and load capacitance introduces a
zero which cancels the pole formed by the amplifier output impedance and CL in the open-loop transfer function.
The OPA2810 drives capacitive loads of up to 35 pF without causing instability. It is recommended to use a
series resistor for larger load capacitance values, as Figure 4 shows for OPA2810 configured as a unity-gain
buffer.
RS
VIN
VO
+
CL
RL
Figure 62. OPA2810 Driving Capacitive Load
26
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Feature Description (continued)
8.3.2 ESD Protection
All the device pins are protected with internal ESD protection diodes to the power supplies as Figure 63 shows.
These diodes provide moderate protection to input overdrive voltages above the supplies . The protection diodes
can typically support 10-mA continuous input and output currents. The differential input clamps only limit the bias
current when the input common-mode voltages are within the supply voltage range, whereas current limiting
series resistors must be added at the inputs if common-mode voltages higher than the supply voltages are
possible. Keep these resistor values as low as possible because using high values degrades noise performance
and frequency response.
VS+
Power Supply
ESD Cell
VIN(1,2)+
300 A
ICLAMP
+
±
VO(1,2)
VIN(1,2)-
VS-
Figure 63. Internal ESD Protection
8.4 Device Functional Modes
8.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
To facilitate testing with common lab equipment, the OPA2810 can be configured to allow for split-supply
operation (see the OPA2810DGK Evaluation Module). This configuration eases lab testing because the mid-point
between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum
analyzers and other lab equipment reference the inputs and outputs to ground. Figure 64 shows the OPA2810
configured as a noninverting amplifier and Figure 65 shows the OPA2810 configured as an inverting amplifier.
For split-supply operation referenced to ground, the power supplies VS+ and VS- are symmetrical around ground
and VREF = GND. Split-supply operation is preferred in systems where the signals swing around ground because
of the ease-of-use; however, the system requires two supply rails.
8.4.2 Single-Supply Operation (4.75 V to 27 V)
Many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power
supply. The OPA2810 can be used with a single supply (negative supply set to ground) with no change in
performance if the input and output are biased within the linear operation of the device. To change the circuit
from split supply to a balanced, single-supply configuration, level shift all the voltages by half the difference
between the power-supply rails. An additional advantage of configuring an amplifier for single-supply operation is
that the effects of PSRR are minimized because the low-supply rail is grounded. See the Single-Supply Op Amp
Design Techniques application report for examples of single-supply designs.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
27
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1
Selection of Feedback Resistors
The OPA2810 is a classic voltage feedback amplifier with each channel having two high-impedance inputs and a
low-impedance output. Standard application circuits include the noninverting and inverting gain configurations as
Figure 64 and Figure 65 show. The DC operating point for each configuration is level-shifted by the reference
voltage VREF which is typically set to midsupply in single-supply operation. VREF is often connected to ground in
split-supply applications.
VSIG
VS+
VREF
VIN
(1+RF/RG)VSIG
+
VO
VREF
±
RG
VS-
VREF
RF
Figure 64. Noninverting Amplifier
VS+
VREF
VSIG
VREF
-(RF/RG)VSIG
+
VO
VIN
RG
VREF
±
VSRF
Figure 65. Inverting Amplifier
The closed-loop gain of an amplifier in noninverting configuration is shown in Equation 1.
VO
§
RF ·
VIN ¨ 1
¸
© RG ¹
VREF
(1)
The closed-loop gain of an amplifier in an inverting configuration is shown in Equation 2.
VO
§ RF ·
VIN ¨
¸
© RG ¹
VREF
(2)
The magnitude of the low-frequency gain is determined by the ratio of the magnitudes of the feedback resistor
(RF) and the gain setting resistor RG. The order of magnitudes of the individual values of RF and RG offer a tradeoff between amplifier stability, power dissipated in the feedback resistor network, and total output noise. The
feedback network increases the loading on the amplifier output. Using large values of the feedback resistors
reduces the power dissipated at the amplifier output. On the other hand, this increases the inherent voltage and
28
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Application Information (continued)
amplifier current noise contribution seen at the output while lowering the frequency at which a pole occurs in the
feedback factor (β). This pole causes a decrease in the phase margin at zero-gain crossover frequency and
potential instability. Using small feedback resistors increases power dissipation and also degrades amplifier
linearity due to a heavier amplifier output load. Figure 66 shows a representative schematic of the OPA2810 in
an inverting configuration with the input capacitors shown.
CCM VS+
-(RF/RG)VSIG
+
VSIG
CDIFF
VIN
VREF
VO
VREF
±
RG
CPCB
CCM
VS-
RF
Figure 66. Inverting Amplifier with Input Capacitors
The effective capacitance seen at the amplifier's inverting input pin is shown in Equation 3 which forms a pole in
β at a cut-off frequency of Equation 4.
CIN
FC
CCM
CDIFF
CPCB
(3)
1
2SRFCIN
(4)
where:
• CCM is the amplifier common-mode input capacitance
• CDIFF is the amplifier differential input capacitance
• and, CPCB is the PCB parasitic capacitance.
Gain (dB)
For low-power systems, greater the values of the feedback resistors, the earlier in frequency does the phase
margin begin to reduce and cause instability. Figure 67 and Figure 68 illustrate the loop gain magnitude and
phase plots, respectively, for the OPA2810 simulation in TINA-TI configured as an inverting amplifier with values
of feedback resistors varying by orders of magnitudes.
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
100
RF = 200 :, RG = 50 :
RF = 10 k:, RG = 2.5 k:
RF = 1 M:, RG = 250 k:
1k
10k
100k
1M
Frequency (Hz)
10M
100M
D801
Figure 67. Loop-Gain vs. Frequency for Circuit of Figure 66
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
29
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Application Information (continued)
100
90
Phase (Degrees)
80
70
60
50
40
30
20
10
0
100
RF = 200 :, RG = 50 :
RF = 10 k:, RG = 2.5 k:
RF = 1 M:, RG = 250 k:
1k
10k
100k
1M
Frequency (Hz)
10M
100M
D802
Figure 68. Loop-Gain Phase vs. Frequency for Circuit of Figure 66
A lower phase margin results in peaking in the frequency response and lower bandwidth as Figure 69 shows,
which is synonymous with overshoot and ringing in the pulse response results. The OPA2810 offers a flat-band
voltage noise density of 6 nV/√Hz. TI recommends selecting an RF so the voltage noise contribution does not
exceed that of the amplifier. Figure 70 shows the voltage noise density variation with value of resistance at 25°C.
A 2-kΩ resistor exhibits a thermal noise density of 5.75 nV/√Hz which is comparable to the flatband noise of the
OPA2810. Hence, TI recommends using an RF lower than 2 kΩ while being large enough to not dissipate
excessive power for the output voltage swing and supply current requirements of the application. The Noise
Analysis and the Effect of Resistor Elements on Total Noise section shows a detailed analysis of the various
contributors to noise.
30
RF = 200 :, RG = 50 :
RF = 10 k:, RG = 2.5 k:
RF = 1 M:, RG = 250 k:
Gain (dB)
20
10
0
-10
10k
100k
1M
Frequency (Hz)
10M
100M
D806
Figure 69. Closed-Loop Gain vs. Frequency for Circuit of Figure 66
Voltage Noise Density (nV/—Hz)
1000
100
10
1
0.1
10
100
1k
10k
100k
Resistance (:)
1M
10M
D803
Figure 70. Thermal Noise Density vs Resistance
30
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Application Information (continued)
9.1.2 Noise Analysis and the Effect of Resistor Elements on Total Noise
The OPA2810 provides a low input-referred broadband noise voltage density of 6 nV/√Hz while requiring a low
3.6-mA quiescent supply current. To take full advantage of this low input noise, careful attention to the other
possible noise contributors is required. Figure 71 shows the operational amplifier noise analysis model with all
the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms
in nV/√Hz or pA/√Hz.
ENI
+
EO
IBN
RS
±
ERS
4kTR S
4kT
RF
RG
RG
4kTR F
IBI
4kT
1.6E 20 J
at 290q K
Figure 71. Operational Amplifier Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation adds all the contributing noise powers at the output by superposition, then
calculates the square root to get back to a spot noise voltage. Figure 71 shows the general form for this output
noise voltage using the terms shown in Equation 5.
EO =
(E
2
NI
2
)
(
+ (IBNRS ) + 4kTRS NG2 + IBIRF
2
) + 4kTRFNG
(5)
Dividing this expression by the noise gain (NG = 1 + RF / RG) shows the equivalent input referred spot noise
voltage at the noninverting input; see Equation 6.
2
EN =
ENI2
+ (IBNRS )
2
4kTRF
æI R ö
+ 4kTRS + ç BI F ÷ +
NG
è NG ø
(6)
Substituting large resistor values into Equation 6 can quickly dominate the total equivalent input referred noise. A
source impedance on the noninverting input of 2-kΩ adds a Johnson voltage noise term equal to that of the
amplifier (6 nV/√Hz).
Table 1 compares the noise contributions from the various terms when the OPA2810 is configured in a
noninverting gain of 5V/V as Figure 72 shows. Two cases are considered where the resistor values in case 2 are
10x the resistor values in case 1. The total output noise in case 1 is 31.3 nV/√Hz while the noise in case 2 is
49.7 nV/√Hz. The large value resistors in case 2 dilute the benefits of selecting a low noise amplifier like the
OPA2810. To minimize total system noise, reduce the size of the resistor values. This increases the amplifiers
output load and results in a degradation of distortion performance. The increased loading increases the dynamic
power consumption of the amplifier. The circuit designer must make the appropriate tradeoffs to maximize the
overall performance of the amplifier to match the system requirements.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
31
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Application Information (continued)
VS+ = 5V
+
EO
Case1: 200
Case2: 2 k
RS
±
VS- = -5V
RG
Case1: 250
Case2: 2.5 k
RF
Case1: 1 k
Case2: 10 k
Figure 72. Comparing Noise Contributors for Two Cases With the Amplifier in a Noninverting Gain of
5 V/V
Table 1. Comparing Noise Contributions for the Circuit in Figure 72
Case 1
Case 2
Noise
Source
Output
Noise
Equation
Source
resistor, RS
ERS
(1+RF/RG)
1.82
nV/√Hz
9.1
82.81
7.77
5.76
nV/√Hz
28.8
829.44
32.41
Gain resistor,
RG
ERG
(RF/RG)
2.04
nV/√Hz
8.16
66.59
6.24
6.44
nV/√Hz
25.76
663.58
25.93
Feedback
resistor, RF
ERF
4.07
nV/√Hz
4.07
16.57
1.55
12.87
nV/√Hz
12.87
165.64
6.47
30
900
84.43
6 nV/√Hz
30
900
35.17
Amplifier
voltage
noise, ENI
Noise
Source
Value
Voltage
Noise Power
Noise
Contribution
Contribution
Contribution
(%)
2
(nV /Hz)
(nV/√Hz)
ENI
6 nV/√Hz
(1+RF/RG)
Noise
Source
Value
Voltage
Noise Power
Noise
Contribution
Contribution
Contribution
(%)
2
(nV /Hz)
(nV/√Hz)
Inverting
current
noise, IBI
IBI
(RF||RG)
5 fA/√Hz
5.0E-3
—
—
5 fA/√Hz
50E-3
—
—
Noninverting
current
noise, IBN
IBNRS
(1+RF/RG)
5 fA/√Hz
1.0E-3
—
—
5 fA/√Hz
10E-3
—
—
32
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
9.2 Typical Applications
9.2.1 Transimpedance Amplifier
The high GBWP and low input voltage and current noise for the OPA2810 make it an ideal wideband
transimpedance amplifier for moderate to high transimpedance gains.
VBIAS
Supply Decoupling not
shown
+5 V
RS
OPA2810
50
+
CD
20 pF
CPCB
0.3 pF
Oscilloscope
with 50
Inputs
-5 V
RF
100 k
CF + CPCB
1.03 pF
Figure 73. Wideband, High-Sensitivity, Transimpedance Amplifier
9.2.1.1 Design Requirements
Design a high-bandwidth, high-gain transimpedance amplifier with the design requirements listed in Table 2.
Table 2. Design Requirements
TARGET BANDWIDTH (MHz)
TRANSIMPEDANCE GAIN (KΩ)
PHOTODIODE CAPACITANCE (pF)
>2
100
20
9.2.1.2 Detailed Design Procedure
Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit
from the low input voltage noise of the OPA2810. This input voltage noise is peaked up over frequency by the
diode source capacitance, and can, in many cases, become the limiting factor to input sensitivity. The key
elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (VBIAS) applied, the
desired transimpedance gain, RF, and the GBWP for the OPA2810 (70 MHz). Figure 73 shows a transimpedance
circuit with the parameters as described in Table 2. With these three variables set (and including the parasitic
input capacitance for the OPA2810 and the PCB added to CD), the feedback capacitor value (CF) may be set to
control the frequency response. Transimpedance Considerations for High-Speed Amplifiers application report
discusses using high-speed amplifiers for transimpedance applications. To achieve a maximally-flat second-order
Butterworth frequency response, set the feedback pole to:
1
2S RF CF
GBWP
4S RF CD
(7)
The input capacitance of the amplifier is the sum of the common-mode and differential capacitance (2.5 +
0.5) pF. The parasitic capacitance from the photodiode package and the PCB is approximately 0.3 pF. Using
Equation 3, this results in a total input capacitance of CD = 23.3 pF. From Equation 7, set the feedback pole at
1.55 MHz. Setting the pole at 1.55 MHz requires a total feedback capacitance of 1.03 pF.
The approximate –3-dB bandwidth of the transimpedance amplifier circuit is shown in:
f
3 dB
GBWP / (2S RF CD ) Hz
(8)
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
33
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
Gain (dB)
Equation 8 estimates a closed-loop bandwidth of 2.19 MHz. Figure 74 and Figure 75 show the loop-gain
magnitude and phase plots from the TINA-TI simulations of the transimpedance amplifier circuit of Figure 73. The
1/β gain curve has a zero from RF and CIN at 70 kHz and a pole from RF and CF cancelling the 1/β zero at 1.5
MHz resulting in a 20 dB/decade rate-of-closure at the loop gain crossover frequency (freqeuncy where AOL =
1/β), ensuring a stable circuit. A phase margin of 62° is obtained with a closed-loop bandwidth of 3 MHz and a
100-kΩ transimpedance gain.
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
100
AOL
1/E
AOLE
1k
10k
100k
1M
Frequency (Hz)
10M
100M
D804
Figure 74. Loop-Gain Magnitude vs Frequency for Transimpedance Amplifier Circuit of Figure 73
100
90
Phase (Degrees)
80
70
60
50
AOL
1/E
AOLE
40
30
20
10
0
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
D805
Figure 75. Loop-Gain Phase vs Frequency for Transimpedance Amplifier Circuit of Figure 73
34
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
9.2.2
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Multichannel Sensor Interface
High-Z input amplifiers are particularly useful when interfaced with sensors that have relatively high output
impedance. Such multichannel systems usually interface these sensors with the signal chain through a
multiplexer. Figure 76 shows one such implementation using an amplifier for interface with each sensor, and
driving into an ADC through a multiplexer. An alternate circuit, shown in Figure 77, may use a single higher
GBWP and fast-settling amplifier at the output of the multiplexer. This gives rise to large signal transients when
switching between channels, where the settling performance of the amplifier and maximum allowed differential
input voltage limits signal chain performance and amplifier reliability, respectively.
+
+
MUX
ADC
+
Figure 76. Multichannel Sensor Interface Using Multiple Amplifiers
OPA2810
ADC
MUX
+
Figure 77. Multichannel Sensor Interface Using a Single Higher GBWP Amplifier
Figure 78 shows the output voltage and input differential voltage when a 8-V step is applied at the noninverting
terminal of the OPA2810 configured as a unity-gain buffer of Figure 77.
Input and Output Voltage (V)
7.5
5
2.5
0
-2.5
VIN
VO
VIN,Diff
-5
Time (10 ns/div)
BD_M
Figure 78. Large-Signal Transient Response Using OPA2810
Because of the fast input transient, the amplifier is slew-limited and the inputs cease to track each other (a
maximum VIN,Diff of 7V is seen in Figure 78) until the output reaches its final value and the negative feedback
loop is closed. For standard amplifiers with a 0.7-1.5V maximum VIN,Diff rating, it is required to use current-limiting
resistors in series with the input pins to protect from irreversible damage, which also limits the device frequency
response. The OPA2810 has built-in input clamps that allow the application of as much as 7V of VIN,Diff, with no
external resistors required and no damage to the device or a shift in performance specifications. Such an inputstage architecture coupled, with its fast settling performance, makes the OPA2810 a good fit for multichannel
sensor multiplexed systems.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
35
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
10 Power Supply Recommendations
The OPA2810 is intended for operation on supplies ranging from 4.75 V to 27 V. The OPA2810 may be operated
on single-sided supplies, split and balanced bipolar supplies or unbalanced bipolar supplies. Operating from a
single supply can have numerous advantages. With the negative supply at ground, the DC errors due to the
–PSRR term can be minimized. Typically, AC performance improves slightly at 10-V operation with minimal
increase in supply current. Minimize the distance (< 0.1") from the power supply pins to high-frequency, 0.01-µF
decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-frequency, 0.01-µF supplydecoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these
capacitors. When a split-supply is used, use these capacitors from each supply to ground. If necessary, place the
larger capacitors further from the device and share these capacitors among several devices in the same area of
the printed circuit board (PCB). An optional supply decoupling capacitor across the two power supplies (for splitsupply operation) reduces second harmonic distortion.
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA2810 requires careful attention to
board layout parasitics and external component types. The OPA2810EVM can be used as a reference when
designing the circuit board. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability—on the noninverting input, it can react with the source
impedance to cause unintentional band-limiting. To reduce unwanted capacitance, open a window around
the signal I/O pins in all of the ground and power planes around those pins. Otherwise, ground and power
planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1") from the power-supply pins to high-frequency 0.01-µF decoupling capacitors.
At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF
to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the supply pins. These
can be placed somewhat farther from the device and shared among several devices in the same area of the
PC board.
3. Careful selection and placement of external components preserve the high frequency performance of
the OPA2810. Resistors must be a low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high
frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use
wirewound type resistors in a high frequency application. Because the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as
close as possible to the output pin. Other network components, such as noninverting input termination
resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal film or surface mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 10 kΩ, this parasitic capacitance can add a pole or zero close to the GBWP of
70 MHz and subsequently affects circuit operation. Keep resistor values as low as possible consistent with
load driving considerations. Lowering the resistor values keep the resistor noise terms low, and minimize the
effect of its parasitic capacitance, however lower resistor values increase the dynamic power consumption
because RF and RG become part of the amplifiers output load network. Transimpedance applications (see
the Transimpedance Amplifier section) can use whatever feedback resistor is required by the application as
long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the
inverting node.
4. Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground
and power planes opened up around them. Estimate the total capacitive load and set RS for sufficient phase
margin and stability. Low parasitic capacitive loads (< 35 pF) may not need an RS because the OPA2810 is
nominally compensated to operate with a 35-pF parasitic load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases (increasing the unloaded phase margin) If a long trace is
36
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
Layout Guidelines (continued)
required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement
a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary
onboard, and a higher impedance environment improves distortion. With a characteristic board trace
impedance defined based on board material and trace dimensions, a matching series resistor into the trace
from the output of the OPA2810 is used as well as a terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and
the input impedance of the destination device— this total effective impedance must be set to match the trace
impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the
series resistor value to obtain sufficient phase margin and stability. This does not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of the destination device is low, the signal attenuates
because of the voltage divider formed by the series output into the terminating impedance.
5. Take care to design the PCB layout for optimal thermal dissipation. For the extreme case of 125°C
operating ambient, using the approximate maximum 177.2°C/W for the two packages, and an internal power
of 24-V supply × 9-mA 125°C supply current (both amplifiers) gives a maximum internal power dissipation of
216 mW. This power gives a 38°C increase from ambient to junction temperature. Load power adds to this
value and this dissipation must also be calculated to determine the worst-case safe operating point.
6. Socketing a high speed part like the OPA2810 is not recommended. The additional lead length and pinto-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the OPA2810 onto the board.
11.1.1 Thermal Considerations
The OPA2810 does not require heat sinking or airflow in most applications. Maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum
of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL
depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). Under this condition
PDL = VS 2 / (4 × RL) where RL includes feedback network loading.
The power in the output stage and not into the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an OPA2810-DGK (VSSOP package) configured as a
unity gain buffer, operating on ±12-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω
load.
PD = 24 V × 9 mA + 122 /(4 × 500 Ω) = 288 mW
Maximum TJ = 25°C + (0.288 W × 177.2°C/W) = 76°C, which is well below the maximum allowed junction
temperature of 150oC.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
37
OPA2810
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
www.ti.com
11.2 Layout Example
VS+
Representative schematic of a
single channel
CBYP
RS
+
±
CBYP
VSRG
RF
Ground and power plane exist on
inner layers.
Place series output resistors
close to output pin to minimize
parasitic capacitance
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
CBYP
RS
1
8
2
7
3
6
RF
RS
RG
Place bypass capacitors
close to power pins
RF
Place gain and feedback resistors
close to pins to minimize stray
capacitance
RG
Place bypass capacitors
close to power pins
4
5
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
CBYP
Figure 79. Layout Recommendation
38
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
OPA2810
www.ti.com
SBOS789C – AUGUST 2017 – REVISED FEBRUARY 2020
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2810DGK Evaluation Module user's guide
• Texas Instruments, OPA810 140-MHz, Rail-to-Rail Input/Output, FET-Input Operational Amplifier data sheet
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
• Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 1
• Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 2
• Texas Instruments, Noise Analysis for High-Speed Op Amps application report
• Texas Instruments, TINA model and simulation tool
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: OPA2810
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2810IDCNR
ACTIVE
SOT-23
DCN
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2810
OPA2810IDCNT
ACTIVE
SOT-23
DCN
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2810
OPA2810IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2810
OPA2810IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2810
OPA2810IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2810
OPA2810IDT
ACTIVE
SOIC
D
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2810
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
