OPA2889

Burr Brown Products from Texas Instruments OP A28 89 OP A2 889 OPA2889 SBOS373 – JUNE 2007 Dual, Low-Power, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable FEATURES • FLEXIBLE SUPPLY RANGE: +2.6V to +12V Single Supply ±1.3V to ±6V Dual Supplies UNITY-GAIN STABLE WIDEBAND ±5V OPERATION: 60MHz (G = +2V/V) OUTPUT VOLTAGE SWING: ±4V HIGH SLEW RATE: 250V/μs LOW QUIESCENT CURRENT: 460μA/ch LOW DISABLE CURRENT: 18μA/ch DESCRIPTION The OPA2889 represents a major step forward in unity-gain stable, voltage-feedback op amps. A new internal architecture provides slew rate and full-power bandwidth previously found only in wideband, current-feedback op amps. These capabilities give exceptional full-power bandwidth. Using a dual ±5V supply, the OPA2889 can deliver a ±4V output swing with over 40mA drive current and 60MHz bandwidth. This combination of features makes the OPA2889 an ideal RGB line driver or single-supply analog-to-digital converter (ADC) input driver or low power twisted pair line receiver. The low 460μA/ch supply current of the OPA2889 is precisely trimmed at +25°C. System power may be reduced further using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, operates the OPA2889 normally. If pulled LOW, the OPA2889 supply current drops to less than 20μA/ch while the output goes into a high-impedance state. RELATED OPERATIONAL AMPLIFIER PRODUCTS • • • • • • • • • • • • • APPLICATIONS VIDEO LINE DRIVING xDSL LINE RECEIVERS HIGH-SPEED IMAGING CHANNELS ADC BUFFERS PORTABLE INSTRUMENTS TRANSIMPEDANCE AMPLIFIERS ACTIVE FILTERS 1kW Vi 0V ® 4V 500pF 200W 1/2 OPA2889 50W +6V 16W +5V ADS8472 SINGLES Low-Power Voltage-Feedback with Disable 16-Bit 1MSPS SAR ADC DUALS OPA2890 OPA2690 OPA2691 TRIPLES OPA890 OPA690 OPA691 OPA692 -6V 200W 750W .01mF 750W Voltage-Feedback Amplifier with Disable (1800V/μs) Current-Feedback Amplifier with Disable (2100V/μs) Fixed Gain OPA3690 OPA3691 OPA3692 +6V 375W VREF/2 -6V 500kHz LP Pole 1/2 OPA2889 16W Low Power, DC-Coupled, Single-to-Differential Driver for ≤100kHz Inputs Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated OPA2889 www.ti.com SBOS373 – JUNE 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE DESIGNATOR D DGS SPECIFIED TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C PACKAGE MARKING OP2889 BZY ORDERING NUMBER OPA2889ID OPA2889IDR OPA2889IDGST OPA2889IDGSR TRANSPORT MEDIA, QUANTITY Rail, 75 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 PRODUCT OPA2889 OPA2889 (1) PACKAGE-LEAD SO-8 MSOP-10 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). OPA2889 Power supply Internal power dissipation Input voltage range Storage temperature range Lead temperature (soldering, 10s) Maximum junction temperature (TJ) Maximum junction temperature (TJ), continuous operation ESD Rating: Human body model (HBM) Charge device model (CDM) Machine model (MM) 2000 1000 150 V V V ±6.5 ±VS –40 to +125 +260 +150 +140 UNIT V V °C °C °C C See Thermal Characteristics PIN ASSIGNMENTS Top View SO-8 Top View MSOP-10 +In A Out A -In A +In A -VS 1 2 3 4 A B 8 7 6 5 +VS DIS A Out B -VS -In B DIS B +In B +In B 1 2 3 4 5 10 9 8 7 6 -In A Out A +VS Out B -In B 2 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 ELECTRICAL CHARACTERISTICS: VS = 5V At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted. OPA2889ID, IDGS TYP PARAMETER AC PERFORMANCE Small-Signal Bandwidth G = +1V/V, VO = 100mVPP, RF = 0Ω G = +2V/V, VO = 100mVPP G = +10V/V, VO = 100mVPP Gain Bandwidth Product Bandwidth for 0.1dB Flatness Peaking at a Gain of +1V/V Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic G = +2V/V, f = 1MHz, VO = 2VPP RL = 200Ω RL ≥ 500Ω 3rd-Harmonic RL = 200Ω RL ≥ 500Ω Input Voltage Noise Input Current Noise Differential Gain Differential Phase Channel-to-Channel Crosstalk DC PERFORMANCE (4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Input Bias Current Drift Input Offset Current Average Input Offset Current Drift INPUT Common-Mode Input Range (CMIR) (5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Common-Mode VCM = 0V VCM = 0V 3.5 || 0.5 170 || 0.8 MΩ || pF MΩ || pF typ typ C C VCM = 0V, Input-referred ±3.9 70 ±3.8 60 3.7 59 3.6 58 V dB min min A A VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V ±50 200 ±150 ±750 66 ±1.5 60 5 58 5.9 20 840 2 225 0.5 57 6.3 20 880 2 235 0.5 dB mV μV/°C nA nA/°C nA nA/°C min max max max max max max A A B A B A B f > 100kHz f > 100kHz G = +2V/V, VO = 1.4VPP, RL = 150Ω G = +2V/V, VO = 1.4VPP, RL = 150Ω f = 5MHz, Input-referred –75 –80 –80 –82 8.4 0.7 0.06 0.04 –85 –65 –73 –74 –80 10 1 –62 –68 –70 –75 11.5 1.2 –60 –65 –68 –72 12 1.4 dBc dBc dBc dBc nV/√Hz pA/√Hz % ° dB max max max max max max typ typ typ B B B B B B C C C G > +20V/V G = +2V/V, VO = 100mVPP VO < 100mVPP , RF =0 Ω G = +2V/V, VO = 2VPP G = +2V/V, VO = 2V Step 0.2V Step G = +1V/V, VO = 2V Step 115 60 8 75 14 1 70 250 6 36 25 175 160 150 40 6 60 36 5 50 32 4.5 45 MHz MHz MHz MHz MHz dB MHz V/μs ns ns ns typ min min min typ typ typ min typ typ typ C B B B C C C B C C C CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) (1) (2) (3) (4) (5) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +4°C at high temperature limit for over temperature specifications. Current is considered positive out-of-node. VCM is the input common-mode voltage. Tested < 3dB below minimum specified CMRR at ±CMIR limits Submit Documentation Feedback 3 OPA2889 www.ti.com SBOS373 – JUNE 2007 ELECTRICAL CHARACTERISTICS: VS = 5V (continued) At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted. OPA2889ID, IDGS TYP PARAMETER OUTPUT Output Voltage Swing No load RL = 100Ω Output Current, Sourcing, Sinking Peak Output Current Closed-Loop Output Impedance DISABLE (MSOP-10 ONLY) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) POWER SUPPLY Specified Operating Voltage Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection (+PSRR) Ratio (–PSRR) THERMAL CHARACTERISTICS Specified Operating Range D and DGS Packages Thermal Resistance, θJA D DGS SO-8 MSOP-10 Junction-to-ambient 100 135 °C/W °C/W typ typ C –40 to +85 °C typ C VS = ±5V, Both channels VS = ±5V, Both channels +VS = 4.5V to 5.5V –VS = -4.5V to -5.5V 0.92 0.92 64 74 ±5 1.3 ±6.0 1 0.8 62 72 6.0 1.05 0.75 61 71 6.0 1.1 0.7 60 70 V V V mA mA dB dB typ typ max max min min min C C A A A A A VDIS = 0V, Each channel VO = 0V Output shorted to ground G = +2V/V, f = 100kHz Disable LOW VDIS = 0, Both channels VIN = 1VDC VIN = 1VDC G = +2V/V, f = 5MHz 36 70 200 70 4 3.3 1.2 15 3.4 1.0 25 3.5 0.9 30 3.55 0.85 35 50 53 55 μA μs ns dB pF V V μA max typ typ typ typ min max max A C C C C A A A ±4.0 ±3.3 ±40 ±60 0.04 ±3.9 ±3.0 ±28 3.8 2.95 25 3.7 2.85 22 V V mA mA Ω min min min typ typ A A A C C CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) 4 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 ELECTRICAL CHARACTERISTICS: VS = +5V At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted. OPA2889ID, IDGS TYP PARAMETER AC PERFORMANCE Small-Signal Bandwidth G = +1V/V, VO = 100mVPP, RF = 0Ω G = +2V/V, VO = 100mVPP G = +10V/V, VO = 100mVPP Gain Bandwidth Product Bandwidth for 0.1dB Flatness Peaking at a Gain of +1V/V Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic G = +2V/V, f = 1MHz, VO = 2VPP RL = 200Ω RL ≥ 500Ω 3rd-Harmonic RL = 200Ω RL ≥ 500Ω Input Voltage Noise Input Current Noise Differential Gain Differential Phase Channel-to-Channel Crosstalk DC PERFORMANCE (4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Input Bias Current Drift Input Offset Current Average Input Offset Current Drift INPUT Most Positive Input Voltage Least Positive Input Voltage Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Common-Mode VCM = 0V VCM = 0V 3.5 || 0.5 170 || 0.8 MΩ || pF MΩ || pF typ typ C C VCM = 0V, Input-referred 4 1 68 3.9 1.1 58 3.8 1.2 57 3.75 1.25 56 V V dB min max min A A A VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V ±50 250 ±150 ±800 64 ±1.5 58 5 56 5.9 20 890 2 275 0.5 55 6.3 20 930 2 285 0.5 dB mV μV/°C nA nA/°C nA nA/°C min max max max max max max A A B A B A B f > 100kHz f > 100kHz G = +2V/V, VO = 1.4VPP, RL = 150Ω G = +2V/V, VO = 1.4VPP, RL = 150Ω f = 5MHz, Input-referred –71 –76 –76 –76 8.5 0.7 0.06 0.04 –85 –61 –69 –70 –74 10.5 1 –58 –64 –66 –69 12 1.1 –56 –61 –64 –66 12.5 1.2 dBc dBc dBc dBc nV/√Hz pA/√Hz % ° dB max max max max max max typ typ typ B B B B B B C C C G > +20V/V G = +2V/V, VO = 100mVPP VO < 100mVPP , RF =0 Ω G = +2V/V, VO = 2VPP G = +2V/V, VO = 2V Step 0.2V Step G = +1V/V, VO = 2V Step 100 50 7 70 14 1 60 200 6.5 38 27 125 110 100 30 5.5 55 26 4.5 45 22 4 40 MHz MHz MHz MHz MHz dB MHz V/μs ns ns ns typ min min min typ typ typ min typ typ typ C B B B C C C B C C C CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) (1) (2) (3) (4) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +4°C at high temperature limit for over temperature specifications. Current is considered positive out-of-node. VCM is the input common-mode voltage. Submit Documentation Feedback 5 OPA2889 www.ti.com SBOS373 – JUNE 2007 ELECTRICAL CHARACTERISTICS: VS = +5V (continued) At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted. OPA2889ID, IDGS TYP PARAMETER OUTPUT Most Positive Output Voltage No load RL = 100Ω Least Positive Output Voltage No Load RL = 100Ω Output Current, Sourcing, Sinking Peak Output Current Closed-Loop Output Impedance DISABLE (MSOP-10 ONLY) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) POWER SUPPLY Specified Operating Voltage Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection (+PSRR) Ratio THERMAL CHARACTERISTICS Specified Operating Range D and DGS Packages Thermal Resistance, θJA D DGS SO-8 MSOP-10 Junction-to-ambient 100 135 °C/W °C/W typ typ C C –40 to +85 °C typ C VS = +5V, Both channels VS = +5V, Both channels +VS = 4.5V to 5.5V 0.85 0.85 60 +5 +2.6 +12 0.95 0.75 +12 1.0 0.7 +12 1.05 0.65 V V V mA mA dB typ typ max max min typ C C A A A C VDIS = 0V, Each channel VO = 0V Output shorted to ground G = +2V/V, f = 100kHz Disable LOW VDIS = 0, both channels VIN = 1VDC VIN = 1VDC G = +2V/V, f = 5MHz 36 70 200 70 4 3.3 1.2 15 3.4 1.0 25 3.5 0.9 30 3.55 0.85 35 50 53 55 μA μs ns dB pF V V μA max typ typ typ typ min max max A C C C C A A A 4 3.85 1 1.15 ±35 ±50 0.04 3.9 3.7 1.1 1.3 ±24 3.8 3.6 1.2 1.4 21 3.7 3.55 1.3 1.45 18 V V V V mA mA Ω min min max max min typ typ A A A A A C C CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) 6 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 TYPICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 100Ω, unless otherwise noted. See Figure 50. SMALL-SIGNAL FREQUENCY RESPONSE 3 0 G = +1V/V R F = 0W 9 6 3 VO = 1VPP LARGE-SIGNAL FREQUENCY RESPONSE Normalized Gain (dB) -3 -6 -9 G = +5V/V -12 -15 VO = 0.1VPP -18 100k 1M G = +2V/V Gain (dB) G = +10V/V 0 -3 VO = 0.5VPP VO = 2VPP VO = 4VPP -6 -9 10M Frequency (Hz) 100M 300M RL = 100W G = +2V/V 1 10 Frequency (MHz) 100 200 Figure 1. SMALL-SIGNAL PULSE RESPONSE 150 100 VO = 200mVPP G = +2V/V 1.5 1.0 Figure 2. LARGE-SIGNAL PULSE RESPONSE VO = 2VPP G = +2V/V Output Voltage (mV) 50 0 -50 -100 -150 Time (10ns/div) Output Voltage (V) 0.5 0 -0.5 -1.0 -1.5 Time (10ns/div) Figure 3. VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE 0.50 0.45 0.40 -dP 0.50 0.45 0.40 0.35 +dP -dG 0.30 0.25 0.20 +dG 0.15 0.10 0.05 0 1 2 Video Loads 3 4 Figure 4. CHANNEL-TO-CHANNEL CROSSTALK -40 Input-Referred 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 Differential Phase (°) Differential Gain (%) -50 Crosstalk (dB) -60 -70 -80 -90 1M 10M 100M 1G Frequency (Hz) Figure 5. Figure 6. Submit Documentation Feedback 7 OPA2889 www.ti.com SBOS373 – JUNE 2007 HARMONIC DISTORTION vs LOAD RESISTANCE -65 VO = 2VPP f = 1MHz G = +2V/V 1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE -70 -72 -74 -76 -78 -80 3rd Harmonic -82 2nd Harmonic VO = 2VPP RL = 200W G = +2V/V Harmonic Distortion (dBc) -75 2nd Harmonic -80 3rd Harmonic -85 -90 100 Load Resistance (W) 1k Harmonic Distortion (dBc) -70 -84 5 6 7 8 9 10 11 12 Supply Voltage (V) Figure 7. HARMONIC DISTORTION vs FREQUENCY -40 -50 -60 -70 -80 -90 3rd Harmonic -100 -110 0.1 1 Frequency (MHz) 10 VO = 2VPP RL = 200W G = +2V/V -55 -60 -65 -70 -75 -80 Figure 8. HARMONIC DISTORTION vs OUTPUT VOLTAGE RL = 200W f = 1MHz G = +2V/V Harmonic Distortion (dBc) Harmonic Distortion (dBc) 2nd Harmonic 2nd Harmonic 3rd Harmonic -85 -90 0.1 1 Output Voltage Swing (VPP) 10 Figure 9. HARMONIC DISTORTION vs NONINVERTING GAIN -65 VO = 2VPP RL = 200W f = 1MHz 2nd Harmonic -75 3rd Harmonic -80 -60 Figure 10. HARMONIC DISTORTION vs INVERTING GAIN VO = 2VPP RL = 200W f = 1MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) -70 -65 -70 2nd Harmonic 3rd Harmonic -75 -85 -80 -90 1 Gain (V/V) 10 -85 1 Gain (-V/V) 10 Figure 11. Figure 12. 8 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 LOW-FREQUENCY INVERTING HARMONIC DISTORTION -85 -90 -95 -100 -105 -110 -115 -120 1k 10k 100k Frequency (Hz) 1M 3rd Harmonic 2nd Harmonic RL = 500W VO = 2VPP G = -1V/V TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -40 5MHz -50 Harmonic Distortion (dBc) Spurious Point (dBc) -60 -70 1MHz -80 500kHz -90 -100 Load Power at Matched 50W Load -8 -6 -4 -2 0 2 4 6 8 Single-Tone Load Power (dBm) Figure 13. RECOMMENDED RS vs CAPACITIVE LOAD 100 9 6 3 0 -3 -6 -9 -12 -15 1 10 100 1000 0 20 40 60 CL = 100pF CL = 47pF Figure 14. FREQUENCY RESPONSE vs CAPACITIVE LOAD VIN 1/2 OPA2889 RS VOUT CL 1kW (1) Gain to Capacitive Load (dB) 750W NOTE: (1) 1kW is optional. 750W RS (W) 10 CL = 10pF CL = 22pF 1 Capacitive Load (pF) 80 100 120 140 160 180 Frequency (MHz) Figure 15. COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION RATIO vs FREQUENCY 80 -PSRR 70 60 50 40 30 20 10 0 1k 10k 100k 1M 10M 100M Frequency (Hz) 0.1 100 1k 10k 100 Figure 16. INPUT VOLTAGE AND CURRENT NOISE Voltage Noise (nV/ÖHz) Current Noise (pA/ÖHz) CMRR and PSRR (dB) +PSRR CMRR 10 Input Voltage Noise (8.4nV/ÖHz) 1 Input Current Noise (0.7pA/ÖHz) 100k Frequency (Hz) 1M 10M 100M Figure 17. Figure 18. Submit Documentation Feedback 9 OPA2889 www.ti.com SBOS373 – JUNE 2007 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 60 55 Quiescent Current (IQ) 1.00 0.95 3.0 TYPICAL DC DRIFT OVER TEMPERATURE 216 180 144 108 72 36 Supply Current (mA) Output Current (mA) 50 45 Output Current, Sourcing 40 35 30 25 20 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Output Current, Sinking 0.90 0.85 0.80 0.75 0.70 0.65 0.60 Input Offset Voltage (mV) 2.5 2.0 1.5 1.0 0.5 0 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Input Offset Voltage (VOS) Input Offset Current (IOS) Figure 19. LARGE-SIGNAL DISABLE/ENABLE RESPONSE 6 8 6 Figure 20. NONINVERTING OVERDRIVE RECOVERY RL = 100W G = +2V/V 4 3 2 Output Voltage Left Scale Input Voltage Right Scale 1 0 -1 -2 -3 -4 Time (10ns/div) VDIS (2V/div) 4 Output Voltage (V) 2 0 4 2 0 -2 -4 -6 -8 -2 3 2 1 0 -1 Time (5ns/div) Figure 21. CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 100 374W 1/2 OPA2889 Output Voltage (1V/div) Figure 22. OPEN-LOOP GAIN AND PHASE 120 Open-Loop Phase 0 -30 Open-Loop Gain -60 -90 -120 -150 -180 -210 100 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) Output Impedance (W) Open-Loop Gain (dB) 750W 80 60 40 20 0 -20 1 750W 0.1 0.01 0.001 1k 10k 100k 1M Frequency (Hz) 10M 100M Figure 23. Figure 24. 10 Submit Documentation Feedback Open-Loop Phase (°) 10 ZO 100 Input Voltage (V) Input Bias and Offset Current (nA) Input Bias Current (IB) OPA2889 www.ti.com SBOS373 – JUNE 2007 DISABLE FEEDTHROUGH -70 -75 Input-Referred COMMON-MODE AND DIFFERENTIAL INPUT IMPEDANCE 1G Common-Mode Input 100M Input Impedance (W) -80 Feedthrough (dB) -85 -90 -95 -100 -105 -110 -115 1 10 Frequency (MHz) 100 10M 1M 100k 10k 1k 100 Differential Input 1k 10k 100k Frequency (Hz) 1M 10M 100M Figure 25. Figure 26. Submit Documentation Feedback 11 OPA2889 www.ti.com SBOS373 – JUNE 2007 TYPICAL CHARACTERISTICS: VS = ±5V, Differential At TA = +25°C, Differential Gain = +2V/V, and RL = 200Ω, unless otherwise noted. See Figure 52 and Figure 53. DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE 3 GD = +1V/V 0 DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE 9 6 Normalized Gain (dB) -3 -6 GD = +5V/V -9 -12 -15 -18 RF = 750W RL = 200W See Figure 53 1 10 Frequency (MHz) 100 200 GD = +10V/V Normalized Gain (dB) GD = +2V/V 3 0 14VPP -3 -6 -9 RL = 200W GD = +2V/V See Figure 53 0 20 40 5VPP and 8VPP 60 80 100 120 140 Frequency (MHz) Figure 27. DIFFERENTIAL DISTORTION vs LOAD RESISTANCE -70 3rd Harmonic -30 -40 Figure 28. DIFFERENTIAL DISTORTION vs FREQUENCY VO = 4VPP RL = 200W GD = +2V/V Harmonic Distortion (dBc) Harmonic Distortion (dBc) -75 3rd Harmonic -50 -60 -70 -80 -80 2nd Harmonic -85 VO = 4VPP f = 1MHZ GD = +2V/V 100 Load Resistance (W) 2nd Harmonic -90 -100 -90 See Figure 53 -110 1k -95 See Figure 53 0.1 1 Frequency (MHz) 10 Figure 29. DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE -60 -65 -70 3rd Harmonic -75 -80 -85 -90 See Figure 53 0.1 1 Output Voltage (VPP) 10 RL = 200W f = 1MHz GD = +2V/V -70 -80 -90 -100 -110 -120 -130 -140 1 See Figure 52 10 Figure 30. DIFFERENTIAL DISTORTION vs FREQUENCY RL_DIFF = 1kW GD = -1V/V VO = 4VPP Harmonic Distortion (dBc) Harmonic Distortion (dBc) 3rd Harmonic 2nd Harmonic 2nd Harmonic 100 Frequency (kHz) 1000 Figure 31. Figure 32. 12 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 TYPICAL CHARACTERISTICS: VS = +5V At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 100Ω, unless otherwise noted. See Figure 51. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 0 G = +1V/V, RF = 0W 9 6 3 VO = 1VPP NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE Normalized Gain (dB) -3 Gain (dB) -6 G = +2V/V -9 G = +5V/V -12 G = +10V/V -15 VO = 0.1VPP -18 100k VO = 0.5VPP 0 VO = 2VPP -3 VO = 3VPP -6 -9 RL = 100W G = +2V/V 1 10 Frequency (MHz) 100 200 1M 10M Frequency (Hz) 100M 200M Figure 33. SMALL-SIGNAL PULSE RESPONSE 2.65 VO = 0.2VPP G = +2V/V 4.0 Figure 34. LARGE-SIGNAL PULSE RESPONSE VO = 2VPP G = +2V/V 2.60 2.55 2.50 2.45 2.40 2.35 Large Signal Output Voltage (V) Time (10ns/div) Small Signal Output Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 Time (10ns/div) Figure 35. RECOMMENDED RS vs CAPACITIVE LOAD 100 9 Figure 36. FREQUENCY RESPONSE vs CAPACITIVE LOAD Gain to Capacitive Load (dB) 6 CL = 10pF 3 CL = 100pF 0 -3 -6 -9 -12 VIN 1/2 OPA2889 750W NOTE: (1) 1kW is optional. CL = 22pF RS (W) 10 CL = 47pF RS VOUT CL 1kW (1) 750W 1 1 10 100 1000 Capacitive Load (pF) -15 0 20 40 60 80 100 120 140 Frequency (MHz) Figure 37. Figure 38. Submit Documentation Feedback 13 OPA2889 www.ti.com SBOS373 – JUNE 2007 TYPICAL CHARACTERISTICS: VS = +5V (continued) At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 100Ω, unless otherwise noted. See Figure 51. NONINVERTING OVERDRIVE RECOVERY 6.5 5.5 4.5 4.0 HARMONIC DISTORTION vs LOAD RESISTANCE -65 VO = 2VPP f = 1MHz G = +2V/V Harmonic Distortion (dBc) Output Voltage (V) 4.5 3.5 2.5 1.5 0.5 -0.5 -1.5 Time (10ns/div) Output Voltage Left Scale Input Voltage Right Scale 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -70 Input Voltage (V) -75 2nd Harmonic 3rd Harmonic -80 -85 100 Load Resistance (W) 1k Figure 39. HARMONIC DISTORTION vs FREQUENCY -30 -40 -50 -60 -70 -80 -90 -100 0.1 1 Frequency (MHz) 10 2nd Harmonic VO = 2VPP RL = 200W to VS/2 G = +2V/V -60 -65 -70 RL = 200W to VS/2 f = 1MHz G = +2V/V Figure 40. HARMONIC DISTORTION vs OUTPUT VOLTAGE Harmonic Distortion (dBc) 3rd Harmonic Harmonic Distortion (dBc) 2nd Harmonic -75 3rd Harmonic -80 -85 -90 0.1 1 Output Voltage Swing (VPP) 10 Figure 41. HARMONIC DISTORTION vs NONINVERTING GAIN -60 -65 2nd Harmonic -70 3rd Harmonic -75 -80 -85 -90 0.1 Gain (V/V) 10 Figure 42. TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -30 -40 5MHz Load Power of Matched 50W Load Harmonic Distortion (dBc) Spurious Point (dBc) -50 -60 -70 -80 -90 -100 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 Single-Tone Load Power (dBm) 1MHz 500kHz Figure 43. Figure 44. 14 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 TYPICAL CHARACTERISTICS: VS = +5V, Differential At TA = +25°C, Differential Gain = +2V/V, and RL = 200Ω, unless otherwise noted. See Figure 52. DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE 6 3 GD = +1V/V RF = 0W GD = +2V/V -3 -6 -9 -12 -15 1 RF = 750W RL = 200W 10 Frequency (MHz) 100 200 GD = +5V/V DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE 9 VO = 1VPP 6 RF = 750W RL = 200W GD = +2V/V Normalized Gain (dB) 0 Normalized Gain (dB) 3 VO = 4VPP 0 -3 -6 -9 0 10 20 30 40 50 60 70 80 90 100 110 Frequency (MHz) GD = +10V/V Figure 45. DIFFERENTIAL DISTORTION vs LOAD RESISTANCE -60 VO = 4VPP f = 1MHz GD = +2V/V -30 -40 Figure 46. DIFFERENTIAL DISTORTION vs FREQUENCY RL = 200W VO = 4VPP GD = +2V/V Harmonic Distortion (dBc) Harmonic Distortion (dBc) -65 3rd Harmonic -50 -60 -70 -80 -90 -100 -110 -70 3rd Harmonic -75 2nd Harmonic -80 2nd Harmonic -85 100 Load Resistance (W) 1k 0.1 1 Frequency (MHz) 10 Figure 47. DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE -60 -65 RL = 400W f = 1MHz GD = +2V/V Figure 48. Harmonic Distortion (dBc) 3rd Harmonic -70 -75 -80 -85 2nd Harmonic -90 -95 -100 0.1 1 Output Voltage (VPP) 10 Figure 49. Submit Documentation Feedback 15 OPA2889 www.ti.com SBOS373 – JUNE 2007 APPLICATIONS INFORMATION WIDEBAND VOLTAGE-FEEDBACK OPERATION The OPA2889 provides an exceptional combination of high output power capability in a dual, wideband, unity-gain stable, voltage-feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage-feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA2889 uses a new input stage that places the transconductance element between two input buffers, using the output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This configuration provides high slew rate (250V/μs) while consuming very low quiescent current (460μA/ch). This exceptional full-power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 8.4nV/√Hz input voltage noise for the OPA2889 is exceptionally low for this type of input stage. Figure 50 shows the dc-coupled, gain of +2V/V, dual power-supply circuit configuration used as the basis of the ±5V Electrical Characteristics and ±5V Typical Chararacteristics. This illustration is for one channel; the other channel is connected similarly. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 100Ω. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 50, the total effective load will be 100Ω || 1.5kΩ. The disable control line (MSOP-10 package only) is typically left open for normal amplifier operation. Two optional components are included in Figure 50. An additional resistor (350Ω) is included in series with the noninverting input. Combined with the 25Ω dc source resistance looking back towards the signal generator, this resistor gives an input bias current cancelling resistance that matches the 375Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power-supply decoupling capacitors to ground, a 0.1μF capacitor is included between the two power-supply pins. In practical printed circuit board (PCB) layouts, this optional-added capacitor typically improves the 2nd-harmonic distortion performance by 3dB to 6dB. +5V +VS 0.1mF 6.8mF + 50W Source 350W VD 50W DIS VI 1/2 OPA2889 VO 50W 50W Load 0.1mF RF 750W RG 750W + -VS -5V 6.8mF 0.1mF Figure 50. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit Figure 51 illustrates the ac-coupled, gain of +2V/V, single-supply circuit configuration used as the basis of the +5V Electrical Characteristics and +5V Typical Chararacteristics. Though not a rail-to-rail design, the OPA2889 requires minimal input and output voltage headroom compared to other very wideband voltage-feedback op amps. It delivers a 2.8VPP output swing on a single +5V supply with > 50MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 51 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 698Ω resistors). Separate bias networks would be required at each input. The input signal is then ac-coupled into the midpoint voltage bias. The input voltage can swing to within 1.1V of either supply pin, giving a 2VPP input signal range centered between the supply pins. The input impedance matching resistor (59Ω) used for testing is adjusted to give a 50Ω input load when the parallel combination of the biasing divider network is included. 16 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 +5V +VS DIFFERENTIAL OPERATION Figure 52 shows the inverting input differential configuration used as the basis for the ±5V and +5V Typical Characteristics. This circuit offers a combination of excellent distortion with low quiescent current. The other possibility is using the OPA2889 in a differential configuration as shown in Figure 53. This figure illustrates the differential noninverting input configuration which has the advantage of showing a high input impedance to any prior stage. +5V GD = 1/2 OPA2889 0.1mF 698W 0.1mF VI 59W 50W VD 698W + 6.8mF DIS 1/2 OPA2889 RF 750W VO 200W VS/2 RF RG RG 750W 0.1mF RG RF RL VOUT Figure 51. DC-Coupled, G = +2, Single-Supply, Specification and Test Circuit Again, an additional resistor (50Ω in this case) is included directly in series with the noninverting input. This minimum recommended value provides part of the dc source resistance matching for the noninverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies ( > 500MHz) using the input parasitic capacitance. The gain resistor (RG) is ac-coupled, giving the circuit a dc gain of +1, which puts the input dc bias voltage (2.5V) on the output as well. The output voltage can swing to within 1V of either supply pin while delivering > 40mA output current. VIN RG RF 1/2 OPA2889 -5V Figure 52. Differential Inverting Specification and Test Circuit +5V GD = 1 + 1/2 OPA2889 2RF RG RF RL RF VIN RG 1/2 OPA2889 -5V Figure 53. Differential Noninverting Specification and Test Circuit Submit Documentation Feedback 17 OPA2889 www.ti.com SBOS373 – JUNE 2007 HIGH-PERFORMANCE DAC TRANSIMPEDANCE AMPLIFIER High-frequency DDS Digital-to-Analog Converters (DACs) require a low distortion output amplifier to retain their SFDR performance into real-world loads. Figure 54 shows a single-ended output drive implementation. The diagram shows the signal output current(s) connected into the virtual ground summing junction(s) of the OPA2889, which is set up as a transimpedance stage or I-V converter. If the DAC requires that its outputs terminate to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the noninverting input of the OPA2889. The dc gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance (CD in Figure 54) produces a zero in the noise gain for the OPA2889 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to: 1 = 2pRFCF GBP 4pRFCD (1) WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers that include a disable pin is to wire multiple amplifier outputs together, then select one of several possible video inputs to source onto a single line. This simple wired-OR video multiplexer can be easily implemented using the OP2889IDGS (MSOP-10 package only), as shown in Figure 55. 50W 1/2 OPA2889 VO = IO RF High-Speed DAC RF1 CF1 IO CD1 RF2 CF2 -IO CD2 1/2 OPA2889 50W -VO = -IO RF which gives a cutoff frequency f–3dB of approximately: f-3dB = GBP 2pRFCD GBP ® Gain Bandwidth Product (Hz) for the OPA2889 (2) Figure 54. DAC Transimpedance Amplifier +5V VDIS 2kW +5V 146W Video 1 75W 340W 1/2 OPA2889 DISA -5V 402W 82.5W 75W Cable 340W +5V 402W 82.5W 1/2 OPA2889 DISB RG-59 75W Load 146W Video 2 75W 2kW -5V Figure 55. 2-Channel Video Multiplexer (SO-14 package only) 18 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this point. The make-before-break disable characteristic of the OPA2889 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that shown in Figure 55. Because both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor are slightly increased to get a signal gain of +1V/V at the matched load and provide a 75Ω output impedance to the cable. The video multiplexer connection (see Figure 55) also ensures that the maximum differential voltage across the inputs of the unselected channel does not exceed the rated ±1.2V maximum for standard video signal levels. See the Disable Operation section for the turn-on and turn-off switching glitches using a 0V input for a single channel is typically less than ±50mV. Where two outputs are switched (see Figure 55), the output line is always under the control of one amplifier or the other as a result of the make-before-break disable timing. In this case, the switching glitches for two 0V inputs drops to < 20mV. HIGH-SPEED DELAY CIRCUIT The OPA2889 makes an ideal amplifier for a variety of active filter designs. Figure 56 illustrates a circuit that uses the two amplifiers within the dual OPA2889 to design a 2-stage analog delay circuit. For simplicity, the circuit uses a dual-supply (±5V) operation, but it can also be modified to operate on a signal supply. The input to the first filter stage is driven by the OPA890 as a gain of +2V/V to isolate the signal input from the filter network. Each of the two filter stages is a 1st-order filter with a voltage gain of +1V/V. The delay time through one filter is given by Equation 3. tGR0 = 2RC (3) For a more accurate analysis of the circuit, consider the group delay for the amplifiers. For example, in the case of the OPA2889, the group delay in the bandwidth from 1MHz to 100MHz is approximately 1.0ns. To account for this delay, modify the transfer function, which now comes out to be: tGR = 2 (2RC + TD) (4) with TD = (1/360) × (dφ/df) = delay of the op amp itself. The values of resistors RF and RG should be equal and low to avoid parasitic effects. If the all-pass filter is designed for very low delay times, include parasitic board capacitances to calculate the correct delay time. Simulating this application using the PSPICE model of the OPA2889 allows this design to be tuned to the desired performance. VIN OPA890 C 1/2 OPA2889 R 750W R C 1/2 OPA2889 VOUT 750W RG 402W RF 402W RG 402W RF 402W Figure 56. 2-Stage, All-Pass Network Submit Documentation Feedback 19 OPA2889 www.ti.com SBOS373 – JUNE 2007 DIFFERENTIAL RECEIVER/DRIVER A very versatile application for a dual operational amplifier is the differential amplifier configuration shown in Figure 57. With both amplifiers of the OPA2889 connected for noninverting operation, the circuit provides a high input impedance whereas the gain can easily be set by just one resistor, RG. When operated in low gains, the output swing may be limited as a result of the common-mode input swing limits of the amplifier itself. An interesting modification of this circuit is to place a capacitor in series with RG. Now the dc gain for each side is reduced to +1V/V, whereas the ac gain still follows the standard transfer function of G = 1 + 2RF/RG. This might be advantageous for applications processing only a frequency band that excludes dc or very low frequencies. An input dc voltage resulting from input bias currents is not amplified by the ac gain and can be kept low. This circuit can be used as a differential line receiver, driver, or as an interface to a differential input ADC. 50W VI The frequency response for a 2MHz Butterworth filter is shown in Figure 58. One advantage for using this type of filter is the independent setting of ωo and Q. Q can be easily adjusted by changing the R3A, B resistors without affecting ωo. 3 0 Gain (dB) -3 -6 -9 -12 10k 100k Frequency (Hz) 1M 10M Figure 58. Multiple Feedback Filter Frequency Response 1/2 OPA2889 RF 750W VDIFF = 1 + 2RF RG VI - (-VI) RO LOW POWER, DC-COUPLED, SINGLE-TO-DIFFERENTIAL DRIVER FOR ≤100kHz INPUT In systems where the input is differential (see front-page figure), the OPA2889 can be used in the inverting configuration with an additional dc bias applied to its positive input so as to keep the input to the ADS8472 within its rated operating voltage range. The dc bias can be derived from the REF3220 or the REF3240 reference voltage ICs. The input configuration shown on the front page of the data sheet is capable of delivering better than 100dB SNR and –100dBc THD at an input frequency of 200kHz. In case band-pass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the band-pass filter is small, so as to minimize the distortion introduced by the filter. In such cases, the gain of the circuit shown on the front page of the data sheet can be increased to keep the input to the ADS8472 large in order to keep the SNR of the system high. Note that the gain of the system from the positive input to the output of the OPA2889 in such a configuration is a function of the ac signal gain. A resistor divider can be used to scale the output of the REF3220 or REF3240 to reduce the voltage at the dc input to OPA2889 to keep the voltage at the input of the converter within its rated operating range. RG RF 750W 50W -VI 1/2 OPA2889 RO Figure 57. High-Speed Differential Receiver SINGLE-SUPPLY MFB DIFFERENTIAL ACTIVE FILTER: 2MHz BUTTERWORTH CONFIGURATION The active filter circuit illustrated in Figure 59 can be easily implemented using the OPA2889. In this configuration, each amplifier of the OPA2889 operates as an integrator. For this reason, this type of application is also called an infinite gain filter implementation. A Butterworth filter can be implemented using the following component ratios: 1 fO = 2´p´R´C R1 = R2 = 0.65 ´ R R3 = 0.375 ´ R C1 = C C2 = 2 ´ C 20 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 +12V 6kW 50W 1/2 OPA2889 1000pF R1A 402W 6kW R3A 232W R2A 402W C2 257pF R2B 402W R3B 232W C1B 129pF C1A 129pF VCM VIN VOUT R1B 402W 50W VCM 1/2 OPA2889 Figure 59. Single-Supply, MFB Active Filter, 2MHz LP Butterworth DESIGN-IN TOOLS DEMONSTRATION FIXTURES Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA2889 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user’s guide. The summary information for these fixtures is shown in Table 1. Table 1. Demonstration Fixtures by Package PRODUCT OPA2889ID OPA2889IDGS PACKAGE SO-8 MSOP-10 ORDERING NUMBER DEM-OPA-SO-2A DEM-OPA-MSOP-2B LITERATURE NUMBER SBOU003A SBOU040 MACROMODELS Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This principle is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2889 is available through the Texas Instruments web page (www.ti.com). This model does a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. It does not do as well in predicting the harmonic distortion or dG/dP characteristics. This model does not attempt to distinguish between the package types in their small-signal ac performance. The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA2889 product folder. Submit Documentation Feedback 21 OPA2889 www.ti.com SBOS373 – JUNE 2007 OPERATING RECOMMENDATIONS OPTIMIZING RESISTOR VALUES Because the OPA2889 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity-gain follower application, the feedback connection should be made with a direct short. Usually, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network presents additional output loading which can degrade the harmonic distortion performance of the OPA2889. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor can cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (see Figure 50) to be less than approximately 400Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 400Ω keeps this pole above 160MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This increase in resistor size is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. approach the predicted value of (GBP/NG). At a gain of +10, the 8MHz bandwidth shown in the Electrical Characteristics agrees closely with that predicted using the simple formula and the typical GBP of 75MHz. The frequency response in a gain of +2V/V may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5V/V. One way to modify the response without affecting the +2V/V signal gain, is to add a 750Ω resistor across the two inputs, as shown in the circuit of Figure 50. A similar technique may be used to reduce peaking in unity-gain (voltage follower) applications. For example, by using a 750Ω feedback resistor along with a 750Ω resistor across the two op amp inputs, the voltage follower response is similar to the gain of +2V/V response of Figure 51. Reducing the value of the resistor across the op amp inputs further limits the frequency response due to increased noise gain. The OPA2889 exhibits minimal bandwidth reduction going to single-supply (+5V) operation as compared with ±5V. This behavior occurs because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. INVERTING AMPLIFIER OPERATION The OPA2889 is a general-purpose, wideband, voltage-feedback op amp; therefore, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. See Figure 60 for a typical inverting configuration where the I/O impedances and signal gain from Figure 50 are retained in an inverting circuit configuration. In the inverting configuration, three key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long PCB trace, or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This consideration is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of –2V/V, setting RG to 50Ω for input matching eliminates the need for RM but requires a 100Ω feedback resistor. This approach has the interesting advantage that the noise gain becomes equal to 2V/V for a 50Ω source impedance—the same as the noninverting circuits BANDWIDTH vs GAIN: NONINVERTING OPERATION Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain increases. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the Electrical Characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) predicts the closed-loop bandwidth. In practice, this principle only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most amplifiers exhibit a more complex response with lower phase margin. The OPA2889 is compensated to give a slightly peaked response in a noninverting gain of 2V/V (see Figure 50). This compensation results in a typical gain of +2V/V bandwidth of 60MHz, far exceeding that predicted by dividing the 75MHz GBP by 2. Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely 22 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 considered in Figure 60 The amplifier output, however, now sees the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values (see Figure 60), and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. +5V Combining this resistance in parallel with the feedback resistor gives the RB = 261Ω used in this example. To reduce the additional high-frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB < 350Ω, the capacitor is not required because the total noise contribution of all other terms will be less than that of the op amp input noise voltage. As a minimum, the OPA2889 requires an RB value of 50Ω to damp out parasitic-induced peaking—a direct short to ground on the noninverting input runs the risk of a very high-frequency instability in the input stage. + 0.1mF 0.1mF RO 50W 50W Load 6.8mF DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier such as the OPA2889 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the open-loop output resistance of the amplifier is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This solution does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The 5 Typical Chararacteristics show the recommended RS versus capacitive load (see Figure 15 and Figure 16) and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2889. Long PCB traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2889 output pin (see the Board Layout Guidelines section). RB 261W 1/2 OPA2889 VO 50W Source VI RG 375W RF 750W VO = -2 VI RM 57.6W 0.1mF + 6.8mF -5V Figure 60. Gain of –2V/V Example Circuit The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 60, the RM value combined in parallel with the external 50Ω source impedance yields an effective driving impedance of 50Ω || 57.6Ω = 26.7Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resulting NG is 2.86V/V for Figure 60, as opposed to only 2V/V if RM could be eliminated as discussed above. Therefore, the bandwidth is slightly lower for the gain of –2V/V circuit of Figure 60 than for the gain of +2V/V circuit of Figure 50. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input (RB). If this resistor is set equal to the total dc resistance looking out of the inverting node, the output dc error, as a result of the input bias currents, is reduced to (Input Offset Current) × RF. If the 50Ω source impedance is dc-coupled in Figure 60, the total resistance to ground on the inverting input is 402Ω. Submit Documentation Feedback 23 OPA2889 www.ti.com SBOS373 – JUNE 2007 DISTORTION PERFORMANCE The OPA2889 provides good distortion performance into a 200Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the noninverting configuration (see Figure 50), this total is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply-decoupling capacitor (0.1μF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). Operating differentially also lowers 2nd-harmonic distortion terms (see the plot on the front page). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The output stage used in the OPA2889 actually holds the difference between fundamental power and the 2ndand 3rd-harmonic powers relatively constant with increasing output power until very large output swings are required ( > 4VPP). This result also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 1MHz, with 4dBm/tone into a matched 50Ω load (that is, 1VPP for each tone at the load, which requires 4VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show –73dBc difference between the test tone powers and the 3rd-order intermodulation spurious powers. This performance is exceptional for an amplifier with only 4.6mW of internal power dissipation. conditions. Figure 61 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI 1/2 OPA2889 IBN RS EO ERS Ö4kTRS RF Ö4kTRF 4kT RG RG IBI 4kT = 1.6E - 20J at +290°K Figure 61. Op Amp Noise Analysis Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 5 shows the general form for the output noise voltage using the terms shown in Figure 61. EO = [E 2 NI + (IBNRS) + 4kTRS ]NG + (IBIRF) + 4kTRFNG 2 2 2 (5) Dividing this expression by the noise gain (NG = (1 + RF/RG)) gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 6. EN = E 2 NI + (IBNRS) + 4kTRS + 2 ( IBIRF NG )2 + 4kTRF NG (6) NOISE PERFORMANCE High slew rate, unity-gain stable, voltage-feedback op amps usually achieve the slew rate at the expense of a higher input noise voltage. However, the 8.4nV/√Hz input voltage noise for the OPA2889 is much lower than that of comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating Evaluating these two equations for the OPA2889 circuit and component values (see Figure 50) gives a total output spot noise voltage of 18.2nV/√Hz and a total equivalent input spot noise voltage of 9.1nV/√Hz. This total includes the noise added by the bias current cancellation resistor (350Ω) on the noninverting input. This total input-referred spot noise voltage is slightly higher than the 8nV/√Hz specification for the op amp voltage noise alone. This result is the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 400Ω. Keeping both (RF || RG) and the noninverting input source impedance less than 400Ω satisfies both noise and frequency response flatness 24 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 considerations. Because the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 60 is not required. +5V Power-supply decoupling not shown. 0.1mF 250W 1/2 OPA2889 VO DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. The power-supply current trim for the OPA2889 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively low 0.75μA input bias current, the close matching between them may be used to reduce the output dc error caused by this current. The total output offset voltage may be reduced by matching the dc source resistances appearing at the two inputs. This matching reduces the output dc error resulting from the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 50, and using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: ±(NG ´ VOS(MAX)) ± (RF ´ IOS(MAX)) = ±(2 ´ 5mV) ± (750W ´ 0.75mA) = ±10.6mV with -(NG = noninverting signal gain) A fine-scale output offset null, or dc operating point adjustment, is often required. Numerous techniques are available for introducing dc offset control into an op amp circuit. Most of these techniques eventually reduce to adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input may be considered. However, the dc offset voltage on the summing junction sets up a dc current back into the source that must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a dc-coupled inverting amplifier, Figure 62 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the dc offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This technique ensures that the adjustment circuit has minimal effect on the loop gain and thus, the frequency response. -5V +5V VI 20kW 10kW 0.1mF 5kW VO VI -5V RF RG ±200mV Output Adjustment RG 375W 5kW RF 750W =- = -2 Figure 62. DC-Coupled, Inverting Gain of –2V/V, with Offset Adjustment DISABLE OPERATION (MSOP-10 Package Only) The OPA2889IDGS provides an optional disable feature that can be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA2889IDGS operates normally. To disable, the control pin must be asserted LOW. Figure 63 shows a simplified internal circuit for the disable control feature. +VS 100kW Q1 150kW VDIS IS Control 4MW -VS Figure 63. Simplified Disable Control Circuit Submit Documentation Feedback 25 OPA2889 www.ti.com SBOS373 – JUNE 2007 In normal operation, base current to Q1 is provided through the 4MΩ resistor, while the emitter current through the 100kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in the Q1 emitter. As VDIS is pulled LOW, additional current is pulled through the 100kΩ resistor, eventually turning on those two diodes (≈18μA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This current shuts off the collector current out of Q1, turning the amplifier off. The supply currents in the disable mode are only those required to operate the circuit of Figure 63. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high-impedance state. If the OPA2889 is operating at a gain of +1V/V, the device shows a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1V/V, the total feedback network resistance (RF + RG) appears as the impedance looking back into the output, but the circuit still shows very high forward and reverse isolation. If configured as an inverting amplifier, the input and output are connected through the feedback network resistance (RF + RG) and the isolation will be very poor as a result. THERMAL ANALYSIS Maximum desired junction temperature sets the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +150°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load; for a grounded resistive load, PDL is at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 × RL), where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2889ID (SO-8 package) in the circuit of Figure 50 operating at the maximum specified ambient temperature of +85°C and with both outputs driving a grounded 75Ω load to +2.5V. PD = 10V ´ 2.5mA + 2[5 /(4 ´ (75W || 1.5kW))] = 200mW 2 Maximum TJ = +85°C + (200mW ´ 125°C/W) = +110°C This absolute worst-case condition does not exceed the specified maximum junction temperature. Actual PDL is normally less than that considered here. Carefully consider maximum TJ in your application. 26 Submit Documentation Feedback OPA2889 www.ti.com SBOS373 – JUNE 2007 BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA2889 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1μF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1μF) across the two power supplies (for bipolar operation) improves 2nd-harmonic distortion performance. Larger (2.2μF to 6.8μF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the printed circuit board (PCB). c) Careful selection and placement of external components preserves the high-frequency performance of the OPA2889. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB traces as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 750Ω feedback used in the Electrical Characteristics is a good starting point for design. Note that a 0Ω feedback resistor is suggested for the unity-gain follower application. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plots of Figure 15 and Figure 16. Low parasitic capacitive loads (< 3pF) may not need an RS because the OPA2889 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin; see Figure 24). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA2889 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. e) Socketing a high-speed part like the OPA2889 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2889 onto the board. Submit Documentation Feedback 27 OPA2889 www.ti.com SBOS373 – JUNE 2007 INPUT AND ESD PROTECTION The OPA2889 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 64. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA2889), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +VCC External Pin Internal Circuitry -VCC Figure 64. Internal ESD Protection 28 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2007 PACKAGING INFORMATION Orderable Device OPA2889ID OPA2889IDG4 OPA2889IDGSR OPA2889IDGSRG4 OPA2889IDGST OPA2889IDGSTG4 OPA2889IDR OPA2889IDRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC MSOP MSOP MSOP MSOP SOIC SOIC Package Drawing D D DGS DGS DGS DGS D D Pins Package Eco Plan (2) Qty 8 8 10 10 10 10 8 8 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jul-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jul-2007 Device Package Pins Site Reel Diameter (mm) 330 178 330 Reel Width (mm) 12 12 12 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 12 8 8 W Pin1 (mm) Quadrant 12 12 12 Q1 Q1 Q1 OPA2889IDGSR OPA2889IDGST OPA2889IDR DGS DGS D 10 10 8 MLA MLA MLA 5.2 5.3 6.4 3.3 3.4 5.2 1.6 1.4 2.1 TAPE AND REEL BOX INFORMATION Device OPA2889IDGSR OPA2889IDGST OPA2889IDR Package DGS DGS D Pins 10 10 8 Site MLA MLA MLA Length (mm) 346.0 0.0 346.0 Width (mm) 346.0 0.0 346.0 Height (mm) 29.0 0.0 29.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jul-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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