OPA992, OPA2992, OPA4992
SBOSA10D – JUNE 2021 – REVISED AUGUST 2022
OPAx992 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
1 Features
3 Description
•
•
•
The OPAx992 family (OPA992, OPA2992, and
OPA4992) is a family of high voltage (40 V) general
purpose operational amplifiers. These devices offer
excellent DC precision and AC performance, including
rail-to-rail input/output, low offset (±210 µV, typ), low
offset drift (±0.25 µV/°C, typ) and low noise (7 nV/√Hz
at 1 kHz, 4.4 nV/√Hz at 10 kHz).
•
•
•
•
•
•
•
•
•
Low offset voltage: ±210 µV
Low offset voltage drift: ±0.25 µV/°C
Low noise: 7 nV/√Hz at 1 kHz, 4.4 nV/√Hz
broadband
High common-mode rejection: 115 dB
Low bias current: ±10 pA
Rail-to-rail input and output
MUX-friendly/comparator inputs
– Amplifier operates with differential inputs up to
supply rail
– Amplifier can be used in open-loop or as
comparator
Wide bandwidth: 10.6-MHz GBW, unity-gain stable
High slew rate: 32 V/µs
Low quiescent current: 2.4 mA per amplifier
Wide supply: ±1.35 V to ±20 V, 2.7 V to 40 V
Robust EMIRR performance
•
•
•
•
•
The OPAx992 family of op amps is available in microsize packages (such as WSON), as well as standard
packages (such as SOT-23, SOIC, and TSSOP), and
is specified from –40°C to 125°C.
Device Information
2 Applications
•
•
•
•
Features such as differential and common-mode input
voltage ranges to the supply rails, high short-circuit
current (±65 mA), and high slew rate (32 V/µs) make
the OPAx992 a flexible, robust, and high-performance
op amp for high-voltage industrial applications.
PART NUMBER(1)
Multiplexed data-acquisition systems
Test and measurement equipment
Motor drive: power stage and control modules
Power delivery: UPS, server, and merchant
network power
ADC driver and reference buffer amplifier
Programmable logic controllers
Analog input and output modules
High-side and low-side current sensing
High precision comparator
PACKAGE
OPA992
OPA2992
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (8)
2.90 mm × 1.60 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
2.00 mm × 2.00 mm
X2QFN
OPA4992
(1)
(2)
(10)(2)
1.50 mm × 2.00 mm
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
This package is preview only.
OPAx992
+
Vshunt
System
Load
BODY SIZE (NOM)
Rshunt
MCU
-
+
-
+
Vo
-
Iload
Vbus
+
–
Vbus
Iload
-
Rshunt
+
–
GND
OPAx992
+
Vshunt
GND
+
-
System
Load
MCU
+
Vo
-
GND
GND
Low-Side Current Sense
GND
GND
High-Side Current Sense
OPAx992 in Current-Sensing Applications
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA992, OPA2992, OPA4992
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SBOSA10D – JUNE 2021 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information for Single Channel..................... 7
6.5 Thermal Information for Dual Channel........................8
6.6 Thermal Information for Quad Channel...................... 8
6.7 Electrical Characteristics.............................................9
6.8 Typical Characteristics.............................................. 12
7 Detailed Description......................................................20
7.1 Overview................................................................... 20
7.2 Functional Block Diagram......................................... 20
7.3 Feature Description...................................................21
7.4 Device Functional Modes..........................................30
8 Application and Implementation.................................. 31
8.1 Application Information............................................. 31
8.2 Typical Applications.................................................. 31
9 Power Supply Recommendations................................34
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 35
11 Device and Documentation Support..........................36
11.1 Device Support........................................................36
11.2 Documentation Support.......................................... 36
11.3 Receiving Notification of Documentation Updates.. 36
11.4 Support Resources................................................. 36
11.5 Trademarks............................................................. 36
11.6 Electrostatic Discharge Caution.............................. 36
11.7 Glossary.................................................................. 37
12 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2022) to Revision D (August 2022)
Page
• Added X2QFN (10) to Description with preview status.......................................................................................1
• Added X2QFN (RUG) package to Pin Configuration and Functions with preview status...................................3
Changes from Revision B (December 2021) to Revision C (March 2022)
Page
• Adjusted the typical CMRR value for VS = 2.7 – 40 V, (V+) – 1 < VCM < V+ (NMOS pair) from "90 dB" to "79
dB" in the Electrical Characteristics section........................................................................................................9
• Adjusted the AOL test condition from "VS = 40 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V" to "VS = 40
V, VCM = VS / 2, (V–) + 0.12 V < VO < (V+) – 0.12 V" in the Electrical Characteristics section..........................9
• Adjusted the typical tON Amplifier Enable Time value from "15 µs" to "5 µs" in the Electrical
Characteristics section........................................................................................................................................9
• Adjusted the typical SHDN pin input bias current value for VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V
from "150 nA" to "400 nA" in the Electrical Characteristics section.................................................................... 9
• Removed "Open-Loop Gain and Phase vs Frequency" figure in Typical Characteristics section.................... 12
Changes from Revision A (October 2021) to Revision B (December 2021)
Page
• Added PSRR specification for OPA4992 release in Electrical Characteristics section.......................................9
• Added clarification to VS = 2.7 V to 40 V PSRR specification noting that specification is for all channel
variants............................................................................................................................................................... 9
• Changed y-axis from linear scale to logarithmic scale in "Input Voltage Noise Spectral Density vs Frequency"
figure in Typical Characteristics section............................................................................................................12
• Corrected typo in Shutdown of Feature Description section from "...specified 10-kΩ load to midsupply (VS /
2)" to "...specified 10-kΩ load to V-"..................................................................................................................29
Changes from Revision * (June 2021) to Revision A (October 2021)
Page
• Changed the device status from Advance Information to Production Data ....................................................... 1
2
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SBOSA10D – JUNE 2021 – REVISED AUGUST 2022
5 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
5
V+
4
OUT
Not to scale
Figure 5-1. OPA992 DBV Package
5-Pin SOT-23
(Top View)
Figure 5-2. OPA992 DCK Package
5-Pin SC70
(Top View)
Table 5-1. Pin Functions: OPA992
PIN
NAME
SOT-23
SC70
IN+
3
1
IN–
4
OUT
1
V+
V–
I/O
DESCRIPTION
I
Noninverting input
3
I
Inverting input
4
O
Output
5
5
—
Positive (highest) power supply
2
2
—
Negative (lowest) power supply
OUT
1
6
V+
V–
2
5
SHDN
+IN
3
4
–IN
Not to scale
Figure 5-3. OPA992S DBV Package
6-Pin SOT-23
(Top View)
Table 5-2. Pin Functions: OPA992S
PIN
NAME
NO.
I/O
DESCRIPTION
+IN
3
I
Noninverting input
–IN
4
I
Inverting input
OUT
1
O
Output
SHDN
5
I
Shutdown: low = amplifier enabled, high = amplifier disabled
V+
6
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
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OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Figure 5-4. OPA2992 D, DDF, PW, and DGK
Package
8-Pin SOIC, SOT-23, TSSOP, and VSSOP
(Top View)
Not to scale
A.
Connect thermal pad to V–. See Section 7.3.10 for more
information.
Figure 5-5. OPA2992 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
(Top View)
Table 5-3. Pin Functions: OPA2992
PIN
NAME
4
NO.
I/O
DESCRIPTION
IN1+
3
I
Noninverting input, channel 1
IN1–
2
I
Inverting input, channel 1
IN2+
5
I
Noninverting input, channel 2
IN2–
6
I
Inverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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IN1+
SBOSA10D – JUNE 2021 – REVISED AUGUST 2022
1
9
IN1–
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
5
10
V–
IN2–
Not to scale
A.
RUG package is preview only.
Figure 5-6. OPA2992S RUG Package
10-Pin X2QFN (A)
(Top View)
Table 5-4. Pin Functions: OPA2992S
PIN
NAME
NO.
I/O
DESCRIPTION
IN1+
10
I
Noninverting input, channel 1
IN1–
9
I
Inverting input, channel 1
IN2+
4
I
Noninverting input, channel 2
IN2–
5
I
Inverting input, channel 2
OUT1
8
O
Output, channel 1
OUT2
6
O
Output, channel 2
SHDN1
2
I
Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See
Shutdown section for more information.
SHDN2
3
I
Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See
Shutdown section for more information.
V+
7
—
Positive (highest) power supply
V–
1
—
Negative (lowest) power supply
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OUT1
1
14
OUT4
IN1±
2
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
Not to scale
Figure 5-7. OPA4992 D and PW Package
14-Pin SOIC and TSSOP
(Top View)
Table 5-5. Pin Functions: OPA4992
PIN
NAME
6
NO.
I/O
DESCRIPTION
IN1+
3
I
Noninverting input, channel 1
IN1–
2
I
Inverting input, channel 1
IN2+
5
I
Noninverting input, channel 2
IN2–
6
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
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SBOSA10D – JUNE 2021 – REVISED AUGUST 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX
0
42
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode
voltage(3)
Differential voltage(3)
Signal input pins
VS + 0.2
Current(3)
Output short-circuit(2)
10
V–
(V–) + 20
V
150
°C
150
°C
150
°C
–55
Junction temperature, TJ
Storage temperature, Tstg
(3)
(4)
mA
Continuous
Operating ambient temperature, TA
(2)
V
–10
Shutdown pin voltage(4)
(1)
UNIT
–65
Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device.
These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside
the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating
Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance.
Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause
excessive heating and eventual destruction.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Cannot exceed V+.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2500
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
2.7
40
V
(V–)
(V+)
V
High level input voltage at shutdown pin (amplifier disabled)
1.1
(V–) + 20 (1)
V
VIL
Low level input voltage at shutdown pin (amplifier enabled)
(V–)
0.2
V
TA
Specified temperature
–40
125
°C
VS
Supply voltage, (V+) – (V–)
VI
Common mode voltage range
VIH
(1)
UNIT
Cannot exceed V+.
6.4 Thermal Information for Single Channel
OPA992, OPA992S
DBV
(SOT-23)
THERMAL METRIC(1)
DCK
(SC70)
5 PINS
6 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
185.4
166.9
198.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
83.9
83.9
94.1
°C/W
RθJB
Junction-to-board thermal resistance
52.5
47.1
45.3
°C/W
ψJT
Junction-to-top characterization parameter
25.4
25.9
16.9
°C/W
ψJB
Junction-to-board characterization parameter
52.1
47.0
45.0
°C/W
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6.4 Thermal Information for Single Channel (continued)
OPA992, OPA992S
DBV
(SOT-23)
THERMAL METRIC(1)
RθJC(bot)
(1)
Junction-to-case (bottom) thermal resistance
DCK
(SC70)
5 PINS
6 PINS
5 PINS
N/A
N/A
N/A
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information for Dual Channel
OPA2992
THERMAL METRIC(1)
D
(SOIC)
DDF
(SOT-23)
DGK
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
Unit
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal
resistance
131.0
149.6
174.2
74.8
183.4
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
73.0
85.3
65.9
93.6
72.4
°C/W
RθJB
Junction-to-board thermal
resistance
74.5
68.6
95.9
42.1
114.0
°C/W
ψJT
Junction-to-top characterization
parameter
25.0
7.9
11.0
3.8
12.1
°C/W
ψJB
Junction-to-board
characterization parameter
73.8
68.4
94.4
41.9
112.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
17.0
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
OPA4992
THERMAL METRIC(1)
PW
(TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
99.0
118.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.1
47.0
°C/W
RθJB
Junction-to-board thermal resistance
54.8
61.9
°C/W
ψJT
Junction-to-top characterization parameter
16.7
5.5
°C/W
ψJB
Junction-to-board characterization parameter
54.4
61.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
8
D
(SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VCM = V–
dVOS/dT
Input offset voltage drift
VCM = V–
±0.21
TA = –40°C to 125°C
TA = –40°C to 125°C
±0.25
OPA992, OPA2992, VCM =
V–, VS = 5 V to 40 V
PSRR
OPA4992, VCM = V–, VS = 5
Input offset voltage versus
V to 40 V
power supply
OPA992, OPA2992,
OPA4992, VCM = V–, VS =
2.7 V to 40 V(1)
±1
±1.2
TA = –40°C to 125°C
DC channel separation
mV
µV/℃
±0.2
±1.3
±0.4
±1.8
±0.8
±7
μV/V
0.4
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±10
pA
IOS
Input offset current
±10
pA
NOISE
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
eN
Input voltage noise density
iN
Input current noise density f = 1 kHz
f = 1 kHz
2.77
μVPP
0.49
µVRMS
7
f = 10 kHz
nV/√Hz
4.4
60
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage
range
Common-mode rejection
ratio
(V–)
(V+)
VS = 40 V, V– < VCM < (V+) –
2 V (PMOS pair)
100
115
VS = 5 V, V– < VCM < (V+) – 2
V (PMOS pair)(1)
75
98
VS = 2.7 V, V– < VCM < (V+) –
TA = –40°C to 125°C
2 V (PMOS pair)
90
VS = 2.7 – 40 V, (V+) – 1 V <
VCM < V+ (NMOS pair)
79
V
dB
See Offset Voltage vs Common-Mode
Voltage (Transition Region)
(V+) – 2 V < VCM < (V+) – 1 V
INPUT IMPEDANCE
ZID
Differential
ZICM
Common-mode
100 || 9
MΩ || pF
6 || 1
TΩ || pF
OPEN-LOOP GAIN
VS = 40 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –
0.1 V
AOL
Open-loop voltage gain
VS = 40 V, VCM = VS / 2,
(V–) + 0.12 V < VO < (V+) –
0.12 V
VS = 5 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –
0.1 V(1)
VS = 2.7 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –
0.1 V(1)
120
TA = –40°C to 125°C
142
104
TA = –40°C to 125°C
125
dB
125
90
TA = –40°C to 125°C
142
105
105
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
VS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF(5)
To 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF
tS
Settling time
MHz
32
V/μs
0.65
To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF
0.3
To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF
0.86
To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF
0.44
Phase margin
G = +1, RL = 10 kΩ, CL = 20 pF
Overload recovery time
VIN × gain > VS
μs
64
°
170
ns
0.00005%
VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
THD+N
10.6
126
dB
0.0032%
Total harmonic distortion +
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω
noise
90
dB
0.00032%
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω
110
dB
OUTPUT
VS = 40 V, RL = no load
Voltage output swing from
rail
Positive and negative
rail headroom
7
VS = 40 V, RL = 10 kΩ
48
60
VS = 40 V, RL = 2 kΩ
220
300
VS = 2.7 V, RL = no load
0.5
VS = 2.7 V, RL = 10 kΩ
5
20
VS = 2.7 V, RL = 2 kΩ
20
50
±65(3)
mV
ISC
Short-circuit current
CLOAD
Capacitive load drive
See Phase Margin vs Capacitive Load
pF
ZO
Open-loop output
impedance
See Open-Loop Output Impedance vs
Frequency
Ω
IO = 0 A
mA
POWER SUPPLY
Quiescent current per
amplifier
IQ
OPA2992, OPA4992, IO = 0 A
OPA992, IO = 0 A
2.4
TA = –40°C to 125°C
2.8
2.84
2.48
TA = –40°C to 125°C
2.92
mA
2.98
SHUTDOWN
IQSD
Quiescent current per
amplifier
VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– + 2 V
ZSHDN
Output impedance during
shutdown
VS = 2.7 V to 40 V, amplifier disabled
VIH
For valid input high, the SHDN pin voltage should be greater
Logic high threshold
than the maximum threshold but less than or equal to V+ or
voltage (amplifier disabled)
(V–) + 20 V, whichever is less
VIL
Logic low threshold
For valid input low, the SHDN pin voltage should be less than
voltage (amplifier enabled) the minimum threshold but greater than or equal to V–
tON
Amplifier enable time (from VS = ±20 V, G = +1, VCM = VS / 2, RL = 10 kΩ connected to
shutdown) (2)
V–
5
µs
tOFF
Amplifier disable time (2)
VS = ±20 V, G = +1, VCM = VS / 2, RL = 10 kΩ connected to
V–
3
µs
SHDN pin input bias
current (per pin)
VS = 2.7 V to 40 V, (V–) + 20 V (4) ≥ SHDN ≥ (V–) + 0.9 V
500
VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V
400
(1)
(2)
10
40
45
10 || 2
GΩ || pF
(V–) + 1.1 V
(V–) + 0.2
V
µA
V
V
nA
Specified by characterization only.
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches 10% (disable) or 90% (enable) of its final value.
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(3)
(4)
(5)
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SBOSA10D – JUNE 2021 – REVISED AUGUST 2022
At high supply voltage, placing the OPAx992 in a sudden short to mid-supply or ground will lead to rapid thermal shutdown. Output
current greater than ISC can be achieved if rapid thermal shutdown is avoided as per Output Voltage Swing vs Output Current.
SHDN pin should not exceed V+ or (V-) + 20 V, whichever is less.
See Slew Rate vs Input Step Voltage for more information.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
30
45
40
25
30
Population (%)
Population (%)
35
25
20
15
20
15
10
10
5
5
0
-675
-525
-375
-225 -75
75
225
Offset Voltage (µV)
375
525
0
675
0.1
0.2
Distribution from 74 amplifiers, TA = 25°C
400
1600
300
1200
Offset Voltage (µV)
Offset Voltage (µV)
2000
200
100
0
-100
-200
400
0
-400
-800
-300
-400
-1600
20
40
60
80
Temperature (°C)
100
120
-2000
-40
140
-20
0
40
60
80
Temperature (°C)
100
120
140
D014
VCM = V+
Data from 74 amplifiers
Figure 6-4. Offset Voltage vs Temperature
Figure 6-3. Offset Voltage vs Temperature
2000
2000
1600
1600
1200
1200
Offset Voltage (µV)
Offset Voltage (µV)
20
D013
VCM = VData from 74 amplifiers
800
400
0
-400
-800
-1200
800
400
0
-400
-800
-1200
-1600
-1600
-2000
-20
-2000
16
-16
-12
-8
-4
0
4
8
Common-Mode Voltage (V)
12
16
20
16.5
17
D015
TA = 25°C
Data from 74 amplifiers
Figure 6-5. Offset Voltage vs Common-Mode Voltage
12
D002
800
-1200
0
0.9
Figure 6-2. Offset Voltage Drift Distribution
500
-20
0.8
Distribution from 74 amplifiers
Figure 6-1. Offset Voltage Production Distribution
-500
-40
0.3
0.4
0.5
0.6
0.7
Offset Voltage Drift (µV/°C)
D001
17.5
18
18.5
19
Common-Mode Voltage (V)
19.5
20
D060
TA = 25°C
Data from 74 amplifiers
Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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6.8 Typical Characteristics (continued)
2000
2000
1600
1600
1200
1200
800
Offset Voltage (µV)
Offset Voltage (µV)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
400
0
-400
-800
-1200
800
400
0
-400
-800
-1200
-1600
-1600
-2000
-20
-2000
16
-16
-12
-8
-4
0
4
8
Common-Mode Voltage (V)
12
16
20
16.5
17
D016
TA = 125°C
Data from 74 amplifiers
20
D061
Figure 6-8. Offset Voltage vs Common-Mode Voltage (Transition
Region)
2000
2000
1600
1600
1200
1200
Offset Voltage (µV)
800
400
0
-400
-800
-1200
800
400
0
-400
-800
-1200
-1600
-1600
-2000
-20
-2000
16
-16
-12
-8
-4
0
4
8
Common-Mode Voltage (V)
12
16
20
16.5
17
D017
TA = –40°C
Data from 74 amplifiers
17.5
18
18.5
19
Common-Mode Voltage (V)
19.5
20
D062
TA = –40°C
Data from 74 amplifiers
Figure 6-9. Offset Voltage vs Common-Mode Voltage
Figure 6-10. Offset Voltage vs Common-Mode Voltage
(Transition Region)
75
500
400
G=-1
G=1
G=11
G=101
G=1001
60
Closed-Loop Gain (dB)
300
Offset Voltage (µV)
19.5
TA = 125°C
Data from 74 amplifiers
Figure 6-7. Offset Voltage vs Common-Mode Voltage
Offset Voltage (µV)
17.5
18
18.5
19
Common-Mode Voltage (V)
200
100
0
-100
-200
-300
45
30
15
0
-15
-30
-400
-500
0
4
8
12
16
20
24
28
Supply Voltage (V)
32
36
VCM = V–
Data from 74 amplifiers
40
-45
100
1k
D018
10k
100k
Frequency (Hz)
1M
10M
D005
Figure 6-12. Closed-Loop Gain vs Frequency
Figure 6-11. Offset Voltage vs Power Supply
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6.8 Typical Characteristics (continued)
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
-20
Input Bias Current and Offset Current (pA)
Input Bias Current and Offset Current (pA)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
IBIB+
IOS
-16
-12
-8
-4
0
4
8
Common-Mode Voltage (V)
12
16
20
D019
50
1600
1400
1200
1000
800
600
400
200
0
-200
-40
-20
0
40
60
80
Temperature (°C)
100
120
140
D020
V+ - 1V
V+ - 2V
35
V+ - 3V
Output Voltage (V)
40
30
25
20
15
V+ - 4V
V+ - 5V
V+ - 6V
V+ - 7V
V+ - 8V
10
-40°C
25°C
125°C
V+ - 9V
5
V+ - 10V
0
0
0
0.5
1
1.5
2
2.5
3
Input Step (V)
3.5
4
4.5
10
20
30
5
40
50
60
70
Output Current (mA)
80
90
100
D021
VS = 40 V
D035
Figure 6-15. Slew Rate vs Input Step Voltage
Figure 6-16. Output Voltage Swing vs Output Current (Sourcing)
V+
V- + 10V
-40°C
25°C
125°C
V- + 9V
V- + 8V
V+ - 1V
Output Voltage (V)
V- + 7V
V- + 6V
V- + 5V
V- + 4V
V- + 3V
V- + 2V
V+ - 2V
V+ - 3V
V+ - 4V
-40°C
25°C
125°C
V- + 1V
V-
V+ - 5V
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
0
10
20
D022
VS = 40 V
30
40
50
60
70
Output Current (mA)
80
90
100
D049
VS = 5 V
Figure 6-17. Output Voltage Swing vs Output Current (Sinking)
14
20
V+
SR+
SR-
45
Output Voltage (V)
IBIB+
IOS
1800
Figure 6-14. Input Bias Current and Offset Current vs
Temperature
Figure 6-13. Input Bias Current and Offset Current vs CommonMode Voltage
Slew Rate (V/Ps)
2000
Figure 6-18. Output Voltage Swing vs Output Current (Sourcing)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
120
V- + 5V
-40°C
25°C
125°C
CMRR & PSRR (dB)
Output Voltage (V)
V- + 4V
CMRR
PSRR+
PSRR-
105
V- + 3V
V- + 2V
V- + 1V
90
75
60
45
30
15
V20
30
40
50
60
70
Output Current (mA)
80
90
0
1k
100
D050
VS = 5 V
80
10
100
1
120
0.1
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
Common-Mode Rejection Ratio (PV/V)
100
Common-Mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (PV/V)
60
100k
1M
Frequency (Hz)
60
100
80
10
100
1
120
0.1
-40
140
140
-20
0
20
D023
80
10
100
1
120
40
60
80
Temperature (°C)
100
120
140
140
Power-Supply Rejection Ratio (µV/V)
100
20
100
120
140
140
D051
Figure 6-22. CMRR vs Temperature
60
Common-Mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (PV/V)
Figure 6-21. CMRR vs Temperature
0
40
60
80
Temperature (°C)
VS = 5 V
1000
-20
D006
1000
VS = 40 V
0.1
-40
10M
Figure 6-20. CMRR and PSRR vs Frequency
Figure 6-19. Output Voltage Swing vs Output Current (Sinking)
1000
10k
Common-Mode Rejection Ratio (dB)
10
100
80
10
100
1
120
0.1
140
0.01
-40
-20
0
D052
20
40
60
80
Temperature (°C)
100
120
Power-Supply Rejection Ratio (dB)
0
160
140
D024
Figure 6-24. PSRR vs Temperature
VS = 2.7 V
Figure 6-23. CMRR vs Temperature
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6.8 Typical Characteristics (continued)
Input Voltage Noise Spectral Density (nV/rtHz)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
2
1.5
Amplitude (PV)
1
0.5
0
-0.5
-1
-1.5
-2
Time (1s/div)
100
10
1
10
100
1k
Frequency (Hz)
D025
Figure 6-25. 0.1-Hz to 10-Hz Noise
Quiescent Current (mA)
Quiescent Current (mA)
2.4
2
1.6
1.2
0.8
0.4
0
4
8
12
16
20
24
28
Supply Voltage (V)
32
36
40
2.6
2.55
2.5
2.45
2.4
2.35
2.3
2.25
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
-40
Vs=2.7V
Vs=5V
Vs=40V
-20
0
100
120
140
D24_
Figure 6-28. Quiescent Current vs Temperature
1000
145
135
Open-Loop Output Impedance (:)
VS = 2.7V
VS = 5V
VS = 40V
140
Open-Loop Gain (dB)
40
60
80
Temperature (°C)
VCM = V–
VCM = V–
130
125
120
115
110
105
-20
0
20
40
60
80
Temperature (°C)
100
120
140
100
10
1
0.1
100
1k
D028
Figure 6-29. Open-Loop Voltage Gain vs Temperature (dB)
16
20
D026
Figure 6-27. Quiescent Current vs Supply Voltage
100
-40
D007
Figure 6-26. Input Voltage Noise Spectral Density vs Frequency
2.8
0
10k
10k
100k
Frequency (Hz)
1M
10M
D099
Figure 6-30. Open-Loop Output Impedance vs Frequency
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6.8 Typical Characteristics (continued)
70
70
60
60
50
50
Overshoot (%)
Overshoot (%)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
40
30
20
40
30
20
RISO = 0:, Overshoot (+)
RISO = 0:, Overshoot (-)
RISO = 50:, Overshoot (+)
RISO = 50:, Overshoot (-)
10
RISO = 0:, Overshoot (+)
RISO = 0:, Overshoot (-)
RISO = 50:, Overshoot (+)
RISO = 50:, Overshoot (-)
10
0
0
0
80
160
240
320
400
Capacitive Load (pF)
480
560
0
80
160
D029
20-mVpp Output Step, G = -1
240
320
400
Capacitive Load (pF)
480
560
D030
20-mVpp Output Step, G = +1
Figure 6-31. Small-Signal Overshoot vs Capacitive Load
Figure 6-32. Small-Signal Overshoot vs Capacitive Load
70
Input
Output
65
Amplitude (2.5V/div)
Phase Margin (°)
60
55
50
45
40
35
30
25
20
0
20
40
60
Time (25µs/div)
80 100 120 140 160 180 200 220
Capacitive Load (pF)
D004
D031
VIN = ±10 Vpp; VS = VOUT = ±9.55 V
G = +1
Figure 6-34. No Phase Reversal
Figure 6-33. Phase Margin vs Capacitive Load
Input
Output
Amplitude (5V/div)
Amplitude (5V/div)
Input
Output
Time (100ns/div)
Time (100ns/div)
D053
D032
G = –10
G = –10
Figure 6-35. Positive Overload Recovery
Figure 6-36. Negative Overload Recovery
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
20
20
Input
Output
Input
Output
10
Amplitude (mV)
Amplitude (mV)
10
0
0
-10
-10
-20
-20
Time (2 µs/div)
Time (2 µs/div)
D054
D033
CL = 20 pF, G = -1, 20-mVpp step response
CL = 20 pF, G = 1, 20-mVpp step response
Figure 6-38. Small-Signal Step Response
Figure 6-37. Small-Signal Step Response
4
4
Input
Output
3
2
Amplitude (V)
2
Amplitude (V)
Input
Output
3
1
0
-1
1
0
-1
-2
-2
-3
-3
-4
-4
Time (2 µs/div)
Time (2 µs/div)
D034
D055
CL = 20 pF, G = 1, 5-Vpp step response
CL = 20 pF, G = -1, 5-Vpp step response
Figure 6-39. Large-Signal Step Response
Figure 6-40. Large-Signal Step Response
45
-60
Vs=40V
Vs=16V
Vs=2.7V
40
35
-70
-80
-90
Crosstalk (dB)
Output (V)
30
25
20
15
-110
-120
-130
10
-140
5
-150
0
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
Figure 6-41. Maximum Output Voltage vs Frequency
18
-100
D009
-160
100
1k
10k
100k
Frequency (Hz)
1M
10M
D011
Figure 6-42. Channel Separation vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted)
120
110
100
EMIRR (dB)
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
D012
Figure 6-43. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx992 family (OPA992, OPA2992, and OPA4992) is a family of high voltage (40-V) general purpose
operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±210 µV, typ), and low offset drift (±0.25 µV/°C, typ).
Special features such as differential and common-mode input voltage range to the supply rail, high short-circuit
current (±65 mA), high slew rate (32 V/µs), and shutdown make the OPAx992 an extremely flexible, robust, and
high-performance operational amplifier for high-voltage industrial applications.
7.2 Functional Block Diagram
+
NCH Input
Stage
–
IN+
40-V
Differential
MUX-Friendly
Front End
+
Slew
Boost
Gain
Stage
Shutdown
Circuitry
Output
Stage
OUT
–
IN-
+
PCH Input
Stage
–
20
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPAx992 uses a special input architecture to eliminate the requirement for input protection diodes but still
provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection
schemes that are activated by fast transient step responses and introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling
time.
V+
V+
VIN+
VIN+
VOUT
OPAx992
40 V
VOUT
~0.7 V
VIN
VIN
V
OPAx992 Provides Full 40-V
Differential Input Range
V
Conventional Input Protection
Limits Differential Input Range
Figure 7-1. OPAx992 Input Protection Does Not Limit Differential Input Capability
Vn = 10 V
RFILT
10 V
1
Ron_mux
Sn
1
D
10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Ron_mux
Sn+1
VIN±
2
~0.7 V
CFILT
CS
VOUT
Idiode_transient
±10 V
Input Low-Pass Filter
Simplified Mux Model
VIN+
Buffer Amplifier
Figure 7-2. Back-to-Back Diodes Create Settling Issues
The OPAx992 family of operational amplifiers provides a true high-impedance differential input capability for
high-voltage applications using a patented input protection architecture that does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input
applications. The OPAx992 tolerates a maximum differential swing (voltage between inverting and non-inverting
pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in applications
with fast-ramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision
Operational Amplifiers for more information.
7.3.2 EMI Rejection
The OPAx992 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx992 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-3 shows the results of this testing on the OPAx992. Table 7-1 shows the EMIRR IN+ values for the OPAx992 at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
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Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
120
110
100
EMIRR (dB)
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
D012
Figure 7-3. EMIRR Testing
Table 7-1. OPAx992 EMIRR IN+ For Frequencies of Interest
FREQUENCY
EMIRR IN+
400 MHz
50.0 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
56.3 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
65.6 dB
Bluetooth®,
2.4 GHz
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
70.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
78.9 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
91.0 dB
5 GHz
22
APPLICATION OR ALLOCATION
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
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7.3.3 Thermal Protection
One channel has load
Consider IQ of two channels
TA = 55°C
PD = 0.954W
JA = 131°C/W
TJ = 131°C/W × 0.954W + 55°C
TJ = 180°C (expected)
30 V
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx992 is 150°C.
Exceeding this temperature causes damage to the device. The OPAx992 has a thermal protection feature that
reduces damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 170°C. Figure 7-4 shows an application example
for the OPA2992 that has significant self heating because of its power dissipation (0.954 W). In this example,
both channels have a quiescent power dissipation while one of the channels has a significant load. Thermal
calculations indicate that for an ambient temperature of 55°C, the device junction temperature reaches 180°C.
The actual device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-4
shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so
the output is 3 V. When self heating causes the device junction temperature to increase above the internal limit,
the thermal protection forces the output to a high-impedance state and the output is pulled to ground through
resistor RL. If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate
between a shutdown and enabled state until the output fault is corrected. Please note that thermal performance
can vary greatly depending on the package selected and the PCB layout design. This example uses the thermal
performance of the SOIC (8) package.
3V
0V
OPA2992
IOUT = 30 mA
+
–
+
RL
3V
100 –
VIN
3V
170ºC
Temperature
Figure 7-4. Thermal Protection
7.3.4 Capacitive Load and Stability
The OPAx992 features an output stage capable of driving moderate capacitive loads, and by leveraging an
isolation resistor, the device can easily be configured to drive larger capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
70
70
RISO = 0:, Overshoot (+)
RISO = 0:, Overshoot (-)
RISO = 50:, Overshoot (+)
RISO = 50:, Overshoot (-)
60
50
Overshoot (%)
Overshoot (%)
50
60
40
30
40
30
20
20
10
10
0
RISO = 0:, Overshoot (+)
RISO = 0:, Overshoot (-)
RISO = 50:, Overshoot (+)
RISO = 50:, Overshoot (-)
0
0
80
160
240
320
400
Capacitive Load (pF)
480
560
0
80
160
D030
Figure 7-5. Small-Signal Overshoot vs Capacitive
Load (20-mVpp Output Step, G = +1)
240
320
400
Capacitive Load (pF)
480
560
D029
Figure 7-6. Small-Signal Overshoot vs Capacitive
Load (20-mVpp Output Step, G = -1)
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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces ringing
and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the OPAx992 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 7-7. Extending Capacitive Load Drive With the OPA992
24
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7.3.5 Common-Mode Voltage Range
The OPAx992 is a 40-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends to both supply rails. This wide range is achieved with paralleled complementary N-channel and Pchannel differential input pairs, as shown in Figure 7-8. The N-channel pair is active for input voltages close to
the positive rail, typically from (V+) – 1 V to the positive supply. The P-channel pair is active for inputs from the
negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) – 2 V to (V+) – 1
V, in which both input pairs are on. This transition region can vary modestly with process variation. Within this
region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded compared to
operation outside this region.
Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
INPMOS
PMOS
IN+
NMOS
NMOS
V-
Figure 7-8. Rail-to-Rail Input Stage
7.3.6 Phase Reversal Protection
The OPAx992 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx992 is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 7-9. For more information on phase reversal, see Op
Amps With Complementary-Pair Input Stages application note.
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Amplitude (2.5V/div)
Input
Output
Time (25µs/div)
D031
Figure 7-9. No Phase Reversal
26
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-10 shows an illustration of the ESD circuits contained in the OPAx992 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
+
–
RF
+VS
VDD
R1
RS
IN–
50
IN+
50
–
+
Power-Supply
ESD Cell
ID
VIN
RL
+
–
VSS
+
–
–VS
TVS
Figure 7-10. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx992 is approximately 170 ns.
7.3.9 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.00002% 0.00312% 0.13185%
1
-61
1
-51
1
-41
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
-31
1
-21
1
-1
1
1
+1
1
0.13185% 0.00312% 0.00002%
1
1
1
+21 +31 +41 +51 +61
Figure 7-11. Ideal Gaussian Distribution
The Figure 7-11 figure shows an example distribution, where µ, or mu, is the mean of the distribution, and
where σ, or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ–σ to µ+σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean
(for example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for OPAx992,
the typical input voltage offset is 210 µV. So 68.2% of all OPAx992 devices are expected to have an offset from
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–210 µV to +210 µV. At 4 σ (±840 µV), 99.9937% of the distribution has an offset voltage less than ±840 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the OPAx992 family has a maximum offset voltage of
1 mV at 25°C, and even though this corresponds to slightly less than 5 σ (≈1 in 1.7 million units), which is
extremely unlikely, TI assures that any unit with larger offset than 1 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the
6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be
an option as a wide guardband to design a system around. In this case, the OPAx992 family does not have
a maximum or minimum for offset voltage drift. But based on the typical value of 0.25 µV/°C in the Electrical
Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 1.5 µV/°C. When
designing for worst-case system conditions, this value can be used to estimate the worst possible offset across
temperature without having an actual minimum or maximum value.
Note that process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.10 Packages With an Exposed Thermal Pad
The OPAx992 family is available in the WSON-8 (DSG) package which features an exposed thermal pad. Inside
the package, the die is attached to this thermal pad using an electrically conductive compound. For this reason,
when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or left
floating. Attaching the thermal pad to a potential other than V– is not allowed, and performance of the device is
not assured when doing so.
7.3.11 Shutdown
The OPAx992S devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 40 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high. The amplifier
is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.1 V and V– + 20 V.
The shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the
negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or
driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The
maximum voltage allowed at the SHDN pins is V– + 20 V or V+, whichever is lower. Exceeding V– + 20V or V+,
whichever is lower, will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The
typical enable time out of shutdown is 15 µs; disable time is 3 µs. When disabled, the output assumes a
high-impedance state. This architecture allows the OPAx992S family to operate as a gated amplifier, multiplexer,
or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
V- is required. If using the OPAx992S without a load, the resulting turnoff time significantly increases.
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7.4 Device Functional Modes
The OPAx992 has a single functional mode and is operational when the power-supply voltage is greater than or
equal to 2.7 V (±1.35 V). The maximum power supply voltage for the OPAx992 is 40 V (±20 V).
The OPAx992S devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
30
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx992 family offers excellent DC precision and AC performance. These devices operate up to 40-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 10.6-MHz
bandwidth and high output drive. These features make the OPAx992 a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
Figure 8-1 shows the OPA992 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision
Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
5V
LOAD
+
OPA992
VOUT
–
ILOAD
RSHUNT
100 m
LM7705
RF
5.76 k
RG
120
Figure 8-1. OPAx992 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Max output voltage: 4.9 V
Maximum shunt voltage: 100 mV
8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1:
VOUT
ILOAD u RSHUNT u Gain
(1)
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The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2:
RSHUNT
VSHUNT _ MAX
100mV
1A
ILOAD _ MAX
100m:
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the OPA992 to produce an output voltage of 0 V to 4.9 V. The gain needed by the OPA992 to
produce the necessary output voltage is calculated using Equation 3:
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the OPA992 to 49 V/V.
Gain 1
RF
RG
(4)
Choosing RF as 5.76 kΩ, RG is calculated to be 120 Ω. RF and RG were chosen as 5.76 kΩ and 120 Ω because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. However, excessively large resistors will generate thermal noise that exceeds the intrinsic noise of the op
amp. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.
8.2.1.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 8-2. Low-Side, Current-Sense, Transfer Function
8.2.2 High Voltage Buffered Multiplexer
The OPAx992S shutdown devices can be configured to create a high voltage, buffered multiplexer. Outputs can
be connected together on a common bus and the shutdown pins can be used to select the desired channel to
pass through. Since the amplifier circuitry has been designed such that disable transitions occur significantly
faster than enable transitions, the amplifier naturally exhibits a "break before make" switch topology. Amplifier
outputs enter a high impedance state when placed in shutdown, so there is no risk of bus contention when
connecting multiple channel outputs together. Additionally, because outputs are isolated from inputs, there is no
concern about the impedance at the input of each channel interacting undesirably with the impedance at the
output, like an amplifier gain stage or ADC driver circuit. Also, because this topology uses amplifiers instead of
MOSFET switches, other common issues with multiplexers such as charge injection or signal error due to RON
effects are eliminated.
32
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Figure 8-3 shows an example topology for a basic 2:1 multiplexer. When SEL is low, channel 1 is selected and
active; when SEL is high, channel 2 is selected and active. For more information on how to use the OPAx992S
shutdown function, see the shutdown section in Section 6.7.
–
Channel 1
Channel 1
Input
+
SEL
Channel 2
Input
Output
+
Channel 2
–
Figure 8-3. High Voltage Buffered Multiplexer
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9 Power Supply Recommendations
The OPAx992 is specified for operation from 2.7 V to 40 V (±1.35 V to ±20 V); many specifications apply from
–40°C to 125°C or with specific supply voltages and test conditions.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section
10.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
VC3
INPUT
OUTPUT
U1
1 +
3
2
–
R3
4
C4
C2
V+
R1
C1
R2
GND
V+
INPUT
Figure 10-1. Schematic for Noninverting Configuration Layout Example
GND
OUTPUT
V-
GND
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration - SC70 (DCK) Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, MUX-Friendly, Precision Operational Amplifiers application brief
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
Texas Instruments, Op Amps With Complementary-Pair Input Stages application note
Texas Instruments, 0-1-A, Single-Supply, Low-Side, Current Sensing Solution reference design (TIPD129)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
36
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: OPA992 OPA2992 OPA4992
OPA992, OPA2992, OPA4992
www.ti.com
SBOSA10D – JUNE 2021 – REVISED AUGUST 2022
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: OPA992 OPA2992 OPA4992
37
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2992IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O92F
Samples
OPA2992IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2JUT
Samples
OPA2992IDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2992D
Samples
OPA2992IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O92G
Samples
OPA2992IPWR
ACTIVE
TSSOP
PW
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2992PW
Samples
OPA4992IDR
ACTIVE
SOIC
D
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA4992D
Samples
OPA4992IPWR
ACTIVE
TSSOP
PW
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O4992PW
Samples
OPA992IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O92DB
Samples
OPA992IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1JS
Samples
OPA992SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O92SD
Samples
POPA2992IDR
ACTIVE
SOIC
D
8
3000
TBD
Call TI
Call TI
-40 to 125
Samples
POPA2992IPWR
ACTIVE
TSSOP
PW
8
3000
TBD
Call TI
Call TI
-40 to 125
Samples
POPA2992SIRUGR
ACTIVE
X2QFN
RUG
10
3000
TBD
Call TI
Call TI
-40 to 125
Samples
POPA4992IPWR
ACTIVE
TSSOP
PW
14
3000
TBD
Call TI
Call TI
-40 to 125
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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