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OPA316-Q1, OPA2316-Q1, OPA4316-Q1
SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
OPAx316-Q1 10-MHz, Rail-to-Rail Input/Output, Low-Voltage, 1.8-V CMOS Operational
Amplifier
1 Features
3 Description
•
•
The OPAx316-Q1 family of single and dual
operational amplifiers represents a new generation of
general-purpose, low-power operational amplifiers.
Featuring rail-to-rail input and output swings, low
quiescent current (400 μA/ch typical) combined with a
wide bandwidth of 10 MHz and very-low noise
(11 nV/√Hz at 1 kHz) makes this family suitable for
circuits requiring a good speed and power ratio. The
low input bias current supports those operational
amplifiers for applications with megaohm source
impedances. The low input bias current of the
OPAx316-Q1 yields a very-low current noise to make
the device attractive for high impedance sensor
interfaces.
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C5
Unity-Gain Bandwidth: 10 MHz
Low IQ: 400 µA/ch
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 11 nV/√Hz at 1 kHz
Low Input Bias Current: ±5 pA
Offset Voltage: ±0.5 mV
Unity-Gain Stable
Internal RFI-EMI Filter
Extended Temperature Range: –40°C to +125°C
2 Applications
•
Automotive Applications:
– ADAS
– Body Electronics and Lighting
– Current Sensing
– Battery Management Systems
The robust design of the OPAx316-Q1 provides easeof-use to the circuit designer: a unity-gain stable,
integrated RFI and EMI rejection filter, no phase
reversal in overdrive condition, and high electrostatic
discharge (ESD) protection (4-kV HBM).
These devices are optimized for low-voltage
operation as low as 1.8 V (±0.9 V) and up to 5.5 V
(±2.75 V). This latest addition of low-voltage CMOS
automotive grade operational amplifiers provide a
family of wide bandwidth, low noise, and low power
that meet the needs of a wide variety of applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
OPA316-Q1
SOT-23 (5)
1.60 mm × 2.90 mm
OPA2316-Q1
VSSOP (8)
3.00 mm × 3.00 mm
OPA4316-Q1
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Single-Pole, Low-Pass Filter
RG
RF
R1
Low-Supply Current (400 µA/ch) for 10-MHz
Bandwidth
VOUT
f-3 dB =
1
2pR1C1
270
100
225
80
180
60
135
Phase
40
90
20
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
(
Phase (º)
C1
Gain (dB)
VIN
120
45
VS
= “2.75 V
V
S = “2.75 V
0
0
Gain
VS
= “0.9
“0.9 VV
V
S =
±20
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
-45
100M
C006
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA316-Q1, OPA2316-Q1, OPA4316-Q1
SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA316-Q1 ............................ 7
Thermal Information: OPA2316-Q1 .......................... 8
Thermal Information: OPA4316-Q1 .......................... 9
Electrical Characteristics......................................... 10
Typical Characteristics ............................................ 12
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Original (November 2016) to Revision A
Page
•
Changed CDM classification reduced from C6 ..................................................................................................................... 1
•
Deleted OPA2316S-Q1 package and body size information from Device Information table ................................................ 1
•
Deleted SC70 (5) (OPA316-Q1), DFN (8), MSOP (8), SOIC (8) (OPA2316-Q1), and SOIC (14) packages
(OPA4316-Q1) from the Device Information table, Thermal Information tables, and pinout diagrams.................................. 1
•
Deleted OPA2316S-Q1 pin diagram and Pin Functions table in Pin Configurations and Functions section ........................ 3
•
Deleted D (SOIC) package from OPA4316-Q1 pin diagram in Pin Configurations and Functions section .......................... 5
•
Changed CDM rating from ±1500 V to ±750 V ...................................................................................................................... 6
•
Deleted OPA2316S-Q1 device thermal information in the Thermal Information table .......................................................... 7
•
Added thermal information for OPA4316-Q1 device .............................................................................................................. 9
•
Deleted the literature numbers in parentheses from the format of TI document references in the Documentation
Support section .................................................................................................................................................................... 27
2
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
5 Pin Configuration and Functions
OPA316-Q1 DBV Package
5-Pin SOT-23
Top View
Pin Functions: OPA316-Q1
PIN
NAME
NO.
–IN
4
+IN
V–
I/O
DESCRIPTION
I
Inverting input
3
I
Noninverting input
2
—
Negative supply or ground (for single-supply operation).
V+
5
—
Positive supply
OUT
1
O
Output
Copyright © 2016–2017, Texas Instruments Incorporated
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3
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
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OPA2316-Q1 DGK Package
8-Pin VSSOP
Top View
Pin Functions: OPA2316-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative supply or ground (for single-supply operation).
V+
8
—
Positive supply
4
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
OPA4316-Q1 PW Package
14-Pin TSSOP
Top View
Pin Functions: OPA4316-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative supply or ground (for single-supply operation)
V+
4
—
Positive supply
Copyright © 2016–2017, Texas Instruments Incorporated
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
MAX
UNIT
7
V
(V+) + 0.5
V
Supply voltage
Signal input pins
Voltage (2)
Common-mode
(V–) – 0.5
Differential
Current (2)
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(3)
mA
Continuous
TA
(2)
V
10
–10
Output short-circuit (3)
(1)
(V+) – (V–) + 0.2
–55
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
6
MAX
UNIT
Supply voltage
1.8
5.5
V
Specified temperature
–40
125
°C
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
6.4 Thermal Information: OPA316-Q1
OPA316-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
Junction-to-ambient thermal resistance (2)
RθJA
(3)
221.7
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
144.7
°C/W
RθJB
Junction-to-board thermal resistance (4)
49.7
°C/W
ψJT
Junction-to-top characterization parameter (5)
26.1
°C/W
ψJB
Junction-to-board characterization parameter (6)
49
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2016–2017, Texas Instruments Incorporated
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
www.ti.com
6.5 Thermal Information: OPA2316-Q1
OPA2316-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
Junction-to-ambient thermal resistance (2)
RθJA
186.6
°C/W
(3)
RθJC(top)
Junction-to-case(top) thermal resistance
78.8
°C/W
RθJB
Junction-to-board thermal resistance (4)
107.9
°C/W
ψJT
Junction-to-top characterization parameter (5)
15.5
°C/W
ψJB
Junction-to-board characterization parameter (6)
106.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
6.6 Thermal Information: OPA4316-Q1
OPA4316-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
14 PINS
Junction-to-ambient thermal resistance (2)
RθJA
117.2
°C/W
(3)
RθJC(top)
Junction-to-case(top) thermal resistance
46.2
°C/W
RθJB
Junction-to-board thermal resistance (4)
58.9
°C/W
ψJT
Junction-to-top characterization parameter (5)
4.9
°C/W
ψJB
Junction-to-board characterization parameter (6)
58.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2016–2017, Texas Instruments Incorporated
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6.7 Electrical Characteristics
VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.5
±2.5
mV
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Drift
PSRR
vs power supply
VS = 5 V
VS = 5 V, TA = –40°C to 125°C
mV
VS = 5 V, TA = –40°C to 125°C
±2
±10
μV/°C
VS = 1.8 V – 5.5 V, VCM = (V–)
±30
±150
µV/V
±250
µV/V
VS = 1.8 V – 5.5 V, VCM = (V–), TA = –40°C to 125°C
Channel separation, dc
±3.5
At dc
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
CMRR
Common-mode rejection ratio
VS = 1.8 V to 2.5 V
(V–) – 0.2
(V+)
V
VS = 2.5 V to 5.5 V
(V–) – 0.2
(V+) + 0.2
V
VS = 1.8 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA= –40°C to 125°C
70
86
dB
VS = 5.5 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA= –40°C to 125°C
76
90
dB
VS = 1.8 V, VCM = –0.2 V to 1.8 V,
TA= –40°C to 125°C
57
72
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V,
TA= –40°C to 125°C
65
80
dB
INPUT BIAS CURRENT
IB
±5
Input bias current
IOS
TA= –40°C to 125°C
±2
Input offset current
TA= –40°C to 125°C
±15
pA
±15
nA
±15
pA
±8
nA
NOISE
En
Input voltage noise (peak-to-peak)
VS = 5 V, f = 0.1 Hz to 10 Hz
3
μVPP
en
Input voltage noise density
VS = 5 V, f = 1 kHz
11
nV/√Hz
in
Input current noise density
f = 1 kHz
1.3
fA/√Hz
INPUT IMPEDANCE
ZID
Differential
2 || 2
1016Ω || pF
ZIC
Common-mode
2 || 4
1011Ω || pF
OPEN-LOOP GAIN
AOL
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
94
100
dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
104
110
dB
90
96
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
100
106
dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ, TA= –40°C to 125°C
86
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ, TA= –40°C to 125°C
84
dB
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 2 kΩ
Open-loop voltage gain
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V, G = 1
10
MHz
φm
Phase margin
VS = 5 V, G = 1
60
Degrees
SR
Slew rate
VS = 5 V, G = 1
6
V/μs
To 0.1%, VS = 5 V, 2-V step , G = 1, CL = 100 pF
1
μs
1.66
μs
0.3
μs
tS
Settling time
tOR
Overload recovery time
VS = 5 V, VIN × gain = VS
Total harmonic distortion + noise (1)
VS = 5 V, VO = 0.5 VRMS, G = 1
f = 1 kHz
THD + N
(1)
10
To 0.01%, VS = 5 V, 2-V step , G = 1, CL = 100 pF
0.0008%
Third-order filter; bandwidth = 80 kHz at –3 dB.
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
Electrical Characteristics (continued)
VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VO
Voltage output swing from supply
rails
VS = 1.8 V, RL = 10 kΩ, TA= –40°C to 125°C
15
mV
VS = 5.5 V, RL = 10 kΩ, TA= –40°C to 125°C
30
mV
VS = 1.8 V, RL = 2 kΩ, TA= –40°C to 125°C
60
mV
VS = 5.5 V, RL = 2 kΩ, TA= –40°C to 125°C
120
mV
ISC
Short-circuit current
VS = 5 V
±50
mA
ZO
Open-loop output impedance
VS = 5 V, f = 10 MHz
250
Ω
POWER SUPPLY
VS
Specified voltage
IQ
Quiescent current per amplifier
VS = 5 V, IO = 0 mA, TA= –40°C to 125°C
1.8
400
Power-on time
VS = 0 V to 5.5 V
200
Copyright © 2016–2017, Texas Instruments Incorporated
5.5
V
500
µA
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µs
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6.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
40
Percentage of Amplifiers (%)
Percentage of Amplifiers (%)
25
20
15
10
5
35
30
25
20
15
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.5
0
-2.0
5
Offset Voltage (mV)
Offset Voltage Drift (µV/ƒC)
C013
C013
Distribution taken from 12551 amplifiers
TA = –40°C to +125°C, Distribution taken from 70 amplifiers
Figure 2. Offset Voltage Drift Distribution
2500
2000
2000
1500
1500
1000
1000
500
500
VOS ( V)
VOS ( V)
Figure 1. Offset Voltage Production Distribution
2500
0
±500
0
±500
±1000
±1000
±1500
±1500
±2000
±2000
±2500
±2500
±75
±50
0
±25
25
50
75
100
125
150
Temperature (ƒC)
0
±1
1
2
3
C001
V+ = 2.75 V, V– = –2.75 V, 9 typical units shown
Figure 4. Offset Voltage vs Common-Mode Voltage
2000
VS = ±2.75 V
VS = ±0.9 V
Gain (dB)
500
0
±500
±1000
120
270
100
225
80
180
60
135
Phase
40
90
20
±1500
45
VS
= “2.75 V
V
S = “2.75 V
0
±2000
Phase (º)
VOS ( V)
±2
VCM (V)
Figure 3. Offset Voltage vs Temperature
0
Gain
VS
= “0.9
“0.9 VV
V
S =
±2500
±20
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
VSUPPLY (V)
V+ = 0.9 V to 2.75 V, V– = –0.9 V to –2.75 V,
9 typical units shown
Figure 5. Offset Voltage vs Power Supply
12
Transition
±3
2500
1000
NChannel
PChannel
C001
9 typical units shown
1500
VCM = 2.95 V
VCM = -2.95 V
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2.8
C001
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
-45
100M
C006
VCM < (V+) – 1.4 V
Figure 6. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
100
100
75
75
AOL (µV/V)
50
50
AOL (µV/V)
VS = 1.8 V
25
VS = 1.8 V
25
0
0
VS = 5.5 V
VS = 5.5 V
-25
-25
-50
-50
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
±75
±50
0
±25
RL = 10 kΩ
75
100
125
150
C001
Figure 8. Open-Loop Gain vs Temperature
100000
25
20
IB+
IB Ios
10000
Input Bias Current and
Input Offset Current (pA)
15
1000
10
Gain (dB)
50
RL = 2 kΩ
Figure 7. Open-Loop Gain vs Temperature
5
0
-5
G = +1
-10
100
10
1
G = +10
-15
G = -1
0
-20
10k
100k
1M
Frequency (Hz)
10M
±75
100M
±50
0
±25
Figure 9. Closed-Loop Gain vs Frequency
25
50
75
100
125
Temperature (ƒC)
C007
150
C001
Figure 10. Input Bias and Offset Current vs Temperature
3
25°C
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
120
-40°C
2
1
Vout (V)
25
Temperature (ƒC)
C001
85°C
125°C
0
125°C
-1
85°C
-2
25°C
-40°C
100
80
60
40
PSRR
20
CMRR
0
-3
0
10
20
30
40
Iout (mA)
50
60
1
10
100
1k
10k
100k
Frequency (Hz)
C001
1M
C011
V+ = 2.75 V, V– = –2.75 V
Figure 11. Output Voltage Swing vs Output Current
Copyright © 2016–2017, Texas Instruments Incorporated
Figure 12. CMRR and PSRR vs Frequency
(Referred to Input)
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Typical Characteristics (continued)
200
Common-Mode Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
150
9 ” 9CM ” 9
VS = 1.8 V, (V-) -
100
- 1.4 V
50
0
9 ” 9CM ” 9
VS = 5.5 V, (V-) -
±50
- 1.4 V
±100
±150
±200
1000
750
500
9 ” 9CM ” 9
VS = 1.8 V, (V-) -
250
0
VS = 5.5 V, (V-) -
±250
9 ” 9CM ” 9
9
±500
±750
±1000
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
0
±25
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 13. CMRR vs Temperature (Narrow Range)
C001
Figure 14. CMRR vs Temperature (Wide Range)
80
60
1 V/div
Power-Supply Rejection Ratio (µV/V)
100
40
20
0
Peak-to-Peak Noise = VRMS × 6.6 = 3 Vpp
-20
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Time (1 s/div)
150
C014
C001
Figure 16. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 15. PSRR vs Temperature
16
15
Voltage Noise (nV/rtHz)
9ROWDJH 1RLVH 'HQVLW\ Q9 ¥+]
1000
100
10
14
13
12
11
10
9
1
8
0.1
1
10
100
Frequency (Hz)
1k
10k
100k
C015
0
0.5
1
1.5
2
2.5
3
3.5
4
Common-Mode Voltage (V)
4.5
5
5.5
C039
ƒ = 1 kHz
Figure 17. Input Voltage Noise Spectral Density vs
Frequency
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Figure 18. Input Voltage Noise vs Common-Mode Voltage
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Typical Characteristics (continued)
Total Harmonic Distortion + Noise (%)
G = +1
G
+1 V/V,
V/V,RL
RL = 2 kN
G
V/V,RL
RL = 10 kN
G = -1 V/V,
0.01
-80
G
V/V,RL
RL = 2 kN
G = -1 V/V,
-100
0.001
-120
100k
0.0001
10
100
1k
10k
Frequency (Hz)
1.
-40
0.1
-60
0.01
-80
0.001
-100
G = +1 V/V, RL
N
G = +1
+1 V/V,
V/V,RL
RL = 2 kN
0.0001
-120
G = -1
G
-1 V/V,
V/V,RL
RL = 10 kN
G = -1
-1 V/V,
V/V,RL
RL = 2 kN
0.00001
0.001
0.01
-140
0.1
1
10
Output Amplitude (VRMS)
C017
Bandwidth = 80 kHz, VOUT = 0.5 VRMS
Total Harmonic Distortion + Noise (dB)
G = +1
G
+1 V/V,
V/V,RL
RL = 10 kN
Total Harmonic Distortion + Noise (dB)
-60
0.1
Total Harmonic Distortion + Noise (%)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
C018
ƒ = 1 kHz, Bandwidth = 80 kHz
Figure 19. THD + N vs Frequency
Figure 20. THD + N vs Amplitude
450
450
425
425
400
IQ (µA)
IQ (µA)
375
350
VS = 5.5 V
400
VS = 1.8 V
325
375
300
275
250
350
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
6
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 21. Quiescent Current vs Supply Voltage
C001
Figure 22. Quiescent Current vs Temperature
10k
50
40
ZO ( )
Overshoot (%)
1k
100
30
RI = 1 kohm
+ 2.75 V
±
+
10
Device
VIN = 100 mVpp
+
±
10
RF = 1 kohm
20
CL
± 2.75 V
0
1
10
100
1k
10k
100k
1M
Frequency (Hz)
10M 100M 1000M
0p
V+ = 2.75 V
Figure 23. Open-Loop Output Impedance vs Frequency
Copyright © 2016–2017, Texas Instruments Incorporated
100p
200p
300p
Capacitive Load (F)
C024
V– = –2.75 V
C025
G = –1 V/V
Figure 24. Small-Signal Overshoot vs Load Capacitance
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
80
VIN
70
VOUT
50
1 V/div
Overshoot (%)
60
40
+ 2.75 V
30
+ 2.75 V
±
±
Device
Device
20
+
VIN = 100 mVpp
+
± 2.75 V
RL
CL
10
0
0p
100p
200p
V+ = 2.75 V
G = +1 V/V
V– = –2.75 V
Time (100 s/div)
300p
Capacitive Load (F)
C027
C026
V+ = 2.75 V
RL = 1 kΩ
V– = –2.75 V
Figure 26. No Phase Reversal
Figure 25. Small-Signal Overshoot vs Load Capacitance
1V
VOUT
5.5 V
RI = 1 kohm
RF = 10 kohm
0V
+ 2.75 V
VIN = 1 Vpp
±
Device
VIN
VOUT
+
±
500 mV/div
500 mV/div
+
± 2.75 V
6.1 VPP
Sine Wave
±
±
VOUT
+
+
± 2.75 V
Saturated
Recovering
Slewing
Saturated
RI = 1 kohm
Slewing
+ 2.75 V
+
VIN
Recovering
RF = 10 kohm
VIN = 1 Vpp
Device
VOUT
+
±
0V
±
± 2.75 V
-5.5 V
VOUT
-1 V
Time (100 ns/div)
Time (100 ns/div)
C028
V+ = 2.75 V
V– = –2.75 V
G = –10 V/V
C029
V+ = 2.75 V
Figure 27. Positive Overload Recovery
V– = –2.75 V
Figure 28. Negative Overload Recovery
+ 2.75 V
CL
10 pF
pF
CL == 10
±
Device
CL
= 100
100 pF
pF
C
L =
Output Voltage (20 mV/div)
G = –10 V/V
+
VIN = 1 Vpp
+
± 2.75 V
RL
CL
200 mV/div
±
+ 2.75 V
VOUT
±
Device
+
VIN = 100 mVpp
+
± 2.75 V
RL
CL
±
VIN
Time (200 ns/div)
Time (100 ns/div)
C030
V+ = 2.75 V
V– = –2.75 V
G = +1 V/V
Figure 29. Small-Signal Step Response
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C031
V+ = 2.75 V
CL = 100 pF
V– = –2.75 V
G = +1 V/V
Figure 30. Large-Signal Step Response
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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017
Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
40
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
100
80
60
40
20
0.1% Settling = ±2 mV
0
-20
20
0
0.1% Settling = ±2 mV
-20
-40
-60
-80
-40
0
0.5
1
1.5
Time ( s)
CL = 100 pF
0
2
1
G = +1 V/V
1.5
2
Time ( s)
CL = 100 pF
Figure 31. Positive Large-Signal Settling Time
C033
G = +1 V/V
Figure 32. Negative Large-Signal Settling Time
70
7
6
Output Voltage (VPP)
60
ISC, Source
ISC (mA)
0.5
C032
50
ISC, Sink
40
VS = 5.5 V
5
VS = 5 V
Maximum output voltage without
slew-rate induced distortion.
4
3
VS = 1.8 V
2
1
30
±75
±50
±25
0
25
50
75
100
125
0
100k
150
Temperature (ƒC)
Figure 33. Short-Circuit Current vs Temperature
10M
C035
Figure 34. Maximum Output Voltage vs
Frequency and Supply Voltage
100
0
80
±20
Crosstalk (dB)
EMIRR IN+ (dB)
1M
Frequency (Hz)
C001
60
40
20
±40
±60
±80
±100
0
±120
10M
100M
1G
Frequency (Hz)
10G
PRF = –10 dBm
Figure 35. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR IN+) vs Frequency
Copyright © 2016–2017, Texas Instruments Incorporated
10
100
1k
10k
100k
1M
Frequency (Hz)
C036
10M
C001
V+ = 2.75 V, V– = –2.75 V
Figure 36. Channel Separation vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx316-Q1 is a family of low-power, rail-to-rail input and output operational amplifiers. These devices
operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The class AB output stage is capable of driving less than or equal to 10-kΩ loads connected to any
point between V+ and ground. The input common-mode voltage range includes both rails and allows the
OPAx316-Q1 series to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes them suitable for driving
sampling analog-to-digital converters (ADCs).
The OPAx316-Q1 family features 10-MHz bandwidth and 6-V/μs slew rate with only 400-μA supply current per
channel, providing good ac performance at very-low-power consumption. DC applications are well served with a
very-low input noise voltage of 11 nV/√Hz at 1 kHz, low input bias current (5 pA), and a typical input offset
voltage of 0.5-mV.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The OPAx316-Q1 operational amplifiers are fully specified and ensured for operation from 1.8 V to 5.5 V. In
addition, many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating
voltages or temperature are illustrated in the Typical Characteristics graphs.
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Feature Description (continued)
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPAx316-Q1 series extends 200 mV beyond the supply rails for
supply voltages greater than 2.5 V. This performance is achieved with a complementary input stage: an Nchannel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV
above the positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, up to (V+) – 1 V to
(V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can
degrade compared to device operation outside this region.
7.3.3 Input and ESD Protection
The OPAx316-Q1 incorporates internal ESD protection circuits on all pins. In the case of input and output pins,
this protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10
mA, as stated in Absolute Maximum Ratings table. Figure 37 shows how a series input resistor can be added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and
the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 37. Input Current Protection
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the OPAx316-Q1 is specified in several ways so the user can select the best match for a given
application, as shown in the Electrical Characteristics table. First, the data sheet gives the CMRR of the device in
the common-mode range below the transition region [VCM < (V+) – 1.4 V]. This specification is the best indicator
of device capability when the application requires use of one of the differential input pairs. Second, the CMRR
over the entire common-mode range is specified at VCM = –0.2 V to 5.7 V for VS = 5.5 V. This last value includes
the variations shown in Figure 4 through the transition region.
7.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the operational amplifier, the dc offset observed at the amplifier output can shift from the
nominal value when EMI is present. This shift is a result of signal rectification associated with the internal
semiconductor junctions. Although EMI can affect all operational amplifier pin functions, the signal input pins are
likely to be the most susceptible. The OPA316-Q1 operational amplifier family incorporates an internal input lowpass filter that reduces the amplifier response to EMI. This filter provides both common-mode and differentialmode filtering. The filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20
dB per decade.
TI developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad
frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR) metric allows operational
amplifiers to be directly compared by the EMI immunity. Figure 35 illustrates the testing results on the OPAx316Q1. For more information, see EMI Rejection Ratio of Operational Amplifiers.
Copyright © 2016–2017, Texas Instruments Incorporated
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Feature Description (continued)
7.3.6 Rail-to-Rail Output
Designed as a low-power, low-noise operational amplifier, the OPAx316-Q1 delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10-kΩ, the output swings typically to within 30 mV of either supply rail regardless
of the power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to
the rails; see Figure 11.
7.3.7 Capacitive Load and Stability
The OPAx316-Q1 is designed for applications where driving a capacitive load is required. As with all operational
amplifiers, there may be specific instances where the OPAx316-Q1 can become unstable. The particular
operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain
(1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an
amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases as the capacitive loading increases. As a conservative best practice, designing for 25%
overshoot (40° phase margin) provides improved stability over process variations. The equivalent series
resistance (ESR) of some very-large capacitors (CL with a value greater than 1 μF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains. See Figure 24 (G = –1 V/V) and
Figure 25 (G = 1 V/V).
Inserting a small resistor (typically 10-Ω to 20-Ω) can increase the capacitive load capability of the amplifier in a
unity-gain configuration, as shown in Figure 38. This resistor significantly reduces the overshoot and ringing
associated with large capacitive loads. One possible problem with this technique, however, is that a voltage
divider is created with the added series resistor and any resistor connected in parallel with the capacitive load.
The voltage divider introduces a gain error at the output that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 38. Improving Capacitive Load Drive
7.3.8 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, either because of the high input voltage or the high gain. After the
device enters the saturation region, the charge carriers in the output devices require time to return back to the
linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified
slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time
and the slew time. The overload recovery time for the OPAx316-Q1 is approximately 300 ns.
7.4 Device Functional Modes
The OPAx316-Q1 devices are powered on when the supply is connected. The devices can operate as a singlesupply operational amplifier or a dual-supply amplifier, depending on the application.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 General Configurations
When receiving low-level signals, the device often requires limiting the bandwidth of the incoming signals into the
system. The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting pin of the
amplifier, as Figure 39 shows.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 39. Single-Pole Low-Pass Filter
If even more attenuation is needed, the device requires a multiple-pole filter. The Sallen-Key filter can be used
for this task, as Figure 40 shows. For best results, the amplifier must have a bandwidth that is eight to 10 times
the filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 40. Two-Pole, Low-Pass, Sallen-Key Filter
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8.2 Typical Application
Some applications require differential signals. Figure 41 shows a simple circuit to convert a single-ended input of
0.1 V to 2.4 V into a differential output of ±2.3 V on a single 2.7-V supply. The output range is intentionally limited
to maximize linearity. The circuit is composed of two amplifiers. One amplifier functions as a buffer and creates a
voltage (VOUT+). The second amplifier inverts the input and adds a reference voltage to generate VOUT–. VOUT+
and VOUT– range from 0.1 V to 2.4 V. The difference (VDIFF) is the difference between VOUT+ and VOUT– , resulting
in a differential output voltage range of 2.3 V.
R2
2.7 V
R1
±
VOUT±
+
R3
+
VREF
2.5 V
R4
V
VDIFF
+
2.7 V
±
VOUT+
+
+
+
VIN
Figure 41. Schematic for a Single-Ended Input to Differential Output Conversion
8.2.1 Design Requirements
Table 1 lists the design requirements:
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Supply voltage
2.7 V
Reference voltage
2.5 V
Input voltage
0.1 V to 2.4 V
Output differential voltage
±2.3 V
Output common-mode voltage
1.25 V
Small-signal bandwidth
5 MHz
8.2.2 Detailed Design Procedure
The circuit in Figure 41 takes a single-ended input signal (VIN) and generates two output signals (VOUT+ and
VOUT–) using two amplifiers and a reference voltage (VREF). VOUT+ is the output of the first amplifier and is a
buffered version of the input signal (VIN) , as shown in Equation 1. VOUT– is the output of the second amplifier that
uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for VOUT– is
given in Equation 2.
VOUT
VIN
(1)
VOUT
22
§ R 4 · § R2 ·
R2
VREF u ¨
¸ u ¨1
¸ VIN u
R
R
R
R1
4¹ ©
1¹
© 3
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(2)
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The differential output signal (VDIFF) is the difference between the two single-ended output signals (VOUT+ and
VOUT–). Equation 3 shows the transfer function for VDIFF. Using conditions in Equation 4 and Equation 5 and
applying the conditions that R1 = R2 and R3 = R4, the transfer function is simplified into Equation 6. Using this
configuration, the maximum input signal is equal to the reference voltage, and the maximum output of each
amplifier is equal to VREF. The differential output range is 2 × VREF. Furthermore, the common-mode voltage is
one half of VREF, as shown in Equation 7.
VDIFF
VOUT
VOUT
VIN
VOUT
VREF
VDIFF
2 u VIN
VCM
VOUT
§ R 4 · § R2 ·
§ R2 ·
VIN u ¨ 1
¸ u ¨1
¸ VREF u ¨
¸
R1 ¹
R1 ¹
©
© R3 R4 ¹ ©
(3)
(4)
VIN
(5)
VREF
VOUT ·
§ VOUT
¨
¸
2
©
¹
(6)
1
VREF
2
(7)
8.2.2.1 Amplifier Selection
Linearity over the input range is key for good dc accuracy. The common-mode input range and output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design, so the OPAx316-Q1 is selected because the bandwidth is greater
than the target of 5 MHz. The bandwidth and power ratio makes this device power efficient and the low offset
and drift ensure good accuracy for moderate precision applications.
8.2.2.2 Passive Component Selection
Because the transfer function of VOUT– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design uses resistors with resistance values of
49.9-kΩ and tolerances of 0.1%. However, if the noise of the system is a key parameter, smaller resistance
values (6-kΩ or lower) can be selected to keep the overall system noise low. This ensures that the noise from the
resistors is lower than the amplifier noise.
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8.2.3 Application Curves
2.50
2.50
2.00
2.00
1.50
1.50
Vout- (V)
Vout+ (V)
The measured transfer functions in Figure 42, Figure 43, and Figure 44 are generated by sweeping the input
voltage from 0.1 V to 2.4 V. The full input range is actually 0 V to 2.5 V, but is restricted to 0.1 V to maintain
optimal linearity. For more details on this design and other alternative devices that can be used in place of the
OPAx316-Q1, see Single-Ended Input to Differential Output Conversion Circuit Reference Design.
1.00
0.50
0.00
0.00
1.00
0.50
0.50
1.00
1.50
2.00
0.00
0.00
2.50
Input voltage (V)
0.50
1.00
1.50
2.00
Input voltage (V)
C027
Figure 42. VOUT+ vs Input Voltage
2.50
C027
Figure 43. VOUT– vs Input Voltage
2.50
2.00
1.50
Vdiff (V)
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
-2.50
0.00
0.50
1.00
1.50
2.00
Input voltage (V)
2.50
C027
Figure 44. VDIFF vs Input Voltage
24
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9 Power Supply Recommendations
The OPAx316-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more information on bypass capacitor placement, see the Layout Guidelines
section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in Figure 45 .
• Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
VIN
as possible.
VS+
VS±
+IN
V+
Use a low-ESR,
ceramic bypass
capacitor.
V±
Use a low-ESR,
ceramic bypass
capacitor.
GND
RG
OUT
±IN
VOUT
GND
Place components
close to the device
and to each other to
reduce parasitic
errors.
RF
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Figure 45. Operational Amplifier Board Layout for Noninverting Configuration
26
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• EMI Rejection Ratio of Operational Amplifiers
• Single-Ended Input to Differential Output Conversion Circuit Reference Design
11.2 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA316-Q1
Click here
Click here
Click here
Click here
Click here
OPA2316-Q1
Click here
Click here
Click here
Click here
Click here
OPA4316-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2316QDGKQ1
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
15E6
OPA2316QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
15E6
OPA316QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
15AD
OPA316QDBVTQ1
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
15AD
OPA4316QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4316Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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