OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
具有停机模式的 20-MHz、
、低噪声、1.8-V、
、
RRI/O, CMOS 运算放大器
查询样品: OPA322, OPA322S, OPA2322, OPA2322S, OPA4322, OPA4322S
特性
1
•
•
•
•
•
•
•
•
23
•
•
增益带宽： 20 MHz
低噪声： 8.5 nV/√Hz （在 1 kHz 频率条件下）
转换速率： 10 V/μs
低 THD + N：
： 0.0005%
轨至轨输入输出 (I/O)
失调电压： 2 mV （最大值）
电源电压： 1.8 V 至 5.5 V
电源电流： 每通道 1.5 mA
– 停机模式： 每个通道的静态电流为 0.1 μA
具有稳定的单位增益
小外形封装：
– SOT23, DFN, MSOP, TSSOP
应用范围
•
•
•
•
•
•
•
传感器信号调节
消费类音频
多极点有源滤波器
控制环路放大器
通信
安全
扫描仪
说明
OPA322 系列包含具有低噪声和轨至轨输入/输出的单
通道、双通道和四通道 CMOS 运算放大器，专为低功
耗、单电源应用而优化。 1.8 V 至 5.5 V 的宽电源范围
以及每通道仅 1.5 mA 的低静态电流，使得这些器件非
常适合于功耗敏感型应用。
由于兼具超低的噪声（在 1 kHz 频率下为 8.5 nV/√Hz
）、高的增益带宽 (20 MHz) 和高转换速率 (10
V/μs)，因而使得 OPA322 系列成为众多应用的理想选
择，包括信号调节及需要高增益的传感器放大。 另
外，OPA322 系列还拥有很低的 THD + N，因此同样
极为适合于消费类音频应用，尤其是单电源系统。
OPAx322S 型号的器件具有一种停机模式，该模式允
许将放大器从正常操作状态切换至待机状态 （待机电
流通常小于 0.1 μA）。
OPA322 （单通道版本） 采用 SOT23-5 和 SOT23-6
封装，而 OPA2322 （双通道版本） 则可提供 MSOP8、MSOP-10、SO-8 和 DFN-8 封装。 四通道版本
OPA4322 采用 TSSOP-14 和 TSSOP-16 封装。 所有
器件版本的规定工作温度范围均为 ―40℃ 至 +125℃
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
English Data Sheet: SBOS538
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE MARKING
OPA322
SOT23-5
DBV
RAD
OPA322S
SOT23-6
DBV
RAF
SO-8
D
O2322A
OPA2322
MSOP-8
DGK
OOZI
DFN-8
DRG
OPCI
OPA2322S
MSOP-10
DGS
OPBI
OPA4322
TSSOP-14
PW
O4322
OPA4322S
TSSOP-16
PW
O4322SA
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or visit
the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, VS = (V+) – (V–)
Signal input pins
Voltage (2)
UNIT
6
V
(V–) – 0.5 to (V+) + 0.5
V
±10
mA
Output short-circuit current (3)
Continuous
mA
Operating temperature, TA
–40 to +150
°C
Storage temperature, Tstg
–65 to +150
°C
Junction temperature, TJ
+150
°C
Human body model (HBM)
4000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
ESD ratings
(1)
(2)
(3)
2
Current
(2)
OPA322, OPA322S, OPA2322,
OPA2322S, OPA4322, OPA4322S
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V, or ±0.9 V to ±2.75 V
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN_x = VS+, unless otherwise noted.
OPA322, OPA322S, OPA2322,
OPA2322S, OPA4322, OPA4322S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input offset voltage
VOS
vs Temperature
dVOS/dT
vs Power supply
PSR
Over temperature
Channel separation
0.5
2
mV
VS = +5.5 V
1.8
6
μV/°C
VS = +1.8 V to +5.5 V
10
50
μV/V
VS = +1.8 V to +5.5 V
20
65
μV/V
At 1 kHz
130
dB
INPUT VOLTAGE
Common-mode voltage range
VCM
Common-mode rejection ratio
CMRR
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) + 0.1 V
Over temperature
90
(V+) + 0.1
100
V
dB
90
dB
INPUT BIAS CURRENT
Input bias current
IB
Over temperature
Input offset current
±10
pA
TA = –40°C to +85°C
±0.2
±50
pA
OPA322, OPA322S, TA = –40°C to +125°C
±800
pA
OPA2322, OPA2322S, TA = –40°C to +125°C
±400
pA
OPA4322, OPA4322S, TA = –40°C to +125°C
±400
pA
IOS
±0.2
Over temperature
±10
pA
TA = –40°C to +85°C
±50
pA
TA = –40°C to +125°C
±400
pA
NOISE
f = 0.1 Hz to 10 Hz
2.8
μVPP
f = 1 kHz
8.5
nV/√Hz
f = 10 kHz
7
nV/√Hz
f = 1 kHz
0.6
fA/√Hz
Differential
5
pF
Common-mode
4
pF
Input voltage noise
Input voltage noise density
en
Input current noise density
in
INPUT CAPACITANCE
OPEN-LOOP GAIN
Open-loop voltage gain
AOL
Phase margin
PM
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
100
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
94
VS = 5 V, CL = 50 pF
FREQUENCY RESPONSE
Gain bandwidth product
Slew rate
Settling time
(1)
dB
dB
47
Degrees
Unity gain
20
MHz
G = +1
10
V/μs
VS = 5.0 V, CL = 50 pF
GBP
SR
To 0.1%, 2-V step, G = +1
0.25
μs
To 0.01%, 2-V step, G = +1
0.32
μs
VIN × G > VS
100
ns
VO = 4 VPP, G = +1, f = 10 kHz, RL = 10 kΩ
0.0005
%
VO = 2 VPP, G = +1, f = 10 kHz, RL = 600 Ω
0.0011
%
tS
Overload recovery time
Total harmonic distortion +
noise (1)
130
THD+N
Third-order filter; bandwidth = 80 kHz at –3 dB.
Copyright © 2011–2012, Texas Instruments Incorporated
3
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V, or ±0.9 V to ±2.75 V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN_x = VS+, unless otherwise noted.
OPA322, OPA322S, OPA2322,
OPA2322S, OPA4322, OPA4322S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
20
mV
30
mV
OUTPUT
Voltage output swing from
both rails
VO
Over temperature
RL = 10 kΩ
RL = 10 kΩ
Short-circuit current
ISC
Capacitive load drive
CL
Open-loop output resistance
RO
VS = 5.5 V
±65
mA
See Typical Characteristics
IO = 0 mA, f = 1 MHz
Ω
90
POWER SUPPLY
Specified voltage range
Quiescent current per amplifier
VS
IQ
1.8
OPA322, OPA322S
IO = 0 mA, VS = +5.5 V
Over temperature
IO = 0 mA, VS = +5.5 V
OPA2322, OPA2322S
IO = 0 mA, VS = +5.5 V
Over temperature
IO = 0 mA, VS = +5.5 V
OPA4322, OPA4322S
IO = 0 mA, VS = +5.5 V
Over temperature
1.6
1.5
1.4
IO = 0 mA, VS = +5.5 V
Power-on time
VS+ = 0 V to 5 V, to 90% IQ level
SHUTDOWN (2)
VS = 1.8 V to 5.5 V
Quiescent current, per amplifier
IQSD
All amplifiers disabled, SHDN = VS–
High voltage (enabled)
VIH
Amplifier enabled
Low voltage (disabled)
VIL
Amplifier disabled
0.1
Amplifier enable time (partial
shutdown) (3)
tON
Partial shutdown; G = 1, VOUT = 0.9 × VS/2
SHDN pin input bias current (per pin)
mA
1.75
mA
1.85
mA
1.65
mA
1.75
mA
μs
0.5
(4)
(4)
µA
V
(V-) + 0.1
Full shutdown; G = 1, VOUT = 0.9 × VS/2
tOFF
mA
2
(V+) - 0.1
tON
Amplifier disable time
V
1.9
28
Amplifier enable time (full
shutdown) (3)
(3)
5.5
IO = 0 mA, VS = +5.5 V
V
10
µs
6
µs
G = 1, VOUT = 0.1 × VS/2
3
µs
VIH = 5.0 V
0.13
µA
VIL = 0 V
0.04
µA
TEMPERATURE
Specified range
–40
+125
°C
Operating range
–40
+150
°C
(2)
(3)
(4)
4
Ensured by design and characterization; not production tested.
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual OPA2322S having both channels A and B disabled (SHDN_A = SHDN_B = VS–) and the quad
OPA4322S having all channels A to D disabled (SHDN_A/B = SHDN_C/D = VS–). For partial shutdown, only one SHDN pin is exercised;
in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
THERMAL INFORMATION: OPA322
OPA322
THERMAL METRIC (1)
OPA322S
DBV
DBV
5 PINS
6 PINS
UNITS
θJA
Junction-to-ambient thermal resistance
219.3
177.5
θJC(top)
Junction-to-case(top) thermal resistance
107.5
108.9
θJB
Junction-to-board thermal resistance
57.5
27.4
ψJT
Junction-to-top characterization parameter
7.4
13.3
ψJB
Junction-to-board characterization parameter
56.9
26.9
θJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
n/a
(1)
°C/W
有关传统和全新热度量的更多信息，请参阅 IC 封装热度量 应用报告 （文献号：SPRA953）。
THERMAL INFORMATION: OPA2322
OPA2322
THERMAL METRIC (1)
OPA2322S
D
DRG
DGK
DGS
8 PINS
8 PINS
8 PINS
10 PINS
θJA
Junction-to-ambient thermal resistance
122.6
50.6
174.8
171.5
θJC(top)
Junction-to-case(top) thermal resistance
67.1
54.9
43.9
43.0
θJB
Junction-to-board thermal resistance
64.0
25.2
95.0
91.4
ψJT
Junction-to-top characterization parameter
13.2
0.6
2.0
1.9
ψJB
Junction-to-board characterization parameter
63.4
25.3
93.5
89.9
θJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
5.7
n/a
n/a
(1)
UNITS
°C/W
有关传统和全新热度量的更多信息，请参阅 IC 封装热度量 应用报告 （文献号：SPRA953）。
THERMAL INFORMATION: OPA4322
OPA4322
THERMAL METRIC (1)
OPA4322S
PW
PW
14 PINS
16 PINS
θJA
Junction-to-ambient thermal resistance
109.8
105.9
θJC(top)
Junction-to-case(top) thermal resistance
34.9
28.1
θJB
Junction-to-board thermal resistance
52.5
51.1
ψJT
Junction-to-top characterization parameter
2.2
0.8
ψJB
Junction-to-board characterization parameter
51.8
50.4
θJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
n/a
(1)
UNITS
°C/W
有关传统和全新热度量的更多信息，请参阅 IC 封装热度量 应用报告 （文献号：SPRA953）。
Copyright © 2011–2012, Texas Instruments Incorporated
5
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
OUT
1
V-
2
+IN
3
DRG PACKAGE(1)(2)
DFN-8
(TOP VIEW)
V+
5
OUT A
4
1
-IN A
2
+IN A
3
V-
4
-IN
DBV PACKAGE
SOT23-6
(TOP VIEW)
8
V+
7
OUT B
6
-IN B
5
+IN B
Exposed
Thermal
Die Pad
on
Underside
PW PACKAGE
TSSOP-14
(TOP VIEW)
VOUT
1
6
V+
V-
2
5
SHDN
+IN
3
4
-IN
OUT A
DGS PACKAGE
MSOP-10
(TOP VIEW)
VOUT A
1
10 V+
-IN A
2
9
VOUT B
+IN A
3
8
-IN B
1
14 OUT D
A
D
13 -IN D
-IN A
2
+IN A
3
12 +IN D
V+
4
11 V-
+IN B
5
10 +IN C
-IN B
6
OUT B
7
B
C
9
-IN C
8
OUT C
A
B
V-
4
7
+IN B
SHDN A
5
6
SHDN B
PW PACKAGE
TSSOP-16
(TOP VIEW)
OUT A
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
6
OUT A
1
-IN A
2
+IN A
3
V-
4
A
B
(1)
Connect thermal pad to V–.
(2)
Pad size: 2mm × 1.2mm.
8
V+
7
OUT B
6
-IN B
5
+IN B
1
16 OUT D
A
D
15 -IN D
-IN A
2
+IN A
3
14 +IN D
V+
4
13 V-
+IN B
5
12 +IN C
-IN B
6
OUT B
7
10 OUT C
SHDN A/B
8
9
B
C
11 -IN C
SHDN C/D
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
TYPICAL CHARACTERISTICS
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
OPEN-LOOP GAIN/PHASE vs FREQUENCY
125
-40
120
100
-60
115
80
-80
60
-100
40
-120
20
-140
-20
10
1
100
1k
10k
100k
1M
10M
Phase (°)
Gain
Phase
0
10 kW Load
Open-Loop Gain (dB)
RL = 10 kW, 50 pF
VS = ±2.5 V
120
Gain (dB)
OPEN-LOOP GAIN vs TEMPERATURE
-20
140
110
2 kW Load
105
100
95
-160
90
-180
100M
85
-50
-25
0
25
100
125
150
Figure 2.
INPUT BIAS CURRENT vs SUPPLY VOLTAGE
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
6
0.8
5
4
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
3
2
1
0
-1
-2
-3
IB+
IBIOS
-4
IBIB+
-0.8
-5
-6
2.9
-3 -2.5 -2 -1.5 -1 -0.5 0
Supply Voltage (±V)
0.5
1
1.5
2
3
2.5
Common-Mode Voltage (V)
Figure 3.
Figure 4.
INPUT BIAS CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
1.6
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-100
IOS
IB+
IB-
IB
IOS
Quiescent Current (mA/Ch)
Input Bias Current (pA)
75
Figure 1.
1
-1
50
Temperature (°C)
Input Bias Current (pA)
Input Bias Current (pA)
Frequency (Hz)
1.55
1.5
1.45
1.4
+125°C
+85°C
1.35
+25°C
-40°C
1.3
-50
-25
0
25
50
75
Temperature (°C)
Figure 5.
Copyright © 2011–2012, Texas Instruments Incorporated
100
125
150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Figure 6.
7
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION HISTOGRAM
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
1
14
0.8
0.6
Offset Voltage (mV)
Number of Amplifiers (%)
12
10
8
6
4
0.4
0.2
0
-0.2
-0.4
-0.6
2
Representative Units
VS = ±2.75 V
-0.8
0
-3
1.5
1.1
1.3
0.9
0.5
0.7
0.1
0.3
-0.1
-0.3
-0.5
-0.7
-1.1
-0.9
-1.3
-1.5
-1
-2
0
-1
1
3
2
Common-Mode Voltage (V)
Offset Voltage (mV)
Figure 7.
Figure 8.
INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
0.1 Hz TO 10 Hz INPUT VOLTAGE NOISE
6
VS = 1.8 V to 5.5 V
5
4
3
100
Voltage (mV)
Voltage Noise (nV/ÖHz)
1000
10
2
1
0
-1
-2
-3
1
-4
10
100
1k
10 k
1M
100 k
0
1
2
3
Frequency (Hz)
G = +10 V/V
-20
10 k
8
1M
8
9
10
10 M
100 M
VS = +5.5 V
RL = 10 kW
CL = 50 pF
G = +100 V/V
20
G = +10 V/V
0
G = +1 V/V
100 k
40
Gain (dB)
Gain (dB)
20
0
7
CLOSED-LOOP GAIN vs FREQUENCY
60
VS = +1.8 V
RL = 10 kW
CL = 50 pF
G = +100 V/V
6
Figure 10.
CLOSED-LOOP GAIN vs FREQUENCY
40
5
Time (s)
Figure 9.
60
4
-20
10 k
G = +1 V/V
100 k
1M
Frequency (Hz)
Frequency (Hz)
Figure 11.
Figure 12.
10 M
100 M
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
6
3
5.5 VS
2
4
Output Voltage (V)
Output Voltage (VPP)
5
3.3 VS
3
2
1
-40°C
+25°C
+125°C
0
-1
1.8 VS
1
-2
RL = 10 kW
CL = 50 pF
VS = ±2.75 V
0
10 k
-3
100 k
10 M
1M
10
0
20
30
Frequency (Hz)
40
50
70
80
Figure 13.
Figure 14.
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
1000
70
G = 1, VS = 1.8 V
VS = ±2.75 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
50
Overshoot (%)
Impedance (W)
60
Output Current (mA)
100
G = 10, VS = 5.5 V
40
30
20
10
0
10
1
10
100
1k
10 k
100 k
1M
10 M 100 M
500
0
1000
Frequency (Hz)
Figure 15.
2500
3000
THD+N vs FREQUENCY
Total Harmonic Distortion and Noise (%)
Total Harmonic Distortion and Noise (%)
THD+N vs AMPLITUDE
0.01
Load = 600 W
0.001
Frequency = 10 kHz
VS = ±2.5 V
G = +1 V/V
Load = 10 kW
0.1
2000
Figure 16.
0.1
0.0001
0.01
1500
Capacitive Load (pF)
1
VIN (VPP)
Figure 17.
Copyright © 2011–2012, Texas Instruments Incorporated
10
0.1
Frequency = 10 kHz
VIN = 2 VPP
VS = ±2.5 V
G = +1 V/V
0.01
Load = 600 W
0.001
Load = 10 kW
0.0001
10
100
1k
10 k
100 k
Frequency (Hz)
Figure 18.
9
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
CHANNEL SEPARATION vs FREQUENCY (for Dual)
0
Frequency = 10 kHz
VIN = 4 VPP
VS = ±2.5 V
G = +1 V/V
VS = ±2.75 V
-20
Channel Separation (dB)
Total Harmonic Distortion and Noise (%)
THD+N vs FREQUENCY
0.1
0.01
Load = 600 W
0.001
-60
-80
-100
-120
Load = 10 kW
0.0001
-40
-140
10
100
1k
1k
100 k
10 k
10 k
1M
Frequency (Hz)
Figure 19.
Figure 20.
SLEW RATE vs SUPPLY VOLTAGE
100 M
10 M
SMALL-SIGNAL STEP RESPONSE
0.1
12
CL = 50 pF
Gain = +1
VS = ±2.75 V
VIN = 100 mVPP
0.075
11.5
0.05
11
Voltage (V)
Slew Rate (V/ms)
100 k
Frequency (Hz)
Rise
10.5
Fall
10
0.025
0
-0.025
-0.05
9.5
VOUT
VIN
-0.075
9
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
-0.1
-0.8
5.6
-0.4
0
0.4
Supply Voltage (V)
Figure 21.
SMALL-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE vs TIME
1.5
0.075
VIN
Gain = -1
VS = ±2.75 V
VIN = 100 mVPP
Voltage (V)
Voltage (V)
Gain = +1
VS = ±2.75 V
VIN = 2 VPP
1
0.05
0
1.6
1.2
Figure 22.
0.1
0.025
0.8
Time (ms)
-0.025
0.5
VOUT
0
-0.5
-0.05
-0.1
-1.6
-1.2
-0.8
-0.4
Time (ms)
Figure 23.
10
-1
VOUT
VIN
-0.075
0
0.4
0.8
-1.5
-0.4
0
0.4
0.8
1.2
1.6
Time (ms)
Figure 24.
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
CMRR AND PSRR vs FREQUENCY
TURN-OFF TRANSIENT
3
Shutdown Signal
Output Signal
2.4
100
1.8
1.2
80
Voltage (V)
Common-Mode Rejection Ratio,
Power-Supply Rejection Ratio (dB)
120
60
40
0.6
0
−0.6
−1.2
−1.8
20
PSRR
CMRR
−2.4
−3
0
1k
100
10k
100k
1M
0
2
4
6
8
Frequency (Hz)
TURN-ON AND TURN-OFF TRANSIENT 5.5V
(High Supply)
Voltage (V)
Voltage (V)
1.2
0.6
0
−0.6
−1.2
−1.8
Shutdown Signal
Output Signal
−2.4
4
18
TURN-ON TRANSIENT
1.8
2
16
Figure 26.
3
0
14
Figure 25.
2.4
−3
10
12
Time (µs)
6
8
10
12
Time (µs)
14
16
18
20
G000
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
−4.5
−5
20
G000
Shutdown Signal
Output Signal
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
G000
Figure 27.
Figure 28.
TURN-ON AND TURN-OFF TRANSIENT 1.8V
(Low Supply)
2
1.5
Voltage (V)
1
0.5
0
−0.5
−1
Shutdown Signal
Output Signal
−1.5
−2
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
G000
Figure 29.
Copyright © 2011–2012, Texas Instruments Incorporated
11
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
APPLICATION INFORMATION
OPERATING VOLTAGE
The OPA322 series op amps are unity-gain stable and can operate on a single-supply voltage (1.8 V to 5.5 V), or
a split-supply voltage (±0.9 V to ±2.75 V), making them highly versatile and easy to use. The power-supply pins
should have local bypass ceramic capacitors (typically 0.001 μF to 0.1 μF). These amplifiers are fully specified
from +1.8 V to +5.5 V and over the extended temperature range of –40°C to +125°C. Parameters that can exhibit
variance with regard to operating voltage or temperature are presented in the Typical Characteristics.
INPUT AND ESD PROTECTION
The OPA322 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as
the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Many input signals are
inherently current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 30 shows how a
series input resistor (RS) may be added to the driven input to limit the input current. The added resistor
contributes thermal noise at the amplifier input and the value should be kept to the minimum in noise-sensitive
applications.
V+
IOVERLOAD
10 mA, Max
VOUT
OPA322
VIN
RS
Figure 30. Input Current Protection
PHASE REVERSAL
The OPA322 op amps are designed to be immune to phase reversal when the input pins exceed the supply
voltages, therefore providing further in-system stability and predictability. Figure 31 shows the input voltage
exceeding the supply voltage without any phase reversal.
4
VIN
VS = ±2.5 V
3
Voltage (V)
2
VOUT
1
0
-1
-2
-3
-4
-500
-250
0
250
500
750
1000
Time (ms)
Figure 31. No Phase Reversal
12
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a
feedback capacitor across the feedback resistor, RF, as shown in Figure 32. This capacitor compensates for the
zero created by the feedback network impedance and the OPA322 input capacitance (and any parasitic layout
capacitance). The effect becomes more significant with higher impedance networks.
CF
RIN
RF
VIN
V+
CIN
RIN ´ CIN = RF ´ CF
OPA322
VOUT
CL
CIN
NOTE: Where CIN is equal to the OPA322 input capacitance (approximately 9 pF) plus any parasitic layout capacitance.
Figure 32. Feedback Capacitor Improves Dynamic Performance
It is suggested that a variable capacitor be used for the feedback capacitor because input capacitance may vary
between op amps and layout capacitance is difficult to determine. For the circuit shown in Figure 32, the value of
the variable feedback capacitor should be chosen so that the input resistance times the input capacitance of the
OPA322 (typically 9 pF) plus the estimated parasitic layout capacitance equals the feedback capacitor times the
feedback resistor:
RIN × CIN = RF × CF
Where:
CIN is equal to the OPA322 input capacitance (sum of differential and common-mode) plus the layout
capacitance.
The capacitor value can be adjusted until optimum performance is obtained.
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
device, the dc offset observed at the amplifier output may shift from the nominal value while EMI is present. This
shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational
amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA322
operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to
EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a
cutoff frequency of approximately 580 MHz (–3 dB), with a roll-off of 20 dB per decade.
OUTPUT IMPEDANCE
The open-loop output impedance of the OPA322 common-source output stage is approximately 90 Ω. When the
op amp is connected with feedback, this value is reduced significantly by the loop gain. For each decade rise in
the closed-loop gain, the loop gain is reduced by the same amount, which results in a ten-fold increase in
effective output impedance. While the OPA322 output impedance remains very flat over a wide frequency range,
at higher frequencies the output impedance rises as the open-loop gain of the op amp drops. However, at these
frequencies the output also becomes capacitive as a result of parasitic capacitance. This characteristic, in turn,
prevents the output impedance from becoming too high, which can cause stability problems when driving large
capacitive loads. As mentioned previously, the OPA322 has excellent capacitive load drive capability for an op
amp with its bandwidth.
Copyright © 2011–2012, Texas Instruments Incorporated
13
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
CAPACITIVE LOAD AND STABILITY
The OPA322 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA322 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier is stable in operation. An op amp in the unity-gain (+1 V/V) buffer configuration and driving a capacitive
load exhibits a greater tendency to become unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA322 remains stable with a pure capacitive load up to
approximately 1 nF.
The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains, as shown in Figure 33. One technique
for increasing the capacitive load drive capability of the amplifier operating in unity gain is to insert a small
resistor (RS), typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 34.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing. The error contributed by the voltage divider, however, may be insignificant. For
instance, with a load resistance, RL = 10 kΩ and RS = 20 Ω, the gain error is only about 0.2%. However, when RL
is decreased to 600 Ω, which the OPA322 is able to drive, the error increases to 7.5%.
70
G = 1, VS = 1.8 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
Overshoot (%)
50
G = 10, VS = 5.5 V
40
30
20
10
0
0
500
1000
1500
2000
2500
3000
Capacitive Load (pF)
Figure 33. Small-Signal Overshoot versus Capacitive Load (100-mVPP output step)
V+
RS
VOUT
OPA322
VIN
10 W to
20 W
RL
CL
Figure 34. Improving Capacitive Load Drive
14
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
OVERLOAD RECOVERY TIME
Overload recovery time is the time required for the output of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly important in applications where small signals must be
amplified in the presence of large transients. Figure 35 and Figure 36 show the positive and negative overload
recovery times of the OPA322, respectively. In both cases, the time elapsed before the OPA322 comes out of
saturation is less than 100 ns. In addition, the symmetry between the positive and negative recovery times allows
excellent signal rectification without distortion of the output signal.
3
2.5
Output
0.5
Input
2
0
1.5
-0.5
Voltage (V)
Voltage (V)
1
VS = ±2.75 V
G = -10
1
0.5
0
-1
-1.5
-2
Input
Output
-0.5
VS = ±2.75 V
G = -10
-2.5
-1
9.75
10
10.25
10.5
10.75
Time (250 ns/div)
Figure 35. Positive Recovery Time
11
-3
9.75
10
10.25
10.5
10.75
11
Time (250 ns/div)
Figure 36. Negative Recovery Time
SHUTDOWN FUNCTION
The SHDN (enable) pin function of the OPAx322S is referenced to the negative supply voltage of the operational
amplifier. A logic level high enables the op amp. A valid logic high is defined as voltage [(V+) – 0.1 V], up to (V+),
applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–), applied to the enable pin.
The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative supply, independent of the
positive supply voltage. This pin should either be connected to a valid high or a low voltage or driven, and not left
as an open circuit.
The logic input is a high-impedance CMOS input. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown of
all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This architecture
allows the OPAx322S to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases with increased
load resistance. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required. If using the OPAx322S without a load, the resulting turn-off time is significantly
increased.
GENERAL LAYOUT GUIDELINES
The OPA322 is a wideband amplifier. To realize the full operational performance of the device, follow good highfrequency printed circuit board (PCB) layout practices. The bypass capacitors must be connected between each
supply pin and ground as close to the device as possible. The bypass capacitor traces should be designed for
minimum inductance.
LEADLESS DFN PACKAGE
The OPA2322 uses the DFN style package (also known as SON), which is a QFN with contacts on only two
sides of the package bottom. This leadless package maximizes PCB space and offers enhanced thermal and
electrical characteristics through an exposed pad. One of the primary advantages of the DFN package is its low
height (0,8 mm).
DFN packages are physically small, and have a smaller routing area. Additionally, they offer improved thermal
performance, reduced electrical parasitics, and a pinout scheme that is consistent with other commonly-used
packages (such as SO and MSOP). The absence of external leads also eliminates bent-lead issues.
Copyright © 2011–2012, Texas Instruments Incorporated
15
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com.cn
The DFN package can easily be mounted using standard PCB assembly techniques. See the application reports,
QFN/SON PCB Attachment (SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017), both available
for download at www.ti.com. The exposed leadframe die pad on the bottom of the DFN package should be
connected to the most negative potential (V–). The dimension of the exposed thermal die pad is 2 mm ×
1,2 mm and is centered.
APPLICATION EXAMPLES
ACTIVE FILTER
The OPA322 is well-suited for active filter applications that require a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. Figure 37 shows a 500-kHz, second-order, low-pass filter using the multiplefeedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth response.
Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is ideal for applications that require
predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of these options:
1. adding an inverting amplifier;
2. adding an additional second-order MFB stage; or
3. using a noninverting filter topology, such as the Sallen-Key (shown in Figure 38).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
R3
549 W
C2
150 pF
R1
549 W
R2
1.24 kW
V+
VIN
VOUT
OPA322
C1
1 nF
V-
Figure 37. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
V+
1.8 kW
19.5 kW
150 kW
VIN = 1 VRMS
3.3 nF
47 pF
OPA322
VOUT
V-
Figure 38. OPA322 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
16
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com.cn
ZHCS022E – JANUARY 2011 – REVISED JUNE 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2012) to Revision E
Page
•
Changed product status from Production Data to Mixed Status .......................................................................................... 1
•
Updated D, DGK pinout drawing .......................................................................................................................................... 6
•
Added Figure 26 to Figure 29 ............................................................................................................................................. 11
•
Added Shutdown Function section ..................................................................................................................................... 15
Changes from Revision C (November 2011) to Revision D
Page
•
Changed product status from Mixed Status to Production Data .......................................................................................... 1
•
Deleted shading and footnote 2 from Package/Ordering Information table ......................................................................... 2
•
Added OPA4322, OPA4322S to the Input Bias Current, Input bias current, Over temperature parameter in Electrical
Characteristics table ............................................................................................................................................................. 3
•
Changed Power Supply, OPA4322, OPA4322S Over temperature parameter maximum specification in the Electrical
Characteristics table ............................................................................................................................................................. 4
Changes from Revision B (July 2011) to Revision C
•
Page
Changed status of OPA2322 SO-8 (D) to production data from product preview ................................................................ 2
Changes from Revision A (May 2011) to Revision B
Page
•
Updated OPA322 SOT23-5 device status from product preview to production data in Package/Ordering Information
table ...................................................................................................................................................................................... 2
•
Changed Input Bias Current Input bias current, Over temperature parameter in Electrical Characteristics table ............... 3
•
Changed Open-Loop Gain, Open-loop voltage gain parameter typical specification in the Electrical Characteristics
table ...................................................................................................................................................................................... 3
•
Changed Open-Loop Gain, Phase margin parameter test conditions in the Electrical Characteristics table ...................... 3
•
Added test conditions to Power Supply section in Electrical Characteristics table .............................................................. 4
•
Changed Power Supply, Quiescent current per amplifier OPA322/S parameter maximum specification in the
Electrical Characteristics ....................................................................................................................................................... 4
•
Changed Power Supply, OPA322 Over temperature parameter maximum specification in the Electrical
Characteristics table ............................................................................................................................................................. 4
•
Changed Power Supply, Quiescent current per amplifier OPA4322/S parameter typical specification in the Electrical
Characteristics ...................................................................................................................................................................... 4
•
Changed Shutdown, Quiescent current, per amplifier parameter maximum specification in Electrical Characteristics
table ...................................................................................................................................................................................... 4
•
Added OPA322S thermal information to Thermal Information: OPA322 table ..................................................................... 5
•
Added OPA2322S thermal information to Thermal Information: OPA2322 table ................................................................. 5
•
Added OPA4322S thermal information to Thermal Information: OPA4322 table ................................................................. 5
•
Updated Figure 1 .................................................................................................................................................................. 7
•
Added Figure 25 ................................................................................................................................................................. 11
•
Changed Overload Recovery Time section ........................................................................................................................ 15
Copyright © 2011–2012, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2025
PACKAGING INFORMATION
Orderable part number
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
OPA2322AID
Active
Production
SOIC (D) | 8
75 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2322A
OPA2322AID.A
Active
Production
SOIC (D) | 8
75 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2322A
OPA2322AIDGKR
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
Call TI | Nipdauag
| Nipdau | Nipdau
Level-2-260C-1 YEAR
-40 to 125
OOZI
OPA2322AIDGKR.A
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OOZI
OPA2322AIDGKRG4
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OOZI
OPA2322AIDGKRG4.A
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OOZI
OPA2322AIDGKT
Active
Production
VSSOP (DGK) | 8
250 | SMALL T&R
Yes
Call TI | Nipdauag
| Nipdau | Nipdau
Level-2-260C-1 YEAR
-40 to 125
OOZI
OPA2322AIDGKT.A
Active
Production
VSSOP (DGK) | 8
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OOZI
OPA2322AIDR
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2322A
OPA2322AIDR.A
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2322A
OPA2322AIDRG4
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2322A
OPA2322AIDRG4.A
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2322A
OPA2322AIDRGR
Active
Production
SON (DRG) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
OPA2322AIDRGR.A
Active
Production
SON (DRG) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
OPA2322AIDRGRG4
Active
Production
SON (DRG) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
OPA2322AIDRGRG4.A
Active
Production
SON (DRG) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
OPA2322AIDRGT
Active
Production
SON (DRG) | 8
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
OPA2322AIDRGT.A
Active
Production
SON (DRG) | 8
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
OPA2322SAIDGSR
Active
Production
VSSOP (DGS) | 10
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
OPA2322SAIDGSR.A
Active
Production
VSSOP (DGS) | 10
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
OPA2322SAIDGST
Active
Production
VSSOP (DGS) | 10
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
OPA2322SAIDGST.A
Active
Production
VSSOP (DGS) | 10
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
OPA2322SAIDGSTG4
Active
Production
VSSOP (DGS) | 10
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
OPA2322SAIDGSTG4.A
Active
Production
VSSOP (DGS) | 10
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
NIPDAU | SN | NIPDAU Level-2-260C-1 YEAR
OPA322AIDBVR
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
-40 to 125
RAD
OPA322AIDBVR.A
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAD
OPA322AIDBVRG4
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAD
OPA322AIDBVRG4.A
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAD
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable part number
(1)
17-Jun-2025
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
OPA322AIDBVT
Active
Production
SOT-23 (DBV) | 5
OPA322AIDBVT.A
Active
Production
OPA322SAIDBVR
Active
Production
OPA322SAIDBVR.A
Active
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAD
SOT-23 (DBV) | 5
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAD
SOT-23 (DBV) | 6
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
Production
SOT-23 (DBV) | 6
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
OPA322SAIDBVRG4
Active
Production
SOT-23 (DBV) | 6
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
OPA322SAIDBVRG4.A
Active
Production
SOT-23 (DBV) | 6
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
OPA322SAIDBVT
Active
Production
SOT-23 (DBV) | 6
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
OPA322SAIDBVT.A
Active
Production
SOT-23 (DBV) | 6
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
OPA4322AIPW
Active
Production
TSSOP (PW) | 14
90 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322A
OPA4322AIPW.A
Active
Production
TSSOP (PW) | 14
90 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322A
OPA4322AIPWR
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322A
OPA4322AIPWR.A
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322A
OPA4322SAIPW
Active
Production
TSSOP (PW) | 16
90 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322SA
OPA4322SAIPW.A
Active
Production
TSSOP (PW) | 16
90 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322SA
OPA4322SAIPWR
Active
Production
TSSOP (PW) | 16
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322SA
OPA4322SAIPWR.A
Active
Production
TSSOP (PW) | 16
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322SA
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2025
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2322, OPA322, OPA4322 :
• Automotive : OPA2322-Q1, OPA322-Q1, OPA4322-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2322AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2322AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2322AIDGKRG4
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2322AIDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2322AIDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2322AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2322AIDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2322AIDRGR
SON
DRG
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2322AIDRGRG4
SON
DRG
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2322AIDRGT
SON
DRG
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2322SAIDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2322SAIDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2322SAIDGSTG4
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA322AIDBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
OPA322AIDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.15
3.1
1.55
4.0
8.0
Q3
OPA322AIDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
OPA322AIDBVRG4
SOT-23
DBV
5
3000
180.0
8.4
OPA322AIDBVT
SOT-23
DBV
5
250
180.0
8.4
OPA322AIDBVT
SOT-23
DBV
5
250
180.0
OPA322SAIDBVRG4
SOT-23
DBV
6
3000
OPA322SAIDBVT
SOT-23
DBV
6
250
OPA4322AIPWR
TSSOP
PW
14
OPA4322SAIPWR
TSSOP
PW
16
3.2
3.2
1.4
4.0
8.0
Q3
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.15
3.1
1.55
4.0
8.0
Q3
180.0
8.4
3.15
3.1
1.55
4.0
8.0
Q3
180.0
8.4
3.15
3.1
1.55
4.0
8.0
Q3
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2322AIDGKR
VSSOP
DGK
8
2500
353.0
353.0
32.0
OPA2322AIDGKR
VSSOP
DGK
8
2500
356.0
356.0
35.0
OPA2322AIDGKRG4
VSSOP
DGK
8
2500
356.0
356.0
35.0
OPA2322AIDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA2322AIDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA2322AIDR
SOIC
D
8
2500
356.0
356.0
35.0
OPA2322AIDRG4
SOIC
D
8
2500
356.0
356.0
35.0
OPA2322AIDRGR
SON
DRG
8
3000
356.0
356.0
35.0
OPA2322AIDRGRG4
SON
DRG
8
3000
356.0
356.0
35.0
OPA2322AIDRGT
SON
DRG
8
250
210.0
185.0
35.0
OPA2322SAIDGSR
VSSOP
DGS
10
2500
356.0
356.0
35.0
OPA2322SAIDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
OPA2322SAIDGSTG4
VSSOP
DGS
10
250
210.0
185.0
35.0
OPA322AIDBVR
SOT-23
DBV
5
3000
213.0
191.0
35.0
OPA322AIDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
OPA322AIDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
OPA322AIDBVRG4
SOT-23
DBV
5
3000
210.0
185.0
35.0
OPA322AIDBVT
SOT-23
DBV
5
250
210.0
185.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA322AIDBVT
SOT-23
DBV
5
250
210.0
185.0
35.0
OPA322SAIDBVRG4
SOT-23
DBV
6
3000
210.0
185.0
35.0
OPA322SAIDBVT
SOT-23
DBV
6
250
210.0
185.0
35.0
OPA4322AIPWR
TSSOP
PW
14
2000
356.0
356.0
35.0
OPA4322SAIPWR
TSSOP
PW
16
2000
356.0
356.0
35.0
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA2322AID
D
SOIC
8
75
506.6
8
3940
4.32
OPA2322AID.A
D
SOIC
8
75
506.6
8
3940
4.32
OPA4322AIPW
PW
TSSOP
14
90
530
10.2
3600
3.5
OPA4322AIPW.A
PW
TSSOP
14
90
530
10.2
3600
3.5
OPA4322SAIPW
PW
TSSOP
16
90
530
10.2
3600
3.5
OPA4322SAIPW.A
PW
TSSOP
16
90
530
10.2
3600
3.5
Pack Materials-Page 5
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
B
6
2X 0.95
1.9
0.1 C
A
3.05
2.75
5
2
4
6X
0.2
0.50
0.25
C A B
3
4X 0 -15
(1.1)
0.15
TYP
0.00
1.45
0.90
4X 4 -15
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/G 08/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/G 08/2024
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/G 08/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0014A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1
2X
5.1
4.9
NOTE 3
3.9
4X (0 -12 )
7
8
14X
B
4.5
4.3
NOTE 4
0.30
0.17
0.1
C A B
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220202/B 12/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0014A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (1.5)
(R0.05) TYP
1
14
14X (0.45)
SYMM
12X (0.65)
8
7
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220202/B 12/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0014A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
14X (1.5)
SYMM
(R0.05) TYP
1
14X (0.45)
14
SYMM
12X (0.65)
8
7
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220202/B 12/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
A
5
(0.1)
2X 0.95
1.9
0.1 C
B
3.05
2.75
1.9
2
(0.15)
4
0.5
5X
0.3
0.2
3
C A B
NOTE 5
4X 0 -15
(1.1)
0.15
TYP
0.00
1.45
0.90
4X 4 -15
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/K 08/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/K 08/2024
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/K 08/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGK0008A
VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
0.25
GAGE PLANE
1.1 MAX
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
TYPICAL
4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGK0008A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (1.4)
8X (0.45)
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214862/A 04/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGK0008A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(4.4)
SOLDER PASTE EXAMPLE
SCALE: 15X
4214862/A 04/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRG 8
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3 x 3, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225794/A
www.ti.com
PACKAGE OUTLINE
DRG0008A
WSON - 0.8 mm max height
SCALE 5.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
1.2 0.1
4
5
2X
1.5
2 0.1
8
1
6X 0.5
8X
PIN 1 ID
8X
0.6
0.4
0.3
0.2
0.1
0.08
C A B
C
4218885/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.2)
SYMM
8X (0.7)
8
1
8X (0.25)
SYMM
(2)
(0.75)
6X (0.5)
4
(R0.05) TYP
5
( 0.2) VIA
TYP
(0.35)
(2.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218885/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.7)
8X (0.25)
METAL
TYP
8
1
SYMM
(1.79)
6X (0.5)
4
5
(R0.05) TYP
(1.13)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218885/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要通知和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的相关应用。 严禁以其他方式对这些资源进行
复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索
赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
版权所有 © 2025，德州仪器 (TI) 公司
