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OPA333-Q1
SBOS522A – JUNE 2010 – REVISED NOVEMBER 2019
OPA333-Q1 Automotive, 1.8-V, Micropower, CMOS, Zero-Drift Operational Amplifier
1 Features
3 Description
•
The OPA333-Q1 CMOS operational amplifier uses a
proprietary
autocalibration
technique
to
simultaneously provide verylow offset voltage (10 μV
maximum) and near-zero drift over time and
temperature. This miniature, high-precision, lowquiescent-current amplifier offers high-impedance
inputs that have a common-mode range 100 mV
beyond the rails, and rail-to-rail output that swings
within 50 mV of the rails. The device can use single
or dual supplies as low as 1.8 V (±0.9 V) and up to
5.5 V (±2.75 V), and is optimized for low-voltage
single-supply operation.
1
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Low offset voltage: 10 μV (maximum)
0.01-Hz to 10-Hz noise: 1.1 μVPP
Quiescent current: 17 μA
Single-supply operation
Supply voltage: 1.8 V to 5.5 V
Rail-to-rail input and output
Microsize 5-pin SOT-23 (DBV) package
2 Applications
•
•
•
•
•
Pump
Position sensor
Vehicle occupant detection sensor
Brake system
Airbag
The OPA333-Q1 device offers excellent commonmode rejection ratio (CMRR) without the crossover
associated with traditional complementary input
stages. This design results in superior performance
for driving analog-to-digital converters (ADCs) without
degradation of differential linearity.
Device Information(1)
PART NUMBER
OPA333-Q1
PACKAGE
SOT-23 (5)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
500 nV/div
0.1-Hz to 10-Hz Noise
1 s/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA333-Q1
SBOS522A – JUNE 2010 – REVISED NOVEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Applications ................................................ 11
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Original (June 2010) to Revision A
Page
•
Changed part number references from OPA333 to OPA333-Q1 throughout text.................................................................. 1
•
Added Pin Configuration and Functions, ESD Ratings, Thermal Information, Feature Description , Device Functional
Modes, Application and Implementation, Power Supply Recommendations, Layout , Device and Documentation
Support , and Mechanical, Packaging, and Orderable Information sections ......................................................................... 1
•
Deleted redundant Ordering Information table; same information already in the package option addendum ....................... 1
•
Changed pinout drawing for accuracy; no change to pin names or pin numbers ................................................................. 3
•
Deleted "one amplifier per package" from note 2 in Absolute Maximum Ratings table ......................................................... 4
•
Changed the TYP and MAX values for the input offset voltage drift parameter in the Electrical Characteristics table ......... 5
•
Added text to Figure 3, Open-Loop Gain vs Frequency, for clarity........................................................................................ 6
•
Deleted Single-Supply, Very-Low-Power ECG Circuit (previously, Figure 9) ...................................................................... 17
2
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
V+
4
-IN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
+IN
3
I
Noninverting input
–IN
4
I
Inverting input
OUT
1
O
Output
V+
5
I
Positive (high) power supply
V–
2
I
Negative (low) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
Signal input pins, voltage
(2)
–0.3
Output short circuit (3)
TJ
Tstg
(1)
(2)
(3)
(4)
7
V
(V+) + 0.3
V
Continuous
Junction temperature
150
°C
Storage temperature
(4)
°C
–65
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current-limited to 10 mA or less.
Short-circuit to ground.
Long-term high-temperature storage, extended use at maximum recommended operating conditions, or both cases may result in a
reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
Device HBM ESD classification level 3A
±4000
Charged-device model (CDM), per AEC Q100-011
Device CDM ESD classification level C6
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage
1.8
5.5
UNIT
V
TA
Specified temperature
–40
125
°C
6.4 Thermal Information
OPA333-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
220.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
97.5
°C/W
RθJB
Junction-to-board thermal resistance
61.7
°C/W
ψJT
Junction-to-top characterization parameter
7.6
°C/W
ψJB
Junction-to-board characterization parameter
61.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at VS = 1.8 V to 5.5 V, TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, VO = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 5 V
dVOS/dT
Input offset voltage drift
VS = 5 V, TA = –40°C to +125°C
PSRR
Power supply rejection ratio
VS = 1.8 V to 5.5 V,
TA = –40°C to +125°C
Long-term stability (1)
2
10
0.02
0.05
μV/°C
1
6
μV/V
See
Channel separation, dc
μV
(1)
0.1
μV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±70
TA = –40°C to +125°C
±200
pA
±200
pA
±140
±400
pA
NOISE
Input voltage noise
in
Input current noise
f = 0.01 Hz to 1 Hz
0.3
f = 0.1 Hz to 10 Hz
1.1
μVPP
f = 10 Hz
100
fA/√Hz
μVPP
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
CMRR
Common-mode rejection ratio
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) + 0.1 V ,
TA = –40°C to +125°C
106
(V+) + 0.1
V
130
dB
Differential
2
pF
Common mode
4
pF
130
dB
INPUT CAPACITANCE
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 100 mV < VO < (V+) – 100 mV,
RL = 10 kΩ, TA = –40°C to +125°C
106
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 100 pF
350
kHz
SR
Slew rate
G=1
0.16
V/μs
OUTPUT
Voltage output swing from rail
ISC
Short-circuit current
CL
Capacitive load drive
RL = 10 kΩ
30
RL = 10 kΩ, TA = –40°C to +125°C
50
mV
85
mV
±5
mA
See Typical Characteristics
Open-loop output impedance
f = 350 kHz, IO = 0 A
Quiescent current per amplifier
IO = 0 A
Quiescent current per
amplifier over temperature
TA = –40°C to +125°C
Turn-on time
VS = 5 V
2
kΩ
POWER SUPPLY
IQ
(1)
17
25
μA
30
μA
100
μs
300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.
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6.6 Typical Characteristics
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
0
0.0025
0.0050
0.0075
0.0100
0.0125
0.0150
0.0175
0.0200
0.0225
0.0250
0.0275
0.0300
0.0325
0.0350
0.0375
0.0400
0.0425
0.0450
0.0475
0.0500
Population
Population
at TA = 25°C, VS = 5 V, and CL = 0 pF (unless otherwise noted)
Offset Voltage (mV)
Offset Voltage Drift (mV/°C)
Figure 2. Offset Voltage Production Distribution
Figure 1. Offset Voltage Production Distribution
140
100
200
120
150
100
AOL (dB)
80
Phase
60
100
40
50
20
CMRR (dB)
250
Phase (°)
120
80
60
0
40
-50
20
-100
0
Gain
0
-20
10
100
1k
10k
100k
1
1M
10
100
1k
10k
3
VS = ±2.75 V
VS = ±0.9 V
+PSRR
2
-PSRR
Output Swing (V)
PSRR (dB)
100
60
40
20
0
6
-40°C
1
+25°C
+125°C
0
+25°C
-40°C
-1
+125°C
+25°C
-2
1
10
100
1k
1M
Figure 4. Common-Mode Rejection Ratio vs Frequency
Figure 3. Open-Loop Gain vs Frequency
120
80
100k
Frequency (Hz)
Frequency (Hz)
10k
100k
1M
-40°C
-3
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Output Current (mA)
Figure 5. Power-Supply Rejection Ratio vs Frequency
Figure 6. Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
100
200
80
150
-IB
60
100
40
-IB
50
IB (pA)
20
IB (pA)
VS = 5.5 V
VS = 1.8 V
-IB
0
0
-20
+IB
-50
-40
-100
-60
+IB
-200
-100
0
1
+IB
-150
-80
2
3
4
5
-50
0
-25
Common-Mode Voltage (V)
25
50
75
100
125
Temperature (°C)
VS = 5 V
Figure 7. Input Bias Current vs Common-Mode Voltage
Figure 8. Input Bias Current vs Temperature
25
G=1
RL = 10 kW
Output Voltage (1 V/div)
20
IQ (mA)
VS = 5.5 V
15
VS = 1.8 V
10
5
0
-50
-25
0
25
50
75
100
125
Temperature (°C)
Time (50 ms/div)
RL = 10 kΩ
G=1
2 V/div
Figure 10. Large-Signal Step Response
G = +1
RL = 10 kW
0
Input
Output
10 kW
+2.5 V
1 kW
1 V/div
Output Voltage (50 mV/div)
Figure 9. Quiescent Current vs Temperature
0
OPA333-Q1
-2.5 V
Time (5 ms/div)
G=1
Time (50 ms/div)
RL = 10 kΩ
Figure 11. Small-Signal Step Response
Figure 12. Positive Overvoltage Recovery
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Typical Characteristics (continued)
600
Input
Settling Time (ms)
1 V/div
2 V/div
4-V Step
500
0
0
10 kW
+2.5 V
1 kW
400
300
200
0.001%
Output
OPA333-Q1
100
0.01%
-2.5 V
0
1
Time (50 ms/div)
10
100
Gain (dB)
4-V step
Figure 14. Settling Time vs Closed-Loop Gain
Figure 13. Negative Overvoltage Recovery
40
35
25
500nV/div
Overshoot (%)
30
20
15
10
5
0
10
100
1000
1s/div
Load Capacitance (pF)
Figure 15. Small-Signal Overshoot vs Load Capacitance
Figure 16. 0.1-Hz to 10-Hz Noise
Voltage Noise (nV/ÖHz)
Continues with no 1/f (flicker) noise.
Current Noise
100
100
Voltage Noise
Current Noise (fA/ÖHz)
1000
1000
10
10
1
10
100
1k
10k
Frequency (Hz)
Figure 17. Current and Voltage Noise Spectral Density vs Frequency
8
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7 Detailed Description
7.1 Overview
The OPA333-Q1 device is a zero-drift, low-power, rail-to-rail input and output operational amplifier. The device
operates from 1.8 V to 5.5 V, is unity-gain stable, and is designed for a wide range of general-purpose
applications. The zero-drift architecture provides ultra-low offset voltage and near-zero offset voltage drift.
The OPA333-Q1 device is unity-gain stable and free from unexpected output phase reversal. The device uses a
proprietary auto-calibration technique to provide low offset voltage and very-low drift over time and temperature.
7.2 Functional Block Diagram
C2
CHOP1
Notch
Filter
CHOP2
GM1
GM2
GM3
OUT
+IN
±IN
GM_FF
C1
7.3 Feature Description
7.3.1 Rail-to-Rail Input Voltage
The OPA333-Q1 input common-mode voltage range extends 0.1 V beyond the supply rails. The OPA333-Q1
device is designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers.
Normally, input bias current is approximately 70 pA; however, input voltages exceeding the power supplies can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor (see Figure 18).
5V
IOVERLOAD
10 mA max
OPA333-Q1
VOUT
VIN
5 kW
(1)
Current-limiting resistor required if input voltage exceeds supply rails by ≥0.5 V.
Figure 18. Input Current Protection
7.3.2 Internal Offset Correction
The OPA333-Q1 op amp uses an auto-calibration technique with a time-continuous 350-kHz op amp in the signal
path. This amplifier is zero corrected every 8 μs using a proprietary technique. At power up, the amplifier requires
approximately 100 μs to achieve specified VOS accuracy. This design has no aliasing or flicker noise.
7.4 Device Functional Modes
The OPA333-Q1 device has a single functional mode. The device is powered on as long as the power supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA333-Q1 is a unity-gain stable, precision operational amplifier with very low offset voltage drift. The
device is also free from output phase reversal. Applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are adequate.
8.1.1 Achieving Output Swing to the Op Amp Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply op amps, problems arise when the output signal approaches 0 V,
near the lower output swing limit of a single-supply op amp. A good single-supply op amp may swing close to
single-supply ground, but will not reach ground. The output of the OPA333-Q1 can be made to swing to ground,
or slightly below, on a single-supply power source. To do so requires the use of another resistor and an
additional, more negative, power supply than the op amp negative supply. A pulldown resistor may be connected
between the output and the additional negative supply to pull the output down below the value that the output
would otherwise achieve (see Figure 19).
V+ = +5 V
VOUT
OPA333-Q1
VIN
RP = 20 kW
Op Amp V- = GND
-5 V
Additional
Negative
Supply
Copyright © 2017, Texas Instruments Incorporated
Figure 19. VOUT Range to Ground
The OPA333-Q1 has an output stage that allows the output voltage to be pulled to its negative supply rail, or
slightly below, using the technique previously described. This technique only works with some types of output
stages. The OPA333-Q1 has been characterized to perform with this technique; however, the recommended
resistor value is approximately 20 kΩ.
NOTE
This configuration increases the current consumption by several hundreds of microamps.
Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occur below –2 mV, but
excellent accuracy returns when the output is again driven above –2 mV. Lowering the resistance of the pulldown
resistor allows the op amp to swing even further below the negative rail. Resistors as low as 10 kΩ can be used
to achieve excellent accuracy down to –10 mV.
10
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8.2 Typical Applications
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 20 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V
to 2 V to and output current of 0 mA to 100 mA. Figure 21 shows the measured transfer function for this circuit.
The low offset voltage and offset drift of the OPA333-Q1 device facilitate excellent dc accuracy for the circuit.
V+
RS2
470
RS3
4.7
IRS2
R4
10 k
VRS2
IRS3
VRS3
C7
2200 pF
R5
330
A2
+
Q2
V+
R3
200
+
Q1
A1
+
VIN
±
C6
1000 pF
R2
10 k
VRS1
RS1
IRS1
VLOAD
RLOAD
2k
ILOAD
Figure 20. High-Side Voltage-to-Current (V-I) Converter
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Typical Applications (continued)
8.2.1.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 5 V dc
• Input: 0 V to 2 V dc
• Output: 0 mA to 100 mA dc
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2333-Q1 CMOS operational amplifier is a highprecision, 5-µV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 50 mV of the positive rail. The OPA2333-Q1 uses chopping techniques to provide low initial offset
voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset error in
the system, making these devices appropriate for precise dc control. The rail-to-rail output stage of the
OPA2333-Q1 makes sure that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in the High-Side V-I
Converter reference design.
8.2.1.3 Application Curve
0.1
Load
Output Current (A)
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
Figure 21. Measured Transfer Function for High-Side V-I Converter
12
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Typical Applications (continued)
8.2.2 Precision, Low-Level Voltage-to-Current (V-I) Converter
The circuit shown in Figure 22 is a precision, low-level voltage-to-current (V-I) converter. The converter translates
in input voltage of 0 V to 5 V and output current of 0 µA to 5 µA. Figure 23 shows the measured transfer function
for this circuit. The low offset voltage and offset drift of the OPA333-Q1 facilitate excellent dc accuracy for the
circuit. Figure 24 shows the calibrated error for the entire range of the circuit.
R3 100 k
C1 10 nF
R4 100 k
5V
VOUT_OPA
OPA333-Q1
5V
+R1
+
+
U2
INA326
R1
40.2 k
Rset
100 k
VOUT_INA
R1
±
VIN
RLOAD
IOUT
R2
R2
200 k
C2 1 nF
+
A
AM1
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Figure 22. Low-Level, Precision V-I Converter
8.2.2.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 5 V dc
• Input: 0 V to 5 V dc
• Output: 0 μA to 5 μA dc
8.2.2.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, RSET, and the
instrumentation amplifier (INA) gain. During operation, the input voltage divided by the INA gain appears across
the set resistor in Equation 1:
VSET = VIN / GINA
(1)
The current through RSET must flow through the load, so IOUT is VSET / RSET × IOUT remains a well-regulated
current as long as the total voltage across RSET and RLOAD does not violate the output limits of the operational
amplifier or the input common-mode limits of the INA. The voltage across the set resistor (VSET) is the input
voltage divided by the INA gain (that is, VSET = 1 V / 10 = 0.1 V). The current is determined by VSET and RSET
shown in Equation 2:
IOUT = VSET / RSET = 0.1 V / 100 kΩ = 1 μA
(2)
A detailed error analysis, design procedure, and additional measured results are given in the Low-Level V-to-I
Converter reference design.
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Typical Applications (continued)
8.2.2.3 Application Curves
100
Measured Output Current Error (pA)
Output Current (µA)
0.1
0.075
0.05
0.025
0
0
80
60
40
20
0
–20
–40
–60
–80
–100
1
3
2
Input Voltage (V)
5
4
0
1
3
4
2
Desired Output Current, Iout_desired (µA)
D002
Figure 23. Measured Transfer Function for Low-Level
Precision V-I
5
D002
Figure 24. Calibrated Output Error for Low-Level V-I
8.2.3 Composite Amplifier
The circuit shown in Figure 25 is a composite amplifier used to drive the reference on the ADS8881. The
OPA333-Q1 provides excellent dc accuracy, and the THS4281 allows the output of the circuit to respond quickly
to the transient current requirements of a typical successive approximation register (SAR) data-converter
reference input. The ADS8881 system was optimized for THD and achieved a measured performance of –110
dB. The linearity of the ADC is shown Figure 26.
REFERENCE DRIVE CIRCUIT
20 k
1 µF
THS4281
+
-
1k
AVDD
+
+
0.2
AVDD
1 µF
OPA333-Q1
1k
+
REF5045
Vout
AVDD
1 µF
10 µF
Vin
Temp
Trim Gnd
1µF
1k
1k
AVDD
AVDD
VIN+
THS4521
+ + -
VCM
10
10 nF
-
+
CONVST
ADS8881
AINM
10
GND
CONVST
+
VIN-
REFP AVDD
AINP
V+
1k
1k
18-Bit 1MSPS
SAR ADC
INPUT DRIVER
Copyright © 2017, Texas Instruments Incorporated
Figure 25. Composite Amplifier Reference Driver Circuit
14
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Typical Applications (continued)
8.2.3.1 Design Requirements
The design requirements for this block design are:
• System supply voltage: 5 V dc
• ADC supply voltage: 3.3 V dc
• ADC sampling rate: 1 MSPS
• ADC reference voltage (VREF): 4.5 V dc
• ADC input signal: A differential input signal with amplitude of Vpk = 4.315 V (–0.4 dBFS to avoid clipping) and
frequency of fIN = 10 kHz are applied to each differential input of the ADC
8.2.3.2 Detailed Design Procedure
The two primary design considerations to maximize the performance of a high-resolution SAR ADC are the input
driver and the reference driver design. The circuit comprises the critical analog circuit blocks, the input driver,
antialiasing filter, and the reference driver. Each analog circuit block should be carefully designed based on the
ADC performance specifications to maximize the distortion and noise performance of the data acquisition system
while consuming low power. The diagram includes the most important specifications for each individual analog
block. This design systematically approaches the design of each analog circuit block to achieve a 16-bit, lownoise and low-distortion data acquisition system for a 10-kHz sinusoidal input signal. The first step in the design
requires an understanding of the requirements for an extremely low-distortion input-driver amplifier. This
understanding helps in the decision of an appropriate input driver configuration and selection of an input amplifier
to meet the system requirements. The next important step is the design of the antialiasing RC filter to attenuate
ADC kickback noise while maintaining amplifier stability. The final design challenge is to design a high-precision
reference driver circuit that provides the required-value VREF with low offset, drift, and noise contributions.
When designing a very low-distortion data-acquisition block, make sure to understand the sources of nonlinearity.
Both the ADC and the input driver introduce nonlinearity in a data-acquisition block. To achieve the lowest
distortion, the input driver for a high-performance SAR ADC must have a distortion that is negligible against the
ADC distortion. This parameter requires the input driver distortion to be 10 dB less than the ADC THD. This
stringent requirement makes sure that the overall THD of the system is not degraded by more than –0.5 dB.
THDAMP < THDADC – 10 dB
(3)
Therefore, make sure to choose an amplifier that meets the previous criteria to avoid the system THD from being
limited by the input driver. The amplifier nonlinearity in a feedback system depends on the available loop gain. A
detailed error analysis, design procedure, and additional measured results are given in the Data Acquisition
Optimized for Lowest Distortion, Lowest Noise reference design.
8.2.3.3 Application Curve
Integral Non-Linearity Error (LSB)
1.5
1
0.5
0
–0.5
–1
–1.5
–4.5
–3.5 –2.5
–1.5 –0.5 0.5
1.5
ADC Differential Input
2.5
3.5
4.5
D002
Figure 26. Linearity of the ADS8881 System
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Typical Applications (continued)
8.2.4 Temperature Measurement
Figure 27 shows a temperature measurement application.
4.096 V
REF3140-Q1
5V
0.1 mF
+
R1
6.04 kW
D1
R9
150 kW
R5
31.6 kW
5V
0.1 mF
+
-
R2
2.94 kW
-
+ +
R2
549 W
R4
6.04 kW
VO
OPA333-Q1
R6
200 W
K-Type
Thermocouple
40.7 mV/°C
Zero
Adjust
R3
60.4 W
Copyright © 2017, Texas Instruments Incorporated
Figure 27. Temperature Measurement
8.2.5 Single Op-Amp Bridge-Amplifier
Figure 28 shows the basic configuration for a bridge amplifier.
VEX
R1
+5V
R R
R R
VOUT
OPA333-Q1
R1
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 28. Single Op-Amp Bridge-Amplifier
8.2.6 Low-Side Current-Monitor
A low-side current shunt monitor is shown in Figure 29. The R1 through R6 resistors are operational resistors
used to isolate the 16-bit ADS1115-Q1 converter from the noise of the digital I2C bus.
High-Voltage Bus
VCM
VDD
VDD
CCM2
LOAD
R6
AINN
ILOAD
VINX
RSHUNT
4-Wire Kelvin
Connection
R3
R4
+
OPA333-Q1
R5
VOUT
±
VSHUNT
R1
CDIFF
ADS1115-Q1
I2C
AINP
CCM1
R2
NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.
Figure 29. Low-Side Current-Monitor
16
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Typical Applications (continued)
8.2.7 High-Side Current Monitor
RG
zener
RSHUNT
(1)
V+
(2)
R1
10 kW
MOSFET rated to
stand-off supply voltage
such as BSS84 for
up to 50 V.
OPA333-Q1
+5V
V+
Two zener
biasing methods
(3)
are shown.
Output
Load
RBIAS
RL
Copyright © 2017, Texas Instruments Incorporated
(1)
Zener rated for op amp supply capability (that is, 5.1 V for OPA333-Q1).
(2)
Current-limiting resistor.
(3)
Choose zener biasing resistor or dual N-MOSFETs (FDG6301N, NTJD4001N, or Si1034).
Figure 30. High-Side Current Monitor
8.2.8 Thermistor Measurement
1 MW
100 kW
60 kW
3V
NTC
Thermistor OPA333-Q1
1 MW
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Figure 31. Thermistor Measurement
8.2.9 Precision Instrumentation Amplifier
V1
-In
INA152
OPA333-Q1
R2
R1
2
5
6
VO
R2
3
1
OPA333-Q1
V2
+In
VO = (1 + 2R2 / R1) (V2 - V1)
Copyright © 2017, Texas Instruments Incorporated
Figure 32. Precision Instrumentation Amplifier
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9 Power Supply Recommendations
The OPA333-Q1 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages greater than 7 V can permanently damage the device (see the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors near the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more details on bypass capacitor placement, see the Layout section.
10 Layout
10.1 Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or dc signal levels with changes in the interfering RF signal. The OPA333-Q1 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. Cancel these thermally-generated potentials by assuring they are equal on
both input terminals. Other layout and design considerations include:
• Use low-thermoelectric-coefficient connections (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
VS±
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 33. Layout Example
18
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
• Texas Instruments, ADS1100 Self-Calibrating, 16-Bit Analog-to-Digital Converter
• Texas Instruments, ADS8881x 18-Bit, 1-MSPS, Serial Interface, microPower, Miniature, True-Differential
Input, SAR Analog-to-Digital Converter
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers (With OPA333 and OPA333-Q1 as an
Example)
• Texas Instruments, High-Side Voltage-to-Current (V-I) Converter
• Texas Instruments, INA152 Single-Supply Difference Amplifier
• Texas Instruments, Low Level (5 μA) V-to-I Converter
• Texas Instruments, REF31xx-Q1 15 ppm/°C Maximum, 100-μA, SOT-23 Series Voltage Reference
• Texas Instruments, Single-Supply Operation Of Operational Amplifiers
• Texas Instruments, THS4281 Very Low-Power, High-Speed, Rail-to-Rail Input and Output Voltage-Feedback
Operational Amplifier
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA333AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
QCNQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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