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OPA356-Q1
SBOS479A – MARCH 2009 – REVISED APRIL 2018
OPA356-Q1 200-MHz CMOS Operational Amplifier
1 Features
2 Applications
•
•
•
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•
•
1
•
•
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•
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Qualified For Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Unity-Gain Bandwidth: 450 MHz
Wide Bandwidth: 200-MHz GBW
High Slew Rate: 360 V/µs
Low Noise: 5.8 nV/√Hz
Excellent Video Performance:
– Differential Gain: 0.02%
– Differential Phase: 0.05°
– 0.1-dB Gain Flatness: 75 MHz
Input Range Includes Ground
Rail-To-Rail Output (Within 100 mV)
Low Input Bias Current: 3 pA
Thermal Shutdown
Single-Supply Operating Range: 2.5 V to 5.5 V
Infotainment Systems
ADAS Systems
Radar
Dynamic Stability Controls (DSC)
3 Description
The OPA356-Q1 is a high-speed voltage-feedback
CMOS operational amplifier designed for video and
other applications requiring wide bandwidth. The
OPA356-Q1 is unity-gain stable and can drive large
output currents. Differential gain is 0.02% and
differential phase is 0.05°. Quiescent current is only
8.3 mA.
The OPA356-Q1 is optimized for operation on single
or dual supplies as low as 2.5 V (±1.25 V) and up to
5.5 V (±2.75 V). The common-mode input range for
the OPA356-Q1 extends 100 mV below ground and
up to 1.5 V from V+. The output swing is within
100 mV of the rails, supporting wide dynamic range.
The OPA356-Q1 is available in the SOT23-5 package
and is specified over the –40°C to 125°C range.
Device Information(1)
PART NUMBER
OPA356-Q1
PACKAGE
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
V+
–VIN
OPA356
Out
+VIN
V–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA356-Q1
SBOS479A – MARCH 2009 – REVISED APRIL 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2009) to Revision A
Page
•
Added Device Information table, ESD Ratings table, Thermal Information table, Feature Description section, Device
Functional Modes section, Application and Implementation section, Power Supply Recommendations section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section .................................................................................................................................................................................... 1
•
Added AEC-Q100 Qualification Features bullet ..................................................................................................................... 1
•
Deleted Ordering Information table ....................................................................................................................................... 3
•
Deleted footnote 2 from Absolute Maximum Ratings table ................................................................................................... 4
•
Deleted the SR, tr, tf, tsettle, and Overload recovery time rows from the Electrical Characteristics table and moved to
the Timing Requirements table .............................................................................................................................................. 5
•
Changed Layout Guidelines title from PCB Layout .............................................................................................................. 19
2
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
Out
1
V-
2
+In
3
5
V+
4
-In
Pin Functions
PIN
NO.
1
NAME
I/O
DESCRIPTION
Out
O
Output pin
2
V–
—
Negative power supply
3
+In
I
Noninverting input pin
4
–In
I
Inverting input pin
5
V+
—
Positive power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Supply voltage, V+ to V–
VIN
Signal input pins voltage range
–0.5
MAX
UNIT
7.5
V
(V+) + 0.5
V
10
mA
125
°C
160
°C
150
°C
V– current
Output short-circuit duration (2)
TA
Operating free-air temperature range
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
Continuous
–40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
V
±500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage, V– to V+
2.7
5.5
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
OPA356-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
185.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
102.5
°C/W
RθJB
Junction-to-board thermal resistance
43.9
°C/W
ψJT
Junction-to-top characterization parameter
18.2
°C/W
ψJB
Junction-to-board characterization parameter
43.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VS = 2.7 V to 5.5 V, RF = 604 Ω, RL = 150 Ω connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOS
Input offset voltage
VS = 5 V, VCM = V– + 0.8 V
ΔVOS/ΔT
Offset voltage drift over temperature
VS = 2.7 V to 5.5 V,
VCM = VS / 2 – 0.15 V
TA (1)
MIN
25°C
TYP
MAX
±2
±9
Full range
mV
±15
Full range
±7
µV/°C
25°C
±80
±350
µV/V
pA
PSRR
Offset voltage drift vs power supply
IB
Input bias current
25°C
3
±50
IOS
Input offset current
25°C
±1
±50
Vn
Input voltage noise density
f = 1 MHz
25°C
5.8
In
Input current noise density
f = 1 MHz
25°C
VCM
Input common-mode voltage range
50
25°C
V– – 0.1
25°C
66
Full range
66
pA
nV/√Hz
fA/√Hz
V+ – 1.5
V
80
CMRR
Input common-mode rejection ratio
ZID
Differential input impedance
25°C
1013 || 1.5
Ω || pF
ZICM
Common-mode input impedance
25°C
1013 || 1.5
Ω || pF
AOL
Open-loop gain
VS = 5.5 V, –0.1 V < VCM < 4 V
UNIT
VS = 5 V, 0.3 V < VO < 4.7 V
25°C
84
Full range
80
G = 1, VO = 100 mVp-p, RF = 0 Ω
G = 2, VO = 100 mVp-p, RL = 50 Ω
Small-signal bandwidth
GBW
Gain-bandwidth product
G = 10, RL = 1 kΩ
25°C
f0.1dB
Bandwidth for 0.1-dB gain flatness
G = 2, VO = 100 mVp-p, RF = 560 Ω
25°C
Slew rate
tr, tf
Rise and fall times
tsettle
Settling time
VS = 5 V, G = 2, 4-V output step
G = 2, VO = 200 mVp-p, 10% to 90%
G = 2, VO = 2 Vp-p, 10% to 90%
0.1%
0.01%
Overload recovery time
Harmonic distortion
Second
harmonic
Third
harmonic
200
25°C
MHz
30
VIN × Gain = VS
25°C
8
25°C
–81
25°C
–93
ns
dBc
NTSC, RL = 150 Ω
25°C
0.02%
NTSC, RL = 150 Ω
25°C
0.05
Peak
ns
120
Differential phase error
Output current (2)
ns
8
25°C
VS = 5 V, RL = 1 kΩ
V/µs
2.4
25°C
0.2
25°C
°
0.3
0.1
0.4
Continuous
(1)
(2)
75
–360
VS = 5 V, RL = 50 Ω
IQ
MHz
+300
VS = 5 V, RL = 150 Ω, AOL > 84 dB
IO
200
Differential gain error
Voltage output swing from rail
MHz
170
VS = 5 V, G = 2, 2-V output step
G = 2, f = 1 MHz, VO = 2 Vp-p,
RL = 200 Ω
dB
100
25°C
G = 2, VO = 100 mVp-p, RL = 1 kΩ
SR
92
450
f–3dB
G = 2, VO = 100 mVp-p, RL = 150 Ω
dB
V
0.6
±60
VS = 5 V
25°C
VS = 3 V
±100
mA
±80
+250
Short-circuit current
25°C
Closed-loop output impedance
25°C
0.02
25°C
8.3
Quiescent current
VS = 5 V, IO = 0
Thermal shutdown junction
temperature
Shutdown
Reset from shutdown
Full range
25°C
mA
–200
Ω
11
14
160
140
mA
°C
Full range TA = –40°C to 125°C.
See Figure 20.
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6.6 Typical Characteristics
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, RL = 150 Ω connected to VS / 2 (unless otherwise noted)
6
3
VO = 0.1Vp-p
0
Normalized Gain (dB)
3
Normalized Gain (dB)
VO = 0.1 Vp-p
G=1
RF = 0
0
–3
G=2
–6
G=5
–9
G = 10
1M
G = –5
10M
Frequency (Hz)
100M
–6
G = –10
–9
–15
100k
1G
Figure 1. Noninverting Small-Signal Frequency Response
100M
1G
Output Voltage (500 mV/div)
G=2
Time (20 ns/div)
Figure 3. Noninverting Small-Signal Step Response
Figure 4. Noninverting Large-Signal Step Response
0.5
VO = 0.1 Vp-p
CL = 0 pF
0.3
RF = 604 Ω
0.2
0.1
0
–0.1
RF = 560 Ω
–0.2
–0.3
RF = 500 Ω
–0.4
–0.5
Harmonic Distortion (dBc)
–50
0.4
Normalized Gain (dB)
10M
Frequency (Hz)
Figure 2. Inverting Small-Signal Frequency Response
G=2
Output Voltage (50 mV/div)
1M
Time (20 ns/div)
f = 1 MHz
RL = 200 Ω
–60
–70
2nd Harmonic
–80
3rd Harmonic
–90
–100
1
10
Frequency (MHz)
100
Figure 5. 0.1-dB Gain Flatness for Various RF
6
G = –2
–12
–12
–15
100k
G = –1
–3
0
1
2
Output Voltage (Vp-p)
3
4
Figure 6. Harmonic Distortion vs Output Voltage
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, RL = 150 Ω connected to VS / 2 (unless otherwise noted)
–50
VO = 2 Vp-p
f = 1 MHz
RL = 200 Ω
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–50
–70
2nd Harmonic
–80
3rd Harmonic
–90
VO = 2 Vp-p
f = 1 MHz
RL = 200 Ω
–60
–70
2nd Harmonic
–80
3rd Harmonic
–90
–100
–100
1
1
10
10
Gain (V/V)
Gain (V/V)
Figure 7. Harmonic Distortion vs Non-Inverting Gain
Figure 8. Harmonic Distortion vs Inverting Gain
–50
–60
VO = 2 Vp-p
RL = 200 Ω
VO = 2 Vp-p
f = 1 MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–50
2nd Harmonic
–70
–80
3rd Harmonic
–90
–60
–70
–80
2nd Harmonic
–90
3rd Harmonic
–100
100k
–100
1M
Frequency (Hz)
10M
100
Figure 9. Harmonic Distortion vs Frequency
Figure 10. Harmonic Distortion vs Load Resistance
3
10k
RL = 10 kΩ
0
Normalized Gain (dB)
Voltage Noise (nV/ √Hz), Current Noise (fA/√Hz)
1k
RL (Ω)
1k
Current Noise
Voltage Noise
100
10
CL = 0 pF
VO = 0.1 Vp-p
–3
RL = 50 Ω
–6
RL = 150 Ω
–9
RL = 1 kΩ
–12
1
10
100
1k
10k
100k
1M
10M
100M
–15
100k
Frequency (Hz)
Figure 11. Input Voltage and Current Noise
Spectral Density vs Frequency
1M
10M
Frequency (Hz)
100M
1G
Figure 12. Frequency Response for Various RL
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, RL = 150 Ω connected to VS / 2 (unless otherwise noted)
120
9
6
Normalized Gain (dB)
CL = 100 pF
RS = 0 Ω
VO = 0.1 Vp-p
100
CL = 47 pF
3
80
RS (Ω)
0
–3
CL = 5.6 pF
60
VIN
40
20
0
1M
10M
Frequency (Hz)
100M
1
1G
90
RS
CL
–9
CL = 47 pF
RS = 36 Ω
VO
OPA356-Q1
1 kΩ
604 Ω
–12
+PSRR
70
60
CMRR
50
40
30
20
(1 kΩ is
Optional)
604 Ω
–PSRR
80
CMRR, PSRR (dB)
VIN
–6
100
Figure 14. Recommended RS vs Capacitive Load
CL = 5.6 pF
RS = 80 Ω
CL = 100 pF
RS = 24 Ω
–3
10
Capacitive Load (pF)
100
G=2
VO = 0.1 Vp-p
0
(1 kΩ is
Optional)
604 Ω
Figure 13. Frequency Response for Various CL
3
Normalized Gain (dB)
1 kΩ
604 Ω
–15
100k
10
–15
0
1M
10M
100M
Frequency (Hz)
1G
10k
Figure 15. Frequency Response vs Capacitive Load
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 16. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Frequency
180
0.40
160
0.35
RL= 1 kΩ
140
120
dG and dP (%/degrees)
Open-Loop Phase (degrees)
Open-Loop Gain (dB)
VO
CL
–9
–12
Phase
100
80
60
RL= 150 Ω
40
Gain
20
0.30
0.25
0.20
dP
0.15
0.10
dG
0.05
0
–20
0
1k
10k
100k
1M
10M
Frequency (Hz)
100M
Figure 17. Open-Loop Gain and Phase
8
RS
OPA356-Q1
–6
1G
1
2
3
Number of 150-Ω Loads
4
Figure 18. Composite Video Differential Gain and Phase
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, RL = 150 Ω connected to VS / 2 (unless otherwise noted)
10n
3
–55°C
Output Voltage (V)
Input Bias Current (pA)
25°C
1n
100
2
125°C
Continuous currents above
60 mA are not recommended
125°C
1
10
–55°C
25°C
1
0
–55
–35
–15
5
25
45
65
Temperature ( °C)
85
105 125 135
0
30
60
90
Output Current (mA)
120
150
VS = 3 V
Figure 19. Input Bias Current vs Temperature
Figure 20. Output Voltage Swing vs Output Current
5
14
25°C
–55°C
4
VS = 5.5 V
10
Output Voltage (V)
Supply Current (mA)
12
8
6
VS = 2.5 V
VS = 3 V
4
VS = 5 V
125°C
3
Continuous currents above
60 mA are not recommended
2
125°C
1
2
–55°C
25°C
0
0
–55
–35
–15
5
25
45
65
Temperature ( °C)
85
0
105 125 135
50
100
150
Output Current (mA)
200
250
VS = 5 V
Figure 21. Supply Current vs Temperature
Figure 22. Output Voltage Swing vs Output Current
6
100
10
Output Voltage (Vp-p)
Output Impedance (Ω)
VS = 5.5 V
5
1
OPA356-Q1
0.1
604 Ω
0.01
ZO
Maximum Output
Voltage Without
Slew-Rate
Induced Distortion
4
3
VS = 2.7 V
2
1
604 Ω
0
0.001
10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 23. Closed-Loop Output Impedance vs Frequency
1
10
Frequency (MHz)
100
Figure 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, RL = 150 Ω connected to VS / 2 (unless otherwise noted)
110
0.2
VO = 2 Vp-p
RL = 1 kΩ
100
Open-Loop Gain (dB)
Output Error (%)
0.1
0
–0.1
–0.2
90
RL = 150 Ω
80
70
–0.3
60
–0.4
0
5
10
15
20
25
30
Time (ns)
35
40
45
–55
50
Figure 25. Output Settling Time to 0.1%
–35
–15
25
45
65
Temperature ( °C)
85
105 125 135
Figure 26. Open-Loop Gain vs Temperature
20
100
18
Power-Supply Rejection Ratio
16
90
CMRR, PSRR (dB)
Percent of Amplifiers (%)
5
14
12
10
8
6
4
80
Common-Mode Rejection Ratio
70
60
2
0
50
–9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9
Offset Voltage (mV)
Figure 27. Offset Voltage Production Distribution
10
–55
–35
–15
5
25
45
65
Temperature ( °C)
85
105 125 135
Figure 28. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Temperature
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7 Detailed Description
7.1 Overview
The OPA356-Q1 operational amplifier is a high-speed, 360-V/μs, amplifier, making the device a great option for
transimpedance applications. The device is unity-gain stable and can operate on a single-supply voltage (2.7 V
to 5.5 V), or a split-supply voltage (±1.35 V to ±2.75 V), making the device highly versatile and simple to use.
The OPA356-Q1 amplifier is specified from 2.7 V to 5.5 V and over the automotive temperature range of –40°C
to +125°C.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN±
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V±
(Ground)
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7.3 Feature Description
7.3.1 Operating Voltage
The OPA356-Q1 is specified over a power-supply range of 2.7 V to 5.5 V (±1.35 V to ±2.75 V). However, the
supply voltage may range from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V (absolute
maximum) can permanently damage the amplifier.
Parameters that vary significantly over supply voltage or temperature are shown in the Typical Characteristics
section of this data sheet.
7.3.2 Output Drive
The output stage of the OPA356-Q1 is capable of driving a standard back-terminated 75-Ω video cable. A backterminated transmission line does not exhibit a capacitive load to its driver. A properly back-terminated 75-Ω
cable does not appear as capacitance; the cable presents only a 150-Ω resistive load to the OPA356-Q1 output.
The output stage can supply high short-circuit current (typically over 200 mA). Therefore, an on-chip thermal
shutdown circuit is provided to protect the OPA356-Q1 from dangerously high junction temperatures. At 160°C,
the protection circuit shuts down the amplifier. Normal operation resumes when the junction temperature cools to
below 140°C.
NOTE
TI does not recommend running a continuous dc current in excess of ±60 mA. See
Figure 20 in the Typical Characteristics section.
7.4 Device Functional Modes
The OPA356-Q1 is powered on when the supply is connected. The device can operate as a single-supply
operational amplifier or dual-supply amplifier depending on the application. The device can also be used with
asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater than 5.5 V
(for example, V– is set to –3.5 V and V+ is set to 1.5 V).
12
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8 Application and Implementation
8.1 Application Information
The OPA355-Q1 is a CMOS, high-speed, voltage-feedback, operational amplifier (op-amp) designed for generalpurpose applications.
The amplifier features a 200-MHz gain bandwidth and 300-V/μs slew rate, but the device is unity-gain stable and
operates as a 1-V/V voltage follower.
The input common-mode voltage range of the device includes ground, which allows the OPA356-Q1 to be used
in virtually any single-supply application up to a supply voltage of 5.5 V.
8.2 Typical Applications
8.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPA356-Q1 a
preferred wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in Figure 29, are the expected diode capacitance
(C(D)), which must include the parasitic input common-mode and differential-mode input capacitance (4 pF + 5
pF), the desired transimpedance gain (R(FB)), and the gain-bandwidth (GBW) for the OPA356-Q1 (20 MHz). With
these three variables set, the feedback capacitor value (C(FB)) is set to control the frequency response. C(FB)
includes the stray capacitance of R(FB), which is 0.2 pF for a typical surface-mount resistor.
(1)
C
(F)
< 1 pF
R (F)
10 M
V(V+)
l
C
(D)
OPA355-Q1
V
(1)
V
O
(V±)
C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB).
Figure 29. Dual-Supply Transimpedance Amplifier
8.2.1.1 Design Requirements
PARAMETER
VALUE
Supply voltage V(V+)
2.5 V
Supply voltage V(V–)
–2.5 V
8.2.1.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole must be set to:
1
=
2 ´ p ´ R(FB) ´ C(FB)
GBW
4 ´ p ´ R(FB) ´ C(D)
(1)
Use Equation 2 to calculate the bandwidth.
ƒ(–3 dB) =
GBW
2 ´ p ´ R(FB) ´ C(D)
(2)
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For other transimpedance bandwidths, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354
(100-MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656 and OPA657 (400-MHz
GBW).
For single-supply applications, the +INx input can be biased with a positive DC voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; this configuration is shown in Figure 30. This bias voltage appears
across the photodiode, providing a reverse bias for faster operation.
0.5 pF
100 k
±
OPA355-Q1
VOUT
+
13.7 k
SFH213
1 F
280
5V
Figure 30. Single-Supply Transimpedance Amplifier
For additional information, see the Compensate Transimpedance Amplifiers Intuitively application bulletin.
8.2.1.2.1 Optimizing The Transimpedance Circuit
To achieve the best performance, select components according to the following guidelines:
1. For lowest noise, select R(FB) to create the total required gain. Using a lower value for R(FB) and adding gain
after the transimpedance amplifier generally produces poorer noise performance. The noise produced by
R(FB) increases with the square-root of R(FB), whereas the signal increases linearly. Therefore, signal-to-noise
ratio improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to amplify (increasing amplification at high frequency).
Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the capacitance.
Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(FB) to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage can help control leakage.
For additional information, see the Noise Analysis of FET Transimpedance Amplifiers and Noise Analysis for
High-Speed Op Amps application bulletins).
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8.2.1.3 Application Curve
105
100
Gain (dB, V/A)
95
90
85
80
75
70
65
60
1000
10000
100000
1000000
Frequency (Hz)
1E+7
5E+7
D001
–3 dB bandwidth is 4.56 MHz
Figure 31. AC Transfer Function
8.2.2 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by means of an amplifier. The input bias current of this
amplifier can load the sensor output and cause a voltage drop across the source resistance, as shown in
Figure 32, where (V(+INx) = VS – I(BIAS) × R(S)). The last term, I(BIAS) × R(S), shows the voltage drop across R(S). To
prevent errors introduced to the system as a result of this voltage, an op amp with very low input bias current
must be used with high impedance sensors. This low current keeps the error contribution by I(BIAS) × R(S) less
than the input voltage noise of the amplifier, so that the input voltage noise does not become the dominant noise
factor. The OPA356-Q1 op amp features very low input bias current (typically 200 fA), and is therefore a
preferred choice for such applications.
R(S)
100 kΩ
IIB
V(+INx)
V(V+)
Device
V(V–)
VO
R(F)
R(G)
Figure 32. Noise as a Result of I(BIAS)
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8.2.3 Driving ADCs
The OPA356-Q1 op amps are designed for driving sampling analog-to-digital converters (ADCs) with sampling
speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPA356-Q1 to drive ADCs
without degradation of differential linearity and THD.
The OPA356-Q1 can be used to buffer the ADC switched input capacitance and resulting charge injection while
providing signal gain. Figure 33 shows the OPA356-Q1 configured to drive the ADS8326.
5V
C1
100 nF
V
5V
(1)
R1
100
(V+)
+INx
OPA355-Q1
(1)
V
C3
1 nF
(V±)
V
I
0 to 4.096 V
±INx
ADS8326
16-Bit
250kSPS
REF IN
(2)
5V
Optional
R2
50 k
SD1
BAS40
±5 V
C2
100 nF
REF3240
4.096 V
C4
100 nF
(1)
Suggested value; may require adjustment based on specific application.
(2)
Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing
limitation. If a negative power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to
true ground potential.
Figure 33. Driving the ADS8326
8.2.4 Active Filter
The OPA356-Q1 is designed for active filter applications that require a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. Figure 34 depicts a 500-kHz, second-order, low-pass filter using the multiplefeedback (MFB) topology. The components are selected to provide a maximally-flat Butterworth response.
Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is preferred for applications
requiring predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (see Figure 35).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
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R3
549 Ω
C2
150 pF
R1
549 Ω
R2
1.24 kΩ
V(V+)
VI
VO
Device
C1
1 nF
V(V–)
Figure 34. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
1.8 kΩ
19.5 kΩ
V(V+)
150 kΩ
VI = 1 VRMS
3.3 nF
47 pF
Device
VO
V(V–)
Figure 35. OPA356-Q1 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
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9 Power Supply Recommendations
The OPA356-Q1 is specified for operation from 2.7 to 5.5 V (±1.35 to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in theTypical Characteristics section.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
Power dissipation depends on power-supply voltage, signal and load conditions. With DC signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
VS – VO. Minimize power dissipation by using the lowest possible power-supply voltage required to ensure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. Application bulletin AB-039, Power Amplifier Stress and Power
Handling Limitations explains how to calculate or measure power dissipation with unusual signals and loads, and
is available on www.ti.com.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 150°C maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature to trigger the thermal protection at 160°C. The thermal
protection must trigger more than 35°C above the maximum expected ambient condition of the application.
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10 Layout
10.1 Layout Guidelines
•
•
•
Good high-frequency PC board layout techniques should be employed for the OPA356-Q1. Generous use of
ground planes, short direct signal traces, and a suitable bypass capacitor located at the V+ pin assure clean,
stable operation. Large areas of copper also provide a means of dissipating heat that is generated within the
amplifier in normal operation.
Sockets are definitely not recommended for use with any high-speed amplifier.
A 10-µF ceramic bypass capacitor is the minimum recommended value; adding a 1-µF or larger tantalum
capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass
capacitance is essential to achieving very low harmonic and intermodulation distortion.
10.2 Layout Example
Noninverting input
terminated in 50 Ÿ.
5
Place bypass capacitors
close to power pins.
2
3
±
Place bypass capacitors
close to power pins.
1
+
Place output resistors close
to output pins to minimize
parasitic capacitance.
4
Place input resistor close to pin 4
to minimize stray capacitance.
Place feedback resistor on the bottom
of PCB between pins 4 and 6.
Remove GND and power plane
under pins 1 and 4 to minimize
stray PCB capacitance.
Ground and power plane exist on inner layers.
Ground and power plane removed from inner layers.
Figure 36. Example Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• OPAx380 Precision, High-Speed Transimpedance Amplifier
• OPAx354 250-MHz, Rail-to-Rail I/O, CMOS Operational Amplifiers
• OPAx300 Low-Noise, High-Speed, 16-Bit Accurate, CMOS Operational Amplifier
• OPAx355 200MHz, CMOS Operational Amplifier With Shutdown
• OPA656 Wideband, Unity-Gain Stable, FET-Input Operational Amplifier
• OPA657 1.6-GHz, Low-Noise, FET-Input Operational Amplifier
• Compensate Transimpedance Amplifiers Intuitively
• Noise Analysis of FET Transimpedance Amplifiers
• Noise Analysis for High-Speed Op Amps
• ADS8326 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling Analog-to-Digital Converter
• FilterPro™
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA356AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OOVQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
