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OPA373, OPA374
OPA2373, OPA2374, OPA4374
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
OPAx373, OPAx374 6.5-MHz, 585-µA, Rail-to-Rail I/O
CMOS Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
The OPA373 and OPA374 families of operational
amplifiers are low power and low cost with excellent
bandwidth (6.5 MHz) and slew rate (5 V/µs). The
input range extends 200 mV beyond the rails and the
output range is within 25 mV of the rails. The speedpower ratio and small size make them ideal for
portable and battery-powered applications.
1
Low Offset: 5 mV (Maximum)
Low IB: 10 pA (Maximum)
High Bandwidth: 6.5 MHz
Rail-to-Rail Input and Output
Single Supply: 2.3 V to 5.5 V
Shutdown: OPAx373
Specified up to 125°C
Microsize Packages: 5-Pin SOT-23,
6-Pin SOT-23, 8-Pin SOT-23, and 10-Pin VSON
The OPA373 family includes a shutdown mode.
Under logic control, the amplifiers can be switched
from normal operation to a standby current that is
less than 1 µA.
The OPA373 and OPA374 families of operational
amplifiers are specified for single or dual power
supplies of 2.7 V to 5.5 V, with operation from 2.3 V
to 5.5 V. All models are specified for –40°C to 125°C.
2 Applications
•
•
•
•
Portable Equipment
Battery-Powered Devices
Active Filters
Driving A/D Converters
Device Information(1)
PART NUMBER
OPA373
OPA374
OPA2373
OPA2374
OPA4374
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (6)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSON (10)
3.00 mm × 3.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (8)
2.90 mm × 1.63 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VCC
VCC
R5
+
R6
ILOAD
R2
R1
+
VBUS
+
VOUT
RSHUNT
±
R3
VCC
RL
R4
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA373, OPA374
OPA2373, OPA2374, OPA4374
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
2
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: OPA373 .................................. 7
Thermal Information: OPA374 .................................. 8
Thermal Information: OPA2373 ................................ 8
Thermal Information: OPA2374 ................................ 8
Thermal Information: OPA4374 ................................ 8
Electrical Characteristics: VS = 2.7 V to 5.5 V .......... 9
Typical Characteristics .......................................... 11
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
9.3 System Examples .................................................. 21
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
26
26
26
26
26
26
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision E (May 2008) to Revision F
Page
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Package/Ordering Information table; refer to Package Option Addendum at the end of this data sheet ................ 4
•
Deleted lead temperature specification from Absolute Maximum Ratings ............................................................................ 7
•
Changed values in the Thermal Information tables to align with JEDEC standards.............................................................. 7
2
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SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
5 Device Comparison Table
DEVICE
NO. OF
CHANNELS
SHUTDOWN
OPA373
1
OPA2373
OPA374
PACKAGE-PIN
SOIC
SOT-23
VSON
VSSOP
TSSOP
Yes
8
6
—
—
—
2
Yes
—
—
10
10
—
1
No
8
5
—
—
—
OPA2374
2
No
8
8
—
—
—
OPA4374
4
No
14
—
—
—
14
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OPA373, OPA374
OPA2373, OPA2374, OPA4374
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
www.ti.com
6 Pin Configuration and Functions
OPA373: DBV Package
6-Pin SOT-23
Top View
A75
(1)
1
Out
OPA373: D Package
8-Pin SOIC
Top View
6
V+
NC
(2)
1
8
Enable
V-
2
5
Enable
-IN
2
7
V+
+IN
3
4
-IN
+IN
3
6
OUT
V-
4
5
NC
(1) Pin 1 of the 6-pin SOT-23 is determined
by orienting the package marking as
shown.
(2)
(2) NC indicates no internal connection.
Pin Functions: OPA373
PIN
I/O
DESCRIPTION
NAME
SOIC
SOT-23
Enable
8
5
I
Enable
–IN
2
4
I
Negative (inverting) input
Positive (noninverting) input
+IN
3
3
I
NC
1, 5
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
6
—
Positive (highest) power supply
OPA2373: DGS Package
10-Pin VSON
Top View
OPA2373: DRC Package
10-Pin VSSOP
Top View
OUT A
1
-IN A
2
-IN B
+IN A
3
+IN B
VEnable A
V+
OUT A
Exposed
thermal
die pad on
underside
(Must be
connected to V-)
-IN A
+IN A
V-
OUT B
9
OUT B
8
-IN B
4
7
+IN B
5
6
Enable B
A
B
Enable B
Enable A
10 V+
Pin Functions: OPA2373
PIN
NAME
I/O
DESCRIPTION
VSON
VSSOP
Enable A
5
5
I
Enable A amplifier
Enable B
6
6
I
Enable B amplifier
–IN A
2
2
I
Inverting input, channel A
+IN A
3
3
I
Noninverting input, channel A
–IN B
8
8
I
Inverting input, channel B
+IN B
7
7
I
Noninverting input, channel B
OUT A
1
1
O
Output, channel A
OUT B
9
9
O
Output, channel B
V–
4
4
—
Negative (lowest) power supply
V+
10
10
—
Positive (highest) power supply
4
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OPA2373, OPA2374, OPA4374
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SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
OPA374: DBV Package
5-Pin SOT-23
Top View
Out
1
V-
2
+IN
3
5
4
OPA374: D Package
8-Pin SOIC
Top View
V+
-IN
(1)
(1)
1
8
NC
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC
NC
(1)
(1) NC indicates no internal connection.
Pin Functions: OPA374
PIN
NAME
I/O
DESCRIPTION
SOIC
SOT-23
–IN
2
4
I
Negative (inverting) input
+IN
3
3
I
Positive (noninverting) input
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
5
—
Positive (highest) power supply
OPA2374: DCN Package
8-Pin SOT-23
Top View
OUT A 1
-IN A 2
8
A
7
B
+IN A 3
V- 4
OPA2374: D Package
8-Pin SOIC
Top View
V+
OUT A 1
OUT B
-IN A 2
6
-IN B
+IN A 3
5
+IN B
V- 4
A
B
8
V+
7
OUT B
6
-IN B
5
+IN B
Pin Functions: OPA2374
PIN
I/O
DESCRIPTION
NAME
SOIC
SOT-23
–IN A
2
2
I
Inverting input, channel A
+IN A
3
3
I
Noninverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN B
5
5
I
Noninverting input, channel B
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
V–
4
4
—
Negative (lowest) power supply
V+
8
8
—
Positive (highest) power supply
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OPA373, OPA374
OPA2373, OPA2374, OPA4374
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
www.ti.com
OPA4374: PW Package
14-Pin TSSOP
Top View
OPA4374: D Package
14-Pin SOIC
Top View
14
OUT D
OUT A
1
13
-IN D
-IN A
2
3
12
+IN D
+IN A
V+
4
11
V-
+IN B
5
10
+IN C
OUT A
1
-IN A
2
+IN A
-IN B
6
OUT B
7
D
A
B
C
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
9
-IN C
8
OUT C
9
-IN C
-IN B
6
8
OUT C
OUT B
7
A
B
D
C
Pin Functions: OPA4374
PIN
I/O
DESCRIPTION
NAME
SOIC
TSSOP
–IN A
2
2
I
Inverting input, channel A
+IN A
3
3
I
Noninverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN B
5
5
I
Noninverting input, channel B
–IN C
9
9
I
Inverting input, channel C
+IN C
10
10
I
Noninverting input, channel C
–IN D
13
13
I
Inverting input, channel D
+IN D
12
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
8
8
O
Output, channel C
OUT D
14
14
O
Output, channel D
V–
11
11
—
Negative (lowest) power supply
V+
4
4
—
Positive (highest) power supply
6
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OPA2373, OPA2374, OPA4374
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SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage
Current
Signal input pin (2)
−0.5
Signal input pin (2)
–10
Operating, TA
(2)
(3)
V
(V+) + 0.5
10
mA
Continuous
–55
150
Junction, TJ
Storage, Tstg
UNIT
7
Output short-circuit (3)
Temperature
(1)
MAX
Supply
150
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage
TA
Operating temperature
MIN
MAX
UNIT
±1.35 (2.7)
±2.75 (5.5)
V
–40
125
°C
7.4 Thermal Information: OPA373
OPA373
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
UNIT
8 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
128.4
184.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
76.7
146.2
°C/W
RθJB
Junction-to-board thermal resistance
68.8
36.4
°C/W
ψJT
Junction-to-top characterization parameter
27.9
33.6
°C/W
ψJB
Junction-to-board characterization parameter
68.3
35.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2003–2016, Texas Instruments Incorporated
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OPA373, OPA374
OPA2373, OPA2374, OPA4374
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
www.ti.com
7.5 Thermal Information: OPA374
OPA374
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
8 PINS
5 PINS
UNIT
220.1
°C/W
RθJA
Junction-to-ambient thermal resistance
125.1
RθJC(top)
Junction-to-case (top) thermal resistance
71.7
129
°C/W
RθJB
Junction-to-board thermal resistance
65.5
46.4
°C/W
ψJT
Junction-to-top characterization parameter
26.2
21
°C/W
ψJB
Junction-to-board characterization parameter
65
45.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: OPA2373
OPA2373
THERMAL METRIC
(1)
DGS (VSON)
DRC (VSSOP)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
170.6
56.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.8
76.7
°C/W
RθJB
Junction-to-board thermal resistance
91
30.6
°C/W
ψJT
Junction-to-top characterization parameter
10.4
3.7
°C/W
ψJB
Junction-to-board characterization parameter
89.6
30.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
11.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.7 Thermal Information: OPA2374
OPA2374
THERMAL METRIC
(1)
D (SOIC)
DCN (SOT-23)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
117.8
171.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
63.1
73.5
°C/W
RθJB
Junction-to-board thermal resistance
58.4
106.3
°C/W
ψJT
Junction-to-top characterization parameter
19.3
15.4
°C/W
ψJB
Junction-to-board characterization parameter
57.9
105.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.8 Thermal Information: OPA4374
OPA4374
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
UNIT
14 PINS
14 PINS
86.5
112.7
°C/W
45
34.1
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
41.1
57.1
°C/W
ψJT
Junction-to-top characterization parameter
12.3
2.9
°C/W
ψJB
Junction-to-board characterization parameter
40.8
56.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
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OPA2373, OPA2374, OPA4374
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SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
7.9 Electrical Characteristics: VS = 2.7 V to 5.5 V
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
5
mV
6.5
mV
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 5 V
Input offset voltage
versus temperature
TA = –40°C to 125°C
dVOS/dT
Input offset voltage
versus drift
TA = –40°C to +125°C
PSRR
Input offset voltage
versus power supply
VS = 2.7 V to 5.5 V,
VCM < (V+) – 2 V
Channel separation, DC
3
TA = 25°C
µV/°C
25
100
TA = –40°C to 125°C
µV/V
150
At f = 1 kHz
0.4
µV/V
128
dB
INPUT VOLTAGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
(V–) – 0.2
(V–) – 0.2 V < VCM < (V+) – 2 V
VS = 5.5 V,
(V–) – 0.2 V < VCM < (V+) + 0.2 V
(V+) + 0.2
V
TA = 25°C
80
TA = –40°C to 125°C
70
90
TA = 25°C
66
dB
TA = –40°C to 125°C
60
dB
dB
INPUT BIAS CURRENT
IB
Input bias current
±0.5
±10
pA
IOS
Input offset current
±0.5
±10
pA
INPUT IMPEDANCE
Differential
1013 || 3
Ω || pF
Common-mode
1013 || 6
Ω || pF
NOISE
Input voltage noise
VCM < (V+) – 2 V, f = 0.1 Hz to 10 Hz
10
µVPP
en
Input voltage noise density
VCM < (V+) – 2 V, f = 10 kHz
15
nV/√Hz
in
Input current noise density
VCM < (V+) – 2 V, f = 10 kHz
4
fA/√Hz
OPEN-LOOP GAIN
AOL
VS = 5 V, RL = 100 kΩ,
0.025 V < VO < 4.975 V
TA = 25°C
94
TA = –40°C to 125°C
80
VS = 5 V, RL = 5 kΩ,
0.125 V < VO < 4.875 V
TA = 25°C
94
TA = –40°C to 125°C
80
Open-loop voltage gain
110
dB
106
dB
OUTPUT
RL = 100 kΩ
Voltage output swing from
rail
RL = 5 kΩ
TA = 25°C
18
TA = –40°C to 125°C
TA = 25°C
100
TA = –40°C to 125°C
ISC
Short-circuit current
See Typical Characteristics
CLOAD
Capacitive load drive
See Typical Characteristics
RO
Open-loop output
impedance
f = 1 MHz, IO = 0 mA
Copyright © 2003–2016, Texas Instruments Incorporated
25
mV
25
mV
125
mV
125
mV
220
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SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
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Electrical Characteristics: VS = 2.7 V to 5.5 V (continued)
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 100 pF
6.5
MHz
SR
Slew rate
CL = 100 pF, G = +1
5
V/µs
0.1%, CL = 100 pF, VS = 5 V,
2-V step, G = +1
1
µs
0.01%, CL = 100 pF, VS = 5 V,
2-V step, G = +1
1.5
µs
Overload recovery time
CL = 100 pF, VIN ● Gain > VS
0.3
µs
Total harmonic distortion +
noise
CL = 100 pF, VS = 5 V, VO = 3 VPP,
G = +1, f = 1 kHz
tS
THD+N
Settling time
0.0013%
ENABLE OR SHUTDOWN
tOFF
Turnoff time
3
tON
Turnon time
12
VL
Logic low threshold
Shutdown
VH
Logic high threshold
Amplifier is active
µs
V–
(V–) + 0.8
V
(V–) + 2
V+
V
Input bias current of Enable
pin
IQ(sd)
µs
0.2
Quiescent current at
shutdown (per amplifier)
< 0.5
µA
1
µA
5.5
V
750
µA
800
µA
POWER SUPPLY
VS
Specified voltage range
2.7
Operating voltage range
IQ
Quiescent current
(per amplifier)
2.3 to 5.5
IO = 0 mA
TA = 25°C
585
TA = –40°C to 125°C
V
TEMPERATURE
Specified range
–40
125
°C
TA
Operating range
–55
150
°C
Tstg
Storage range
–65
150
°C
10
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7.10 Typical Characteristics
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2 (unless otherwise noted)
120
0
100
Gain
80
-30
60
-60
40
-90
Phase
Phase Margin (°)
Open-Loop Gain (dB)
100
30
PSRR and CMRR (dB)
120
CMRR
80
40
20
-120
0
-150
20
-180
0
-20
10
100
1k
10k
100k
1M
PSRR
60
100
10M
1k
10k
Frequency (Hz)
Figure 1. Open-Loop Gain and Phase vs Frequency
1M
10M
Figure 2. Power-Supply and Common-Mode
Rejection Ratio vs Frequency
0.100
Total Harmonic Distortion+Noise (%)
1000
Voltage Noise (nV/ÖHz)
100k
Frequency (Hz)
100
RL = 5kW
G = 10V/V
0.010
G = 1V/V
0.001
10
10
100
1k
10k
10
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 3. Input Voltage Noise Spectral Density vs Frequency
Figure 4. Total Harmonic Distortion + Noise vs Frequency
130
120
RL = 100kW
VS = 5.5V
110
VCM = -0.2V to 3.5V
120
CMRR (dB)
AOL, PSRR (dB)
100
110
RL = 5kW
100
90
80
VCM = -0.2V to 5.7V
70
PSRR
60
90
50
80
40
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 5. Open-Loop Gain and Power-Supply
Rejection Ratio vs Temperature
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150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Figure 6. Common-Mode Rejection Ratio vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2 (unless otherwise noted)
800
800
700
Quiescent Current (mA)
Quiescent Current (mA)
VOUT = 1/2[(V+) - (V-)]
600
500
400
300
700
600
500
400
300
-50
-25
0
25
50
75
100
125
150
2.0
2.5
3.0
Temperature (°C)
Figure 7. Quiescent Current vs Temperature
5.0
5.5
Figure 8. Quiescent Current vs Supply Voltage
+ISC
Short-Circuit Current (mA)
Short-Circuit Current (mA)
4.5
+ISC
14
12
10
8
-ISC
6
4
2
10
8
-ISC
6
4
2
0
0
-50
-25
0
25
50
75
100
2.0
125
2.5
3.0
3.5
4.0
4.5
5.0
Temperature (°C)
Power-Supply Voltage (V)
Figure 9. Short-Circuit Current vs Temperature
Figure 10. Continuous Short-Circuit Current
vs Power-Supply Voltage
5.5
3
10k
2
1k
Output Voltage (V)
Input Bias Current (pA)
4.0
12
16
100
10
1
1
0
-1
-55°C
25°C
150°C
-2
0.1
-50
12
3.5
Supply Voltage (V)
-3
-25
0
25
50
75
100
125
0
2
4
6
8
10
12
14
16
18
20
Temperature (°C)
Output Current (mA)
Figure 11. Input Bias Current vs Temperature
Figure 12. Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2 (unless otherwise noted)
6
VS = 5.5V
VS = 5V
4
3
Population
Output Voltage (VPP)
5
VS = 2.5V
2
1
0
10k
100k
1M
10M
-5
-4
-3
Typical production distribution
of packaged units.
1
2
3
4
5 5.5
50mV/div
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Offset Voltage Drift (mV/°C)
200ns/div
Figure 15. Offset Voltage Drift Magnitude
Production Distribution
Figure 16. Small-Signal Step Response
CL = 100pF
Refer to the Capacitive Load
and Stability section for tips
on improving performance.
40
G = +1V/V
1V/div
Small-Signal Overshoot (%)
0
CL = 100pF
Population
1
50
-1
Figure 14. Offset Voltage Production Distribution
Figure 13. Maximum Output Voltage vs Frequency
60
-2
Offset Voltage (mV)
Frequency (Hz)
30
20
G = 10V/V
RFB = 10kW
10
0
10
100
1k
10k
Load Capacitance (pF)
Figure 17. Small-Signal Overshoot vs Load Capacitance
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400ns/div
Figure 18. Large-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°C, RL = 10 kΩ connected to VS/2, and VOUT = VS/2 (unless otherwise noted)
140
100
G = +1V/V, All Channels
RL = 5kW
Channel Separation (dB)
Settling Time (ms)
120
10
0.01%
0.1%
1
100
80
60
40
20
0
0.1
1
14
Closed-Loop Gain (V/V)
10K
100K
Frequency (Hz)
Figure 19. Settling Time vs Closed-Loop Gain
Figure 20. Channel Separation vs Frequency
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100
10
100
1K
1M
10M
100M
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8 Detailed Description
8.1 Overview
The OPAx373 and OPAx374 operational amplifiers (op amps) are suitable for a broad range of general-purpose
applications. As unity-gain stable devices and outstanding AC performance, these op amps are ideal for audio
applications. The class AB output stage is capable of driving 100-kΩ loads connected to any point between V+
and ground. These devices are well-suited for nearly any single-supply application up to a supply voltage of
5.5 V because the input common-mode voltage range includes both rails. Rail-to-rail input and output swing
significantly increases the overall device dynamic range, especially in low-supply applications.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The OPA373 and OPA374 op amps are specified and tested over a power-supply range of 2.7 V to 5.5 V
(±1.35 V to ±2.75 V). However, the supply voltage may range from 2.3 V to 5.5 V (±1.15 V to ±2.75 V). Supply
voltages higher than 7 V (absolute maximum) can permanently damage the amplifier. Parameters that vary over
supply voltage or temperature are shown in the Typical Characteristics.
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Feature Description (continued)
8.3.2 Common-Mode Voltage Range
The input common-mode voltage range of the OPA373 and OPA374 series extends 200 mV beyond the supply
rails. This extended range is achieved with a complementary input stage: an N-channel input differential pair in
parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) − 1.65 V to 200 mV above the positive supply, while the P-channel pair is on for inputs from
200 mV below the negative supply to approximately (V+) − 1.65 V. There is a 500-mV transition region, typically
(V+) − 1.9 V to (V+) − 1.4 V, in which both pairs are on. This 500-mV transition region, shown in Figure 21, can
vary ±300 mV with process variation. Thus, the transition region (that is, both stages on) can range from
(V+) − 2.2 V to (V+) − 1.7 V on the low end, up to (V+) − 1.6 V to (V+) − 1.1 V on the high end. Within the
500-mV transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded, compared to
device operation outside this region.
2.0
Offset Voltage (mV)
1.5
1.0
0.5
0
- 0.5
- 1.0
- 1.5
- 2.0
-0.5 0
V+
V-
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common-Mode Voltage (V)
Figure 21. Behavior of Typical Transition Region at Room Temperature
8.3.3 Rail-to-Rail Input
The input common-mode range extends from (V−) − 0.2 V to (V+) + 0.2 V. For normal operation, inputs must be
limited to this range. The absolute maximum input voltage is 500 mV beyond the supplies. Inputs greater than
the input common-mode range but less than the maximum input voltage, while not valid, do not cause any
damage to the op amp. Unlike some other op amps, if input current is limited, the inputs may go beyond the
supplies without phase inversion, as shown in Figure 22.
G = +1V/V, VS = 5V
VIN
VOUT
1V/div
5V
0V
1ms/div
Figure 22. OPA373: No Phase Inversion With Inputs Greater Than the Power-Supply Voltage
Normally, input bias current is approximately 500 fA; however, input voltages exceeding the power supplies by
more than 500 mV can cause excessive current to flow in or out of the input pins. Momentary voltages greater
than 500 mV beyond the power supply can be tolerated if the current on the input pins is limited to 10 mA. This
limiting is easily accomplished with an input resistor; see Figure 23. Many input signals are inherently currentlimited to less than 10 mA, therefore, a limiting resistor is not required.
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Feature Description (continued)
V+
IOVERLOAD
10mA max
R
VOUT
OPA373
VIN
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Figure 23. Input Current Protection for Voltages Exceeding the Supply Voltage
8.3.4 Rail-to-Rail Output
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For light resistive
loads ( > 100 kΩ), the output voltage can typically swing to within 18 mV from the supply rails. With moderate
resistive loads (5 kΩ to 50 kΩ), the output can typically swing to within 100 mV from the supply rails and maintain
high open-loop gain. See Figure 12 for more information.
8.3.5 Capacitive Load and Stability
The OPA373 series op amps can drive a wide range of capacitive loads. However, under certain conditions, all
op amps may become unstable. Op amp configuration, gain, and load value are some of the factors to consider
when determining stability. An op amp in unity-gain configuration is the most susceptible to the effects of
capacitive load. The capacitive load reacts with the op amp output resistance, along with any additional load
resistance, to create a pole in the small-signal response that degrades the phase margin. The OPA373 series op
amps perform well in unity-gain configuration, with a pure capacitive load up to approximately 250 pF. Increased
gains allow the amplifier to drive more capacitance. See Figure 17 for further details.
One method of improving capacitive load drive in the unity-gain configuration is to insert a small (10-Ω to 20-Ω)
resistor, RS, in series with the output, as shown in Figure 24. This configuration significantly reduces ringing while
maintaining DC performance for purely capacitive loads. When there is a resistive load in parallel with the
capacitive load, RS must be placed within the feedback loop as shown to allow the feedback loop to compensate
for the voltage divider created by RS and RL.
V+
RS
10W to 20W
OPA373
VOUT
VIN
RL
CL
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Figure 24. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
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Feature Description (continued)
In unity-gain inverter configuration, phase margin can be reduced by the reaction between the capacitance at the
op amp input and the gain setting resistors, thus degrading capacitive load drive. Best performance is achieved
by using small-valued resistors. However, when large-valued resistors cannot be avoided, a small (4-pF to 6-pF)
capacitor, CFB, can be inserted in the feedback, as shown in Figure 25. This technique significantly reduces
overshoot by compensating the effect of capacitance, CIN, which includes the amplifier input capacitance and
printed-circuit board (PCB) parasitic capacitance.
CFB
RF
V+
RI
VIN
OPA373
VOUT
CIN
CL
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Figure 25. Improving Capacitive Load Drive
For example, when driving a 100-pF load in unity-gain inverter configuration, adding a 6-pF capacitor in parallel
with the 10-kΩ feedback resistor decreases overshoot from 57% to 12%, as shown in Figure 26.
60
G = -1V/V
RFB = 10kW
Overshoot (%)
50
40
30
20
10
CFB = 6pF
0
10
100
1k
10k
Load Capacitance (pF)
Figure 26. Improving Capacitive Load Drive
8.3.6 Enable or Shutdown
The OPA373 and OPA374 series op amps typically require 585-µA quiescent current. The enable or shutdown
feature of the OPA373 allows the op amp to be shut off to reduce this current to less than 1 µA.
8.4 Device Functional Modes
The OPAx374 has a single functional mode and is operational when the power-supply voltage is greater than
2.7 V (±1.35 V). The maximum power supply voltage for the OPAx374 is 5.5 V (±2.75 V).
The OPAx373 has two functional modes: active and shutdown. When the voltage at the Enable pin is from V– to
(V–) + 0.8 V, the device is in shutdown and consumes less than 0.5 µA of quiescent current (typical). To activate,
or enable, the device, the voltage at the Enable pin must be from (V–) + 2 V to V+. When active, the powersupply requirements are the same as the OPAx374.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA373 and OPA374 series op amps are unity-gain stable and suitable for a wide range of general-purpose
applications. Rail-to-rail input and output make them ideal for driving sampling analog-to-digital converters
(ADCs). Excellent AC performance makes them well-suited for audio applications. The class AB output stage is
capable of driving 100-kΩ loads connected to any point between V+ and ground.
The input common-mode voltage range includes both rails, allowing the OPA373 and OPA374 series op amps to
be used in virtually any single-supply application up to a supply voltage of 5.5 V. Rail-to-rail input and output
swing significantly increases dynamic range, especially in low-supply applications. Power-supply pins must be
bypassed with 0.01-µF ceramic capacitors.
9.2 Typical Application
This single-supply, low-side, bidirectional current-sensing solution detects load currents from –1 A to 1 A. The
single-ended output spans from 110 mV to 3.19 V. This design uses the OPA2374 because of its rail-to-rail input
and output range and cost compared to performance. One of the amplifiers is configured as a difference
amplifier, and the other amplifier provides the reference voltage.
3.3 V
3.3 V
VREF
R5 = 10 NŸ
+
U1B
R6 = 10 NŸ
R2 =
15.4 NŸ
ILOAD = ±1 A
VBUS
+
±
R1 = 1 NŸ
+
RSHUNT = 0.1 Ÿ
+
VSHUNT
±
VOUT = 1.65V ±1.54 V
R3 = 1 NŸ
U1A
3.3 V
RL = 5 NŸ
R4 = 15.4 NŸ
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Single-Supply, Low-Side, Bidirectional Current-Sensing Solution
9.2.1 Design Requirements
This design has the following requirements:
• Supply voltage: 3.3 V
• Input: –1 A to 1 A
• Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor (RSHUNT) to develop the shunt voltage, VSHUNT. The shunt
voltage is then amplified by the difference amplifier, which consists of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
where
•
•
VSHUNT = ILOAD ´ RSHUNT
GainDiff_Amp =
VREF = VCC ´
•
R4
R3
R6
R5 + R6
(1)
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4/R3 matches the ratio of R2/R1. The ratio of R2/R1 impacts the
CMRR of the difference amplifier, which ultimately translates to an offset error.
This is a low-side measurement. Therefore, the value of VSHUNT is the ground potential for the system load. Thus,
it is important to place a maximum value on VSHUNT. In this design, the maximum value for VSHUNT is set to
100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
|VSHUNT_Max| 100 mV
RSHUNT_Max = |I
= 100 mW
=
1A
LOAD_Max|
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
was selected. If greater accuracy is required, select a 0.1% resistor or better.
Because the load current is bidirectional, the shunt voltage range is –100 mV to 100 mV. This voltage is divided
down by R1 and R2 before reaching the op amp, U1A. Take care to ensure that the voltage present at the
noninverting node of U1A is within the common-mode range of the device.
It is therefore important to use an op amp, such as the OPA374, that has a common-mode range that extends
below the negative supply voltage.
Given a symmetric load current of –1 A to 1 A, the voltage divider resistors (R5 and R6) must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% was selected. To minimize power consumption,
10-kΩ resistors were used.
To set the gain of the difference amplifier, the common-mode range and output swing of the OPA374 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and output swing of the OPA374,
given a 3.3-V supply.
–200 mV < VCM < 3.5 V
100 mV < VOUT < 3.2 V
(3)
(4)
The gain of the difference amplifier can now be calculated as shown in Equation 5.
VOUT_Max - VOUT_Min
3.2 V - 100 mV
V
= 15.5
GainDiff_Amp =
=
V
RSHUNT ´ (IMAX - IMIN)
100 mW ´ [1 A - (- 1 A)]
(5)
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because it is the
nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4V/V.
Because the gain error of the circuit primarily depends on R1 through R4, 0.1% resistors were selected. This
value reduces the likelihood that the design requires a two-point calibration. A simple one-point calibration, if
desired, removes the offset errors introduced by the 0.5% resistors.
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Typical Application (continued)
9.2.3 Application Curve
Output Voltage (V)
3.3
1.65
0
-1
0
-0.5
0.5
1
Input Current (A)
Figure 28. Output Voltage vs Input Current
9.3 System Examples
9.3.1 Driving ADCs
The OPA373 and OPA374 series op amps are optimized for driving medium-speed sampling ADCs. The
OPA373 and OPA374 op amps buffer the ADC input capacitance and resulting charge injection, while providing
signal gain.
The OPA373 is shown driving the ADS7816 in a basic noninverting configuration, as Figure 29 shows. The
ADS7816 is a 12-bit, MicroPower sampling converter in the 8-pin VSSOP package. When used with the lowpower, miniature packages of the OPA373, the combination is ideal for space-limited, low-power applications. In
this configuration, an RC network at the ADC input can be used to provide anti-aliasing filtering.
+5V
0.1mF
8 V+
500W
0.1mF
1
VREF
DCLOCK
+In
OPA373
ADS7816
12-Bit A/D
2
VIN
-In
3300pF
DOUT
CS/SHDN
3
7
6
5
Serial
Interface
GND 4
VIN = 0V to 5V for
0V to 5V output.
RC network filters high-frequency noise.
NOTE: A/D Input = 0 to VREF
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Figure 29. The OPA373 in Noninverting Configuration Driving the ADS7816
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System Examples (continued)
Figure 30 shows the OPA373 driving the ADS7816 in a speech bypass-filtered data acquisition system. This
small, low-cost solution provides the necessary amplification and signal conditioning to interface directly with an
electret microphone. This circuit operates with VS = 2.7 V to 5 V.
V+ = +2.7V to +5V
Passband 300Hz to 3kHz
R9
510kW
R1
1.5kW
R2
1MW
R4
20kW
C3
33pF
C1
1000pF
R7
51kW
R8
150kW
8 V+
VREF 1
7
OPA373
Electret
Microphone
+IN
R3
1MW
(1)
C2
1000pF
R6
100kW
OPA373
ADS7816 6
12-Bit A/D
5
2
-IN
DCLOCK
DOUT
CS/SHDN
Serial
Interface
3
4 GND
R5
20kW
G = 100
Copyright © 2016, Texas Instruments Incorporated
Figure 30. The OPA2373 as a Speech Bypass-Filtered Data Acquisition System
The OPA373 is shown in the inverting configuration described in Figure 31. In this configuration, filtering may be
accomplished with the capacitor across the feedback resistor.
+5V
330pF
0.1mF
5kW
0.1mF
5kW
VIN
1
8 V+
500kW
DCLOCK
+IN
OPA373
ADS7816
12-Bit A/D
2
-IN
3300pF
VIN = 0V to -5V for 0V to 5V output.
VREF
DOUT
CS/SHDN
3
7
6
5
Serial
Interface
GND 4
NOTE: A/D Input = 0 to VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 31. The OPA373 in Inverting Configuration Driving the ADS7816
Figure 32 shows the OPA373 configured as a three-pole, Sallen-Key, Butterworth low-pass filter.
22
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Product Folder Links: OPA373 OPA374 OPA2373 OPA2374 OPA4374
OPA373, OPA374
OPA2373, OPA2374, OPA4374
www.ti.com
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
System Examples (continued)
C3
330pF
R1
11.7kW
1/2
R2
2.72kW
R3
21.4kW
OPA373
1/2
OPA373
C1
680pF
C2
330pF
Copyright © 2016, Texas Instruments Incorporated
Figure 32. Three-Pole, Sallen-Key, Butterworth Low-Pass Filter
10 Power Supply Recommendations
The OPAx373 and OPAx374 are specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V). Parameters
that can exhibit significant variance with regard to operating voltage are presented in the Typical Characteristics.
11 Layout
11.1 Layout Guidelines
The leadframe die pad must be soldered to a thermal pad on the PCB. A mechanical data sheet showing an
example layout is attached at the end of this data sheet. Refinements to this layout may be required based on
assembly process requirements.
Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad.
The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the
leadframe die pad to the heat sink area on the PCB. Soldering the exposed pad significantly improves boardlevel reliability during temperature cycling, key push, package shear, and similar board-level tests.
Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide
structural integrity and long-term reliability.
11.1.1 VSON Package
The OPA2373 is available in a 10-pin VSON package, which is a VQFN package with lead contacts on only two
sides of the bottom of the package. This leadless, near-chip-scale package maximizes board space and
enhances thermal and electrical characteristics through an exposed pad. VSON packages are physically small,
have a smaller routing area, improved thermal performance, and improved electrical parasitics, with a pinout
scheme that is consistent with other commonly-used packages, such as SOIC and VSSOP. Additionally, the
absence of external leads eliminates bent-lead issues.
The VSON package can be easily mounted using standard PCP assembly techniques. See QFN/SON PCB
Attachment and Quad Flatpack No-Lead Logic Packages, both available for download at www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the package must be connected to V−.
Copyright © 2003–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OPA373 OPA374 OPA2373 OPA2374 OPA4374
23
OPA373, OPA374
OPA2373, OPA2374, OPA4374
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
www.ti.com
11.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 33. Operational Amplifier Board Layout for Noninverting Configuration
24
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Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: OPA373 OPA374 OPA2373 OPA2374 OPA4374
OPA373, OPA374
OPA2373, OPA2374, OPA4374
www.ti.com
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation
tool these TI packages: D or U (8-pin SOIC), PW (8-pin TSSOP), DGK (8-pin MSOP), DBV (6-pin SOT-23, 5-pin
SOT23, and 3-pin SOT-23), DCK (6-pin SC-70 and 5-pin SC-70), and DRL (6-pin SOT-563). The DIP Adapter
EVM may also be used with terminal strips or may be wired directly to existing circuits.
12.1.1.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, MSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
12.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
12.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
Copyright © 2003–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OPA373 OPA374 OPA2373 OPA2374 OPA4374
25
OPA373, OPA374
OPA2373, OPA2374, OPA4374
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
www.ti.com
12.2 Documentation Support
12.2.1 Related Documentation
The following documents are relevant to using the OPAx373, OPAx374, and recommended for reference. All are
available for download at www.ti.com (unless otherwise noted):
• 36-V, 1-kW Brushless DC Motor Drive With Stall Current Limit of < 1-µs Response Time Reference Design
(TIDU852)
• OPA373 EMI Immunity Performance (SBOZ009)
• AB-045 Op Amp Performance Analysis (SBOA054)
• AB-067 Single-Supply Operation of Operational Amplifiers (SBOA059)
• AB-105 Tuning in Amplifiers (SBOA067)
• QFN/SON PCB Attachment (SLUA271)
• Quad Flatpack No-Lead Logic Packages (SCBA017)
12.3 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA373
Click here
Click here
Click here
Click here
Click here
OPA2373
Click here
Click here
Click here
Click here
Click here
OPA374
Click here
Click here
Click here
Click here
Click here
OPA2374
Click here
Click here
Click here
Click here
Click here
OPA4374
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
26
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Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: OPA373 OPA374 OPA2373 OPA2374 OPA4374
OPA373, OPA374
OPA2373, OPA2374, OPA4374
www.ti.com
SBOS279F – SEPTEMBER 2003 – REVISED SEPTEMBER 2016
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2003–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OPA373 OPA374 OPA2373 OPA2374 OPA4374
27
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2373AIDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
Call TI | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
AYO
Samples
OPA2373AIDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
Call TI | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
AYO
Samples
OPA2373AIDRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCEQ
Samples
OPA2373AIDRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCEQ
Samples
OPA2374AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
2374A
Samples
OPA2374AIDCNR
ACTIVE
SOT-23
DCN
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ATP
Samples
OPA2374AIDCNRG4
ACTIVE
SOT-23
DCN
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ATP
Samples
OPA2374AIDCNT
ACTIVE
SOT-23
DCN
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ATP
Samples
OPA2374AIDCNTG4
ACTIVE
SOT-23
DCN
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ATP
Samples
OPA2374AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
2374A
Samples
OPA2374AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
OPA
2374A
Samples
OPA373AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
373A
Samples
OPA373AIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A75
Samples
OPA373AIDBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A75
Samples
OPA373AIDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A75
Samples
OPA373AIDBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A75
Samples
OPA373AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
373A
Samples
OPA373AIDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
373A
Samples
OPA374AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
374A
OPA374AIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A76
Samples
OPA374AIDBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A76
Samples
OPA374AIDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A76
Samples
OPA374AIDBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A76
Samples
OPA374AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
374A
Samples
OPA374AIDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
374A
Samples
OPA4374AID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4374A
Samples
OPA4374AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4374A
Samples
OPA4374AIPWR
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4374A
Samples
OPA4374AIPWRG4
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4374A
Samples
OPA4374AIPWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
4374A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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