OPA3875
www.ti.com ............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
Triple 2:1 High-Speed Video Multiplexer
FEATURES
DESCRIPTION
1
• 700MHz SMALL-SIGNAL BANDWIDTH
(AV = +2)
• 425MHz, 4VPP BANDWIDTH
• 0.1dB GAIN FLATNESS to 150MHz
• 4ns CHANNEL SWITCHING TIME
• LOW SWITCHING GLITCH: 40mVPP
• 3100V/µs SLEW RATE
• 0.025%/0.025° DIFFERENTIAL GAIN, PHASE
• HIGH GAIN ACCURACY: 2.0V/V ±0.4%
The OPA3875 offers a very wideband, 3-channel, 2:1
multiplexer in a small SSOP-16 package. Using only
11mA/ch, the OPA3875 provides three, gain of +2,
video amplifier channels with greater than 400MHz
large-signal bandwidth (4VPP). Gain accuracy and
switching glitch are improved over earlier solutions
using a new (patented) input stage switching
approach. This technique uses current steering as the
input switch while maintaining an overall closed-loop
design. Gain matching between each of the
3-channel pairs is also significantly improved using
this technique ( 100kHz
6.7
7.0
7.2
7.4
nV/√Hz
max
B
Input Current Noise
f > 100kHz
3.8
4.2
4.6
4.9
pA/√Hz
max
B
NTSC Differential Gain
RL = 150Ω
0.025
%
typ
C
NTSC Differential Phase
RL = 150Ω
0.025
C
Slew Rate
VO = ±2V
3100
VO = 0.5V Step
Bandwidth for 0.1dB Gain Flatness
SFDR
°
typ
V/µs
min
B
460
ps
typ
C
VO = 1.4V Step
600
ps
typ
C
Channel to Channel, RL = 150Ω
±0.05
±0.25
±0.3
±0.35
%
max
A
All inputs, RL = 150Ω
±0.1
±0.5
±0.6
±0.7
%
max
A
All three outputs
±3
±9
±10
±12
mV
max
A
All Hostile Crosstalk
f = 50MHz, RL = 150Ω
–50
dB
typ
C
Channel-to-Channel Crosstalk
f = 50MHz, RL = 150Ω
–58
dB
typ
C
RL = 150Ω
4
ns
typ
C
Turn On
9
ns
typ
C
Turn Off
60
ns
typ
C
SEL (Channel Select) Switching Glitch
All Inputs to Ground, At Matched Load
40
mVPP
typ
C
EN (Chip-Select) Switching Glitch
All Inputs to Ground, At Matched Load
15
mVPP
typ
C
50MHz, Chip Disabled (EN = High)
–68
dB
typ
C
Rise Time and Fall Time
2800
2700
2600
CHANNEL-TO-CHANNEL PERFORMANCE
Gain Match
Output Offset Voltage Mismatch
CHANNEL AND CHIP-SELECT PERFORMANCE
SEL (Channel Select) Swtiching Time
EN (Chip Select) Switching Time
All Hostile Disable Feedthrough
Maximum Logic 0
EN, SEL
0.8
0.8
0.8
V
max
B
Minimum Logic 1
EN, SEL
2.0
2.0
2.0
V
min
B
EN Logic Input Current
0V to 4.5V
75
100
125
150
µA
max
A
SEL Logic Input Current
0V to 4.5V
160
200
250
300
µA
max
A
Output Offset Voltage
RIN = 0Ω, G = +2V/V
±2.5
±14
±15.8
±17
mV
max
A
Average Output Offset Voltage Drift
RIN = 0Ω, G = +2V/V
±50
±50
µV/°C
max
B
±19.5
±20.5
µA
max
A
±40
±40
nA/°C
max
B
1.5
1.6
%
max
A
DC PERFORMANCE
Input Bias Current
±5
±18
Average Input Bias Current Drift
Gain Error (from 2V/V)
VO = ±2V
0.4
1.4
INPUT
Input Voltage Range
±2.8
V
typ
C
Input Resistance
1.75
MΩ
typ
C
Channel Selected
0.9
pF
typ
C
Channel Deselected
0.9
pF
typ
C
Chip Disabled
0.9
pF
typ
C
Input Capacitance
(1)
(2)
(3)
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C tested specifications.
Junction temperature = ambient at low temperature limit; junction temperature = ambient +36°C at high temperature limit for over
temperature specifications.
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ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2, RL = 150Ω, unless otherwise noted.
OPA3875
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
CONDITIONS
+25°C
+25°C (2)
0°C to
70°C (3)
–40°C to
+85°C (3)
UNITS
MIN/
MAX
TEST
LEVEL (1)
A
OUTPUT
Output Voltage Range
Output Current
Output Resistance
Output Capacitance
±3.5
±3.4
±3.35
±3.3
V
min
VO = 0V, Linear Operation
±70
±50
±45
±40
mA
min
A
Chip enabled
0.3
Ω
typ
C
A
Chip Disabled, Maximum
800
912
915
918
Ω
max
Chip Disabled, Minumum
800
688
685
682
Ω
min
A
Chip Disabled
2
pF
typ
C
POWER SUPPLY
Specified Operating Voltage
V
typ
C
Minimum Operating Voltage
±5
±3.0
±3.0
±3.0
V
min
B
Maximum Operating Voltage
±6.3
±6.3
±6.3
V
max
A
Maximum Quiescent Current
Chip Selected, VS = ±5V
33
34
35
36
mA
max
A
Minimum Quiescent Current
Chip Selected, VS = ±5V
33
31
30
27
mA
min
A
Maximum Quiescent Current
Chip Deselected
0.9
1.2
1.4
1.5
mA
max
A
(+PSRR)
Input-Referred
56
50
48
47
dB
min
A
(–PSRR)
Input-Referred
55
51
49
48
dB
min
A
–40 to +85
°C
typ
C
85
°C/W
typ
C
Power-Supply Rejection Ratio
THERMAL CHARACTERISTICS
Specified Operating Range D Package
Thermal Resistance θJA
DBQ
4
Junction-to-Ambient
SSOP-16
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www.ti.com ............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V
At G = +2 and RL = 150Ω, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
0.2
1
0.1
4
0
Gain Flatness
Right Scale
3
-0.1
2
-0.2
VO = 500mVPP
RL = 150W
G = +2V/V
1
-0.3
0
8
6
5
10M
100M
4
3
VO = 4VPP
2
1
VO = 1VPP
0
-1
-3
1G
0
100
200 300 400 500 600 700
Frequency (Hz)
Figure 2.
NONINVERTING PULSE RESPONSE
0.3
Large-Signal 4VPP
Right Scale
-20
2.0
-30
1.5
0.2
1.0
Small-Signal 0.4VPP
Left Scale
0.1
0.5
0
0
-0.1
-0.5
-0.2
-1.0
-0.3
-1.5
-0.4
-2.0
100MHz Square-Wave Input
-0.5
Input-Referred
EN = +5V
-40
Isolation (dB)
RL = 150W
G = +2V/V
ALL INPUT DISABLE FEEDTHROUGH vs FREQUENCY
2.5
Large-Signal Output Voltage (V)
Small-Signal Output Voltage (V)
0.4
800 900 1000
Frequency (100MHz/div)
Figure 1.
0.5
VO = 2VPP
VO = 5VPP
-2
-0.4
1M
RL = 150W
G = +2V/V
7
Gain (dB)
Gain (dB)
6
LARGE-SIGNAL FREQUENCY RESPONSE
0.3
Frequency Response
Left Scale
Normalized Gain Flatness (dB)
7
-50
-60
-70
-80
-90
-100
-2.5
-110
1M
Time (1ns/div)
10M
100M
1G
Frequency (Hz)
Figure 3.
Figure 4.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
8
80
Gain to Capacitive Load (dB)
60
50
RS (W)
0.1dB Peaking Targeted
7
70
40
30
20
10
CL = 10pF
6
5
4
3
CL = 47pF
2
1
RS
0
CL
-1
1kW
(1)
CL = 22pF
75W
-2
0
CL = 100pF
x2
75W
NOTE: (1) 1kW is optional.
-3
1
10
100
1000
1
10
100
400
Frequency (MHz)
Capacitive Load (pF)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
-40
VO = 2VPP
f = 10MHz
-65
2nd-Harmonic
-70
-75
-80
3rd-Harmonic
-85
-50
-55
-60
2nd-Harmonic
-65
-70
-75
-80
3rd-Harmonic
-85
-90
dBc = dB Below Carrier
-90
100
VO = 2VPP
RL = 150W
f = 10MHz
-45
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
dBc = dB Below Carrier
-95
2.5
1k
-55
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
-85
-90
-95
-60
2nd-Harmonic
-65
-70
-75
-80
3rd-Harmonic
-85
-90
dBc = dB Below Carrier
10
0.5
100
1.5
2.5
3.5
4.5
5.5
Frequency (MHz)
Output Voltage Swing (VPP)
Figure 9.
Figure 10.
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
6.5 7.0
OUTPUT VOLTAGE AND CURRENT LIMITIATIONS
5
-50
RL = 100W
Load Power at Matched 50W Load
dBc = dB Below Carrier
4
1W Internal
Power Limit
3
2
-70
VOUT (V)
Third-Order Spurious Level (dBc)
6.0
-100
1
50MHz
-80
20MHz
100W Load Line
1
25W Load Line
0
-1
-2
10MHz
50W Load Line
-3
-90
1W Internal
Power Limit
-4
-100
-6
-4
-2
0
2
4
6
8
10
-5
-200
-150
-100
-50
0
50
100
150
200
IO (mA)
Single-Tone Load Power (dBm)
Figure 11.
6
5.5
RL = 150W
f = 10MHz
-95
dBc = dB Below Carrier
-100
-60
5.0
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
-60
4.5
Figure 8.
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-55
4.0
Figure 7.
VO = 2VPP
RL = 150W
-50
3.5
Supply Voltage (±V)
HARMONIC DISTORTION vs FREQUENCY
-45
3.0
Resistance (W)
Figure 12.
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www.ti.com ............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
VSEL
RL = 150W
VIN_Ch1 = 400MHz, 1VPP
VIN_Ch0 = 0VDC
Output Voltage
VSEL
VIN_Ch0 = +0.5VDC
VIN_Ch1 = -0.5VDC
Time (5ns/div)
Figure 14.
DISABLE/ENABLE TIME
Output Voltage (V)
At Matched Load
(0V input both channels)
10
0
-10
-20
6
VSEL
4
2
0
-2
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
Output Voltage
VEN
Channel Select (V)
Output Voltage (mV)
CHANNEL SWITCHING GLITCH
40
20
VIN_Ch1 = 0V
VIN_Ch0 = 200MHz, 1VPP
Time (20ns/div)
Time (10ns/div)
Figure 15.
Figure 16.
CHANNEL-TO-CHANNEL CROSSTALK
-20
Input-Referred
At Matched Load
-30
10
5
-40
0
-5
6
VEN
4
2
0
-2
Time (100ns/div)
Enable Voltage (V)
-10
Crosstalk (dB)
Output Voltage (V)
DISABLE/ENABLE SWITCHING GLITCH
20
15
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
Time (5ns/div)
Figure 13.
30
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
Channel Select (V)
Output Voltage
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
Enable Voltage (V)
Output Voltage (V)
CHANNEL-TO-CHANNEL SWITCHING TIME
Channel Select (V)
Output Voltage (V)
CHANNEL SWITCHING
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
B0 Selected
B1 Driven
-50
-60
R1 Selected
R0 Driven
-70
-80
-90
1M
10M
100M
1G
Frequency (Hz)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
ALL HOSTILE AND ADJACENT-CHANNEL CROSSTALK vs
FREQUENCY
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
0
10k
Input-Referred
Output Impedance (W)
-10
-30
-40
Adjacent Channel Crosstalk
-50
-60
Disabled
1k
100
10
1
All Hostile Crosstalk
Enabled
-70
-80
1M
10M
100M
0.1
100k
1G
1M
Figure 19.
Figure 20.
INPUT IMPEDANCE vs FREQUENCY
PSRR vs FREQUENCY
Power-Supply Rejection Ratio (dB)
100k
10k
1k
100
100k
1M
10M
100M
-PSRR
50
+PSRR
40
30
20
10
0
100
1G
1k
10k
100k
Figure 21.
SUPPLY CURRENT vs TEMPERATURE
4.5
Output Offset Voltage (mV)
38
Supply Current (mA)
36
34
32
30
28
26
24
22
25
50
100M
1G
TYPICAL DC DRIFT OVER TEMPERATURE
5.0
0
10M
Figure 22.
40
-25
1M
Frequency (Hz)
Frequency (Hz)
75
100
125
10
Output Offset Voltage (VOS)
Left Scale
9
4.0
8
3.5
7
3.0
6
2.5
5
2.0
1.5
4
Input Bias Current (IB)
Right Scale
3
1.0
2
0.5
1
0
-50
0
-25
Ambient Temperature (°C)
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 23.
8
1G
60
1M
20
-50
100M
Frequency (Hz)
10M
Input Impedance (W)
10M
Frequency (Hz)
Input Bias Current (mA)
Crosstalk (dB)
-20
Figure 24.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE
Voltage Noise (nV/ÖHz)
Current noise (pA/ÖHz)
100
10
Voltage Noise (6.7nV/ÖHz)
Input Current Noise (3.8pA/ÖHz)
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 25.
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APPLICATIONS INFORMATION
2:1 HIGH-SPEED VIDEO MULTIPLEXER
OPERATION
The OPA3875 can be used as a triple 2:1 high-speed
video multiplexer, as illustrated in the front page
schematic for an RGB signal. Figure 26 shows a
simplified version of the front page schematic in
which one output is shown with its input and output
impedance matching resistors.
RGB VIDEO INVERTER
Figure 27 illustrates an extension of the previously
shown RGB switching circuit with a noninverting
signal going through channel 1 and an inverted signal
going through channel two. Here, the output
impedance of the OPA3875 is set to 75Ω. Looking at
the input part of this circuit, we see that the RGB
signal is inverted with an OPA3693 fixed gain set in
an inverting configuration with a reference voltage on
the noninverting node. The reference voltage, set
here at 0.714V, has a gain of 1 at the output of the
OPA3691 as the input signal is AC-coupled (not
represented here). This bias voltage is required to
prevent the video from swinging negative. Note also
that the 75Ω input matching impedance is set here by
the parallel combination of 92Ω and 402Ω. In order
not to disturb the sync, color burst, and blanking if
present, the inverting amplifiers are only switched on
during active video.
LOGO INSERTER
Figure 28 illustrates the principle of overlaying a
picture in a picture. The picture comes through U1;
the signal to be overlayed comes through U2. Here
we have a reference voltage of 0.714V in channel 2
indicating that we will highlight a section of the picture
with white (for NTSC-related RGB video). How much
white comes through depends on the combination of
select 1 and select 2 pins as well as the series output
resistance of each OPA3875. To match the 75Ω
output impedance of the video cable, the parallel
combination of the series output resistance (R and
nR) needs to be 75Ω. The two select pins gives us 2
bits of control. By selecting n = 2, you have the
capability of a 0% highlight (full original video signal),
33% highlight, 66% highlight, and 100% highlight (all
white). By selecting n = 3, you have 0%, 25%, 75%,
and 100% highlight capabilities, etc.
+5V
1/3 OPA3875
VIN_1
x1
75W
75W
VOUT
402W
VIN_2
x1
75W
402W
EN
-5V
Channel
Select
Figure 26. Triple 2:1 High-Speed Video Multiplexer
10
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+5V
OPA3875
RIN
x1
75W
92W
ROUT
402W
GIN
x1
402W
92W
BIN
75W
x1
92W
GOUT
300W
402W
300W
1/3
OPA3693
x1
402W
VREF
300W
75W
BOUT
300W
1/3
OPA3693
402W
x1
VREF
402W
300W
300W
1/3
OPA3693
x1
VREF
VREF = 0.749V
-5V
Channel
Select
EN
Figure 27. RGB Video Inverter
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+5V
U1
OPA3875
RIN
x1
RO
75W
ROUT
402W
GIN
x1
402W
75W
RO
x1
BIN
GOUT
75W
402W
402W
x1
RO
BOUT
x1
402W
402W
x1
VREF
EN
-5V
Select 1
Select 2
U2
OPA3875
x1
nRO
402W
x1
402W
nRO
x1
402W
x1
402W
nRO
x1
402W
402W
VREF = 0.714V
RO || nRO = 75W
x1
VREF
-5V
EN
Figure 28. Logo Inserter
12
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ADC INPUT MUX
Figure 29 shows the OPA3875 used as a multiplexer in a high-speed data acquisition signal chain.
+5V
250W
OPA3875
+3.3V
VCC
VIN1
x1
250W
IN
250W
VCM
402W
IN
402W
250W
250W
+3.3V
VCC
VIN2
x1
250W
IN
VCM
250W
402W
250W
250W
+3.3V
VCC
x1
250W
IN
250W
VIN4
VCM
402W
402W
x1
VIN6
x1
-5V
Channel
Select
1/2
ADS5232
IN
x1
VIN5
1/2
ADS5232
IN
402W
VIN3
1/2
ADS5232
250W
EN
Figure 29. ADC Input Multiplexer
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DESIGN-IN TOOLS
DEMONSTRATION FIXTURE
A printed circuit board (PCB) is available to assist in
the initial evaluation of circuit performance using the
OPA3875. The fixture is offered free of charge as an
unpopulated PCB, delivered with a user's guide. The
summary information for this fixture is shown in
Table 1.
Table 1. OPA3875 Demonstration Fixture
PRODUCT
PACKAGE
ORDERING NUMBER
LITERATURE
NUMBER
OPA3875IDBQ
SSOP-16
DEM-OPA-SSOP-3E
SBOU043
The demonstration fixture can be requested at the
Texas Instruments web site at (www.ti.com) through
the OPA3875 product folder.
MACROMODELS AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the OPA875 is available through the Texas
Instruments web site at www.ti.com. Use three of
these models to simulate the OPA3875. These
models do a good job of predicting small-signal AC
and transient performance under a wide variety of
operating conditions. They do not do as well in
predicting the harmonic distortion or dG/dP
characteristics. These models do not attempt to
distinguish between the package types in their
small-signal AC performance nor do they predict
channel-to-channel effects.
problem have been suggested. When the primary
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the
capacitive load. This isolation resistor does not
eliminate the pole from the loop response, but rather
shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the
capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Characteristics show the recommended
RS versus capacitive load and the resulting frequency
response at the load; see Figure 5 and Figure 6,
respectively. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the
OPA3875. Long PCB traces, unmatched cables, and
connections to multiple devices can easily cause this
value to be exceeded. Always consider this effect
carefully, and add the recommended series resistor
as close as possible to the OPA3875 output pin (see
the Board Layout Guidelines section).
DC ACCURACY
The OPA3875 offers excellent DC signal accuracy.
Parameters that influence the output DC offset
voltage are:
• Output offset voltage
• Input bias current
• Gain error
• Power-supply rejection ratio
• Temperature
Leaving both temperature and gain error parameters
aside, the output offset voltage envelope can be
described as shown in Equation 1:
VOSO_envelope = VOSO + (RS·Ib) x G ± |5 - (VS+)| x 10
± |-5 - (VS+)| x 10
OPERATING SUGGESTIONS
+ VCM x 10
- CMRR
20
(1)
DRIVING CAPACITIVE LOADS
One of the most demanding, yet very common load
conditions is capacitive loading. Often, the capacitive
load is the input of an ADC—including additional
external capacitance that may be recommended to
improve ADC linearity. A high-speed device such as
the OPA3875 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the device open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
14
- PSRR20
- PSRR+
20
With:
VOSO: Output offset voltage
RS: Input resistance seen by R0, R1, G0, G1, B0,
or B1.
Ib: Input bias current
G: Gain
VS+: Positive supply voltage
VS–: Negative supply voltage
PSRR+: Positive supply PSRR
PSRR–: Negative supply PSRR
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Evaluating the front-page schematic, using a
worst-case, +25°C offset voltage, bias current and
PSRR specifications and operating at ±6V, gives a
worst-case output equal to Equation 2:
- 50
20
±14mV + 75W x ±18mA x 2 ± |5 - 6| x 10
± |-5 - (-6)| x 10
- 51
20
= ±22.7mV
(2)
NOISE PERFORMANCE
The OPA3875 offers an excellent balance between
voltage and current noise terms to achieve low output
noise. As long as the AC source impedance looking
out of the noninverting node is less than 100Ω, this
current noise will not contribute significantly to the
total output noise. Figure 30 shows this device noise
analysis model with all the noise terms included. In
this model, all noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
DISTORTION PERFORMANCE
+5V
The OPA3875 provides good distortion performance
into a 100Ω load on ±5V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads. Generally, until the
fundamental signal reaches very high frequency or
power levels, the 2nd-harmonic dominates the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the
load impedance improves distortion directly. Also,
providing an additional supply decoupling capacitor
(0.01µF) between the supply pins (for bipolar
operation) improves the 2nd-order distortion slightly
(3dB to 6dB).
1/3 OPA3875
en
x1
RS
ib
eo
x1
eRS
402W
4kTRS
402W
-5V
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the 2nd-harmonic increasing at
a little less than the expected 2X rate while the
3rd-harmonic increases at a little less than the
expected 3X rate. Where the test power doubles, the
2nd-harmonic increases only by less than the
expected 6dB, whereas the 3rd-harmonic increases
by less than the expected 12dB. This also shows up
in the two-tone, 3rd-order intermodulation spurious
(IM3) response curves. The 3rd-order spurious levels
are extremely low at low output power levels. The
output stage continues to hold them low even as the
fundamental power reaches very high levels. As the
Typical
Characteristics
show,
the
spurious
intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not
decrease significantly. For two tones centered at
20MHz, with 4dBm/tone into a matched 50Ω load
(that is, 1VPP for each tone at the load, which requires
4VPP for the overall 2-tone envelope at the output
pin), the Typical Characteristics show a 82dBc
difference between the test-tone power and the
3rd-order intermodulation spurious levels.
Channel
Select
EN
Figure 30. Noise Model
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 3 shows the
general form for the output noise voltage using the
terms shown in Figure 30.
eo = 2
2
2
en + (ibRS) + 4kTRS
(3)
Dividing this expression by the device gain (2V/V)
gives the equivalent input-referred spot noise voltage
at the noninverting input as shown in Equation 4.
en =
2
2
en + (ibRS) + 4kTRS
(4)
Evaluating these two equations for the OPA3875
circuit and component values shown in Figure 26
gives a total output spot noise voltage of 13.6nV/√Hz
and a total equivalent input spot noise voltage of
6.8nV/√Hz. This total input-referred spot noise
voltage is higher than the 6.7nV/√Hz specification for
the mux voltage noise alone. This number reflects the
noise added to the output by the bias current noise
times the source resistor.
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OPA3875
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THERMAL ANALYSIS
Heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired
junction temperature will set the maximum allowed
internal power dissipation as discussed in this
document. In no case should the maximum junction
temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by TA +
PD × θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load but, for a grounded resistive load, is
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
supplies). Under this condition PDL = VS2/(4 × RL),
where RL includes feedback network loading.
Note that it is the power in the output stage and not in
the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ
using an OPA3875 in the circuit of Figure 26
operating at the maximum specified ambient
temperature of +85°C with all three outputs driving a
grounded 100Ω load to +2.5V:
2
PD = 10V ´ 36mA + 3(5 /4 ´ (100W || 804W)) = 571mW
Maximum TJ = +85°C + (0.57W ´ 85°C/W) = 133°C
This worst-case condition is approaching the
maximum +150°C junction temperature. Normally,
this extreme case is not encountered. Careful
attention to internal power dissipation is required.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high
frequency amplifier such as the OPA3875 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
capacitance on the output pin can cause instability:
on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To
reduce unwanted capacitance, a window around the
signal I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
16
b) Minimize the distance (< 0.25") from the
power-supply pins to high frequency 0.1µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections (on pins 9, 11, 13, and 15)
should always be decoupled with these capacitors.
An optional supply decoupling capacitor across the
two power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA3875. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially leaded resistors can
also provide good high-frequency performance.
Again, keep their leads and PCB trace length as short
as possible. Never use wirewound type resistors in a
high-frequency
application.
Other
network
components, such as noninverting input termination
resistors, should also be placed close to the package.
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the plot of Figure 5. Low parasitic
capacitive loads (< 5pF) may not need an RS
because the OPA3875 is nominally compensated to
operate with a 2pF parasitic load. If a long trace is
required, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher
impedance environment will improve distortion as
shown in the Distortion versus Load plots.
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With a characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the output
of the OPA3875 is used as well as a terminating
shunt resistor at the input of the destination device.
Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and
the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA3875 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If
the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the
series resistor value as shown in Figure 5. This will
not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
e) Socketing a high-speed part like the OPA3875
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA3875 onto the board.
INPUT AND ESD PROTECTION
The OPA3875 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins have limited ESD protection using internal
diodes to the power supplies as shown in Figure 31.
+VCC
External
Pin
Internal
Circuitry
-VCC
Figure 31. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA3875), current-limiting
series resistors should be added into the two inputs.
Keep these resistor values as low as possible
because high values degrade both noise performance
and frequency response.
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OPA3875
SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com
Revision History
Changes from Revision C (September 2007) to Revision D .......................................................................................... Page
•
Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C ................................................................................................................................................................................... 2
Changes from Revision B (December 2006) to Revision C ........................................................................................... Page
•
18
Changed the ordering number column in Table 1. .............................................................................................................. 14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA3875IDBQ
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP3875
OPA3875IDBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP3875
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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