OPA388, OPA2388, OPA4388
SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
OPAx388 Precision, Zero-Drift, Zero-Crossover, True Rail-to-Rail, Input/Output
Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
The OPAx388 (OPA388, OPA2388, and OPA4388)
series of precision operational amplifiers are ultra-low
noise, fast-settling, zero-drift, zero-crossover devices
that provide rail-to-rail input and output operation.
These features and excellent ac performance,
combined with only 0.25 µV of offset and 0.005
µV/°C of drift over temperature, makes the OPAx388
a great choice for driving high-precision, analog-todigital converters (ADCs) or buffering the output of
high-resolution, digital-to-analog converters (DACs).
This design results in excellent performance when
driving analog-to-digital converters (ADCs) without
degradation of linearity. The OPA388 (single version)
is available in the VSSOP-8, SOT23-5, and SOIC-8
packages. The OPA2388 (dual version) is offered in
the VSSOP-8 and SO-8 packages. The OPA4388
(quad version) is offered in the TSSOP-14 and
SO-14 packages. All versions are specified over the
industrial temperature range of –40°C to +125°C.
Ultra-low offset voltage: ±0.25 µV
Zero drift: ±0.005 µV/°C
Zero crossover: 140-dB CMRR true RRIO
Low noise: 7.0 nV√Hz at 1 kHz
No 1/f noise: 140 nVPP (0.1 Hz to 10 Hz)
Fast settling: 2 µs (1 V to 0.01%)
Gain bandwidth: 10 MHz
Single supply: 2.5 V to 5.5 V
Dual supply: ±1.25 V to ±2.75 V
True rail-to-rail input and output
EMI/RFI filtered inputs
Industry-standard packages:
– Single in SOIC-8, SOT-23-5, and VSSOP-8
– Dual in SOIC-8 and VSSOP-8
– Quad in SOIC-14 and TSSOP-14
2 Applications
Merchant network and server PSU
Notebook PC power adapter design
Weigh scale
Lab and field instrumentation
Battery test
Electronic thermometer
Temperature transmitter
Device Information
PART NUMBER
OPA388
OPA2388
OPA4388
5V
RG
REF5025
R4
100 k
R2
25 k
5V
5V
5V
+SENSE
±
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm x 3.90 mm
TSSOP (14)
5.00 mm x 4.40 mm
2.53
3
2.52
2
2.51
1
2.5
0
2.49
-1
+
GND
RG = 1 kŸ
GND
±SENSE
Load Cell
GND
GND
-2
2.48
OPA388
+
R2
10 k
4.90 mm × 3.90 mm
±
OPA388
VOUT
BODY SIZE (NOM)
SOIC (8)
For all available packages, see the package option
addendum at the end of the data sheet.
R3
25 k
R4
100 k
PACKAGE(1)
200 NŸ
G=5+
RG
The OPA388 in a High-CMRR, Instrumentation
Amplifier Application
Non-Linearity (ppm)
(1)
Output Voltage (V)
•
•
•
•
•
•
•
2.47
±100 ±80 ±60 ±40 ±20
-3
0
20
û5 5 SSP
40
60
80
100
C001
The OPA388 Allows Precision, Low-Error
Measurements
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA388, OPA2388, OPA4388
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information: OPA388.................................... 6
6.5 Thermal Information: OPA2388.................................. 7
6.6 Thermal Information: OPA4388.................................. 7
6.7 Electrical Characteristics: VS = ±1.25 V to ±2.75
V (VS = 2.5 to 5.5 V)..................................................... 7
6.8 Typical Characteristics.............................................. 10
7 Detailed Description......................................................18
7.1 Overview................................................................... 18
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................20
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Applications.................................................. 21
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Related Links.......................................................... 27
11.4 Receiving Notification of Documentation Updates.. 27
11.5 Support Resources................................................. 27
11.6 Trademarks............................................................. 28
11.7 Electrostatic Discharge Caution.............................. 28
11.8 Glossary.................................................................. 28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2019) to Revision D (July 2020)
Page
• Changed OPA2388 SOIC-8 (D) package from advanced information (preview) to production data (active) .... 1
• Changed typical application schematic to show correct locations for reference designators............................. 1
• Changed Figure 8-5 to show correct locations for reference designators ....................................................... 25
Changes from Revision B (January 2019) to Revision C (May 2019)
Page
• Changed OPA4388 from advanced information (preview) to production data (active)....................................... 1
• Added VOS specifications for OPA4388.............................................................................................................7
• Added dVOS/dT specifications for OPA4388......................................................................................................7
• Added PSRR specifications for OPA4388.......................................................................................................... 7
• Added IB specifications for OPA4388.................................................................................................................7
• Added IOS specifications for OPA4388.............................................................................................................. 7
• Added CMRR specifications for OPA4388..........................................................................................................7
• Added AOL specifications for OPA4388............................................................................................................. 7
Changes from Revision A (July 2018) to Revision B (January 2019)
Page
• Changed OPA388 DBV (SOT-23) package from preview to production data ....................................................1
• Deleted redundant temperature specification in EC table.................................................................................. 7
• Added Figure 6, Offset Voltage vs Supply Voltage: OPA4388 .........................................................................10
• Added Figure 7, Offset Voltage Long Term Drift ..............................................................................................10
• Changed Figure 50, OPA388 Layout Example; updated for accuracy............................................................. 26
2
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
Changes from Revision * (December 2016) to Revision A (July 2018)
Page
• Changed device status from Production Data to Production Data/Mixed Status................................................1
• Added top navigator link for TI reference design................................................................................................ 1
• Added preview notes to 5-pin SOT-23 (OPA388), 8-pin SOIC (OPA2388), 14-pin SOIC, and 14-pin TSSOP
(OPA4388) packages in Device Information table.............................................................................................. 1
• Added package preview notes to Pin Configuration and Functions section....................................................... 4
• AOL test condition changed to 0.15 V from 0.1 V...............................................................................................7
• AOL test condition changed to 0.15 V from 0.1 V...............................................................................................7
• AOL test condition changed to 0.25 V from 0.2 V...............................................................................................7
• AOL test condition changed to 0.3 V from 0.25 V...............................................................................................7
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
5 Pin Configuration and Functions
OUT
1
V±
2
5
±
+
+IN
3
4
NC
1
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
V+
±IN
Not to scale
Not to scale
Figure 5-1. OPA388 DBV Package, 5-Pin SOT-23,
Top View
Figure 5-2. OPA388 D and DGK Packages, 8-Pin
SOIC and VSSOP, Top View
Pin Functions: OPA388
PIN
OPA388
NAME
4
I/O
DESCRIPTION
D (SOIC),
DGK (VSSOP)
DBV (SOT-23)
–IN
2
4
I
Inverting input
+IN
3
3
I
Noninverting input
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
5
—
Positive (highest) power supply
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
OUT A
1
8
V+
±IN A
2
7
+IN A
3
V±
4
OUT A
1
14
OUT D
OUT B
±IN A
2
13
±IN D
6
±IN B
+IN A
3
12
+IN D
5
+IN B
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Figure 5-3. OPA2388 8-Pin SOIC (D) Package and
8-Pin VSSOP (DGK) Package, Top View
Not to scale
Figure 5-4. OPA4388 14-Pin SOIC (D) and
TSSOP-14 (PW) Packages, Top View
Pin Functions: OPA2388 and OPA4388
PIN
OPA2388
OPA4388
D (SOIC),
DGK (VSSOP)
D (SOIC),
PW (TSSOP)
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
—
9
I
Inverting input, channel C
–IN D
—
13
I
Inverting input, channel D
+IN A
3
3
I
Noninverting input, channel A
NAME
–IN A
I/O
DESCRIPTION
+IN B
5
5
I
Noninverting input, channel B
+IN C
—
10
I
Noninverting input, channel C
+IN D
—
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
—
8
O
Output, channel C
OUT D
—
14
O
Output, channel D
V–
4
11
—
Negative (lowest) power supply
V+
8
4
—
Positive (highest) power supply
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
Supply voltage
VS = (V+) – (V–)
Single-supply
(V–) – 0.5
(V+) + 0.5
Differential
±10
Operating, TA
Continuous
Continuous
–55
150
Junction, TJ
mA
150
Storage, Tstg
(2)
V
(V+) – (V–) + 0.2
Current
(1)
V
±3
Output short circuit(2)
Temperature
UNIT
6
Dual-supply
Common-mode
Voltage
Signal input pins
MAX
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Single-supply
Dual-supply
Specified temperature
NOM
MAX
2.5
5.5
±1.25
±2.75
–40
125
UNIT
V
°C
6.4 Thermal Information: OPA388
OPA388
THERMAL
D (SOIC)
DBV (SOT-23)
DGK (VSSOP)
8 PINS
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
116
145.7
177
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
60
94.8
69
°C/W
RθJB
Junction-to-board thermal resistance
56
43.4
100
°C/W
ΨJT
Junction-to-top characterization parameter
12.8
24.7
9.9
°C/W
ΨJB
Junction-to-board characterization parameter
55.9
43.1
98.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
n/a
°C/W
(1)
6
METRIC(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
6.5 Thermal Information: OPA2388
OPA2388
THERMAL
METRIC(1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
120.0
165
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.3
53
°C/W
RθJB
Junction-to-board thermal resistance
65.6
87
°C/W
ΨJT
Junction-to-top characterization parameter
9.6
4.9
°C/W
ΨJB
Junction-to-board characterization parameter
64.4
85
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4388
OPA4388
THERMAL METRIC(1)
D (SOIC)
PW (TSSOP)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
86.4
109.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.3
27.4
°C/W
RθJB
Junction-to-board thermal resistance
41.0
56.1
°C/W
ΨJT
Junction-to-top characterization parameter
11.3
1.5
°C/W
ΨJB
Junction-to-board characterization parameter
40.7
54.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics: VS = ±1.25 V to ±2.75 V (VS = 2.5 to 5.5 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT Input offset voltage drift
PSRR
Power-supply rejection
ratio
OPA388, OPA2388
±0.25
±5
VS = 5.5 V
OPA4388
±2.25
±8
TA = –40°C to +125°C
OPA388, OPA2388
TA = –40°C to +125°C, VS = 5.5 V
OPA4388
TA = –40°C to +125°C
OPA388, OPA2388
±0.005
±0.05
TA = –40°C to +125°C, VS = 5.5 V
OPA4388
±0.005
±0.05
TA = –40°C to +125°C
OPA388, OPA2388
OPA4388
±7.5
µV
±10.5
±0.1
±1
±1.25
±3.5
µV/°C
µV/V
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
6.7 Electrical Characteristics: VS = ±1.25 V to ±2.75 V (VS = 2.5 to 5.5 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±30
±350
UNIT
INPUT BIAS CURRENT
RIN = 100 kΩ, OPA388, OPA2388
IB
Input bias current
TA = 0°C to +85°C
±400
TA = –40°C to
+125°C
±700
±30
RIN = 100 kΩ, OPA4388
±500
TA = 0°C to +85°C
±600
TA = –40°C to
+125°C
±800
±700
RIN = 100 kΩ, OPA388, OPA2388
IOS
Input offset current
TA = 0°C to +85°C
±800
TA = –40°C to
+125°C
±800
pA
±1000
RIN = 100 kΩ, OPA4388
TA = 0°C to +85°C
±1100
TA = –40°C to
+125°C
±1100
NOISE
EN
Input voltage noise
eN
Input voltage noise
density
IN
Input current noise
density
f = 0.1 Hz to 10 Hz
0.14
f = 10 Hz
7
f = 100 Hz
7
f = 1 kHz
7
f = 10 kHz
7
f = 1 kHz
µVPP
nV/√Hz
100
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) + 0.1 V
CMRR
Common-mode
rejection ratio
(V–) < VCM < (V+) + 0.1 V,
TA = –40°C to +125°C
(V+) + 0.1
VS = ±1.25
V
OPA388,
OPA2388
124
138
VS = ±1.25
V
OPA4388
102
110
VS = ±2.75 V
124
140
VS = ±1.25
V
OPA388,
OPA2388
114
134
VS = ±1.25
V
OPA4388
102
107
124
140
(V–) – 0.05 V < VCM < (V+) + 0.1 V,
VS = ±2.75 V
TA = –40°C to +125°C
V
dB
INPUT IMPEDANCE
8
zid
Differential input
impedance
100 || 2
MΩ || pF
zic
Common-mode input
impedance
60 || 4.5
TΩ || pF
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
6.7 Electrical Characteristics: VS = ±1.25 V to ±2.75 V (VS = 2.5 to 5.5 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(V–) + 0.15 V < VO < (V+) – 0.15 V, RLOAD = 10 kΩ
126
148
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ,
OPA388, OPA2388
TA = –40°C to +125°C
120
126
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ, VS = 5.5 V
OPA4388
TA = –40°C to +125°C
120
126
(V–) + 0.25 V < VO < (V+) – 0.25 V, RLOAD = 2 kΩ
126
148
(V–) + 0.30 V < VO < (V+) – 0.30 V,
OPA388, OPA2388
RLOAD = 2 kΩ
120
148
(V–) + 0.30 V < VO < (V+) – 0.30 V,
RLOAD = 2 kΩ, VS = 5.5 V
OPA4388
TA = –40°C to +125°C
120
126
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
dB
FREQUENCY RESPONSE
GBW
Unity-gain bandwidth
SR
Slew rate
G = 1, 4-V step
THD+N
Total harmonic
distortion + noise
G = 1, f = 1 kHz, VO = 1 VRMS
tS
tOR
MHz
5
V/µs
0.0005%
To 0.1%
VS = ±2.5 V, G = 1,
1-V step
0.75
µs
To 0.01%
VS = ±2.5 V, G = 1,
1-V step
2
µs
10
µs
Settling time
Overload recovery time
10
VIN × G = VS
OUTPUT
Positive rail
VO
Voltage output swing
from rail
No load
1
15
RLOAD = 10 kΩ
5
20
RLOAD = 2 kΩ
20
50
5
15
RLOAD = 10 kΩ
10
20
RLOAD = 2 kΩ
40
60
10
25
No load
Negative rail
TA = –40°C to +125°C, both rails, RLOAD = 10 kΩ
mV
VS = 5.5 V
±60
mA
VS = 2.5 V
±30
mA
100
Ω
ISC
Short-circuit current
CLOAD
Capacitive load drive
See Figure 6-26
ZO
Open-loop output
impedance
f = 1 MHz, IO = 0 A, see Figure 6-25
POWER SUPPLY
VS = ±1.25 V (VS = 2.5 V)
IQ
Quiescent current per
amplifier
VS = ±2.75 V (VS = 5.5 V)
IO = 0 A
1.7
2.4
TA = –40°C to
+125°C, IO = 0 A
1.7
2.4
IO = 0 A
1.9
2.6
TA = –40°C to
+125°C, IO = 0 A
1.9
2.6
mA
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
6.8 Typical Characteristics
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 6-1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 6-1
Offset Voltage Drift Distribution From –40°C to +125°C
Figure 6-2
Offset Voltage vs Temperature
Figure 6-3
Offset Voltage vs Common-Mode Voltage
Figure 6-4
Offset Voltage vs Power Supply: OPA388 and OPA2388
Figure 6-5
Offset Voltage vs Power Supply: OPA4388
Figure 6-6
Offset Voltage Long Term Drift
Figure 6-7
Open-Loop Gain and Phase vs Frequency
Figure 6-8
Closed-Loop Gain and Phase vs Frequency
Figure 6-9
Input Bias Current vs Common-Mode Voltage
Figure 6-10
Input Bias Current vs Temperature
Figure 6-11
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 6-12
CMRR and PSRR vs Frequency
Figure 6-13
CMRR vs Temperature
Figure 6-14
PSRR vs Temperature
Figure 6-15
0.1-Hz to 10-Hz Noise
Figure 6-16
Input Voltage Noise Spectral Density vs Frequency
Figure 6-17
THD+N Ratio vs Frequency
Figure 6-18
THD+N vs Output Amplitude
Figure 6-19
Spectral Content
Figure 6-20, Figure 6-21
Quiescent Current vs Supply Voltage
Figure 6-22
Quiescent Current vs Temperature
Figure 6-23
Open-Loop Gain vs Temperature
Figure 6-24
Open-Loop Output Impedance vs Frequency
Figure 6-25
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
Figure 6-26
No Phase Reversal
Figure 6-27
Positive Overload Recovery
Figure 6-28
Negative Overload Recovery
Figure 6-29
Small-Signal Step Response (10-mV Step)
Figure 6-30, Figure 6-31
Large-Signal Step Response (4-V Step)
Figure 6-32 , Figure 6-33
Settling Time
Figure 6-34, Figure 6-35
Short-Circuit Current vs Temperature
Figure 6-36
Maximum Output Voltage vs Frequency
Figure 6-37
EMIRR vs Frequency
Figure 6-38
10
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
15
50
45
10
Amplifiers (%)
Amplifiers (%)
40
5
35
30
25
20
15
10
5
5
5
4
4
3
3
Input Offset Voltage ( V)
Input Offset Voltage ( V)
0.05
0.04
0.02
0.01
0
0.03
C001
Figure 6-2. Offset Voltage Drift Distribution From –40°C to
+125°C
2
1
0
±1
±2
±3
±4
2
1
0
±1
±2
±3
VCM = ±2.85 V
VCM = 2.85 V
±4
±5
±5
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
150
±3
8
6
Input Offset Voltage (PV)
3
2
1
0
±1
±2
VS = ± 2.75 V
-2
-4
-8
1.2
1.6
1.8
2.0
2.2
Supply Voltage (V)
2.4
2.6
3
C003
0
-6
1.4
2
2
±5
1.2
1
4
±4
1.0
0
Figure 6-4. Offset Voltage vs Common-Mode Voltage
4
VS = ± 1.25 V
±1
Input Common-mode Voltage (V)
5
±3
±2
C001
Figure 6-3. Offset Voltage vs Temperature
Input Offset Voltage ( V)
-0.01
Input Offset Voltage Drift (µV/ƒC)
C002
Figure 6-1. Offset Voltage Production Distribution
-0.02
-0.03
Input Offset Voltage (µV)
-0.04
-0.05
5
4
3
2
1
0
-1
-2
-3
-4
0
-5
0
2.8
3.0
VS = r 1.25 V
1.4
1.6
C001
Figure 6-5. Offset Voltage vs Supply Voltage: OPA388 and
OPA2388
VS = r 2.75 V
1.8
2
2.2
Supply Voltage (V)
2.4
2.6
2.8
C308
Figure 6-6. Offset Voltage vs Supply Voltage: OPA4388
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6.8 Typical Characteristics (continued)
20
160
15
140
180
Open-Loop Gain
120
Open-Loop Gain (dB)
10
5
0
-5
-10
Open-Loop Phase
100
90
80
60
45
40
20
0
0
-15
135
Open-Loop Phase (°)
Input Offset Voltage Delta (nV)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
±20
-45
±40
-20
0
20
40
60
80
Days
100
120
140
1
160
10
100
1k
10k 100k
Frequency (Hz)
C309
1M
10M
C021
3 typical units
Figure 6-8. Open-Loop Gain and Phase vs Frequency
Figure 6-7. Offset Voltage Long Term Drift
1500
G = +1
G= +10
G= +100
40
Input Bias Current (pA)
Closed-Loop Gain (dB)
60
20
0
-20
1000
500
0
±500
100
1k
10k
100k
1M
10M
±3
Frequency (Hz)
±2
Figure 6-9. Closed-Loop Gain and Phase vs Frequency
0
±1
1
2
3
Input Common-mode Voltage (V)
C004
C001
Figure 6-10. Input Bias Current vs Common-Mode Voltage
3
1.5
2.5
2
Output Voltage (V)
Input Bias Current (nA)
1.3
1.0
0.8
0.5
0.3
25°C
1
0.5
0
-0.5
125°C
-1
±40°C
-1.5
-2
ios
-2.5
-3
0.0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Figure 6-11. Input Bias Current vs Temperature
12
1.5
150
0
10
20
30
40
50
60
Output Current (mA)
C001
70
80
90
100
C001
Figure 6-12. Output Voltage Swing vs Output Current (Maximum
Supply)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Common-Mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
140
120
100
80
60
CMRR
40
+PSRR
20
±PSRR
180
0.001
160
0.01
140
0.1
120
1
100
0
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
10
±75
±50 ±25
50
75
100 125 150
C001
0.001
160
0.01
140
0.1
120
1
Input Voltage Noise (50 nV/div)
180
Power-Supply Rejection Ratio (µV/V)
Power-Supply Rejection Ratio (dB)
25
Figure 6-14. CMRR vs Temperature
Figure 6-13. CMRR and PSRR vs Frequency
10
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Time (1 s/div)
150
C001
C017
Figure 6-15. PSRR vs Temperature
Figure 6-16. 0.1-Hz to 10-Hz Noise
Total Harmonic Distortion + Noise (%)
1000
100
10
1
1
10
100
1k
Frequency (Hz)
10k
100k
0.01
0.001
-100
0.0001
20
200
2k
Frequency (Hz)
C002
Figure 6-17. Input Voltage Noise Spectral Density vs Frequency
-80
G = -1, 10k- Load
G = -1, 2k- Load
G = -1, 600- Load
G = +1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
-120
20k
Total Harmonic Distortion + Noise (dB)
Voltage Noise Spectral Density (nV/¥Hz)
0
Temperature (ƒC)
C004
100
Common-Mode Rejection Ratio (µV/V)
160
C004
Figure 6-18. THD+N Ratio vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0.001
0.0001
0.001
G = -1, 600- Load
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 600- Load
G = +1, 2k- Load
G = +1, 10k- Load
0.01
-100
-120
0.1
±20
FFT Spectral Content (dBc)
-80
0.01
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
0
-60
0.1
±40
±60
±80
±100
±120
±140
±160
±180
100
1
Output Amplitude (VRMS)
1k
10k
100k
Frequency (Hz)
C004
C004
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 10 kΩ, BW = 90 kHz
Figure 6-20. Spectral Content (With 10-kΩ Load)
Figure 6-19. THD+N vs Output Amplitude
0
2.5
±40
Quiescent Current (mA)
FFT Spectral Content (dBc)
±20
±60
±80
±100
±120
±140
2
1.5
1
0.5
±160
0
±180
100
1k
10k
100k
Frequency (Hz)
0
0.5
1
1.5
2
2.5
3
Supply Voltage (V)
C004
C001
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 2 kΩ, BW = 90 kHz
Figure 6-21. Spectral Content (With 2-kΩ Load)
Figure 6-22. Quiescent Current vs Supply Voltage
0.001
180
2.5
DC Open-loop Gain (dB)
2
1.5
1
0.5
0.1
140
VS = ± 1.1 V
120
1
100
0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Figure 6-23. Quiescent Current vs Temperature
14
0.01
160
150
DC Open-loop Gain (µV/V)
Quiescent Current (mA)
VS = ± 2.75 V
10
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
C001
Figure 6-24. Open-Loop Gain vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
90
100
G = -1
80
70
Overshoot (%)
Open-loop Output Impedance (Ÿ)
1k
10
1
60
50
40
30
100m
G = +1
20
10m
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
100M
10
100
Figure 6-25. Open-Loop Output Impedance vs Frequency
1000
Capacitive Load (pF)
C003
C004
Figure 6-26. Small-Signal Overshoot vs Capacitive Load (10-mV
Step)
Voltage (1 V/div)
Voltage (1.25 V/div)
VIN
VOUT
VOUT
VIN
Time (45 ms/div)
Time (200 ns/div)
C017
C017
Figure 6-27. No Phase Reversal
Figure 6-28. Positive Overload Recovery
VOUT
Voltage (2.5 mV/div)
Voltage (1 V/div)
VIN
VIN
VOUT
Time (200 ns/div)
Time (2.5 µs/div)
C017
C017
G = +1
Figure 6-29. Negative Overload Recovery
Figure 6-30. Small-Signal Step Response (10-mV Step)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VOUT
VIN
VIN
Voltage (1 V/div)
Voltage (2.5 mV/div)
VOUT
Time (2.5 µs/div)
Time (500 ns/div)
C017
C017
G = –1
Falling output
Figure 6-31. Small-Signal Step Response (10-mV Step)
Figure 6-32. Large-Signal Step Response (4-V Step)
VOUT
0.01% Settling = “100µV
Voltage (1 V/div)
Output Voltage (100 µV/div)
VIN
Time (500 ns/div)
Time (500 ns/div)
C017
C017
Rising output
0.01% settling = ±100 µV
Figure 6-33. Large-Signal Step Response (4-V Step)
Figure 6-34. Settling Time (1-V Positive Step)
100
0.01% Settling = “200µV
ISC, Sink
Short-Circuit Current (mA)
Output Voltage (100 µV/div)
90
80
70
60
50
ISC, Source
40
30
20
10
0
Time (500 ns/div)
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C017
150
C001
0.01% settling = ±200 µV
Figure 6-35. Settling Time (1-V Negative Step)
16
Figure 6-36. Short-Circuit Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
7
140
VS = ±2.5V
120
EMIRR IN+ (dB)
Output Voltage (VPP)
6
5
160
Maximum output voltage without
slew-rate induced distortion.
4
3
2
VS = ±0.9V
100
80
60
40
1
20
0
100
1k
10k
100k
1M
10M
Frequency (Hz)
0
10M
100M
1000M
Frequency (Hz)
C001
C004
PRF = –10 dBm
Figure 6-37. Maximum Output Voltage vs Frequency
Figure 6-38. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx388 family of zero-drift amplifiers is engineered with the unique combination of a proprietary precision
auto-calibration technique paired with a low-noise, low-ripple, input charge pump. These amplifiers offer ultra-low
input offset voltage and drift and achieve excellent input and output dynamic linearity. The OPAx388 operate
from 2.5 V to 5.5 V, is unity-gain stable, and are designed for a wide range of general-purpose and precision
applications. The integrated, low-noise charge pump allows true rail-to-rail input common-mode operation
without distortion associated with complementary rail-to-rail input topologies (input crossover distortion). The
OPAx388 strengths also include 10-MHz bandwidth, 7-nV/√ Hz noise spectral density, and no 1/f noise, making
the OPAx388 optimal for interfacing with sensor modules and buffering high-fidelity, digital-to-analog converters
(DACs).
7.2 Functional Block Diagram
Low-noise
Charge-pump
GM_FF
CLK
CLK
CCOMP
+IN
OUT
±IN
GM1
GM2
GM3
CCOMP
Ripple Reduction
Technology
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7.3 Feature Description
7.3.1 Operating Voltage
The OPAx388 family of operational amplifiers can be used with single or dual supplies from an operating range
of VS = 2.5 V (±1.25 V) up to 5.5 V (±2.75 V). Supply voltages greater than 7 V can permanently damage
the device (see the Absolute Maximum Ratings table). Key parameters that vary over the supply voltage or
temperature range are shown in the Typical Characteristics section.
7.3.2 Input Voltage and Zero-Crossover Functionality
The OPAx388 input common-mode voltage range extends 0.1 V beyond the supply rails. This amplifier family
is designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers. Operating a complementary rail-to-rail input amplifier with signals traversing the transition region
results in unwanted non-linear behavior and polluted spectral content. Figure 7-1 and Figure 7-2 contrast the
performance of a traditional complementary rail-to-rail input stage amplifier with the performance of the zerocrossover OPA388. Significant harmonic content and distortion is generated during the differential pair transition
(such a transition does not exist in the OPA388). Crossover distortion is eliminated through the use of a single
differential pair coupled with an internal low-noise charge pump. The OPAx388 maintains noise, bandwidth, and
offset performance throughout the input common-mode range, thus reducing printed circuit board (PCB) and bill
of materials (BOM) complexity through the reduction of power-supply rails.
20
0
Complementary Input Stage
OPA388 Zero-Crossover Input Stage
FFT Spectral Content (dBV)
Input Offset Voltage ( V)
15
10
5
0
±5
±10
VCM = ±2.85 V
VCM = 2.85 V
±15
±20
±40
±60
Traditional Rail-to-Rail
Input Stage
±80
±100
±120
OPA388 Zero-Crossover Input Stage
±20
±140
±3
±2
±1
0
1
Input Common-mode Voltage (V)
2
3
10
Figure 7-1. Input Crossover Distortion Nonlinearity
100
1k
Frequency (Hz)
C003
10k
C004
Figure 7-2. Input Crossover Distortion Spectral
Content
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Typically, input bias current is approximately ±30 pA. Input voltages exceeding the power supplies, however,
can cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power
supply can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in Figure 7-3.
Current-limiting resistor
required if input voltage
exceeds supply rails by
> 0.3V.
+5V
IOVERLOAD
10 mA max
VOUT
VIN
5 NŸ
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Figure 7-3. Input Current Protection
7.3.3 Input Differential Voltage
The typical input bias current of the OPAx388 during normal operation is approximately 30 pA. In overdriven
conditions, the bias current can increase significantly. The most common cause of an overdriven condition
occurs when the operational amplifier is outside of the linear range of operation. When the output of the
operational amplifier is driven to one of the supply rails, the feedback loop requirements cannot be satisfied and
a differential input voltage develops across the input pins. This differential input voltage results in activation
of parasitic diodes inside the front-end input chopping switches that combine with 10-kΩ electromagnetic
interference (EMI) filter resistors to create the equivalent circuit shown in Figure 7-4. Notice that the input bias
current remains within specification in the linear region.
100 W
Clamp
+In
CORE
-In
100 W
Copyright © 2016, Texas Instruments Incorporated
Figure 7-4. Equivalent Input Circuit
7.3.4 Internal Offset Correction
The OPA388 family of operational amplifiers uses an auto-calibration technique with a time-continuous, 200-kHz
operational amplifier in the signal path. This amplifier is zero-corrected every 5 µs using a proprietary technique.
At power-up, the amplifier requires approximately 1 ms to achieve the specified VOS accuracy. This design has
no aliasing or flicker noise.
7.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc
offset at the amplifier output can shift from its nominal value when EMI is present. This shift is a result of
signal rectification associated with the internal semiconductor junctions. Although all operational amplifier pin
functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPAx388 operational
amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both
common-mode and differential-mode filtering are provided by the input filter. The filter is designed for a cutoff
frequency of approximately 20 MHz (–3 dB), with a rolloff of 20 dB per decade.
7.4 Device Functional Modes
The OPA388 has a single functional mode and is operational when the power-supply voltage is greater than
2.5 V (±1.25 V). The maximum specified power-supply voltage for the OPAx388 is 5.5 V (±2.75 V).
20
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx388 is a unity-gain stable, precision operational amplifier family free from unexpected output and
phase reversal. The use of proprietary zero-drift circuitry gives the benefit of low input offset voltage over time
and temperature, as well as lowering the 1/f noise component. As a result of the high PSRR, these devices
work well in applications that run directly from battery power without regulation. The OPAx388 family is optimized
for full rail-to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature,
high-precision, low-noise amplifiers offer high-impedance inputs that have a common-mode range 100 mV
beyond the supplies without input crossover distortion and a rail-to-rail output that swings within 5 mV of the
supplies under normal test conditions. The OPAx388 series of precision amplifiers is designed for upstream
analog signal chain applications in low or high gains, as well as downstream signal chain functions such as DAC
buffering.
8.2 Typical Applications
8.2.1 Bidirectional Current-Sensing
This single-supply, low-side, bidirectional current-sensing solution detects load currents from –1 A to +1 A. The
single-ended output spans from 110 mV to 3.19 V. This design uses the OPAx388 because of its low offset
voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and the other
amplifier provides the reference voltage.
Figure 8-1 shows the solution.
VCC
VREF
VCC
R5
+
U1B
ILOAD
R6
R2
VBUS
+
±
R1
+
+
VSHUNT
±
RSHUNT
VOUT
R3
U1A
RL
VCC
R4
Figure 8-1. Bidirectional Current-Sensing Schematic
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8.2.1.1 Design Requirements
This solution has the following requirements:
•
•
•
Supply voltage: 3.3 V
Input: –1 A to 1 A
Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.1.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor (RSHUNT) to develop the shunt voltage, VSHUNT. The
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
(1)
where
• VSHUNT = ILOAD ´ RSHUNT
R
GainDiff_Amp = 4
R3
•
•
VREF = VCC ´
R6
R5 + R6
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of
the difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set
to 100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
RSHUNT(Max) =
VSHUNT(Max) 100 mV
= 100 mW
=
ILOAD(Max)
1A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
was selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to 100 mV. This voltage is
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present
at the noninverting node of U1A is within the common-mode range of the device. Therefore, use an operational
amplifier, such as the OPA388, that has a common-mode range that extends below the negative supply voltage.
Finally, to minimize offset error, note that the OPA388 has a typical offset voltage of merely ±0.25 µV (±5 µV
maximum).
Given a symmetric load current of –1 A to 1 A, the voltage divider resistors (R5 and R6) must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% was selected. To minimize power consumption,
10-kΩ resistors were used.
22
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To set the gain of the difference amplifier, the common-mode range and output swing of the OPA388 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPA388 given a 3.3-V supply.
–100 mV < VCM < 3.4 V
(3)
100 mV < VOUT < 3.2 V
(4)
The gain of the difference amplifier can now be calculated as shown in Equation 5.
GainDiff_Amp =
VOUT_Max - VOUT_Min
3.2 V - 100 mV
V
= 15.5
=
V
100 mW ´ [1 A - (- 1A)]
RSHUNT ´ (IMAX - IMIN)
(5)
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because this number is
the nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.1.3 Application Curve
Output Voltage (V)
3.30
1.65
0
-1.0
-0.5
0
Input Current (A)
0.5
1.0
Figure 8-2. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current
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8.2.2 Single Operational Amplifier Bridge Amplifier
Figure 8-3 shows the basic configuration for a bridge amplifier.
VEX
R1
R
R
R
R
+5V
VOUT
VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 8-3. Single Operational Amplifier Bridge Amplifier Schematic
8.2.3 Precision, Low-Noise, DAC Buffer
The OPA388 can be used for a precision DAC buffer, as shown in Figure 8-4, in conjunction with the DAC8830.
The OPA388 provides an ultra-low drift, precision output buffer for the DAC. A wide range of DAC codes can
be used in the linear region because the OPA388 employs zero-crossover technology. A precise reference is
essential for maximum accuracy because the DAC8830 is a 16-bit converter.
VDD VREF
RFB
±
INV
Serial Interface
DAC8830
DGND
OPA388
VOUT
+
AGND
Copyright © 2016, Texas Instruments Incorporated
Figure 8-4. Precision DAC Buffer
24
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8.2.4 Load Cell Measurement
Figure 8-5 shows the OPA388 in a high-CMRR dual-op amp instrumentation amplifier with a trim resistor and
6-wire load cell for precision measurement. Figure 8-6 illustrates the output voltage as a function of load cell
resistance change, along with the nonlinearity of the system.
R3
25 k
R4
100 k
5V
REF5025
RG
R4
100 k
R2
25 k
5V
5V
5V
+SENSE
±
±
OPA388
OPA388
VOUT
+
R2
10 k
+
GND
GND
±SENSE
Load Cell
GND
G=5+
GND
200 NŸ
RG
2.53
3
2.52
2
2.51
1
2.5
0
2.49
-1
2.48
-2
RG = 1 kŸ
2.47
±100 ±80 ±60 ±40 ±20
Non-Linearity (ppm)
Output Voltage (V)
Figure 8-5. Load Cell Measurement Schematic
-3
0
20
40
60
80
100
û5 5 SSP
C001
Figure 8-6. Load Cell Measurement Output
9 Power Supply Recommendations
The OPAx388 family of devices is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Parameters
that can exhibit significant variance with regard to operating voltage are presented in the Typical Characteristics
section.
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10 Layout
10.1 Layout Guidelines
Paying attention to good layout practice is always recommended. Keep traces short and, when possible, use
a printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device
pins as possible. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied
throughout the analog circuit to improve performance and provide benefits such as reducing the electromagnetic
interference (EMI) susceptibility.
For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring
they are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 10-1. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
RF
VS+
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
Figure 10-2. OPA388 Layout Example
26
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
11.1.1.2 TI Precision Designs
The OPAx388 family is featured on TI Precision Designs, available online at www.ti.com/ww/en/analog/precisiondesigns/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and
offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of
materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Circuit board layout techniques
• Texas Instruments, DAC883x 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters data
sheet
11.3 Related Links
Table 11-1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA388
Click here
Click here
Click here
Click here
Click here
OPA2388
Click here
Click here
Click here
Click here
Click here
OPA4388
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
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SBOS777D – NOVEMBER 2016 – REVISED JULY 2020
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2388ID
ACTIVE
SOIC
D
8
75
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
OP2388
OPA2388IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1D36
OPA2388IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1D36
OPA2388IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
OP2388
OPA388ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA388
OPA388IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14KV
OPA388IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14KV
OPA388IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14LV
OPA388IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14LV
OPA388IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA388
OPA4388ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4388
OPA4388IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4388
OPA4388IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4388
OPA4388IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4388
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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