OPA404KPG4

OPA404 Quad High-Speed Precision Difet ® OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● WIDE BANDWIDTH: 6.4MHz ● HIGH SLEW RATE: 35V/µs ● LOW OFFSET: ±750µV max ● PRECISION INSTRUMENTATION ● ● ● ● ● ● LOW BIAS CURRENT: ±4pA max ● LOW SETTLING: 1.5µs to 0.01% ● STANDARD QUAD PINOUT OPTOELECTRONICS SONAR, ULTRASOUND PROFESSIONAL AUDIO EQUIPMENT MEDICAL EQUIPMENT DETECTOR ARRAYS DESCRIPTION The OPA404 is a high performance monolithic Difet ®(dielectrically-isolated FET) quad operational amplifier. It offers an unusual combination of verylow bias current together with wide bandwidth and fast slew rate. Noise, bias current, voltage offset, drift, and speed are superior to BIFET® amplifiers. +VCC –In +In Cascode Laser-trimming of thin-film resistors gives very low offset and drift—the best available in a quad FET op amp. Output The OPA404's input cascode design allows high precision input specifications and uncompromised highspeed performance. Standard quad op amp pin configuration allows upgrading of existing designs to higher performance levels. The OPA404 is unity-gain stable. –VCC OPA404 Simplified Circuit (Each Amplifier) Difet ®, Burr-Brown Corp. BIFET®, National Semiconductor Corp. SBOS149 International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1986 Burr-Brown Corporation PDS-677F Printed in U.S.A. August 1995 SPECIFICATIONS ELECTRICAL At VCC = ±15VDC and TA = +25°C unless otherwise noted. OPA404AG, KP, KU (1) PARAMETER CONDITIONS MIN INPUT NOISE Voltage: fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10Hz Current: fB = 0.1Hz to 10Hz fO = 0.1Hz thru 20kHz OFFSET VOLTAGE Input Offset Voltage KP, KU Average Drift KP, KU Supply Rejection KP, KU Channel Separation TYP MAX OPA404BG MIN 32 19 15 12 1.4 0.95 12 0.6 VCM = 0VDC TA = TMIN to TMAX ±VCC = 12V to 18V 80 76 100Hz, RL = 2kΩ TYP OPA404SG MAX MIN * * * * * * * * ±260 ±750 ±3 ±5 100 100 125 ±1mV ±2.5mV * MAX * * * * * * * * ±750 * * 86 TYP nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fA, p-p fA/√Hz * µV µV µV/°C µV/°C dB dB dB * * * * UNITS * * BIAS CURRENT Input Bias Current KP, KU VCM = 0VDC ±1 ±1 ±8 ±12 * ±4 * * pA pA OFFSET CURRENT Input Offset Current KP, KU VCM = 0VDC 0.5 0.5 8 12 * 4 * * pA pA IMPEDANCE Differential Common-Mode 1013 || 1 1014 || 3 VOTAGE RANGE Common-Mode Input Range Common-Mode Rejection KP, KU RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current Ω || pF Ω || pF ±10.5 88 84 +13, –11 100 100 * 92 * * * * * * V dB dB RL ≥ 2kΩ 88 100 92 * * * dB Gain = 100 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ Gain = –1, RL = 2kΩ CL = 100 pF, 10V Step 4 6.4 570 35 0.6 1.5 5 * * * * * * * * * * * MHz kHz V/µs µs µs * * * * * * * * * * * * V mA Ω pF mA RL = 2kΩ VO = ±10VDC 1MHz, Open Loop Gain = +1 POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent TEMPERATURE RANGE Specification KP, KU Operating KP, KU Storage KP, KU θ Junction-Ambient KP, KU * * VIN = ±10VDC OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Gain Bandwidth Full Power Response Slew Rate Settling Time: 0.1% 0.01% * * 24 ±11.5 +13.2, –13.8 ±5 ±10 80 1000 ±10 ±27 28 * * ±40 * ±15 ±5 IO = 0mADC Ambient Temperature Ambient Temperature Ambient Temperature 9 –25 0 –55 –25 –65 –40 * * * * ±18 10 * +85 +70 +125 +85 +150 +125 100 120/100 * * * * * * * * * * * VDC * * VDC mA –55 +125 * * * * * * °C °C °C °C °C °C °C/W °C/W * * *Specifications same as OPA404AG. NOTE: (1) OPA404KU may be marked OPA404U. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA404 2 ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted. OPA404AG, KP, KU PARAMETER TEMPERATURE RANGE Specification Range KP, KU CONDITIONS MIN Ambient Temperature –25 0 INPUT OFFSET VOLTAGE Input Offset Voltage KP KU Average Drift KP, KU Supply Rejection TYP VCM = 0VDC 75 OPA404BG MAX MIN +85 +70 * ±450 ±1 ±3 ±5 96 2mV ±3.5 TYP OPA404SG MAX MIN * –55 TYP ±1.5mV * ±550 * 80 MAX UNITS +125 °C °C ±2.5mV µV mV µV/°C µV/°C dB * * 70 93 BIAS CURRENT Input Bias Current VCM = 0VDC ±32 ±200 * ±100 ±500 ±5nA pA OFFSET CURRENT Input Offset Current VCM = 0VDC 17 100 * 50 260 2.5nA pA VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection KP, KU OPEN-LOOP GAIN, DC Open-Loop Voltage Gain RATED OUTPUT Voltage Output Current Output Short Circuit Current POWER SUPPLY Current, Quiescent VIN = ±10VDC ±10 82 80 ±12.7, –10.6 99 99 * 86 * * ±10 +12.6, –10.5 80 88 V dB dB RL ≥ 2kΩ 82 94 86 * 80 dB RL = 2kΩ VO = ±10VDC VO = 0VDC ±11.5 ±12.9, –13.8 ±5 ±9 ±8 ±20 ±50 * * * * * * * ±11 +12.7, –13.8 * ±8 * * IO = 0mADC 9.3 * * 10.5 88 9.4 * V mA mA 11 mA * Specification same as OPA404AG. ORDERING INFORMATION MODEL OPA404KP OPA404KU(1) OPA404AG OPA404BG OPA404SG PACKAGE INFORMATION PACKAGE TEMPERATURE RANGE MODEL 14-Pin Plastic DIP 16-Pin Plastic SOIC 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Ceramic DIP 0°C to +70°C 0°C to +70°C –25°C to +85°C –25°C to +85°C –55°C to +125°C OPA404KP OPA404KU(2) OPA404AG OPA404BG OPA404SG NOTE: (1) OPA404KU may be marked OPA404U. PACKAGE PACKAGE DRAWING NUMBER(1) 14-Pin Plastic DIP 16-Pin Plastic SOIC 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Ceramic DIP 010 211 169 169 169 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. (2) OPA404KU may be marked OPA404U. ABSOLUTE MAXIMUM RATINGS Supply ............................................................................................. ±18VDC Internal Power Dissipation(1) ......................................................... 1000mW Differential Input Voltage(2) ............................................................. ±36VDC Input Voltage Range(2) ................................................................... ±18VDC Storage Temperature Range ... P, U = –40°C/+125°C, G = –65°C/+150°C Operating Temperature Range .. P, U = –25°C/+85°C, G = –55°C/+125°C Lead Temperature (soldering, 10s) .................................................... 300°C SOIC (soldering, 3s) ..................................................................... +260°C Output Short-Circuit Duration(3) ................................................. Continuous Junction Temperature ....................................................................... +175°C NOTES: (1) Packages must be derated based on θJC = 30°C/W or θJA = 120°C/W. (2) For supply voltages less than ±18VDC the absolute maximum input voltage is equal to: 18V > VIN > –VCC – 8V. See Figure 2. (3) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. PIN CONFIGURATION Top View Out A –In A Top View “U” (SOIC) Package “G” or “P” (DIP) Package 14 Out D 1 A D + In A 3 12 +In D + VCC 4 11 –VCC 1 –In A 2 16 Out D 15 –In D A 13 –In D 2 Out A + In A 3 14 +In D + VCC 4 13 –VCC +In B 5 12 +In C B +In B 5 B D C 10 +In C – In B 6 11 –In C C – In B 6 9 –In C Out B 7 10 Out C Out B 7 8 Out C NC 8 9 NC ® 3 OPA404 DICE INFORMATION 2 3 1 14 NC 13 4 12 NC NC PAD FUNCTION PAD FUNCTION 1 2 3 4 5 6 7 Output A –Input A +Input A +VCC +Input B –Input B Output B 8 9 10 11 12 13 14 Output C –Input C +Input C –VCC +Input D –Input D Output D Substrate Bias: –VCC NC: No connection MECHANICAL INFORMATION NC NC 5 11 6 7 8 NC 9 Die Size Die Thickness Min. Pad Size MILS (0.001") MILLIMETERS 108 x 108 ±5 20 ±3 4x4 2.74 x 2.74 ±0.13 0.51 ±0.08 0.10 x 0.10 Backing None 10 OPA404 DIE TOPOGRAPHY TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15VDC unless otherwise noted. POWER SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE INPUT CURRENT NOISE SPECTRAL DENSITY 110 CMR and PSR (dB) Current Noise (fA/ Hz) 100 10 1 PSR 105 100 CMR 95 90 0.1 1 10 100 1k 10k Frequency (Hz) 100k 1M –75 –50 –25 0 +25 +50 Temperature (°C) +75 +100 +125 BIAS AND OFFSET CURRENT vs TEMPERATURE TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE 1k 10nA 10nA 1nA 1nA 100 100 100 OPA404 + Resistor 10 Bias Current 10 10 Offset Current 1 1 Resistor noise only 1 0.1 100 1k 10k 100k 1M Source Resistance (Ω) 10M 100M –25 0 +25 +50 +75 Ambient Temperature (°C) ® OPA404 0.1 –50 4 +100 +125 Offset Current (pA) RS Bias Current (pA) Voltage Noise, EO (nV/ Hz) EO TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE POWER SUPPLY REJECTION vs FREQUENCY 10 1 Offset Current 0.1 0.1 Power Supply Rejection (dB) Bias Current 1 140 Offset Current (pA) 0.01 0.01 –15 –10 –5 0 +5 +10 80 + – 60 40 20 0 1 10 100 1k 10k 100k 1M Common-Mode Voltage (V) Frequency (Hz) COMMON-MODE REJECTION vs FREQUENCY COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 10M 120 120 Common-Mode Rejection (dB) Common-Mode Rejection (dB) 100 +15 140 100 80 60 40 20 110 100 90 80 70 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) –15 0 +5 –5 Common-Mode Voltage (V) OPEN-LOOP FREQUENCY RESPONSE GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE 140 –10 +10 10 RL = 2kΩ CL = 100pF +15 40 100 Ø 80 –90 60 –135 40 AOL Gain Bandwidth (MHz) –45 Phase Shift (Degrees) 120 Voltage Gain (dB) 120 8 36 GBW 35 6 Slew Rate 4 Slew Rate (V/µs) Bias Current (pA) 10 34 20 2 –180 0 1 10 100 1k 10k 100k 1M 10M 33 –75 Frequency (Hz) –50 0 +25 +50 –25 +75 Ambient Temperature (°C) +100 +125 ® 5 OPA404 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE OPEN-LOOP GAIN vs TEMPERATURE 8 38 120 36 GBW 6 34 110 Voltage Gain (dB) 7 Slew Rate (V/µs) Gain Bandwidth (MHz) AV = +1 RL = 10kΩ 100 90 Slew Rate 5 80 32 0 5 10 Supply Voltage (±VCC) 20 15 –75 –50 MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY –25 +75 0 +25 +50 Ambient Temperature (°C) +100 +125 LARGE SIGNAL TRANSIENT RESPONSE 10 Output Voltage (V) Output Voltage (Vp-p) 30 20 10 0 –10 RL = 2kΩ 0 1M 100k Frequency (Hz) 10k 10M 0 1 2 3 4 5 Time(µs) SETTLING TIME vs CLOSED-LOOP GAIN SMALL SIGNAL TRANSIENT RESPONSE 5 150 4 Settling Time (µs) Output Voltage (mV) 100 50 0 –50 3 2 0.01% –100 RL = 2kΩ CL = 100pF 1 –150 0.1% 0 0 1 Time(µs) –1 2 ® OPA404 –10 –100 Closed-Loop Gain (V/V) 6 –1k TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE CHANNEL SEPARATION vs FREQUENCY 150 Channel Separation (dB) Supply Current (mA) 11 10 9 8 RL = ∞ 140 130 120 RL = 2kΩ 110 0 7 –75 –50 –25 0 +25 +50 +75 Ambient Temperature (°C) +100 +125 10 TOTAL HARMONIC DISTORTION vs FREQUENCY 1k Frequency (Hz) 10k 100k OPEN-LOOP GAIN vs SUPPLY VOLTAGE 1 104 AV = +101V/V 40.2kΩ 402Ω 0.1 6.5Vrms Voltage Gain 2kΩ AV = +101V/V 0.01 100 96 AV = +1V/V Test Limit 0.001 0.1 1 10 1k 100 Frequency (Hz) 10k 92 100k 0 5 10 Supply Voltage (±VCC) 15 20 INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k Voltage Noise (nV/ Hz) THD + N (% rms) 100 100 10 1 1 10 100 1k 10k Frequency (Hz) 100k 1M ® 7 OPA404 APPLICATIONS INFORMATION GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. OFFSET VOLTAGE ADJUSTMENT The OPA404 offset voltage is laser-trimmed and will require no further trim for most applications. If desired, offset voltage can be trimmed by summing (see Figure 1). With this trim method there will be no degradation of input offset drift. Leakage currents across printed circuit boards can easily exceed the bias current of the OPA404. To avoid leakage, utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high impedance input leads and should be connected to a low-impedance point which is at the signal input potential. (See Figure 3). In 1/4 OPA404 Out Non-Inverting –15V 100kΩ 150kΩ 20Ω ±2mV Offset Trim +15V Out In Inverting INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-tosubstrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. In Out Unlike BIFET amplifiers, the Difet OPA404 requires input current limiting resistors only if its input voltage is greater than 8 volts more negative than –VCC. A 10kΩ series resistor will limit the input current to a safe value with up to ±15V input levels even if both supply voltages are lost. (See Figure 2 and Absolute Maximum Ratings). Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier. For input guarding, guard top and bottom of board. FIGURE 3. Connection of Input Guard. HANDLING AND TESTING Measuring the unusually low bias current of the OPA404 is difficult without specialized test equipment; most commercial benchtop testers cannot accurately measure the OPA404 bias current. Low-leakage test sockets and special test fixtures are recommended if incoming inspection of bias current is to be performed. To prevent surface leakage between pins, the DIP package should not be handled by bare fingers. Oils and salts from fingerprints or careless handling can create leakage currents that exceed the specified OPA404 bias currents. INPUT CURRENT vs INPUT VOLTAGE WITH ±VCC PINS GROUNDED Input Current (mA) +2 If necessary, DIP packages and PC board assemblies can be cleaned with Freon TF®, baked for 30 minutes at 85°C, rinsed with de-ionized water, and baked again for 30 minutes at 85°C. Surface contamination can be prevented by the application of a high-quality conformal coating to the cleaned PC board assembly. Maximum Safe Current IIN V 0 –1 Maximum Safe Current –2 –15 –10 –5 0 +5 +10 +15 Input Voltage (V) FIGURE 2. Input Current vs Input Voltage with ±VCC Pins Grounded. ® OPA404 Out In FIGURE 1. Offset Voltage Trim. +1 Buffer 8 BIAS CURRENT CHANGE vs COMMON-MODE VOLTAGE The input bias currents of most popular BIFET operational amplifiers are affected by common-mode voltage (Figure 4). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely low bias current of the OPA404 is not compromised by common-mode voltage. APPLICATIONS CIRCUITS Figures 5 through 11 are circuit diagrams of various applications for the OPA404. 1MΩ 10kΩ Operate 80 In Input Bias Current (pA) LF156/157 TA = +25°C; curves taken from mfg. published typical data 70 2 100Ω 3 Zero 1/4 OPA404 1 100kΩ 60 50 AD547 40 LF155 100kΩ LF156/157 30 Polypropylene 1µF 20 10 0 –10 Out LF155 AD547 OPA404 Gain = –100 VOS < 10µV Drift ≈ 0.05µV/°C Zero Droop ≈ 1µV/s Referred to Input 6 OPA404 7 1/4 OPA404 OP-15/16/17 5 –20 –15 –10 –5 0 +5 +10 +15 Common-Mode Voltage (VDC) FIGURE 4. Input Bias Current vs Common-Mode Voltage. FIGURE 5. Auto-Zero Amplifier. 10kΩ ≈10pF (1) 1MΩ 6 IN914 2 Input 3 1/4 OPA404 (1) 1 (1) 5 1/4 OPA404 7 Output Droop ≈ 0.1mV/s IN914 2N4117 0.01µF Polstyrene NOTE: (1) Reverse polarity for negative peak detection. FIGURE 6. Low-Droop Positive Peak Detector. ® 9 OPA404 2 1 1 1/4 OPA404 Output = 1µA/V 3 Differential Input 3 E1 1MΩ 6 2 E1 IO R Load IO = (E1 – E2) /R 5 INA105 FIGURE 7. Voltage-Controlled Microamp Current Source.