OPA4197QPWRQ1

OPA197-Q1, OPA2197-Q1, OPA4197-Q1 OPA197-Q1, OPA2197-Q1, SBOS918A – MARCH 2018 – REVISEDOPA4197-Q1 JANUARY 2021 SBOS918A – MARCH 2018 – REVISED JANUARY 2021 www.ti.com OPAx197-Q1 36-V, Precision, Rail-to-Rail Input/Output, Low-Offset Voltage, Low-Input Bias Current e-trim™ Operational Amplifiers 1 Features 3 Description • The OPAx197-Q1 family (OPA197-Q1, OPA2197-Q1, and OPA4197-Q1) is part of a new generation of 36-V, e-trim™ operational amplifiers. The OPAx197-Q1 family of e-trim operational amplifiers uses a proprietary method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. • • • • • • • • • • • • • • AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA Low offset voltage: ±250 µV (maximum) Low offset voltage drift: ±0.2 µV/°C Low noise: 5.5 nV/√Hz at 1 kHz High common-mode rejection: 140 dB Low bias current: ±5 pA Rail-to-rail input and output Wide bandwidth: 10 MHz GBW High slew rate: 20 V/µs Low quiescent current: 1 mA per amplifier Wide supply: ±2.25 V to ±18 V, 4.5 V to 36 V EMI/RFI filtered inputs Differential input-voltage range to supply rail High capacitive load drive capability: 1 nF Industry-standard packages: – Single and dual channel in very-small, 8-pin VSSOP – Quad channel in 14-pin TSSOP These devices offer outstanding dc precision and ac performance, including rail-to-rail input/output, low offset (±5 µV, typical), low offset drift (±0.2 µV/°C, typical), and a 10-MHz bandwidth. Unique features such as differential input-voltage range to the supply rail, high output current (±65 mA), high capacitive load drive of up to 1 nF, and high slew rate (20 V/µs) make the OPAx197-Q1 robust, highperformance op amps for high-voltage industrial applications. Device Information 2 Applications • • • • PACKAGE(1) PART NUMBER Inverter and motor control DC/DC converter On-board (OBC) and wireless charger Battery management system (BMS) OPA197-Q1 OPA2197-Q1 OPA4197-Q1 (1) BODY SIZE (NOM) VSSOP (8) 3.00 mm × 3.00 mm TSSOP (14) 5.00 mm × 4.40 mm For all available packages, see the package option addendum at the end of the data sheet. 100 66 Typical Units Shown 75 VOS ( V) 50 25 0 ±25 ±50 ±75 ±100 ±75 ±50 ±25 0 25 50 75 Temperature (ƒC) 100 125 150 C001 The OPAx197-Q1 Maintains Ultra-Low Input Offset Voltage Over Temperature An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings ....................................... 6 6.2 ESD Ratings .............................................................. 6 6.3 Recommended Operating Conditions ........................6 6.4 Thermal Information: OPA197-Q1 ............................. 7 6.5 Thermal Information: OPA2197-Q1 ........................... 7 6.6 Thermal Information: OPA4197-Q1 ........................... 7 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) .........................................................8 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) ......................................................10 6.9 Typical Characteristics.............................................. 12 7 Detailed Description......................................................21 7.1 Overview................................................................... 21 7.2 Functional Block Diagram......................................... 21 7.3 Feature Description...................................................22 7.4 Device Functional Modes..........................................28 8 Application and Implementation.................................. 29 8.1 Application Information............................................. 29 8.2 Typical Applications.................................................. 29 9 Power Supply Recommendations................................33 10 Layout...........................................................................33 10.1 Layout Guidelines................................................... 33 10.2 Layout Examples.................................................... 34 11 Device and Documentation Support..........................35 11.1 Device Support........................................................35 11.2 Documentation Support.......................................... 35 11.3 Receiving Notification of Documentation Updates.. 35 11.4 Support Resources................................................. 35 11.5 Trademarks............................................................. 36 11.6 Electrostatic Discharge Caution.............................. 36 11.7 Glossary.................................................................. 36 12 Mechanical, Packaging, and Orderable Information.................................................................... 36 4 Revision History Changes from Revision * (March 2018) to Revision A (January 2021) Page • Added OPA4197-Q1 and associated content..................................................................................................... 1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 5 Pin Configuration and Functions NC 1 –IN 2 +IN 3 V– 4 8 NC – 7 V+ + 6 OUT 5 NC Not to scale Figure 5-1. OPA197-Q1 DGK Package, 8-Pin VSSOP, Top View Pin Functions: OPA197-Q1 PIN NAME +IN I/O NO. 3 DESCRIPTION I Noninverting input Inverting input –IN 2 I NC 1, 5, 8 — No internal connection (can be left floating) OUT 6 O Output V+ 7 — Positive (highest) power supply V– 4 — Negative (lowest) power supply Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 3 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 OUT A 1 8 V+ –IN A 2 7 OUT B +IN A 3 6 –IN B V– 4 5 +IN B Not to scale Figure 5-2. OPA2197-Q1 DGK Package, 8-Pin VSSOP, Top View Pin Functions: OPA2197-Q1 PIN 4 I/O DESCRIPTION NAME DGK (VSSOP) +IN A 3 I Noninverting input, channel A +IN B 5 I Noninverting input, channel B –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 OUT A 1 14 OUT D –IN A 2 13 –IN D +IN A 3 12 +IN D V+ 4 11 V– +IN B 5 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C Not to scale Figure 5-3. OPA4197-Q1 PW Package, 14-Pin TSSOP, Top View Pin Functions: OPA4197-Q1 PIN I/O DESCRIPTION NAME NO. +IN A 3 I Noninverting input, channel A +IN B 5 I Noninverting input, channel B +IN C 10 I Noninverting input, channel C +IN D 12 I Noninverting input, channel D –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B –IN C 9 I Inverting input, channel C –IN D 13 I Inverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V+ 4 — Positive (highest) power supply V– 11 — Negative (lowest) power supply Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 5 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN VS Supply voltage Single supply, VS = (V+) 40 Dual supply, VS = (V+) – (V–) Common-mode Signal input voltage MAX ±20 (V–) – 0.5 Signal input current Output short circuit(2) Class IIA TA Operating temperature –55 TJ Junction temperature Tstg Storage temperature (2) V ±10 mA 150 °C 150 °C 150 °C Continuous Latch-up per JESD78D (1) V (V+) + 0.5 (V+) – (V–) + 0.2 Differential UNIT –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE UNIT OPA197-Q1, OPA2197-Q1 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM ESD classification level 3A ±4000 Charge device model (CDM), per AEC Q100-011 CDM ESD classification level C4A ±500 Human-body model (HBM), per AEC Q100-002(1) HBM ESD classification level 2 ±2000 Charge device model (CDM), per AEC Q100-011 CDM ESD classification level C5 ±750 V OPA4197-Q1 V(ESD) (1) Electrostatic discharge V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN 6 VS Supply voltage TA Operating temperature Submit Document Feedback Single supply, VS = (V+) Dual supply, VS = (V+) – (V–) NOM MAX 4.5 36 ±2.25 ±18 –40 125 UNIT V °C Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.4 Thermal Information: OPA197-Q1 OPA197-Q1 THERMAL METRIC(1) DGK (VSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 180.4 °C/W RθJC(top) Junction-to-case(top) thermal resistance 67.9 °C/W RθJB Junction-to-board thermal resistance 102.1 °C/W ψJT Junction-to-top characterization parameter 10.4 °C/W ψJB Junction-to-board characterization parameter 100.3 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Thermal Information: OPA2197-Q1 OPA2197-Q1 THERMAL METRIC(1) DGK (VSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 158 °C/W RθJC(top) Junction-to-case(top) thermal resistance 48.6 °C/W RθJB Junction-to-board thermal resistance 78.7 °C/W ψJT Junction-to-top characterization parameter 3.9 °C/W ψJB Junction-to-board characterization parameter 77.3 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Thermal Information: OPA4197-Q1 OPA4197-Q1 THERMAL METRIC(1) PW (TSSOP) UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 108.1 °C/W RθJC(top) Junction-to-case(top) thermal resistance 26.3 °C/W RθJB Junction-to-board thermal resistance 54.4 °C/W ψJT Junction-to-top characterization parameter 1.4 °C/W ψJB Junction-to-board characterization parameter 53.3 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 7 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±25 ±250 TA = 0°C to 85°C ±30 ±350 TA = –40°C to +125°C ±50 ±400 ±10 ±250 TA = 0°C to 85°C ±25 ±350 TA = –40°C to +125°C ±50 ±500 TA = 0°C to 85°C ±0.5 ±2.5 TA = –40°C to +125°C ±0.8 ±4.5 TA = –40°C to +125°C ±0.3 ±1.0 µV/V ±5 ±20 pA ±5 nA ±2 ±20 pA ±2 nA VCM = (V+) – 1.5 V dVOS/dT Input offset voltage drift PSRR Power-supply rejection ratio µV µV/°C INPUT BIAS CURRENT IB Input bias current IOS Input offset current TA = –40°C to +125°C TA = –40°C to +125°C NOISE En Input voltage noise Input voltage noise density en f = 0.1 Hz to 10 Hz 1.3 (V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz (V–) – 0.1 V < VCM < (V+) – 3 V 4 (V–) – 0.1 V < VCM < (V+) – 3 V (V+) – 1.5 V < VCM < (V+) + 0.1 V Input current noise density in f = 100 Hz µVPP 10.5 f = 1 kHz 5.5 f = 100 Hz 32 f = 1 kHz nV/√Hz 12.5 f = 1 kHz 1.5 fA/√Hz INPUT VOLTAGE Common-mode voltage VCM CMRR Common-mode rejection ratio (V–) – 0.1 (V+) + 0.1 (V–) – 0.1 V < VCM < (V+) – 3 V 120 140 (V–) < VCM < (V+) – 3 V, TA = –40°C to +125°C 114 126 100 120 86 100 (V+) – 1.5 V < VCM < (V+) TA = –40°C to +125°C V dB INPUT IMPEDANCE 8 ZID Differential ZIC Common-mode Submit Document Feedback 100 || 1.6 MΩ || pF 1 || 6.4 1013Ω || pF Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued) at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 120 134 114 126 126 140 120 134 MAX UNIT OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 2 kΩ (V–) + 0.3 V < VO < (V+) – 0.3 V, RL = 10 kΩ TA = –40°C to +125°C TA = –40°C to +125°C dB FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate G = 1, 10-V step To 0.01% ts Settling time To 0.001% tOR Overload recovery time VIN × G = VS THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, VO = 3.5 VRMS Crosstalk 10 MHz 20 V/µs G = 1, 10-V step 1.4 G = 1, 5-V step 0.9 G = 1, 10-V step 2.1 G = 1, 5-V step 1.8 µs 200 ns µs 0.00008% OPA4197-Q1 at dc 150 dB OPA4197-Q1, f = 100 kHz 130 dB OUTPUT No load Positive rail VO Voltage output swing from rail ISC 95 110 RL = 2 kΩ 430 500 5 15 RL = 10 kΩ 95 110 RL = 2 kΩ 430 500 Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance 15 RL = 10 kΩ No load Negative rail 5 ±65 mV mA See Section 6.9 f = 1 MHz, IO = 0 A; see Figure 6-29 375 Ω POWER SUPPLY IQ Quiescent current per IO = 0 A amplifier 1 TA = –40°C to +125°C 1.2 1.5 mA TEMPERATURE Thermal protection 140 Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 °C Submit Document Feedback 9 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VCM = (V+) – 3 V TA = 0°C to 85°C TA = –40°C to +125°C VOS Input offset voltage (V+) – 3.5 V < VCM < (V+) – 1.5 V VCM = (V+) – 1.5 V Input offset voltage drift VCM = (V+) – 3 V dVOS/dT Input offset voltage drift VCM = (V+) – 1.5 V PSRR Power-supply rejection ratio TA = –40°C to +125°C dVOS/dT ±5 ±250 ±8 ±350 ±10 ±400 µV See Section 7.3.6 ±10 ±250 TA = 0°C to 85°C ±25 ±350 TA = –40°C to +125°C ±50 ±500 ±0.5 ±2.5 ±0.8 ±4.5 TA = –40°C to +125°C µV/°C ±2 µV/V INPUT BIAS CURRENT IB Input bias current IOS Input offset current ±5 ±20 ±5 nA ±2 ±20 pA ±2 nA TA = –40°C to +125°C TA = –40°C to +125°C pA NOISE En Input voltage noise Input voltage noise density en (V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz (V–) – 0.1 V < VCM < (V+) – 3 V (V+) – 1.5 V < VCM < (V+) + 0.1 V Input current noise density in 1.3 (V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz µVPP 4 f = 100 Hz 10.5 f = 1 kHz 5.5 f = 100 Hz 32 f = 1 kHz nV/√Hz 12.5 f = 1 kHz 1.5 fA/√Hz INPUT VOLTAGE Common-mode voltage range VCM (V–) – 0.1 (V–) – 0.1 V < VCM < (V+) – 3 V CMRR Common-mode rejection ratio (V+) – 1.5 V < VCM < (V+) TA = –40°C to +125°C TA = –40°C to +125°C (V+) – 3 V < VCM < (V+) – 1.5 V (V+) + 0.1 94 110 90 104 100 120 84 100 V dB See Section 6.9 INPUT IMPEDANCE ZID Differential ZIC Common-mode 10 Submit Document Feedback 100 || 1.6 MΩ || pF 1 || 6.4 1013Ω || pF Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued) at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 2 kΩ TA = –40°C to +125°C (V–) + 0.3 V < VO < (V+) – 0.3 V, RL = 10 kΩ TA = –40°C to +125°C 110 120 100 114 110 126 110 120 dB 10 MHz 20 V/µs 1 µs ns dB FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate G = 1, 5-V step ts Settling time To 0.01%, VS = ±3 V, G = 1, 5-V step tOR Overload recovery time VIN × G = VS 200 OPA4197-Q1 at dc 150 dB OPA4197-Q1, f = 100 kHz 130 dB Crosstalk OUTPUT No load Positive rail VO Voltage output swing from rail ISC 95 110 RL = 2 kΩ 430 500 5 15 RL = 10 kΩ 95 110 RL = 2 kΩ 430 500 Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance 15 RL = 10 kΩ No load Negative rail 5 ±65 mV mA See Section 6.9 f = 1 MHz, IO = 0 A; see Figure 6-29 375 Ω POWER SUPPLY IQ Quiescent current per IO = 0 A amplifier 1 TA = –40°C to +125°C 1.2 1.5 mA TEMPERATURE Thermal protection 140 Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 °C Submit Document Feedback 11 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) Table 6-1. Table of Graphs DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 6-1 to Figure 6-6 Offset Voltage Drift Distribution Figure 6-7 to Figure 6-8 Offset Voltage vs Temperature Figure 6-9 Offset Voltage vs Common-Mode Voltage Figure 6-10 to Figure 6-12 Offset Voltage vs Power Supply Figure 6-13 Open-Loop Gain and Phase vs Frequency Figure 6-14 Closed-Loop Gain and Phase vs Frequency Figure 6-15 Input Bias Current vs Common-Mode Voltage Figure 6-16 Input Bias Current vs Temperature Figure 6-17 Output Voltage Swing vs Output Current (maximum supply) Figure 6-18 CMRR and PSRR vs Frequency Figure 6-19 CMRR vs Temperature Figure 6-20 PSRR vs Temperature Figure 6-21 0.1-Hz to 10-Hz Noise Figure 6-22 Input Voltage Noise Spectral Density vs Frequency Figure 6-23 THD+N Ratio vs Frequency Figure 6-24 THD+N vs Output Amplitude Figure 6-25 Quiescent Current vs Supply Voltage Figure 6-26 Quiescent Current vs Temperature Figure 6-27 Open Loop Gain vs Temperature Figure 6-28 Open Loop Output Impedance vs Frequency Small Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 6-29 Figure 6-30, Figure 6-31 No Phase Reversal Figure 6-32 Positive Overload Recovery Figure 6-33 Negative Overload Recovery Figure 6-34 Small-Signal Step Response (100 mV) Figure 6-35, Figure 6-36 Large-Signal Step Response Figure 6-37 Settling Time Figure 6-38 to Figure 6-41 Short-Circuit Current vs Temperature Figure 6-42 Maximum Output Voltage vs Frequency Figure 6-43 Propagation Delay Rising Edge Figure 6-44 Propagation Delay Falling Edge Figure 6-45 Crosstalk vs Frequency Figure 6-46 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 50 22 Distribution Taken From 190 Amplifiers 40 18 16 Amplifiers (%) 14 12 10 8 6 30 20 10 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 75 50 25 0 0 0 -25 2 -50 4 -75 Percentage of Amplifiers (%) 20 Offset Voltage (µV) Offset Voltage (V) C013 TA = 125°C Figure 6-1. Offset Voltage Production Distribution at 25°C Distribution Taken From 190 Amplifiers Distribution Taken From 190 Amplifiers 70 60 50 50 Amplifiers (%) 60 40 30 40 30 20 10 10 0 0 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 20 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 70 Offset Voltage (µV) Offset Voltage (µV) TA = 85°C TA = 0°C Figure 6-3. Offset Voltage Production Distribution at 85°C Figure 6-4. Offset Voltage Production Distribution at 0°C 50 40 35 35 25 20 75 50 0 25 5 0 0 10 5 -25 15 10 -50 15 Offset Voltage (µV) TA = –25°C 75 20 50 25 30 25 30 -75 Amplifiers (%) 40 -75 Amplifiers (%) Distribution Taken From 190 Amplifiers 45 0 Distribution Taken From 190 Amplifiers 45 -50 50 -25 Amplifiers (%) Figure 6-2. Offset Voltage Production Distribution at 125°C Offset Voltage (µV) TA = –40° C Figure 6-5. Offset Voltage Production Distribution at –25°C Figure 6-6. Offset Voltage Production Distribution at –40°C Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 13 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 50 30 Distribution Taken From 75 Amplifiers Distribution Taken From 75 Amplifiers 25 Amplifiers (%) 30 20 20 15 10 10 Offset Voltage Drift (µV/ƒC) 0.8 0.6 0.7 0.4 0.5 0.2 0.3 0 0.1 -0.2 -0.1 -0.4 -0.3 -0.6 -0.5 -0.8 0 1.1 0.9 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 -0.7 -0.9 -1.1 0 5 -0.7 Amplifiers (%) 40 Offset Voltage Drift (µV/ƒC) TA = –40°C to +125°C TA = 0°C to 85°C Figure 6-7. Offset Voltage Drift Distribution from –40°C to +125°C Figure 6-8. Offset Voltage Drift Distribution from 0°C to 85°C 50 100 75 25 Offset Voltage (V) 50 VOS (V) 25 0 –25 0 VCM = –18.1 V –25 –50 –75 –50 –100 –75 –50 –25 0 25 50 75 100 125 –20 150 –15 –10 –5 0 5 10 15 20 Common-Mode Voltage (V) Temperature ( °C) C001 Figure 6-10. Offset Voltage vs Common-Mode Voltage Figure 6-9. Offset Voltage vs Temperature 100 200 75 150 5 Typical Units Shown VCM = +18.1 V 25 Offset Voltage (µV) Offset Voltage (V) 50 VCM = –18.1 V 0 –25 P-Channel N-Channel –50 50 0 –50 –100 VCM = +2.35 V VCM = –2.35 V –150 –75 Transition –100 12.5 100 13.5 14.5 15.5 16.5 17.5 18.5 Common-Mode Voltage (V) Transition P-Channel –200 –2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 N-Channel 1.0 1.5 2.0 2.5 Common-Mode Voltage (V) VS = ±2.25 V Figure 6-11. Offset Voltage vs Common-Mode Voltage 14 Submit Document Feedback Figure 6-12. Offset Voltage vs Common-Mode Voltage Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 50 40 120.0 Open-Loop Gain 30 135 100.0 20 Gain (dB) 10 0 –10 80.0 Phase 60.0 90 40.0 Phase (°) Offset Voltage (µV) 180 140.0 10 Typical Units Shown –20 20.0 –30 45 0.0 –40 –50 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 1 10 100 1k 10k 100k Frequency (Hz) Power Supply Voltage (V) 1M CLOAD = 15 pF VS = ±2.25 V to ±18 V Figure 6-14. Open-Loop Gain and Phase vs Frequency Figure 6-13. Offset Voltage vs Power Supply 60.0 20 G = -100 G = +1 G = -1 G = -10 15 Input Bias Current (pA) 40.0 Gain (dB) 0 10M 100M –20.0 20.0 0.0 IB– 10 5 0 IB+ –5 –10 –15 –20 ±20.0 1000 10k 100k 1M 18.0 10M Frequency (Hz) Figure 6-15. Closed-Loop Gain and Phase vs Frequency 0.0 9.0 18.0 Common-Mode Voltage (V) C001 Figure 6-16. Input Bias Current vs Common-Mode Voltage (V–) + 5 6000 Out pu Voltage Swing (V) IB+ IB Ios 5000 Input Bias Current (pA) 9.0 C003 4000 3000 2000 1000 +125°C (V–) + 3 (V–) + 2 – 40°C (V–) + 1 (V–) Ios 0 (V–) + 4 (V–) – 1 ±1000 ±75 ±50 ±25 0 25 50 75 100 125 150 Temperature (ƒC) Figure 6-17. Input Bias Current vs Temperature 175 0 10 20 30 40 50 Output Current (mA) C001 60 70 80 C001 Figure 6-18. Output Voltage Swing vs Output Current (Maximum Supply) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 15 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) Common-Mode Rejection Ratio (µV/V) Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) 160.0 140.0 120.0 100.0 80.0 60.0 +PSRR 40.0 CMRR 20.0 -PSRR 0.0 10 8 6 4 VS = ±2.25 V, VCM = V+ - 3 V 2 0 ±2 VS = ±18 V, VCM = 0 V ±4 ±6 ±8 ±10 1 10 100 1k 10k 100k Frequency (Hz) 1M ±75 ±50 ±25 0 25 50 75 100 125 150 Temperature (ƒC) C012 Figure 6-19. CMRR and PSRR vs Frequency C001 Figure 6-20. CMRR vs Temperature 0.6 Noise (400 nV/div) Power-Supply Rejection Ratio (µV/V) 1 0.8 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 Peak-to-Peak Noise = VRMS × 6.6 = 1.30 µVpp –1 –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Time (1 s/div) 150 C001 C001 Figure 6-22. 0.1-Hz to 10-Hz Noise Figure 6-21. PSRR vs Temperature Total Harmonic Distortion + Noise (%) Voltage Noise Density (nV/√Hz) 0.1 VCM = V+ – 100 mV N-Channel Input 100 10 VCM = 0 V P-Channel Input 1 0.1 1 10 100 Frequency (Hz) 1k 10k Submit Document Feedback G = +1 V/V, RL = 2 kΩ G = –1 V/V, RL = 10 kΩ 0.01 –80 G = –1 V/V, RL = 2 kΩ 0.001 –100 0.0001 –120 0.00001 100k C002 Figure 6-23. Input Voltage Noise Spectral Density vs Frequency 16 –60 G = +1 V/V, RL = 10 kΩ Total Harmonic Distortion + Noise (dB) 1000 –140 10 100 1k 10k Frequency (Hz) VOUT = 3.5 VRMS BW = 80 kHz Figure 6-24. THD+N Ratio vs Frequency Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) 1.2 –60 0.01 –80 0.001 –100 0.0001 G = +1 G = +1 G = –1 G = –1 0.00001 0.01 –120 V/V, RL = 10 kΩ V/V, RL = 2 kΩ V/V, RL = 10 kΩ V/V, RL = 2 kΩ 0.1 Quiescent Current (mA) 0.1 Total Harmonic Distortion + Noise (dB) Total Harmonic Distortion + Noise (%) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 1.0 0.9 0.8 –140 1 1.1 0 10 4 8 12 16 20 24 28 32 36 Supply Voltage (V) Output Amplitude (VRMS) f = 1 kHz, BW = 80 kHz Figure 6-26. Quiescent Current vs Supply Voltage Figure 6-25. THD+N vs Output Amplitude 1.2 3.0 VS = 4.5 V VS = 36 V Open-Loop Gain (µV/V) Quiescent Current (mA) 2.0 1.1 VS = ±18 V 1 VS = ±2.25 V 0.9 1.0 0.0 –1.0 –2.0 0.8 –3.0 75 50 25 0 25 50 75 100 125 Temperature (°C) 150 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) C001 RL = 10 kΩ Figure 6-27. Quiescent Current vs Temperature Figure 6-28. Open-Loop Gain vs Temperature 10k 50 45 + 18 V 1k Overshoot (%) Output Impedance ( ) 40 100 35 + VIN - 30 - RISO OPA197-Q1 + CL -18 V 25 20 RISO = 0 0 Ω 15 25 RISO = 25 Ω 10 RISO = 50 Ω 5 0 10 0 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 10p RI = 1 kΩ Figure 6-29. Open-Loop Output Impedance vs Frequency 100p 1n Capacitive Load (F) C016 RF = 1 kΩ G = –1 Figure 6-30. Small-Signal Overshoot vs Capacitive Load (100mV Output Step) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 17 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 50 - 35 - RISO VIN + RL CL + + - 37 VPP -18 V Sine Wave (±18.5 V) -18 V - 30 VOUT OPA197-Q1 OPA197-Q1 + 5 V/div Overshoot (%) 40 VIN + 18 V + 18 V 45 25 20 15 VOUT RISO = 0 Ω0 RISO = 25 25 Ω RISO = 50 50 Ω 10 5 0 10p 100p Time (200 μs/div) 1n Capacitive Load (F) G=1 Figure 6-32. No Phase Reversal Figure 6-31. Small-Signal Overshoot vs Capacitive Load (100mV Output Step) + 18 V VOUT + VIN + 18 V OPA197-Q1 - VOUT + -18 V VOUT + VIN VOUT OPA197-Q1 5 V/div + 5 V/div - - - 18 V VIN VIN Time (200 ns/div) RI = 1 kΩ Time (200 ns/div) RF = 10 kΩ G = –10 RI = 1 kΩ Figure 6-33. Positive Overload Recovery G = –10 RF = 10 kΩ Figure 6-34. Negative Overload Recovery + 18 V - + OPA197-Q1 + 20 mV/div 20 mV/div VIN + 18 V - - CL - 18 V OPA197-Q1 + VIN + -18 V RL CL - Time (120 ns/div) Time (100 ns/div) CL = 10 pF RL = 1 kΩ G=1 Figure 6-35. Small-Signal Step Response (100 mV) 18 Submit Document Feedback CL = 10 pF G = –1 Figure 6-36. Small-Signal Step Response (100 mV) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 2 V/div Output Delta from Final Value (mV) 4 + 18 V - + OPA197-Q1 + VIN - CL -18 V 3 2 1 0 –1 0.01% Settling = ±1 mV –2 –3 Step Applied at t = 0 –4 0 Time (300 ns/div) RL = 1 kΩ 0.5 0.75 CL = 10 pF G = –1 1.25 1.5 1.75 2 G=1 Figure 6-38. Settling Time (10-V Positive Step) 4 Output Delta from Final Value (mV) 4 3 2 1 0 0.01% Settling = ±500 μV –1 –2 –3 Step Applied at t = 0 –4 3 2 1 0 –1 0.01% Settling = ±1 mV –2 –3 Step Applied at t = 0 –4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 Time (μs) 1 1.2 1.4 1.6 1.8 2 Time (μs) G=1 G=1 Figure 6-39. Settling Time (5-V Positive Step) Figure 6-40. Settling Time (10-V Negative Step) 80 4 ISC, Source 3 Short-Circuit Current (mA) Output Delta from Final Value (mV) 1 Time (μs) Figure 6-37. Large-Signal Step Response Output Delta from Final Value (mV) 0.25 2 1 0 0.01% Settling = ±500 μV –1 –2 ISC, Sink 60 40 20 –3 Step Applied at t = 0 0 –4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Time (μs) 1.8 –75 –50 –25 0 25 50 75 100 125 Temperature (°C) 150 C001 G=1 Figure 6-41. Settling Time (5-V Negative Step) Figure 6-42. Short-Circuit Current vs Temperature Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 19 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 30 Maximum output voltage without slew-rate induced distortion. VS = ±15 V Overdrive = 100 mV Output Voltage (5 V/div) Output Voltage (VPP) 25 20 15 VS = ±5 V 10 VS = ±2.25 V 5 tpLH = 0.97 s VOUT Voltage 0 10k 100k 1M Time (200 ns/div) 10M Frequency (Hz) C025 C033 Figure 6-44. Propagation Delay Rising Edge Figure 6-43. Maximum Output Voltage vs Frequency -100 VOUT Voltage Crosstalk (db) Output Voltage (1 V/div) -80 tpLH = 1.1 s Overdrive = 100 mV -120 -140 -160 Time (200 ns/div) -180 1k 10k Figure 6-45. Propagation Delay Falling Edge 20 Submit Document Feedback 100k 1M Frequency (Hz) C026 Figure 6-46. Crosstalk vs Frequency Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 7 Detailed Description 7.1 Overview The OPAx197-Q1 family of e-trim operational amplifiers use a proprietary method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are set, further communication to the trim structure is permanently disabled. Section 7.2 shows the simplified diagram of the OPAx197-Q1. Unlike previous e-trim op amps, the OPAx197-Q1 uses a patented two-temperature trim architecture to achieve a very-low offset voltage of 25 µV (maximum) and low voltage offset drift of 0.5 µV/°C (maximum) over the full specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers especially useful for high-impedance industrial sensors, filters, and high-voltage data acquisition. 7.2 Functional Block Diagram + NCH Input Stage ± IN+ 36-V Differential Front End Slew Boost High Capacitive Load Compensation + Output Stage VOUT ± IN± + PCH Input Stage ± e-WULPŒ Package Level Trim Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 21 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 7.3 Feature Description 7.3.1 Input Protection Circuitry The OPAx197-Q1 use a unique input architecture to eliminate the need for input protection diodes but still provide robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure 7-1 can be activated by fast transient step responses, and can introduce signal distortion and settlingtime delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling time, as shown in Figure 7-3. V+ V+ + VIN+ + VIN+ VOUT VOUT OPAx197-Q1 36 V ~0.7 V VIN VIN V OPA197-Q1 Provides Full 36-V Differential Input Range V Conventional Input Protection Limits Differential Input Range Copyright © 2018, Texas Instruments Incorporated Figure 7-1. OPAx197-Q1 Input Protection Does Not Limit Differential Input Capability Vn = +10 V RFILT +10 V 1 Ron_mux Sn 1 D +10 V CFILT 2 ~±9.3 V CS CD Vn+1 = ±10 V RFILT ±10 V Vin± 2 Ron_mux Sn+1 ~0.7 V CS CFILT Vout Idiode_transient ±10 V Input Low Pass Filter Vin+ Buffer Amplifier Simplified Mux Model Figure 7-2. Back-to-Back Diodes Create Settling Issues Output Delta From Final Value (mV) 100 Standard Input Diode Structure Extends Settling Time 80 60 40 0.1% Settling = ±10 mV 20 0 –20 OPA197-Q1 Input Structure Offers Fast Settling –40 –60 –80 –100 0 5 10 15 20 25 30 35 Time (µs) 40 45 50 55 60 C040 Figure 7-3. OPAx197-Q1 Protection Circuit Maintains Fast-Settling Transient Response 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 The OPAx197-Q1 family of operational amplifiers provides a true high-impedance differential input capability for high-voltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making these devices the optimal op amps for multichannel, high-switched, input applications. The OPAx197-Q1 tolerate a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up to 36 V, making these devices an excellent choice for use as comparators or in applications with fast-ramping input signals, such as multiplexed data-acquisition systems; see Figure 8-1. 7.3.2 EMI Rejection The OPAx197-Q1 use integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx197-Q1 benefit from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 7-4 shows the results of this testing on the OPAx197-Q1. Table 7-1 shows the EMIRR IN+ values for the OPAx197-Q1 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 7-1 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the TI application report EMI Rejection Ratio of Operational Amplifiers available for download from www.ti.com. 160.0 140.0 PRF = -10 dBm VSUPPLY = ±18 V VCM = 0 V EMIRR IN+ (dB) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 10M 100M 1G Frequency (Hz) 10G C017 Figure 7-4. EMIRR Testing Table 7-1. OPAx197-Q1 EMIRR IN+ For Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 44.1 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 52.8 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 61.0 dB Bluetooth®, 2.4 GHz 802.11b, 802.11g, 802.11n, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 69.5 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.7 dB 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 105.5 dB 5 GHz Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 23 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 7.3.3 Phase Reversal Protection The OPAx197-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPAx197-Q1 is a rail-to-rail input op amp; therefore, the commonmode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 7-5. VIN + 18 V VOUT 5 V/div OPA197-Q1 + + - 37 VPP -18 V Sine Wave (±18.5 V) VOUT Time (200 μs/div) Figure 7-5. No Phase Reversal 7.3.4 Thermal Protection +30 V VOUT The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the OPAx197-Q1 is 150°C and exceeding this maximum temperature causes damage to the device. The OPAx197-Q1 have a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 140°C. Figure 7-6 shows an application example for the OPAx197-Q1 that has significant self heating (159°C) because of the power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of 65°C, the device junction temperature must reach 187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 7-6 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. TA = 65°C PD = 0.81W R JA = 116°C/W TJ = 116°C/W × 0.81W + 65°C TJ = 159°C (expected) 3V Normal Operation 0V Output High-Z 150°C OPAx197-Q1 + ± VIN 3V + RL 3V 100 Ÿ ± 140ºC Temperature IOUT = 30 mA Copyright © 2017, Texas Instruments Incorporated Figure 7-6. Thermal Protection 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 7.3.5 Capacitive Load and Stability The OPAx197-Q1 feature a patented output stage capable of driving large capacitive loads, and in a unity-gain configuration, directly drive up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of these amplifiers to drive greater capacitive loads; see Figure 7-7 and Figure 7-8. The particular op-amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier is stable in operation. 50 50 45 + 18 V 45 - + 18 V 35 + VIN - 30 - 40 RISO OPA197-Q1 + Overshoot (%) Overshoot (%) 40 CL -18 V 25 35 + VIN + RL 25 RISO = 0 0 Ω 15 25 RISO = 25 Ω 15 10 RISO = 50 Ω 10 20 RISO = 0 Ω0 RISO = 25 25 Ω RISO = 50 50 Ω 5 0 0 10p 100p 1n CL -18 V - 30 20 5 RISO OPA197-Q1 10p 100p Capacitive Load (F) 1n Capacitive Load (F) Figure 7-7. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 7-8. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10Ω to 20-Ω) resistor, RISO, in series with the output, as shown in Figure 7-9. This resistor significantly reduces ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the OPAx197-Q1 a great choice for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-9 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin, and results using the OPAx197-Q1 are summarized in Table 7-2. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIPD128 details complete design goals, simulation, and test results. +Vs Vout Riso + Vin + ± Cload -Vs Figure 7-9. Extending Capacitive Load Drive With the OPAx197-Q1 Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 25 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 Table 7-2. OPAx197-Q1 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and Measured Results PARAMETER VALUE Capacitive Load 100 pF 1000 pF 0.01 µF 0.1 µF 1 µF Phase Margin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60° RISO (Ω) 47 360 24 100 20 51 6.2 15.8 2 4.7 Measured Overshoot (%) 23.2 8.6 10.4 22.5 9 22.1 8.7 23.1 8.6 21 8.6 Calculated PM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2° For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, see TI Precision Design TIPD128Capacitive Load Drive Solution using an Isolation Resistor. 7.3.6 Common-Mode Voltage Range The OPAx197-Q1 are 36-V, true rail-to-rail input operational amplifiers with an input common-mode range that extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 7-10. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically ( V+) –3 V to (V+) – 1.5 V, in which both input pairs are on. This transition region can vary modestly with process variation, and within this region, PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded compared to operation outside this region. +Vsupply IS1 VIN± PCH1 PCH2 NCH4 NCH3 VIN+ e-trimTM FUSE BANK VOS TRIM VOS DRIFT TRIM ±Vsupply Figure 7-10. Rail-to-Rail Input Stage 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when possible. The OPAx197-Q1 use a precision trim for both the N-channel and P-channel regions. This technique enables significantly lower levels of offset than previous-generation devices, causing variance in the transition region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in Figure 7-11. Transition Region N-Channel Region P-Channel Region 200 200 100 100 Input Offset Voltage ( V) Input Offset Voltage ( V) P-Channel Region 0 ±100 OPA197 e-Trim Input Offset Voltage vs Vcm ±200 Transition Region N-Channel Region 0 ±100 ±200 Input Offset Voltage vs Vcm without e-Trim Input ±300 ±15.0 ±14.0 « 11.0 12.0 13.0 Common-Mode Voltage (V) 14.0 15.0 ±300 ±15.0 ±14.0 « 11.0 12.0 13.0 Common-Mode Voltage (V) 14.0 15.0 Figure 7-11. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers 7.3.7 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 7-12 shows an illustration of the ESD circuits contained in the OPAx197-Q1 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 27 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 TVS + ± RF +VS OPAx197-Q1 VDD R1 IN± 100 Ÿ IN+ 100 Ÿ RS ± + Power Supply ESD Cell VIN RL + ± VSS + ± ±VS TVS Copyright © 2017, Texas Instruments Incorporated Figure 7-12. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level. Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events. 7.3.8 Overload Recovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx197-Q1 is approximately 200 ns. 7.4 Device Functional Modes The OPAx197-Q1 have a single functional mode and is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power supply voltage for the OPAx197-Q1 is 36 V (±18 V). 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The OPAx197-Q1 family offers outstanding dc precision and ac performance. These devices operate up to 36-V supply rails and offer true rail-to-rail input and output, ultra-low offset voltage and offset voltage drift, as well as 10-MHz bandwidth and high capacitive load drive. These features make the OPAx197-Q1 a robust, highperformance operational amplifier for high-voltage industrial applications. 8.2 Typical Applications 8.2.1 16-Bit Precision Multiplexed Data-Acquisition System Figure 8-1 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the OPAx197-Q1 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. 1 2 Very Low Output Impedance Input-Filter Bandwidth High-Impedance Inputs No Differential Input Clamps Fast Settling-Time Requirements Attenuate High-Voltage Input Signal Fast-Settling Time Requirements Stability of the Input Driver 4 Attenuate ADC Kickback Noise VREF Output: Value and Accuracy Low Temp and Long-Term Drift Voltage Reference CH0+ OPAx197-Q1 ±20-V, 10-kHz Sine Wave 3 + RC Filter Buffer RC Filter Reference Driver + CH0- OPAx197-Q1 Gain Network OPAx197-Q1 Gain Network + 4:2 Mux REFP + OPAx197-Q1 CH3+ OPAx197-Q1 + + Antialiasing Filter SAR ADC + VINM OPAx197-Q1 CH3- n 16 Bits 400 kSPS High-Voltage Level Translation VCM High-Voltage Multiplexed Input CONV Gain Network ±20-V, 10-kHz Sine Wave VINP OPAx197-Q1 Gain Network REF3240 Voltage Divider OPA350 VCM Generation Circuit Counter n 5 Shmidtt Trigger Delay Digital Counter For Multiplexer Fast logic transition Copyright © 2017, Texas Instruments Incorporated Figure 8-1. OPAx197-Q1 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for HighVoltage Inputs With Lowest Distortion Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 29 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 8.2.1.1 Design Requirements The primary objective is to design a ±20-V, differential, 4-channel, multiplexed data acquisition system with lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure sine-wave input. The design requirements for this block design are: • • • • • System supply voltage: ±15 V ADC supply voltage: 3.3 V ADC sampling rate: 400 kSPS ADC reference voltage (REFP): 4.096 V System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency (fIN) of 10 kHz are applied to each differential input of the multiplexer. 8.2.1.2 Detailed Design Procedure The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 8-1. The circuit is a multichannel data acquisition signal chain consisting of an input low-pass filter, mux, mux output buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit resolution and lowest distortion system. Figure 8-1 includes the most important specifications for each individual analog block. This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next step is to design a digital interface to switch the mux input channels with minimum delay. The final design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage with low offset, drift, and noise contributions. For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD151, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High Voltage Inputs with Lowest Distortion. 8.2.1.3 Application Curve Integral Nonlinearity Error (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –20 –15 –10 –5 0 5 10 15 20 ADC Differential Input (V) Figure 8-2. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 8.2.2 Slew-Rate Limit for Input Protection In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages. By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output current and slew rate of the OPAx197-Q1 make these devices the optimal amplifiers to achieve slew-rate control for both dual- and single-supply systems.Figure 8-3 shows the OPAx197-Q1 in a slew-rate limit design. Op Amp Gain Stage Slew Rate Limiter C1 470 nF R1 1.69 NŸ VEE VEE + R2 1.6 0Ÿ VIN OPAx197-Q1 V+ VOUT OPAx197-Q1 V+ VCC RL 10 NŸ VCC Copyright © 2017, Texas Instruments Incorporated Figure 8-3. Slew-Rate Limiter Uses One Op Amp For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see TI Precision Design TIPD140, Slew Rate Limiter Uses One Op Amp. Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 31 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 8.2.3 Precision Reference Buffer The OPAx197-Q1 feature high output-current-drive capability and low input offset voltage, making these devices an excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the 10-µF ceramic capacitor shown in Figure 8-4, a 37.4-Ω isolation resistor (RISO), provides separation of two feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output (VOUT). Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still provide a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability components: RF, RFx , CF , and RISO. RF 1 kŸ RFx 10 kŸ CF 39 nF RISO 37.4 Ÿ VOUT OPAx197-Q1 V+ CL 10 µF VREF 2.5 V VCC Copyright © 2017, Texas Instruments Incorporated Figure 8-4. Precision Reference Buffer 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 9 Power Supply Recommendations The OPAx197-Q1 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Section 6.9. CAUTION Supply voltages larger than 40 V can permanently damage the device; see Absolute Maximum Ratings. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Section 10. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • • • • • • • • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace. Place the external components as close as possible to the device. As illustrated in Figure 10-2, keep RF and RG close to the inverting input to minimize parasitic capacitance. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. For best performance, clean the PCB following board assembly. Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 33 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 10.2 Layout Examples + VIN VOUT RG RF Figure 10-1. Schematic Representation Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors RF VS+ N/C N/C GND ±IN V+ VIN +IN OUTPUT V± N/C RG GND GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitors Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ Simulation Software (Free Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ simulation software is a free, fully functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI simulation software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quickstart tool. Note These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.2 TI Precision Designs The OPA197 is featured in several Texas Instruments (TI) Precision Designs, available online at http:// www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report • Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor reference design 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 Submit Document Feedback 35 OPA197-Q1, OPA2197-Q1, OPA4197-Q1 www.ti.com SBOS918A – MARCH 2018 – REVISED JANUARY 2021 11.5 Trademarks e-trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments. TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA197-Q1 OPA2197-Q1 OPA4197-Q1 PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) OPA197QDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 197 OPA2197QDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2197 OPA4197QPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 O4197Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of