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OPA4277-EP
SBOS714 – NOVEMBER 2014
OPA4277-EP High Precision Operational Amplifier
1 Features
•
•
•
•
•
•
•
•
•
1
3 Description
Ultra-Low Offset Voltage: 10 μV
Ultra-Low Drift: ±0.1 μV/°C
High Open-Loop Gain: 134 dB
High Common-Mode Rejection: 140 dB
High-Power Supply Rejection: 130 dB
Low Bias Current: 1-nA Max
Wide Supply Range: ±2 to ±18 V
Low Quiescent Current: 800 μA/Amplifier
Supports Defense, Aerospace, and Medical
Applications
– Controlled Baseline
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
2 Applications
•
•
•
•
•
•
•
Transducer Amplifier
Bridge Amplifier
Temperature Measurements
Strain Gage Amplifier
Precision Integrator
Battery Powered Instruments
Test Equipment
The OPA4277-EP precision operational amplifier
replaces the industry standard OP-177. It offers
improved noise, wider output voltage swing, and is
twice as fast with half the quiescent current. Features
include ultra-low offset voltage and drift, low bias
current, high common-mode rejection, and high
power supply rejection.
The OPA4277-EP operates from ±2- to ±18-V
supplies with excellent performance. Unlike most
operational amplifiers which are specified at only one
supply
voltage,
the
OPA4277-EP
precision
operational amplifier is specified for real-world
applications; a single limit applies over the ±5- to ±15V supply range. High performance is maintained as
the amplifier swings to the specified limits. Because
the initial offset voltage (±20-μV max) is so low, user
adjustment is usually not required.
The OPA4277-EP is easy to use and free from phase
inversion and overload problems found in some
operational amplifiers. It is stable in unity gain and
provides excellent dynamic behavior over a wide
range of load conditions. The OPA4277-EP features
completely independent circuitry for lowest crosstalk
and freedom from interaction, even when overdriven
or overloaded.
Device Information(1)
PART NUMBER
OPA4277MDTEP
PACKAGE
SOIC (14)
BODY SIZE (NOM)
3.91 mm × 8.65 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
R2
R1
OPA4277
No bias current
cancellation resistor
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA4277-EP
SBOS714 – NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1 Trademarks ........................................................... 16
11.2 Electrostatic Discharge Caution ............................ 16
11.3 Glossary ................................................................ 16
Detailed Description ............................................ 10
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
7.1 Overview ................................................................. 10
4 Revision History
2
DATE
REVISION
NOTES
November 2014
*
Initial release.
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5 Pin Configuration and Functions
D Package
14 Pins
(Top View)
Out D
Out A
1
14
–In A
2
13
–In D
+In A
3
12
+In D
A
D
V+
4
11
V–
+In B
5
10
+In C
–In B
6
9
–In C
Out B
7
8
Out C
B
C
Pin Functions
PIN
I/O
DESCRIPTION
1
O
Amplifier output A
2
I
Inverting amplifier input A
3
I
Noninverting amplifier input A
4
P
Positive amplifier power supply input
+IN B
5
I
Noninverting amplifier input B
–IN B
6
I
Inverting amplifier input B
OUT B
7
O
Amplifier output B
OUT C
8
O
Amplifier output C
–IN C
9
I
Inverting amplifier input C
+IN C
10
I
Noninverting amplifier input C
V–
11
P
Negative amplifier power supply input
+IN D
12
I
Noninverting amplifier input D
–IN D
13
I
Inverting amplifier input D
OUT D
14
O
Amplifier output D
NAME
NO.
OUT A
–IN A
+IN A
V+
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
MIN
MAX
UNIT
36
V
(V+) + 0.7
V
Supply voltage
Input voltage
(V–) – 0.7
Output short circuit
Continuous
Operating temperature
125
°C
Junction temperature
150
°C
Lead temperature (soldering, 10 s)
300
°C
(1)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
Tstg
Electrostatic
discharge
V(ESD)
(1)
MIN
MAX
UNIT
–55
125
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
–2000
2000
Machine model (MM)
–100
100
Storage temperature range
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Dual supply voltage
TJ
Operating junction temperature
MAX
UNIT
±5
±15
V
–55
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
OPA4277-EP
D (14 PINS)
RθJA
Junction-to-ambient thermal resistance
66.3
RθJC(top)
Junction-to-case (top) thermal resistance
19.3
RθJB
Junction-to-board thermal resistance
26.8
ψJT
Junction-to-top characterization parameter
2.1
ψJB
Junction-to-board characterization parameter
26.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TJ = 25°C, and RL = 2 kΩ, VS = ±5 to ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
dVOS/dT
Input offset voltage
±20
Input offset voltage over temperature TJ = –55°C to 125°C
Input offset voltage drift
±0.15
vs time
PSRR
Input offset voltage
µV
µV/°C
0.2
vs power supply, VS = ±2 to ±18 V
±0.3
TJ = –55°C to 125°C; VS = ±2 to
±18 V
Channel separation
±65
±140
dc
µV/mo
±1
µV/V
±1
µV/V
0.1
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±0.5
TJ = –55°C to 125°C
±2.8
nA
±7.5
±0.5
TJ = –55°C to 125°C
±2.8
nA
±7.5
NOISE
Input voltage noise
en
Input voltage noise density
in
Current noise density
ƒ = 0.1 to 10 Hz
0.22
ƒ = 10 Hz
12
ƒ = 100 Hz
8
ƒ = 1 kHz
8
ƒ = 10 kHz
µVpp
nV/√Hz
8
ƒ = 1 kHz
0.2
pA/√Hz
INPUT VOLTAGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection
(V–) + 2
VCM = (V–) + 2 V to (V+) – 2 V
115
TJ = –55°C to 125°C; VCM = (V–) + 2
V to (V+) – 2 V
115
(V+) – 2
V
140
dB
INPUT IMPEDANCE
Differential
Common mode
VCM = (V–) + 2 V to (V+) – 2 V
100 || 3
MΩ || pF
250 || 3
GΩ || pF
OPEN-LOOP GAIN
VO = (V–) + 0.5 V to (V+) – 1.2 V,
RL = 10 kΩ
AOL
Open-loop voltage gain
140
VO = (V–) + 1.5 V to (V+) – 1.5 V,
RL = 2 kΩ
126
TJ = –55°C to 125°C; VO = (V–) +
1.5 V to (V+) – 1.5 V, RL = 2 kΩ
126
134
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
Setting time
THD + N
Total harmonic distortion + noise
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1
MHz
0.8
V/µs
0.1%, VS = ±15 V, G = 1, 10-V step
14
0.01%, VS = ±15 V, G = 1, 10-V step
16
1 kHz, G = 1, VO = 3.5 Vrms
µs
0.002%
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Electrical Characteristics (continued)
At TJ = 25°C, and RL = 2 kΩ, VS = ±5 to ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
TJ = –55°C to 125°C; RL = 10 kΩ
(V–) + 0.5
(V+) – 1.2
TJ = –55°C to 125°C; RL = 2 kΩ
(V–) + 1.5
(V+) – 1.5
VO
Voltage output
ISC
Short-circuit current
±35
CLOAD
Capacitive load drive
See Typical Characteristics
V
mA
POWER SUPPLY
VS
Specified voltage
±5
Operating voltage
IQ
±2
Quiescent current (per amplifier)
IO = 0
±790
±15
V
±18
V
±825
TJ = –55°C to 125°C; IO = 0
±900
µA
6.6 Typical Characteristics
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
140
140
0
120
100
–30
80
–60
φ
60
–90
40
–120
20
–150
0
–180
+PSR
–PSR
PSR, CMR (dB)
AOL (dB)
120
CL = 0
CL = 1500pF
Phase (°)
G
100
80
CMR
60
40
20
0
–20
0.1
1
10
100
1k
10k
100k
1M
0.1
10M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 2. Power Supply and Common-Mode Rejection vs
Frequency
Figure 1. Open-Loop Gain/Phase vs Frequency
Noise signal is bandwidth limited to
lie between 0.1Hz and 10Hz.
Current Noise
100
50nV/div
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)
1000
Voltage Noise
10
1
1
10
100
1k
10k
1s/div
Frequency (Hz)
Figure 3. Input Noise and Current Noise Spectral Density vs
Frequency
6
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Figure 4. Input Noise Voltage vs Time
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
1
120
THD+Noise (%)
Channel Separation (dB)
140
100
Dual and quad devices. G = 1,
all channels. Quad measured
channel A to D or B to C —other
combinations yield similar or
improved rejection.
80
60
0.1
G = 10, RL = 2kΩ, 10kΩ
0.01
G = 1, RL = 2kΩ, 10kΩ
0.001
40
10
100
1k
10k
100k
1M
10
100
1k
Frequency (Hz)
10k
100k
Frequency (Hz)
VOUT = 3.5 Vrms
Figure 5. Channel Separation vs Frequency
Figure 6. Total Harmonic Distortion + Noise vs Frequency
35
16
12
Typical distribution
of packaged units.
Single, dual, and
quad included.
30
Percent of Amplifiers (%)
Percent of Amplifiers (%)
14
Typical distribution
of packaged units.
Single, dual, and
quad included.
10
8
6
4
25
20
15
10
5
2
0
0
0
– 50– 45– 40– 35– 30– 25– 20– 15– 10– 5 0 5 10 15 20 25 30 35 40 45 50
Offset Voltage (µV)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Offset Voltage (µV/°C)
Figure 7. Offset Voltage Production Distribution
Figure 8. Offset Voltage Drift Production Distribution
5
160
4
Input Bias Current (nA)
AOL, CMR, PSR (dB)
150
CMR
140
AOL
130
PSR
120
3
2
1
0
–1
–2
Curves represent typical
production units.
–3
110
–4
100
–75
–5
–50
–25
0
25
50
75
100
Temperature ( °C)
Figure 9. AOL, CMR, PSR vs Temperature
Copyright © 2014, Texas Instruments Incorporated
125
–75
–50
–25
0
25
50
75
100
125
Temperature ( °C)
Figure 10. Input Bias Current vs Temperature
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Typical Characteristics (continued)
100
950
90
900
80
70
850
±I Q
800
60
50
750
–ISC
700
40
+ISC
650
30
2.0
1.0
0.5
0.0
–1.0
20
550
10
–1.5
500
–75
0
–2.0
–25
0
25
50
75
100
VCM = 0V
–0.5
600
–50
Curve shows normalized change in
bias current with respect to VS = ±10V
(+20V). Typical I B may range from
–0.5nA to +0.5nA at V S = ±10V.
1.5
∆IB (nA)
1000
Short-Circuit Current (mA)
Quiescent Current (µA)
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
0
125
5
10
Figure 11. Quiescent Current and Short-Circuit Current vs
Temperature
30
35
40
Quiescent Current (µA)
per amplifier
VS = ±5V
∆IB (nA)
25
1000
Curve shows normalized change in bias current
with respect to VCM = 0V. Typical I B may range
from –05.nA to +0.5nA at V CM = 0V.
1.0
20
Figure 12. Change in Input Bias Current vs Power Supply
Voltage
2.0
1.5
15
Supply Voltage (V)
Temperature (°C)
0.5
0.0
–0.5
VS = ±15V
–1.0
900
800
700
600
–1.5
–2.0
500
–15
–10
–5
0
5
10
15
0
Common-Mode Voltage (V)
±10
±15
±20
Supply Voltage (V)
Figure 13. Change in Input Bias Current vs Common-Mode
Voltage
Figure 14. Quiescent Current vs Supply Voltage
30
100
VS = ±15V
50
Output Voltage (V PP)
25
Settling Time (µs)
±5
0.01%
0.1%
20
20
15
10
VS = ±5V
5
0
10
±1
±10
±100
Gain (V/V)
10-V step
10k
100k
1M
Frequency (Hz)
CL = 1500 pF
Figure 15. Settling Time vs Closed-Loop Gain
8
1k
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Figure 16. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
60
(V+)
Gain = –1
–55°C
(V+) – 2
50
(V+) – 3
125°C
(V+) – 4
Overshoot (%)
Output Voltage Swing (V)
(V+) – 1
25°C
(V+) – 5
(V–) + 5
25°C
125°C
(V–) + 4
40
Gain = +1
30
20
(V–) + 3
Gain = ±10
(V–) + 2
10
–55°C
(V–) + 1
0
(V–)
0
±5
±10
±15
±20
±25
10
±30
100
1k
10k
100k
Load Capacitance (pF)
Output Current (mA)
Figure 18. Small-Signal Overshoot vs Load Capacitance
2V/div
20mV/div
Figure 17. Output Voltage Swing vs Output Current
1µs/div
10µs/div
G=1
CL = 1500 pF
VS = 15 V
G=1
CL = 0 pF
VS = 15 V
Figure 20. Small-Signal Step Response
20mV/div
Figure 19. Large-Signal Step Response
1µs/div
G=1
CL = 1500 pF
VS = 15 V
Figure 21. Small-Signal Step Response
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7 Detailed Description
7.1 Overview
The OPA4277-EP precision operational amplifier replaces the industry standard OP-177. It offers improved
noise, wider output voltage swing, and is twice as fast with half the quiescent current. Features include ultra-low
offset voltage and drift, low bias current, high common-mode rejection, and high power supply rejection.
7.2 Functional Block Diagram
Vsupply+
Vin+
+
Vout
Vin±
±
Vsupply±
7.3 Feature Description
The OPA4277-EP operates from ±2- to ±18-V supplies with excellent performance. Unlike most operational
amplifiers which are specified at only one supply voltage, the OPA4277-EP precision operational amplifier is
specified for real-world applications; a single limit applies over the ±5- to ±15-V supply range. High performance
is maintained as the amplifier swings to the specified limits. Because the initial offset voltage (±50 μV max) is so
low, user adjustment is usually not required.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA4277 is unity-gain stable and free from unexpected output phase reversal, making it easy to use in a
wide range of applications. Applications with noisy or high-impedance power supplies may require decoupling
capacitors close to the device pins. In most cases, 0.1-μF capacitors are adequate.
8.2 Typical Application
V+
Trim Range: Exceeds
Offset Voltage Specification
0.1µF
20kΩ
7
1
2
3
0.1µF
8
OPA4277 6
4
OPA4277 single op amp only.
Use offset adjust pins only to null
offset voltage of op amp—see text.
V–
Figure 22. OPA4277 Offset Voltage Trim Circuit
8.2.1 Design Requirements
For the thermocouple low-offset, low-drift loop measurement with diode cold junction compensation (see
Figure 25), Table 1 lists the design parameters needed with gain = 50.
2RF
G 1
50
R
(1)
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
RF
10 kΩ
R
412 Ω
8.2.2 Detailed Design Procedure
8.2.2.1 Offset Voltage Adjustment
The OPA27 is laser-trimmed for very-low offset voltage and drift so most circuits do not require external
adjustment. However, offset voltage trim connections are provided on pins 1 and 8. The user can adjust offset
voltage by connecting a potentiometer as shown in Figure 22. Only use this adjustment to null the offset of the
operational amplifier. This adjustment should not be used to compensate for offsets created elsewhere in a
system because this can introduce additional temperature drift.
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8.2.2.2 Input Protection
The inputs of the OPA4277 are protected with 1-kΩ series input resistors and diode clamps. The inputs can
withstand ±30-V differential inputs without damage. The protection diodes conduct current when the inputs are
overdriven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the
operational amplifier.
8.2.2.3 Input Bias Current Cancellation
The input stage base current of the OPA4277 is internally compensated with an equal and opposite cancellation
circuit. The resulting input bias current is the difference between the input stage base current and the
cancellation current. This residual input bias current can be positive or negative.
When the bias current is canceled in this manner, the input bias current and input offset current are
approximately the same magnitude. As a result, it is not necessary to use a bias current cancellation resistor, as
is often done with other operational amplifiers (see Figure 23). A resistor added to cancel input bias current
errors may actually increase offset voltage and noise.
R2
R2
R1
R1
Op Amp
OPA4277
RB = R2 || R1
No bias current
cancellation resistor
(see text)
(a)
(b)
Conventional op amp with external bias
current cancellation resistor.
OPA4277 with no external bias current
cancellation resistor.
Figure 23. Input Bias Current Cancellation
V+
1/2
OPA4277
VOUT = (V1 – V2)(1 +
R2
R1
)
R2
V–
R–∆R
Load
Cell
V1
R+∆R
R+∆R
V2
V+
R1
1/2
OPA4277
R–∆R
V–
R2
R1
For integrated solution see: INA126, INA2126 (dual)
INA125 (on-board reference)
INA122 (single-supply)
Figure 24. Load Cell Amplifier
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IREG ∼ 1mA
5V
12
V+
Type J
VLIN
1/2
OPA4277
13
RF
10kΩ
4
R
412Ω
+
VIN
1
IR1
3
11
VREG
10
V+
RG
RG
1250Ω
RF
10kΩ
14
IR2
B
XTR105
E
RG
9
8
IO
1/2
OPA4277
1kΩ
2
25Ω
7
IRET
V–
50Ω
–
VIN
+
–
IO = 4mA + (V IN – VIN) 40
RG
6
RCM = 1250Ω
(G = 1 +
2RF
= 50)
R
0.01µF
Figure 25. Thermocouple Low Offset, Low Drift Loop Measurement With Diode Cold Junction
Compensation
8.2.3 Application Curve
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
Offset Voltage Change (µV)
3
2
1
0
–1
–2
–3
0
15
30
45
60
75
90
105
120
Time from Power Supply Turn-On (s)
Figure 26. Warm-Up Offset Voltage Drift
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9 Power Supply Recommendations
OPA4277 operates from ±2- to ±18-V supplies with excellent performance. Unlike most operational amplifiers
which are specified at only one supply voltage, the OPA4277 is specified for real-world applications; a single limit
applies over the ±5- to ±15-V supply range. This allows a customer operating at VS = ±10 V to have the same
assured performance as a customer using ±15-V supplies. In addition, key parameters are assured over the
specified temperature range, –55°C to 125°C. Most behavior remains unchanged through the full operating
voltage range (±2 to ±18 V). Parameters which vary significantly with operating voltage or temperature are shown
in the typical performance curves.
10 Layout
10.1 Layout Guidelines
The leadframe die pad should be soldered to a thermal pad on the PCB. Mechanical drawings located in
Mechanical, Packaging, and Orderable Information show the physical dimensions for the package and pad.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
The OPA4277 has very-low offset voltage and drift. To achieve highest performance, optimize circuit layout and
mechanical conditions. Offset voltage and drift can be degraded by small thermoelectric potentials at the
operational amplifier inputs. Connections of dissimilar metals generate thermal potential, which can degrade the
ultimate performance of the OPA4277. Cancel these thermal potentials by assuring that they are equal in both
input terminals.
• Keep the thermal mass of the connections made to the two input terminals similar.
• Locate heat sources as far as possible from the critical input circuitry.
• Shield operational amplifier and input circuitry from air currents such as cooling fans.
14
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Copyright © 2014, Texas Instruments Incorporated
OPA4277-EP
www.ti.com
SBOS714 – NOVEMBER 2014
10.2 Layout Example
Figure 27. Board Layout Example
Copyright © 2014, Texas Instruments Incorporated
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15
OPA4277-EP
SBOS714 – NOVEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
OPA4277MDTEP
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
-55 to 125
OPA4277EP
V62/14625-01XE
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
-55 to 125
OPA4277EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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