OPA310, OPA2310, OPA4310
SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
OPAx310 High Output Current, Fast Shutdown, Low Voltage (1.5 V to 5.5 V), RRIO,
3-MHz Operational Amplifier
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
High output current: ±150-mA typical ISC at 5.5 V
Fast enable from shutdown: 0.9-µs typical
Wide operational supply voltage: 1.5 V to 5.5 V
Low input offset voltage: ±250-µV typical
Fail-safe inputs: No diode from inputs to V+
Optimized quiescent current: 165-µA/ch typical
Rail-to-rail input and output
Gain bandwidth product: 3-MHz typical at 5.5 V
Thermal noise floor: 16-nV/√Hz typical
Unity-gain stable
Drives up to 250-pF without sustained oscillations
Internal RFI and EMI filtered input pins
Operating temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
•
Optical modules
Reference buffers, guard amplifiers
Microphone pre-amplifiers
Lighting and LED Drivers
4-20 mA loop drivers
Programmable current source
Low side current sensing circuitry
also be used as a reference buffer, guard amplifier, or
as a discrete LDO.
The robust design of the OPAx310 family simplifies
circuit design. These op amps feature an integrated
RFI and EMI rejection filter with no-phase reversal in
input overdrive conditions. These devices also deliver
excellent AC performance with a gain bandwidth of
3 MHz and can drive up to 250 pF of cap load
with no sustained oscillations, enabling designers
to achieve both improved performance and a lowerpower consumption.
Device Information
PART NUMBER(1)
OPA310
CHANNEL COUNT
Single
DBV (SOT-23, 5)
2.90 mm × 2.80 mm
DCK (SC70, 5)
2.1 mm × 1.25 mm
DPW (X2SON, 5)(2)
0.80 mm × 0.80 mm
DRL (SOT-5X3, 5)
OPA310S
OPA2310
Single, Shutdown
Dual
3 Description
The OPAx310 family of op amps includes single
(OPA310), dual (OPA2310), and quad-channel
(OPA4310), low-voltage (1.5 V to 5.5 V), high
output current operational amplifiers (op amps) with
rail-to-rail input and output swing capabilities. The
OPAx310S also features a very fast shutdown
response and has a typical enable time of 0.9-µs
that allows for power savings when the application
involves duty cycling the amplifier signal chain.
OPAx310 family has a robust ESD performance with
fail safe input ESD structure where there are no
diodes connected from inputs to the positive power
supply rail.
PACKAGE SIZE(3)
PACKAGE
OPA2310S
OPA4310
Dual, Shutdown
(2)
1.60 mm × 1.60 mm
DBV (SOT-23, 6)
2.90 mm × 2.80 mm
DCK (SC70, 6)
2.00 mm × 1.25 mm
D (SOIC, 8)
4.90 mm × 6.00 mm
DDF (SOT-23, 8)(2)
2.90 mm × 2.80 mm
DSG (WSON, 8)
2.00 mm × 2.00 mm
DGK (VSSOP, 8)
3.00 mm × 4.90 mm
PW (TSSOP, 8)(2)
3.00 mm × 6.40 mm
RUG (X2QFN, 10)
1.50 mm × 2.00 mm
DGQ (HVSSOP, 10)
Quad
(2)
3.00 mm × 4.90 mm
D (SOIC, 14)
8.65 mm × 6.00 mm
PW (TSSOP, 14)
5.00 mm × 6.40 mm
RUC (X2QFN, 14)(2) 2.00 mm × 2.00 mm
OPA4310S
Quad, Shutdown
RTE (WQFN, 16)
3.00 mm × 3.00 mm
DYY (SOT-23, 16)
4.20 mm × 2.00 mm
(2)
(1)
(2)
(3)
For all available packages, see the orderable addendum at
the end of the data sheet.
Package is for preview only.
The package size (length × width) is a nominal value and
includes pins, where applicable.
LED / EML
–
OPAx310 is offered in power pad, standard, small
size package variants and has an internal current limit
protection, thermal shutdown protection that enables
additional robustness when operating with high output
current. OPAx310 can swing very close to the rails
and has a short-circuit current of 75-mA minimum
across temperature at 5.5-V power supply. Additional
output current capability can be achieved by carefully
connecting multiple op amps in parallel. OPAx310
devices are an excellent choice for LED driver, LCD
driver, laser driver, TEC driver applications and can
DAC
+
OPA2310
GND
–
MCU
+
GND
LED / EML Biasing With Current Sense
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA310, OPA2310, OPA4310
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications................................................................ 11
7.1 Absolute Maximum Ratings...................................... 11
7.2 ESD Ratings .............................................................11
7.3 Recommended Operating Conditions....................... 11
7.4 Thermal Information for Single Channel................... 11
7.5 Thermal Information for Dual Channel......................12
7.6 Thermal Information for Quad Channel.................... 12
7.7 Electrical Characteristics...........................................13
7.8 Typical Characteristics.............................................. 17
8 Detailed Description......................................................27
8.1 Overview................................................................... 27
8.2 Functional Block Diagram......................................... 27
8.3 Feature Description...................................................28
8.4 Device Functional Modes..........................................32
9 Application and Implementation.................................. 33
9.1 Application Information............................................. 33
9.2 Typical Application.................................................... 33
9.3 Power Supply Recommendations.............................35
9.4 Layout....................................................................... 35
10 Device and Documentation Support..........................37
10.1 Documentation Support.......................................... 37
10.2 Receiving Notification of Documentation Updates..37
10.3 Support Resources................................................. 37
10.4 Electrostatic Discharge Caution..............................37
10.5 Glossary..................................................................37
11 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2022) to Revision F (June 2023)
Page
• Updated the Device Information table format to include channel count and package leads.............................. 1
• Updated the ESD ratings of OPA310 and OPA4310.........................................................................................11
Changes from Revision D (October 2022) to Revision E (December 2022)
Page
• Removed preview tag for the OPA2310S RUG and OPA4310 D, PW packages...............................................1
• Removed preview tag for the OPA2310S RTE and OPA4310 D, PW packages................................................4
• Added shutdown quiescent current for OPA2310S in the Specifications section............................................. 11
Changes from Revision C (September 2022) to Revision D (October 2022)
Page
• Changed OPA310 / OPA310S DBV, DCK packages from "Preview" to "Production".........................................1
• Removed preview tag for the OPA310 / OPA310S DBV, DCK packages...........................................................4
• Changed enable time max limit to 1.6-µs in Specifications section.................................................................. 11
Changes from Revision B (July 2022) to Revision C (September 2022)
Page
• Updated typical enable time to 0.9-µs................................................................................................................ 1
• Removed preview tag for the OPA310 DBV and OPA4310S RTE packages.....................................................1
• Deleted shutdown section is on preview foot note from the Specifications section.......................................... 11
Changes from Revision A (June 2022) to Revision B (July 2022)
Page
• Changed DGK from "Preview" to "Production"...................................................................................................1
• Updated Device Comparison section to include information about shutdown....................................................4
• Removed preview tag for the DGK package...................................................................................................... 4
• Added shutdown section is on preview foot note to the Specifications section................................................ 11
• Updated the ESD and Electrical Overstress section to show ESD structures on the shutdown pin.................31
2
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
Changes from Revision * (April 2022) to Revision A (June 2022)
Page
• Changed status from "Advance Information" to "Production Data".................................................................... 1
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
5 Device Comparison Table
DEVICE
NO. OF
CHANNELS
SC70
DCK
SOIC
D
SOT-23
DBV
SOT-23
DDF(1)
SOT-553
DRL(1)
SOT-23
DYY(1)
TSSOP
PW
VSSOP
DGK
HVSSOP
DGQ(1)
WQFN
RTE
WSON
DSG
X2QFN
RUC(1)
X2SON
DPW(1)
X2QFN
RUG
OPA310
1
NO
5
—
5
5
—
—
—
—
—
—
—
5
—
OPA310S
1
YES
6
—
6
—
—
—
—
—
—
—
—
—
—
OPA2310
2
NO
—
8
—
8
—
—
8
8
—
—
8
—
—
—
OPA2310S
2
YES
—
—
—
—
—
—
—
—
10
—
—
—
—
10
OPA4310
4
NO
—
14
—
—
—
—
14
—
—
—
—
14
—
—
OPA4310S
4
YES
—
—
—
—
—
16
—
—
—
16
—
—
—
—
(1)
4
PACKAGE LEADS
SHDN
Packages are preview only.
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
6 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
5
V+
4
OUT
Not to scale
Figure 6-1. OPA310 DBV Package,
5-Pin SOT-23
(Top View)
OUT
Figure 6-2. OPA310 DCK and DRL Package,
5-Pin SC70 and 5-Pin SOT-5X3
(Top View)
1
5
V+
4
IN+
3
V±
IN±
2
Not to scale
Figure 6-3. OPA310 DPW Package,
5-Pin X2SON
(Top View)
Table 6-1. Pin Functions: OPA310
PIN
(1)TYPE
DESCRIPTION
SOT-23
SC70,
SOT-5X3
X2SON
IN–
4
3
2
I
Inverting input
IN+
3
1
4
I
Noninverting input
OUT
1
4
1
O
Output
V–
2
2
3
I
Negative (low) supply or ground (for single-supply
operation)
V+
5
5
5
I
Positive (high) supply
NAME
(1)
I = input, O = output
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
OUT
1
6
V+
V±
2
5
SHDN
IN+
3
4
IN±
IN+
1
6
V+
V±
2
5
SHDN
IN±
3
4
OUT
Not to scale
Not to scale
Figure 6-5. OPA310S DCK Package,
6-Pin SC70
(Top View)
Figure 6-4. OPA310S DBV Package,
6-Pin SOT-23
(Top View)
Table 6-2. Pin Functions: OPA310S
PIN
NAME
SOT-23
SC70
IN–
4
3
IN+
3
OUT
1
SHDN
DESCRIPTION
I
Inverting input
1
I
Noninverting input
4
O
Output
5
5
I
Shutdown: low = amp disabled, high = amp enabled
See Shutdown Function for more information
V–
2
2
I
Negative (low) supply or ground (for single-supply operation)
V+
6
6
I
Positive (high) supply
(1)
6
(1)TYPE
I = input, O = output
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OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Figure 6-6. OPA2310 D, DDF, DGK, and PW
Package,
8-Pin SOIC, SOT-23-THIN, VSSOP, and TSSOP
(Top View)
Not to scale
Connect exposed thermal pad to V–. See Section 8.3.10 for
more information.
Figure 6-7. OPA2310 DSG Package,
8-Pin WSON with Exposed Thermal Pad
(Top View)
Table 6-3. Pin Functions: OPA2310
PIN
NAME
NO.
(1)TYPE
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
I
Negative (low) supply or ground (for single-supply operation)
V+
8
I
Positive (high) supply
(1)
I = input, O = output
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IN1+
SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
1
9
SHDN1
IN2+
V+
3
Thermal
9
OUT2
8
IN2+
V–
4
7
IN2–
SHDN1
5
6
SHDN2
OUT1
7
4
2
10
Pad
8
3
IN1–
IN1+
V+
Not to scale
Figure 6-9. OPA2310S DGQ Package,
10-Pin HVSSOP
(Top View)
5
SHDN2
2
1
IN1±
10
V±
OUT1
6
OUT2
IN2±
Not to scale
Figure 6-8. OPA2310S RUG Package,
10-Pin X2QFN
(Top View)
Table 6-4. Pin Functions: OPA2310S
PIN
NAME
HVSSOP
(1)TYPE
DESCRIPTION
IN1–
9
2
I
Inverting input, channel 1
IN1+
10
3
I
Noninverting input, channel 1
IN2–
5
7
I
Inverting input, channel 2
IN2+
4
8
I
Noninverting input, channel 2
OUT1
8
1
O
Output, channel 1
OUT2
6
9
O
Output, channel 2
SHDN1
2
5
I
Shutdown: low = amp disabled, high = amp enabled, channel 1
See Shutdown Function for more information
SHDN2
3
6
I
Shutdown: low = amp disabled, high = amp enabled, channel 2
See Shutdown Function for more information
V–
1
4
I
Negative (low) supply or ground (for single-supply operation)
V+
7
10
I
Positive (high) supply
(1)
8
X2QFN
I = input, O = output
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2
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
IN1±
1
IN1+
2
V+
OUT4
IN1±
12
IN4±
11
IN4+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
13
OUT4
7
14
14
1
6
OUT1
OUT1
SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
OUT3
OUT2
Not to scale
Figure 6-10. OPA4310 D and PW Package,
14-Pin SOIC and TSSOP
(Top View)
Not to scale
Figure 6-11. OPA4310 RUC Package,
14-Pin X2QFN
(Top View)
Table 6-5. Pin Functions: OPA4310
PIN
NAME
SOIC, TSSOP X2QFN
(1)TYPE
DESCRIPTION
IN1–
2
1
I
Inverting input, channel 1
IN1+
3
2
I
Noninverting input, channel 1
IN2–
6
5
I
Inverting input, channel 2
IN2+
5
4
I
Noninverting input, channel 2
IN3–
9
8
I
Inverting input, channel 3
IN3+
10
9
I
Noninverting input, channel 3
IN4–
13
12
I
Inverting input, channel 4
IN4+
12
11
I
Noninverting input, channel 4
OUT1
1
14
O
Output, channel 1
OUT2
7
6
O
Output, channel 2
OUT3
8
7
O
Output, channel 3
OUT4
14
13
O
Output, channel 4
V–
11
10
I
Negative (low) supply or ground (for single-supply operation)
V+
4
3
I
Positive (high) supply
(1)
I = input, O = output
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IN1+
1
V+
2
IN4±
OUT1
1
16
OUT4
IN1–
2
15
IN4–
IN1+
3
14
IN4+
V+
4
13
V–
IN2+
5
12
IN3+
IN2–
6
11
IN3–
OUT2
7
10
OUT3
SHDN12
8
9
13
OUT4
14
OUT1
15
16
IN1±
SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
8
4
7
IN2±
Pad
6
3
5
IN2+
SHDN34
A.
OUT3
SHDN34
SHDN12
OUT2
Not to scale
A.
Connect thermal pad to V–.
Not to scale
Connect thermal pad to V–.
Figure 6-13. OPA4310S DYY Package,
16-Pin SOT-23-THIN
(Top View)
Figure 6-12. OPA4310S RTE Package,
16-Pin WQFN With Exposed Thermal Pad
(Top View)
Table 6-6. Pin Functions: OPA4310S
PIN
NAME
WQFN
SOT-23THIN
(1)TYPE
DESCRIPTION
IN1+
1
3
I
Noninverting input, channel 1
IN1–
16
2
I
Inverting input, channel 1
IN2+
3
5
I
Noninverting input, channel 2
IN2–
4
6
I
Inverting input, channel 2
IN3+
10
12
I
Noninverting input, channel 3
IN3–
9
11
I
Inverting input, channel 3
IN4+
12
14
I
Noninverting input, channel 4
IN4–
13
15
I
Inverting input, channel 4
SHDN12
6
8
I
Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2.
See Shutdown Function for more information
SHDN34
7
9
I
Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4.
See Shutdown Function for more information
OUT1
15
1
O
Output, channel 1
OUT2
5
7
O
Output, channel 2
OUT3
8
10
O
Output, channel 3
OUT4
14
16
O
Output, channel 4
V–
11
13
I
Negative (low) supply or ground (for single-supply operation)
V+
2
4
I
Positive (high) supply
10
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
7
V
6.0
V
Supply voltage, VS = (V+) – (V–) Supply voltage, VS = (V+) – (V–)
Common-mode voltage
(2) (3)
– 0.5
Differential voltage (2) (3)
Signal input pins
±6.0
Current (3)
–10
Output short-circuit (4)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
(4)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Input pins can swing beyond (V+) as long as they stay with in 6.0 V. No diode structure from input pins to (V+).
Input pins are diode-clamped to (V–). Input signals that 0.3 V below (V–) must be current-limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
PART NUMBER
OPA2310
OPA2310
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
(2)
VALUE
UNIT
±4000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JS-002
±1500
V
OPA310, OPA4310 V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
V
OPA310, OPA4310 V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JS-002 (2)
±1500
V
(1)
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
VS
Supply voltage, (V+) – (V–)
VI
Input voltage range
TA
Specified temperature
MIN
MAX
1.5
5.5
UNIT
V
– 0.1
5.6
V
–40
125
°C
7.4 Thermal Information for Single Channel
OPA310
THERMAL METRIC (1)
OPA310S
DBV
(SOT-23)
DCK
(SC70)
DPW (2)
(X2SON)
DRL (2)
(X2SON)
DBV
(SOT-23)
DCK
(SC70)
UNIT
5 PINS
5 PINS
5 PINS
5 PINS
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
211.5
214.6
TBD
TBD
190.7
195.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
109.4
110.0
TBD
TBD
110.5
122.9
°C/W
RθJB
Junction-to-board thermal resistance
77.8
60.7
TBD
TBD
70.8
55.5
°C/W
ψJT
Junction-to-top characterization parameter
45.2
32.1
TBD
TBD
47.4
38.3
°C/W
ψJB
Junction-to-board characterization parameter
77.5
60.4
TBD
TBD
70.5
55.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
TBD
TBD
n/a
n/a
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.5 Thermal Information for Dual Channel
OPA2310
THERMAL METRIC (1)
OPA2310S
DSG
(WSON)
D
(SOIC)
DDF (2)
(SOT-23-8)
DGK
(VSSOP)
PW (2)
(TSSOP)
DGQ (2)
(HVSSOP)
RUG
(X2QFN)
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
90.1
139.0
TBD
187.7
TBD
TBD
179.4
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
112.1
81.2
TBD
78.1
TBD
TBD
66.7
°C/W
RθJB
Junction-to-board thermal
resistance
56.3
82.4
TBD
109.5
TBD
TBD
104.5
°C/W
ψJT
Junction-to-top
characterization parameter
9.2
31.3
TBD
17.9
TBD
TBD
1.4
°C/W
ψJB
Junction-to-board
characterization parameter
56.3
81.6
TBD
107.9
TBD
TBD
104.2
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
31.8
N/A
TBD
N/A
TBD
TBD
n/a
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.6 Thermal Information for Quad Channel
OPA4310
THERMAL METRIC (1)
OPA4310S
RUC (2)
(X2QFN)
D
(SOIC)
PW
(TSSOP)
RTE
(WQFN)
DYY (2)
(SOT)
UNIT
14 PINS
14 PINS
14 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
101.5
128.2
57.6
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
TBD
57.8
58.7
62.4
TBD
°C/W
RθJB
Junction-to-board thermal resistance
TBD
58.0
71.4
32.9
TBD
°C/W
ψJT
Junction-to-top characterization parameter
TBD
20.9
13.0
3.4
TBD
°C/W
ψJB
Junction-to-board characterization
parameter
TBD
57.6
70.8
32.9
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
TBD
n/a
n/a
16.6
TBD
°C/W
(1)
(2)
12
For more information about traditional and new thermal metrics, see the, Semiconductor and IC Package Thermal Metrics application
report.
This package option is on preview.
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.7 Electrical Characteristics
For VS = (V+) – (V–) = 1.5 V to 5.5 V (±0.75 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.25
±1.3
UNIT
OFFSET VOLTAGE
VOS
Input offset
voltage
dVOS/dT
PSRR
VCM = V–
VCM = V–
TA = –40°C to 125°C
±1.4
Input offset
voltage drift
VCM = V–
TA = –40°C to 125°C
Input offset
voltage versus
power supply
VS = 1.5 V to 5.5 V , VCM = V–
Channel
separation
f = 10 kHz
±1
±0.5
±10
mV
µV/℃
±50
µV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias
current (1)
VS = 1.8 V and VS = 5 V
±1
±30
pA
IOS
Input offset
current (1)
VS = 1.8 V and VS = 5 V
±0.5
±25
pA
EN
Input voltage
noise
f = 0.1 to 10 Hz
eN
Input voltage
noise density
iN
Input current
noise (3)
NOISE
4
f = 100 Hz
32
f = 1 kHz
16
f = 10 kHz
13
f = 1 kHz
10
μVPP
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode
VS = 1.8 V
voltage range (1)
TA = –40°C to 125°C
(V–)
(V+)
V
Common-mode
VS = 5.5 V
voltage range (1)
TA = –40°C to 125°C
(V–) – 0.1
(V+) + 0.1
V
VS = 1.8 V, (V–) ≤ VCM ≤ (V+) – 0.6 V
VS = 1.8 V, (V–) ≤ VCM ≤ (V+) – 0.6 V
CMRR
Common-mode
rejection ratio
TA = –40°C to 125°C
VS = 5.5 V, (V–) ≤ VCM ≤ (V+) – 0.6 V
75
85
dB
65
78
dB
83
95
dB
VS = 5.5 V, (V–) ≤ VCM ≤ (V+) – 0.6 V
TA = –40°C to 125°C
75
85
Full Range: VS = 1.8 V, (V–) ≤ VCM ≤ (V+)
TA = –40°C to 125°C
57.5
70
Full Range: VS = 5.5 V
(V–) – 0.1 V ≤ VCM ≤ (V+) + 0.1 V
TA = –40°C to 125°C
66.5
80
dB
INPUT IMPEDANCE
ZID
Differential
Input
Impedance
ZICM
Common-mode
Input
Impedance
80 || 1.4
GΩ || pF
100 || 0.5
GΩ || pF
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.5 V to 5.5 V (±0.75 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS = 1.8 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ to VS / 2
102
115
dB
VS = 1.8 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 2 kΩ to VS / 2
95
105
dB
VS = 5.5 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 10 kΩ to VS / 2
109
125
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ to VS / 2
105
115
dB
VS = 1.8 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ to VS / 2
90
100
OPEN-LOOP GAIN
Open-loop
voltage gain
Open-loop
voltage gain(2)
AOL
Open-loop
voltage gain
VS = 1.8 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 2 kΩ to VS / 2
VS = 5.5 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 10 kΩ to VS / 2
90
TA = –40°C to 125°C
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ to VS / 2
Open-loop
voltage gain (6)
VS = 3.3 V, (V–) + 0.25 V < VO < (V+) – 0.25 V,
IL = ±50 mA
dB
105
TA = 25°C
90
100
80
102
dB
2.5
MHz
FREQUENCY RESPONSE
Gain-bandwidth
product
GBW
SR
Slew rate
VS = 1.8 V, G = +1, RL = 10 kΩ, CL = 100 pF
VS = 5.5 V, G = +1, RL = 10 kΩ, CL = 100 pF
3
MHz
VS = 1.8 V, G = +1, RL = 10 kΩ
2.8
V/μs
VS = 5.5 V, G = +1, RL = 10 kΩ
3
V/μs
G = +1, VO = 1 VRMS, f = 1 kHz,
RL = 10 kΩ to VS / 2
THD+N
0.0005
%
Total harmonic
G = +1, VO = 1 VRMS, f = 1 kHz,
distortion + noise
RL = 2 kΩ to VS / 2
(4)
0.0035
%
G = +1, VO = 1 VRMS, f = 1 kHz,
RL = 600 Ω to VS / 2
0.0080
%
tS
Settling time
PM
Phase margin
To 0.1%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF
1.8
To 0.1%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF
1.3
To 0.01%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF
2.3
To 0.01%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF
1.6
G = +1, RL = 10 kΩ connected to VS/2, CL = 10 pF
60
°
G = +1, RL = 10 kΩ connected to VS/2, Phase Margin = 40°
75
pF
G = +1, RL = 10 kΩ connected to VS/2,
No Sustained Oscillations
250
pF
VIN × gain > VS
0.6
μs
75
dB
CL Drive
Cap Load Drive
toverload
Overload
recovery time
EMIRR
Electro-magnetic
interference
f = 1.8 GHz, VIN_EMIRR = 100 mV
rejection ratio
14
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.5 V to 5.5 V (±0.75 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VS = 1.8 V, RL = 2 kΩ to VS / 2
10
21
VS = 1.8 V, RL = 10 kΩ to VS / 2
2
UNIT
OUTPUT
VOH
Voltage output
swing from
positive rail
VS = 1.8 V, RL = 2 kΩ to VS / 2
TA = –40°C to 125°C
VS = 1.8 V, RL = 10 kΩ to VS / 2
TA = –40°C to 125°C
26
VS = 5.5 V, RL = 2 kΩ to VS / 2
3.5
VS = 5.5 V, RL = 10 kΩ to VS / 2
VOL
Voltage output
swing from
negative rail
0.75
VS = 5.5 V, RL = 2 kΩ to VS / 2
TA = –40°C to 125°C
VS = 5.5 V, RL = 10 kΩ to VS / 2
TA = –40°C to 125°C
20
9
30
14
VS = 1.8 V, RL = 2 kΩ to VS / 2
5.5
15
VS = 1.8 V, RL = 10 kΩ to VS / 2
1.2
10
VS = 1.8 V, RL = 2 kΩ to VS / 2
TA = –40°C to 125°C
VS = 1.8 V, RL = 10 kΩ to VS / 2
TA = –40°C to 125°C
25
VS = 5.5 V, RL = 2 kΩ to VS / 2
3.5
0.75
17.5
10
VS = 5.5 V, RL = 2 kΩ to VS / 2
TA = –40°C to 125°C
27.5
VS = 5.5 V, RL = 10 kΩ to VS / 2
TA = –40°C to 125°C
11
Short-circuit
current (5)
VS = 1.8 V
Short-circuit
current (2) (5)
VS = 1.8 V, TA = –40℃ to 125℃
Short-circuit
current (5)
VS = 5.5 V, OPA2310
ISC
Short-circuit
current (5)
VS = 5.5 V, OPA310 and OPA4310
ZO
Open-loop
output
impedance
f = 10 kHz
mV
45
VS = 5.5 V, RL = 10 kΩ to VS / 2
ISC
11
51
±20
mA
±6
±75
mA
±150
mA
±110
mA
1000
Ω
POWER SUPPLY
VS = 1.5 V, IO = 0 A, SHDN = V+ for shutdown
devices
IQ
Quiescent
current per
amplifier
Power-on time
VS = 1.5 V, IO = 0 A, SHDN = V+ for shutdown
devices
TA = –40°C to 125°C
VS = 5.5 V, IO = 0 A, SHDN = V+ for shutdown
devices
TA = –40°C to 125°C
At TA = 25°C, VS = 5.5 V, VS ramp rate > 0.3 V/µs
165
190
µA
165
210
µA
165
200
215
125
µA
μs
SHUTDOWN
IQ_SHDN
Shutdown
current per
amplifier
IQ_SHDN
Shutdown
current per
amplifier
IQ_SHDN
Shutdown
current per
amplifier (1)
IQ_SHDN
Shutdown
current per
amplifier (1)
Output
ZOUT_SHDN impedance
during
shutdown
All amplifiers disabled, SHDN = V–, OPA4310S
0.100
0.150
µA
All amplifiers disabled, SHDN = V–, OPA310S
0.265
0.475
µA
All amplifiers disabled, SHDN = V–, OPA2310S
0.200
0.375
µA
All amplifiers disabled, SHDN = V–, TA = –40℃ to 85℃, OPA4310S
0.300
µA
All amplifiers disabled, SHDN = V–, TA = –40℃ to 85℃, OPA310S
0.700
µA
All amplifiers disabled, SHDN = V–, TA = –40℃ to 85℃, OPA2310S
0.600
µA
Amplifier disabled
43 || 11.5
GΩ || pF
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.5 V to 5.5 V (±0.75 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
VSHDN_IH
Logic high
threshold
voltage
(amplifier
enabled)
VSHDN_IL
Logic low
threshold
voltage
(amplifier
disabled)
tON
Amplifier enable
time (full
shutdown) (7) (1)
G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–
1
tOFF
Amplifier disable
G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V–
time (7)
1
IB_SHDN
SHDN pin input (V+) ≥ SHDN ≥ (V–) + 1 V
bias current (per
(V–) ≤ SHDN ≤ (V–) + 0.2 V
pin)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
16
MAX
(V–) + 1.2
UNIT
V
(V–) + 0.2
V
1.6
µs
µs
50
100
nA
Max data is specified based on characterization results.
Min data is specified based on characterization results.
Typical input current noise data is specified based on design simulation results.
Third-order filter; bandwidth = 80 kHz at –3 dB.
Short circuit current specified here is the average of sourcing and sinking short circuit currents.
AOL is measured as the difference between (VOSA – VOSB) / (VOUTA – VOUTB). VOSA is the offset measured when the OUT pin is biased
at (V+) - 0.25 V while the device sources 50 mA and VOSB is the offset measured when the OUT pin is biased at (V–) + 0.25 V while
the device sinks 50 mA.
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.8 Typical Characteristics
18
24
16
21
14
18
12
8
H01_
VCM = VS / 2
Mean = –36 µV
TA = 25°C
Sigma = 215 µV
1.5
1.4
1.2
1
1.1
0.9
0.8
0.7
1.3
H02_
Input Offset Voltage Drift (µV/°C)
Input Offset Voltage (µV)
VS = 5.5 V
No. of devices = 70
0.6
0
600
500
400
300
200
0
100
-100
-200
-300
0
-400
2
0
-500
4
3
0.5
6
6
0.4
9
10
0.3
12
0.2
15
0.1
Amplifiers (%)
27
-600
Amplifiers (%)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
VS = 5.5 V
VCM = VS / 2
TA = –40°C to +125°C
No. of devices = 70
Mean = 0.5 µV/°C
Sigma = 0.3 µV/°C
Figure 7-1. Offset Voltage Distribution Histogram
30
24
27
21
24
21
Amplifiers (%)
18
15
12
9
18
15
12
H03_
VCM = VS / 2
Mean = 0.6 pA
TA = 25°C
Sigma = 1.2 pA
Figure 7-3. Input Bias Current Distribution Histogram
VS = 5.5 V
No. of devices = 140
9.5
9
8
8.5
7.5
7
6.5
6
5.5
5
VCM = VS / 2
Mean = 4.6 pA
H04_
TA = 85°C
Sigma = 1.3 pA
Figure 7-4. Input Bias Current Distribution Histogram
27
16
24
14
21
12
18
Amplifiers (%)
Amplifiers (%)
4.5
Input Bias Current (pA)
Input Bias Current (pA)
VS = 5.5 V
No. of devices = 140
4
3.5
3
2.5
1.5
6
5.5
5
4.5
4
3
3.5
2.5
1.5
2
1
0
0.5
-0.5
-1
0
-1.5
3
0
-2
6
3
2
9
6
-2.5
Amplifiers (%)
Figure 7-2. Offset Voltage Drift Distribution Histogram
27
15
12
9
10
8
6
4
6
Input Offset Current (pA)
VS = 5.5 V
No. of devices = 140
VCM = VS / 2
Mean = 0.2 pA
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-1
-0.5
0
-1.5
0
-2
2
-2.5
3
H05_
TA = 25°C
Sigma = 1.5 pA
Figure 7-5. Input Offset Current Distribution Histogram
Input Offset Current (pA)
VS = 5.5 V
No. of devices = 70
VCM = VS / 2
Mean = 0.3 pA
H06_
TA = 85°C
Sigma = 1.6 pA
Figure 7-6. Input Offset Current Distribution Histogram
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.8 Typical Characteristics (continued)
800
1800
600
1400
1000
Input Offset Voltage (µV)
Input Offset Voltage (µV)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
400
200
0
-200
-400
600
200
-200
-600
-1000
-600
-1400
-800
-40
-20
0
20
40
60
80
Temperature (°C)
VS = 5.5 V, VCM = V–
100
120
-1800
-40
140
No. of devices = 72
20
40
60
80
Temperature (°C)
100
120
140
D05_
No. of devices = 72
Figure 7-8. Input Offset Voltage vs Temperature
1600
800
1200
600
Input Offset Voltage (µV)
Input Offset Voltage (µV)
0
VS = 5.5 V, VCM = V+
Figure 7-7. Input Offset Voltage vs Temperature
800
400
0
-400
-800
-1200
400
200
0
-200
-400
-600
-1600
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5
Input Common-Mode Voltage (V)
2
2.5
-800
-3
3
-2.2
D07_
V+ = 2.75 V, V– = –2.75 V
No. of devices = 72
-1.4
-0.6
0.2
1
Input Common-Mode Voltage (V)
1.8
D08_
V+ = 2.75 V, V– = –2.75 V, (V–) < VCM < (V+) – 0.6 V
No. of devices = 72
Figure 7-9. Offset Voltage vs Common-Mode
Figure 7-10. Offset Voltage vs Common-Mode
1400
1000
1000
600
Input Offset Voltage (µV)
Input Offset Voltage (µV)
-20
D06_
200
-200
-600
600
200
-200
-600
-1000
-1000
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Input Common-Mode Voltage (V)
2.8
V+ = 2.75 V, V– = –2.75 V, VCM > (V+) – 0.6 V
No. of devices = 72
Figure 7-11. Offset Voltage vs Common-Mode
18
2.9
D09_
-1400
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
VCM = (V–)
4.5
5
5.5
D09_
No. of devices = 72
Figure 7-12. Offset Voltage vs Supply Voltage
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SBOSAA1F – APRIL 2022 – REVISED JUNE 2023
7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
10
IBIB+
30
20
Input Offset Current (pA)
10
7
5
3
2
1
0.7
0.5
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
8
7
6
5
4
3
2
1
-40
140
-20
0
20
D13_
VS = 5.5 V, VCM = VS/2
IBIB+
Input Offset Current (pA)
Input Bias Current (pA)
10
5
0
-5
-0.75
0.25
1.25
Input Common-Mode Voltage (V)
2.25
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
-1.5
-1.8
-2.1
-2.75
140
D14_
IOS
-1.75
D15_
-0.75
0.25
1.25
Input Common-Mode Voltage (V)
2.25
D16_
V+ = 2.75 V, V– = –2.75 V, VCM = VS/2
V+ = 2.75 V, V– = –2.75 V, VCM = VS/2
Figure 7-16. IOS vs Common-Mode Voltage
Figure 7-15. IB vs Common-Mode Voltage
160
90
150
140
75
120
60
90
45
60
30
30
15
0
120
100
Gain (dB)
Open-Loop Gain (dB)
120
Figure 7-14. IOS vs Temperature
15
-1.75
100
VS = 5.5 V, VCM = VS/2
Figure 7-13. IB vs Temperature
-10
-2.75
40
60
80
Temperature (°C)
80
60
40
0
-30
-15
-60
-30
20
VS = 5.5 V
VS = 1.5 V
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
RL = 10 kΩ
-45
100
Gain
Phase
Phase (degree)
Input Bias Current (pA)
100
70
50
-90
-120
1k
140
10k
100k
Frequency (Hz)
1M
10M
D003
CL = 10 pF
D18_
Figure 7-18. Open-Loop Gain and Phase vs Frequency
Figure 7-17. Open-Loop Gain vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
50
1800
G = -1
G=1
G = 10
G = 100
40
1600
30
1400
Gain (dB)
Open-Loop Output Impedance (:)
2000
1200
1000
20
10
800
0
600
-10
400
200
-20
100
0
10k
100k
1M
Frequency (Hz)
10k
100k
Frequency (Hz)
1M
10M
D017
CL = 10 pF
D008
Figure 7-19. Open-Loop Output Impedance vs Frequency
Figure 7-20. Closed-Loop Gain vs Frequency
2.8
-2.2
-40°C
25°C
85°C
125°C
-2.3
Output Voltage (V)
2.7
Output Voltage (V)
1k
10M
2.6
2.5
2.4
2.3
-2.4
-2.5
-2.6
-40°C
25°C
85°C
125°C
-2.7
2.2
-2.8
0
20
40
60
80
100 120
Output Current (mA)
140
160
180
0
40
80
D32_
V+ = 2.75 V, V– = –2.75 V
120
160
Output Current (mA)
200
240
270
D33_
V+ = 2.75 V, V– = –2.75 V
Figure 7-21. Output Voltage Swing vs Output Current (Sourcing)
Figure 7-22. Output Voltage Swing vs Output Current (Sinking)
1.1
0.2
-40°C
25°C
125°C
0.9
0
Output Voltage (V)
Output Voltage (V)
0.7
0.5
0.3
0.1
-0.2
-0.4
-0.6
-0.1
-40°C
25°C
125°C
-0.8
-0.3
-0.5
-1
0
2
4
6
8 10 12 14 16
Output Current (mA)
18
20
22
24
0
2
4
6
D34_
V+ = 0.9 V, V– = –0.9 V
Figure 7-23. Output Voltage Swing vs Output Current (Sourcing)
20
8
10 12 14 16 18 20 22 24 26 28
Output Current (mA)
D35_
V+ = 0.9 V, V– = –0.9 V
Figure 7-24. Output Voltage Swing vs Output Current (Sinking)
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
55
90
50
Power-Supply Rejection Ratio (µV/V)
100
80
PSRR (dB)
70
60
50
40
30
20
10
0
100
PSRR - (dB)
PSRR+ (dB)
1k
10k
100k
Frequency (Hz)
1M
45
40
35
30
25
20
15
10
5
0
-40
10M
-20
0
20
40
60
80 100
Temperature (°C)
D010
Figure 7-25. PSRR vs Frequency
120
140
160
D11_
VS = 1.5 V to 5.5 V
Figure 7-26. DC PSRR vs Temperature
110
140
Common-Mode Rejection Ratio (dB)
CMRR (dB)
CMRR (dB)
90
70
50
30
10
1k
10k
100k
Frequency (Hz)
1M
120
100
80
60
40
20
0
-40
10M
-20
0
D010
Figure 7-27. CMRR vs Frequency
20
40
60
80
Temperature (°C)
100
120
140
D12_
VS = 5.5 V, (V–) < VCM < (V+) – 0.6 V
Input Voltage Noise Spectral Density (nV/rtHz)
Figure 7-28. DC CMRR vs Temperature
3
Amplitude (1 PV/div)
2
1
0
-1
-2
Time (1 s/div)
100
80
70
60
50
40
30
20
10
10
100
D14_
Figure 7-29. 0.1-Hz to 10-Hz Voltage Noise in Time Domain
1k
Frequency (Hz)
10k
100k
D007
Figure 7-30. Input Voltage Noise Spectral Density
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
-60
-40
RL = 2 k:
RL = 10 k:
RL = 100 k:
-50
THD+N (dB)
THD+N (dB)
-70
-80
-90
-100
-60
-70
-80
-110
-90
100
VS = 5.5 V
BW = 80 kHz
1k
Frequency (Hz)
10k
100
VCM = 2.5 V
VOUT = 0.5 VRMS
G=1
VS = 5.5 V
BW = 80 kHz
Figure 7-31. THD + N vs Frequency
G = –1
-30
-30
-45
-45
-60
-75
-60
-75
-90
-90
-105
-105
10m
VS = 5.5 V
G=1
100m
Amplitude(VRMS)
RL = 2 k:
RL = 10 k:
RL = 100 k:
-15
THD+N (dB)
THD+N (dB)
D030
VCM = 2.5 V
VOUT = 0.5 VRMS
Figure 7-32. THD + N vs Frequency
RL = 2 k:
RL = 10 k:
RL = 100 k:
-120
1m
-120
1m
1
10m
D031
VCM = 2.5 V
BW = 80 kHz
f = 1 kHz
VS = 5.5 V
G = –1
Figure 7-33. THD + N vs Amplitude
100m
Amplitude(VRMS)
VCM = 2.5 V
BW = 80 kHz
1
D031
f = 1 kHz
Figure 7-34. THD + N vs Amplitude
180
180
170
170
Quiescent Current (µA)
Quiescent Current (µA)
10k
0
-15
160
150
140
130
160
150
140
130
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
VCM = VS/2
5.5
D38_
120
-2.75
-1.75
-0.75
0.25
1.25
Input Common-Mode Voltage (V)
2.25
D39_
V+ = 2.75 V, V– = –2.75 V
Figure 7-35. Quiescent Current vs Supply Voltage
22
1k
Frequency (Hz)
D030
0
120
1.5
RL = 2 k:
RL = 10 k:
RL = 100 k:
Figure 7-36. Quiescent Current vs Common-Mode Voltage
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
180
60
170
50
Overshoot (%)
Quiescent Current (µA)
160
150
140
130
40
30
20
120
RISO = 0 :, Overshoot (+)
RISO = 0 :, Overshoot (-)
RISO = 50 :, Overshoot (+)
RISO = 50 :, Overshoot (-)
10
110
VS = 1.5 V
VS = 5.5 V
100
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
0
0
140
50
100
150
Capacitive Load (pF)
D40_
G = –1
VCM = VS/2
200
250
D010
VIN = 100 mVpp
Figure 7-38. Small Signal Overshoot vs Capacitive Load
Figure 7-37. Quiescent Current vs Temperature
60
57
54
51
Phase Margin (°)
Overshoot (%)
50
40
30
20
45
42
39
36
33
RISO = 0 :, Overshoot (+)
RISO = 0 :, Overshoot (-)
RISO = 50 :, Overshoot (+)
RISO = 50 :, Overshoot (-)
10
48
30
27
20
40
60
0
0
50
G=1
100
150
Capacitive Load (pF)
200
250
80
100 120 140 160 180 200 220 240
Capacitive Load (pF)
D004
Figure 7-40. Phase Margin vs Capacitive Load
D023
VIN = 100 mVpp
Figure 7-39. Small Signal Overshoot vs Capacitive Load
3
4
VIN
VOUT
3
2
Input
Output
Amplitude (1 V/div)
Amplitude (V)
2
1
0
-1
1
0
-1
-2
-2
-3
-4
-3
Time (40 µs/div)
Time (1 Ps/div)
D22_
D021
G=1
VIN = 6 VPP
G = –10
Figure 7-41. No Phase Reversal
VIN = 600 mVPP
Figure 7-42. Overload Recovery
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
3
10
Input
Output
Input
Output
2
Amplitude (mV)
Amplitude ( 1V/div)
5
1
0
-1
0
-5
-2
-10
-3
Time (20 µs/div)
Time (1 Ps/div)
D22_
G = –10
D025
G=1
VIN = 600 mVPP
VIN = 10 mVPP
CL = 10 pF
Figure 7-44. Small-Signal Step Response
Figure 7-43. Overload Recovery
10
3
Input
Output
Input
Output
2
Amplitude (V)
Amplitude (mV)
5
0
1
0
-1
-5
-2
-10
-3
Time (20 µs/div)
Time (20 µs/div)
D026
G = –1
VIN = 10 mVPP
D027
CL = 10 pF
G=1
Output delta from final value (15 mv/div)
Time (0.25 Ps/div)
D12_
G=1
VIN = 4 VPP
CL = 10 pF
Figure 7-46. Large-Signal Step Response
Output delta from final value (10 mV/div)
Figure 7-45. Small-Signal Step Response
VIN = 4 VPP
Time (0.25 Ps/div)
CL = 10 pF
Figure 7-47. Large-Signal Settling Time (Negative)
D029
G=1
VIN = 4 VPP
CL = 10 pF
Figure 7-48. Large-Signal Settling Time (Positive)
24
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
4
6
Input
Output
3
VS = 5.5 V
VS = 1.8 V
5
4
1
Output (V)
Amplitude (V)
2
0
-1
3
2
-2
1
-3
0
-4
1
10
100
Time (20 µs/div)
VIN = 4 VPP
1M
10M
100M
D036
Figure 7-50. Maximum Output Voltage vs Frequency
D028
G = –1
1k
10k
100k
Frequency (Hz)
CL = 10 pF
Figure 7-49. Large-Signal Step Response
500
SHDN Quiescent Current (nA)
Short-Circuit Current (mA)
200
100
0
-100
-200
Sinking
Sourcing
-300
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
200
100
1
D37_
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
D44_
Figure 7-52. Shutdown Mode Quiescent Current vs Supply
Voltage
Figure 7-51. Short-Circuit Current vs Temperature
3
1200
VS = 1.5 V
VS = 5.5 V
2.5
2
Shutdown Voltage (V)
Output Voltage (V)
1.5
400
Amplitude (V)
SHDN Quiescent Current (nA)
300
0
140
VS = 5.5 V
800
400
0
-400
1
0.5
0
-0.5
-1
-1.5
-800
-2
-2.5
-1200
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
-3
Time (2 µs/div)
D45_
Figure 7-53. Shutdown Mode Quiescent Current vs Temperature
D50_
V+ = 2.75 V, V– = –2.75 V
Figure 7-54. Amplifier Enable Response
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
3
120
Shutdown Voltage
Output Voltage
2.5
2
110
100
90
1
EMIRR (dB)
Amplitude (V)
1.5
0.5
0
-0.5
-1
80
70
60
50
-1.5
40
-2
30
-2.5
-3
20
10M
Time (2 µs/div)
100M
Frequency (Hz)
D51_
V+ = 2.75 V, V– = –2.75 V
Figure 7-55. Amplifier Disable Response
1G
D42_
Figure 7-56. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
-80
-90
Crosstalk (dB)
-100
-110
-120
-130
-140
-150
-160
100
1k
10k
100k
Frequency (Hz)
1M
10M
D42_
Figure 7-57. Channel Separation
26
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8 Detailed Description
8.1 Overview
The OPAx310 family of op amps includes single (OPA310), dual (OPA2310), and quad-channel (OPA4310),
ultra-low-voltage (1.5 V to 5.5 V), high output current operational amplifiers (op amps) with rail-to-rail input and
output swing capabilities. The OPAx310 also features a very fast shutdown response and has an enable time
specification of just 0.9-µs typical. This feature allows for power savings when the application involves duty
cycling the amplifier signal chain. OPAx310 has robust ESD performance with fail safe input ESD structure
where there are no diodes connected from inputs to the positive power supply rail.
OPAx310 is offered in power pad, standard, small size packages and has an internal current limit, thermal
shutdown protection that enables additional robustness when operating with high output current. OPAx310 can
swing very close to the rails and has a short circuit current of ±75-mA minimum across temperature at 5.5-V
power supply while consuming just 165 μA of quiescent current. This combination of low voltage, low IQ, and
high output current capability makes this device quite unique and an excellent choice for a wide range of
general-purpose and high current applications. Additional output current capability can be easily achieved by
connecting multiple op amps in parallel. These devices are excellent choice for LED driver, LCD driver, Laser
driver, TEC driver applications and can also be used as a reference buffer, guard amplifier or as a discrete LDO.
The input common-mode voltage range includes both rails, and allows the OPAx310 series to be used in many
single-supply or dual supply configurations. Rail-to-rail input and output swing significantly increases dynamic
range, especially in low-supply applications, and makes these devices an excellent choice for driving low speed
sampling analog-to-digital converters (ADCs). Further, the class AB output stage is capable of driving smaller
resistive loads connected to any point between V+ and ground.
The OPAx310 can drive up to 75 pF with a typical phase margin of 40° and features 3 MHz gain bandwidth
product, 3 V/μs slew rate with 4 μVp-p integrated noise (0.1 Hz to 10 Hz) while consuming only 165 μA supply
current per channel, thus providing a good AC performance at a very low power consumption. DC applications
are also well served with a low input bias current (1 pA typical), a good input offset voltage (0.25 mV typical) and
a good PSRR (10 μV/V typical), CMRR (80 dB typical), and AOL (125 dB typical).
The robust design of the OPAx310 family simplifies circuit design. These op amps feature an integrated radio
frequency immunity (RFI) and electro-magnetic interference (EMI) rejection filter, unity-gain stability, and nophase reversal in input overdrive conditions.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The OPAx310 series of operational amplifiers is fully specified from 1.8 V to 5.5 V and is tested for amplifier
operation from 1.5 V to 1.8 V. In addition, many specifications apply from –40°C to 125°C. Parameters that
vary significantly with operating voltages or temperature are provided in the Typical Characteristics. TI highly
recommends to bypass power-supply pins with at least 0.01-μF ceramic capacitors.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPAx310 series extends to either supply rails. This is true even
when operating at the ultra-low supply voltage of 1.5 V, all the way up to the standard supply voltage of 5.5 V.
This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel
with a P-channel differential pair. Refer to the Functional Block Diagram for more details.
For most amplifiers with a complementary input stage, one of the input pairs, usually the P-channel input pair,
is designed to deliver slightly better performance in terms of input offset voltage, offset drift over the N-channel
pair. Consequently, the P-channel pair is designed to cover the majority of the common mode range with the
N-channel pair slated to slowly take over at a certain threshold voltage from the positive rail. Just after the
threshold voltage, both the input pairs are in operation for a small range referred to as the transition region.
Beyond this region, the N-channel pair completely takes over. Within the transition region, PSRR, CMRR, offset
voltage, offset drift, and THD can be degraded compared to device operation outside this region. Hence, most
applications generally prefer operating in the P-channel input range where the performance is slightly better.
For the OPAx310, the P-channel pair is typically active for input voltages from (V–) to (V+) – 0.4 V and the
N-channel pair is typically active for input voltages from the positive supply to (V+) – 0.4 V. The transition region
occurs typically from (V+) – 0.5 V to (V+) – 0.3 V, in which both pairs are on. These voltage levels mentioned
above can vary with process variations associated with threshold voltage of transistors. In the OPAx310, 200-mV
transition region mentioned above can vary up to 200 mV in either direction. Thus, the transition region (both
stages on) can range from (V+) – 0.7 V to (V+) – 0.5 V on the low end, up to (V+) – 0.3 V to (V+) – 0.1 V on the
high end.
Recollecting the fact that a P-channel input pair usually offers better performance over a N-channel input
pair, the OPAx310 is designed to offer a much wider P-channel input pair range, in comparison to most
complimentary input amplifiers in the industry. A side-by-side comparison of the OPAx310 and the TLV900x
is provided below. Note that the TLV900x is designed for P-channel pair operation only until 1.4 V from the
positive rail, while the OPAx310 is designed for P-channel pair operation until 0.7 V from the positive rail. This
additional 700 mV of P-channel input pair range for the OPAx310 is particularly useful when operating at lower
supply voltages (1.5 V, 1.8 V, and so forth) where the P-channel input range usually gets limited to a great
extent.
Thus the wide common mode swing of input signal can be accommodated more easily within the P-channel
input pair of the OPAx310, while likely avoiding the transition region, thereby maintaining linearity.
28
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1600
2000
1200
1500
800
1000
Offset Voltage (μV)
Input Offset Voltage (µV)
www.ti.com
400
0
-400
500
0
-500
-800
-1000
-1200
-1500
-1600
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5
Input Common-Mode Voltage (V)
2
2.5
3
-2000
-4
-3
-2
D07_
V+ = 2.75 V, V– = –2.75 V
Figure 8-1. OPAx310 Offset Voltage vs CommonMode
-1
0
1
2
Common-Mode Voltage (V)
3
4
D004
V+ = 2.75 V, V– = –2.75 V
Figure 8-2. TLV900x Offset Voltage vs CommonMode
8.3.3 Rail-to-Rail Output
Designed as a micro-power, high output current operational amplifier, the OPAx310 delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. At room temperature and for resistive loads up to 2 kΩ, the output swings to within a maximum of
20 mV of either supply rail at 5.5 V power supply. Different load conditions change the ability of the amplifier to
swing close to the rails.
8.3.4 Capacitive Load and Stability
The OPAx310 is designed to be used in applications where driving a capacitive load is required. As with all
operational amplifiers, there can be specific instances where the OPAx310 can become unstable. The particular
operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain
(1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an
amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases when capacitive loading increases. When operating in the unity-gain configuration, the
OPAx310 remains stable with a pure capacitive load up to approximately 75 pF with a good phase margin of
40° typical and has no sustained oscillations up to 250 pF. The equivalent series resistance (ESR) of some
very large capacitors (CL greater than 1 μF) is sufficient to alter the phase characteristics in the feedback loop
such that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive
increasingly larger capacitance. This increased capability is evident when measuring the overshoot response of
the amplifier at higher voltage gains.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor (typically 10 Ω to 20 Ω) in series with the output, as shown in Figure 8-3.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
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+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 8-3. Improving Capacitive Load Drive
8.3.5 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or high gain. After one of the
output devices enters the saturation region, the output stage requires additional time to return to the linear
operating state which is referred to as overload recovery time. After the output stage returns to linear operating
state, the amplifier begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an
overload condition) is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx310 family is approximately 0.75-µs typical.
8.3.6 EMI Rejection
The OPAx310 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications (radio frequency interference - RFI) and densely-populated boards
with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design
techniques; the OPAx310 benefits from these design improvements. Texas Instruments has developed the ability
to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum
extending from 10 MHz to 6 GHz. Figure 8-4 shows the results of this testing on the OPAx310. Table 8-1
shows the EMIRR IN+ values for the OPAx310 at particular frequencies commonly encountered in real-world
applications. The EMI Rejection Ratio of Operational Amplifiers application report contains detailed information
on the topic of EMIRR performance relating to op amps and is available for download from www.ti.com.
120
110
100
EMIRR (dB)
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
D42_
Figure 8-4. EMIRR Testing
30
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Table 8-1. OPAx310 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
48 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
58 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
75 dB
Bluetooth®,
2.4 GHz
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
90 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
95 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
102 dB
5 GHz
8.3.7 ESD and Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and relevance to an electrical overstress event is
helpful. Figure 8-5 shows the ESD circuits contained in the OPAx310 devices. The ESD protection circuitry
involves several current-steering diodes connected from the input and output pins and routed back to the internal
power supply lines, where the input and output pins meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
Note that the OPAx310 features no current-steering diodes connected between the input and positive powersupply pin.
V+
Power Supply
ESD Cell
+IN
+
OUT
–
– IN
SHDN
V–
Figure 8-5. Equivalent Internal ESD Circuitry
8.3.8 Input ESD Protection
The OPAx310 family incorporates internal ESD protection circuits on all pins. For inputs, this protection primarily
consists of fail safe ESD input structures which feature no current-steering diodes connected between the input
and positive power-supply pin as shown in the Figure 8-5. This feature is very useful during power sequencing
scenarios where input signal can be present before the positive power supply rail. A fail safe input ESD structure
prevents any short between inputs and positive power supply.
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8.3.9 Shutdown Function
The OPAx310 S devices feature SHDN pins that disable the op amp, placing the op amp into a low-power
standby mode. In this mode, the op amp typically consumes less than 500-nA at room temperature. The SHDN
pins are active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 500-mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to provide for smooth switching characteristics. To make sure of optimal
shutdown behavior, the SHDN pins must be driven with valid logic signals. A valid logic low is defined as a
voltage between V– and (V–) + 0.2 V. A valid logic high is defined as a voltage between (V–) + 1.2 V and V+. To
enable the amplifier, the SHDN pins must be driven to a valid logic high. To disable the amplifier, the SHDN pins
must be driven to a valid logic low. TI highly recommends that the shutdown pin be connected to a valid high or
a low voltage or driven. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage
level damages the device.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature can be
used to greatly reduce the average current and extend battery life. The enable and disable time is targeted to be
under 1-µs for full shutdown of all channels. When disabled, the output assumes a high-impedance state. This
architecture allows the OPAx310S to be operated as a gated amplifier (or to have the device output multiplexed
onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To make sure that shutdown (disable) is within a specific shutdown time, the specified
10-kΩ load to midsupply (VS / 2) is required.
8.3.10 Packages with an Exposed Thermal Pad
The OPAx310 family is available in packages such as the WQFN-16 (RTE), which feature an exposed thermal
pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For
this reason, when using a package with an exposed thermal pad, the thermal pad must be connected to (V–).
Attaching the thermal pad to a potential other then (V–) is not allowed, and the performance of the device may
not be consistent with the Electrical Characteristics table when doing so.
8.4 Device Functional Modes
The OPAx310 devices have one functional mode. These devices are powered on as long as the power-supply
voltage is between 1.5 V (±0.75 V) and 5.5 V (±2.75 V).
The OPAx310S devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Shutdown Function for more information.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPAx310 family of rail-to-rail input and output operational amplifiers is specifically designed for high output
current applications. The devices operate from 1.5 V to 5.5 V, are unity-gain stable, and are also an excellent
choice for a wide range of general-purpose applications. The class AB output stage is capable of driving small
resistive loads connected to any point between V+ and V– as long as the device is not forced into short circuit
mode or thermal shutdown mode. The input common-mode voltage range includes both rails and allows the
OPAx310 series to be used in many single-supply or dual supply configurations.
9.2 Typical Application
9.2.1 OPAx310 Low-Side, Current Sensing Application
Figure 9-1 shows the OPAx310 configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5V
+
Device
RSHUNT
0.1 Ÿ
VSHUNT
í
VOUT
í
+
RF
57.6 NŸ
RG
1.2 NŸ
Figure 9-1. OPAx310 in a Low-Side, Current-Sensing Application
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9.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Maximum output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
9.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is given in Equation 1.
VOUT = ILOAD × RSHUNT × Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2 .
V
RSHUNT = ISHUNT_MAX = 100 mV
1 A = 100 mΩ
(2)
LOAD_MAX
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the OPAx310 to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the
OPAx310 to produce the necessary output voltage is calculated using Equation 3.
V
− VOUT_MIN
Gain = OUT_MAX
VIN_MAX − VIN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the OPAx310 to 49 V/V.
R
Gain = 1 + R F
(4)
G
Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the
measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system; choose an impedance that is ideal for the system
parameters.
9.2.1.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
Figure 9-2. Low-Side, Current-Sense Transfer Function
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9.3 Power Supply Recommendations
The OPAx310 family is specified for operation from 1.5 V to 5.5 V (±0.75 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Electrical Characteristics presents parameters that can exhibit significant variance
with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.
9.4 Layout
9.4.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. One bypass capacitor from V+ to ground is adequate for single-supply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
Place the external components as close to the device as possible, as shown in Layout Example. Keeping R1
and R2 close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
TI recommends cleaning the PCB following board assembly for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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9.4.2 Layout Example
VC3
INPUT
OUTPUT
U1
1 +
3
2
–
R3
4
C4
C2
V+
R1
C1
R2
GND
V+
INPUT
Figure 9-3. Schematic for Noninverting Configuration Layout Example
GND
OUTPUT
V-
GND
Figure 9-4. Operational Amplifier Board Layout for Noninverting Configuration - SC70 (DCK) Package
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers (With OPA333 and OPA333-Q1 as an
Example) application report
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2310IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
O231
Samples
OPA2310IDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2310D
Samples
OPA2310IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O23G
Samples
OPA2310SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1NZ
Samples
OPA310IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
O310
Samples
OPA310IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1NN
Samples
OPA310SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
O31S
Samples
OPA310SIDCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1NP
Samples
OPA4310IDR
ACTIVE
SOIC
D
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA4310D
Samples
OPA4310IPWR
ACTIVE
TSSOP
PW
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O4310PW
Samples
OPA4310SIRTER
ACTIVE
WQFN
RTE
16
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O4310S
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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