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OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
OPAx322x 20-MHz, Low-Noise, 1.8-V, RRI/O,
CMOS Operational Amplifier With Shutdown
1 Features
3 Description
•
•
•
•
•
•
•
•
The OPAx322x series consists of single, dual, and
quad-channel CMOS operational amplifiers featuring
low noise and rail-to-rail inputs and outputs optimized
for low-power, single-supply applications. Specified
over a wide supply range of 1.8 V to 5.5 V, the low
quiescent current of only 1.5 mA per channel makes
these devices well-suited for power-sensitive
applications.
1
•
•
Gain Bandwidth: 20 MHz
Low Noise: 8.5 nV√Hz at 1 kHz
Slew Rate: 10 V/μs
Low THD+N: 0.0005%
Rail-to-Rail I/O
Offset Voltage: 2 mV (maximum)
Supply Voltage: 1.8 V to 5.5 V
Supply Current: 1.5 mA/ch
– Shutdown: 0.1 μA/ch
Unity-Gain Stable
Small Packages:
– SOT-23, SON, VSSOP, TSSOP
The combination of very low noise (8.5 nV√Hz at
1 kHz), high-gain bandwidth (20 MHz), and fast slew
rate (10 V/μs) make the OPAx322x family ideal for a
wide range of applications, including signal
conditioning and sensor amplification requiring high
gains. Featuring low THD+N, the OPAx322x series is
also excellent for consumer audio applications,
particularly for single-supply systems.
2 Applications
•
•
•
•
•
•
•
The OPAx322S models include a shutdown mode
that allow the amplifiers to be switched from normal
operation to a standby current that is typically less
than 0.1 μA.
Sensor Signal Conditioning
Consumer Audio
Multi-Pole Active Filters
Control-Loop Amplifiers
Communications
Security
Scanners
The OPA322 (single version) is available in 5-pin
SOT-23 and 6-pin SOT-23, while the OPA2322 (dual
version) is offered in 8-pin VSSOP, 10-pin VSSOP, 8pin SOIC, and 8-pin SON packages. The quad
version OPA4322 comes in 14-pin TSSOP and 16-pin
TSSOP packages. All versions are specified for
operation from –40°C to +125°C.
Zero-Crossover Rail-to-Rail Input Stage
Eliminates Distortion
Device Information(1)
1
PART NUMBER
0.8
Offset Voltage (mV)
0.6
0.4
2.90 mm × 1.60 mm
OPA322S
SOT-23 (6)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SON (8)
3.00 mm × 3.00 mm
OPA2322S
VSSOP (10)
3.00 mm × 3.00 mm
OPA4322
TSSOP (14)
5.00 mm × 4.40 mm
OPA4322S
TSSOP (16)
5.00 mm × 4.40 mm
OPA2322
-0.2
-0.4
-0.6
Representative Units
VS = ±2.75 V
-0.8
-1
-3
-2
-1
0
1
2
3
BODY SIZE (NOM)
SOT-23 (5)
0.2
0
PACKAGE
OPA322
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Common-Mode Voltage (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: OPA322, OPA322S ................ 8
Thermal Information: OPA2322, OPA2322S ............ 8
Thermal Information: OPA4322, OPA4322S ............ 8
Electrical Characteristics........................................... 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example ................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
26
26
26
26
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2012) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Changed device package descriptions to current standards ................................................................................................. 1
•
Deleted Package/Ordering Information table; see Package Option Addendum at the end of this data sheet ...................... 7
Changes from Revision D (March 2012) to Revision E
Page
•
Changed product status from Production Data to Mixed Status ............................................................................................ 1
•
Updated D and DGK pinout drawing ...................................................................................................................................... 5
•
Added Figure 26 to Figure 29............................................................................................................................................... 15
•
Added Shutdown Function section ....................................................................................................................................... 20
Changes from Revision C (November 2011) to Revision D
Page
•
Changed product status from Mixed Status to Production Data ............................................................................................ 1
•
Added OPA4322, OPA4322S to the Input Bias Current, Input bias current, Over temperature parameter in Electrical
Characteristics table ............................................................................................................................................................... 9
•
Changed Power Supply, OPA4322, OPA4322S Over temperature parameter maximum specification in the Electrical
Characteristics table ............................................................................................................................................................. 10
Changes from Revision B (July 2011) to Revision C
•
2
Page
Changed status of OPA2322 SO-8 (D) to production data from product preview ................................................................. 1
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Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
Changes from Revision A (May 2011) to Revision B
Page
•
Added OPA322S thermal information to OPA322 Thermal Information table ....................................................................... 8
•
Added OPA2322S thermal information to OPA2322 Thermal Information table ................................................................... 8
•
Added OPA4322S thermal information to OPA4322 Thermal Information table ................................................................... 8
•
Changed Input Bias Current Input bias current, Over temperature parameter in Electrical Characteristics table................. 9
•
Changed Open-Loop Gain, Open-loop voltage gain parameter typical specification in the Electrical Characteristics table . 9
•
Changed Open-Loop Gain, Phase margin parameter test conditions in the Electrical Characteristics table ........................ 9
•
Changed Power Supply, Quiescent current per amplifier OPA322/S parameter maximum specification in the
Electrical Characteristics ...................................................................................................................................................... 10
•
Changed Power Supply, OPA322 Over temperature parameter maximum specification in the Electrical
Characteristics table ............................................................................................................................................................. 10
•
Changed Power Supply, Quiescent current per amplifier OPA4322/S parameter typical specification in the Electrical
Characteristics ...................................................................................................................................................................... 10
•
Added test conditions to Power Supply section in Electrical Characteristics table .............................................................. 10
•
Changed Shutdown, Quiescent current, per amplifier parameter maximum specification in Electrical Characteristics
table ...................................................................................................................................................................................... 10
•
Updated Figure 1.................................................................................................................................................................. 11
•
Added Figure 25 ................................................................................................................................................................... 15
•
Changed Overload Recovery Time section.......................................................................................................................... 19
Changes from Original (January 2011) to Revision A
•
Page
Changed document status to Production Data ...................................................................................................................... 1
Copyright © 2011–2016, Texas Instruments Incorporated
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3
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
5 Pin Configuration and Functions
OPA322: DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
4
OPA322S: DBV Package
6-Pin SOT-23
Top View
V+
VOUT
1
6
V+
V-
2
5
SHDN
+IN
3
4
-IN
-IN
Pin Functions: OPA322, OPA322S
PIN
NAME
OPA322
OPA322S
I/O
DESCRIPTION
SOT-23
SOT-23
–IN
4
4
I
Inverting input
+IN
3
3
I
Noninverting input
OUT
1
1
O
Output
SHDN
—
5
I
Shutdown control (active low)
V–
2
2
—
Negative (lowest) power supply
V+
5
6
—
Positive (highest) power supply
4
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Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
OPA2322: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
-IN A
2
+IN A
3
V-
4
A
B
OPA2322: DRG Package
8-Pin SON
Top View
8
V+
7
OUT B
-IN A
2
6
-IN B
+IN A
3
5
+IN B
V-
4
1
OUT A
Exposed
Thermal
Die Pad
on
Underside
(1)
Connect thermal pad to V–.
(2)
Pad size: 2 mm × 1.2 mm.
8
V+
7
OUT B
6
-IN B
5
+IN B
OPA2322S: DGS Package
10-Pin VSSOP
Top View
VOUT A
1
-IN A
2
10 V+
9
VOUT B
8
-IN B
A
+IN A
3
B
V-
4
7
+IN B
SHDN A
5
6
SHDN B
Pin Functions: OPA2322, OPA2322S
PIN
OPA2322
OPA2322S
I/O
DESCRIPTION
NAME
SOIC,
VSSOP
SON
VSSOP
–IN A
2
2
2
I
Inverting input, channel A
+IN A
3
3
3
I
Noninverting input, channel A
–IN B
6
6
8
I
Inverting input, channel B
+IN B
5
5
7
I
Noninverting input, channel B
OUT A
1
1
—
O
Output, channel A
OUT B
7
7
—
O
Output, channel B
SHDN A
—
—
5
I
Shutdown control, channel A (active low)
SHDN B
—
—
6
I
Shutdown control, channel B (active low)
V–
4
4
4
—
Negative (lowest) power supply
V+
8
8
10
—
Positive (highest) power supply
VOUT A
—
—
1
O
Output, channel A
VOUT B
—
—
9
O
Output, channel B
Copyright © 2011–2016, Texas Instruments Incorporated
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5
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
PW Package
14-Pin TSSOP
Top View
OUT A
1
PW Package
16-Pin TSSOP
Top View
OUT A
14 OUT D
A
D
1
16 OUT D
A
D
15 -IN D
13 -IN D
-IN A
2
3
12 +IN D
+IN A
3
14 +IN D
V+
4
11 V-
V+
4
13 V-
+IN B
5
10 +IN C
+IN B
5
12 +IN C
-IN B
6
9
-IN C
-IN B
6
OUT B
7
8
OUT C
OUT B
7
10 OUT C
SHDN A/B
8
9
-IN A
2
+IN A
B
C
B
C
11 -IN C
SHDN C/D
Pin Functions: OPA4322, OPA4322S
PIN
NAME
OPA4322
OPA4322S
I/O
DESCRIPTION
TSSOP
TSSOP
–IN A
2
2
I
Inverting input, channel A
+IN A
3
3
I
Noninverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN B
5
5
I
Noninverting input, channel B
–IN C
9
11
I
Inverting input, channel C
+IN C
10
12
I
Noninverting input, channel C
–IN D
13
15
I
Inverting input, channel D
+IN D
12
14
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
8
10
O
Output, channel C
OUT D
14
16
O
Output, channel D
SHDN A/B
—
8
I
Shutdown control, channels A and B (active low)
9
I
Shutdown control, channels C and D (active low)
SHDN C/D
V–
11
13
—
Negative (lowest) power supply
V+
4
4
—
Positive (highest) power supply
6
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Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS = (V+) – (V–)
Voltage
Signal input pins
(2)
Signal input pins (2)
Current
Operating, TA
(1)
(2)
(3)
V
(V+) + 0.5
V
–10
10
mA
150
°C
150
°C
150
°C
Continuous
–40
Junction, TJ
Storage, Tstg
UNIT
6
(V–) – 0.5
Output short-circuit (3)
Temperature
MAX
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Specified voltage
1.8
5.5
V
TA
Specified temperature
–40
125
°C
Copyright © 2011–2016, Texas Instruments Incorporated
UNIT
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7
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
6.4 Thermal Information: OPA322, OPA322S
THERMAL METRIC (1)
OPA322
OPA322S
DBV (SOT-23)
DBV (SOT-23)
5 PINS
6 PINS
UNITS
RθJA
Junction-to-ambient thermal resistance
219.3
177.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
107.5
108.9
°C/W
RθJB
Junction-to-board thermal resistance
57.5
27.4
°C/W
ψJT
Junction-to-top characterization parameter
7.4
13.3
°C/W
ψJB
Junction-to-board characterization parameter
56.9
26.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2322, OPA2322S
OPA2322
THERMAL METRIC
(1)
OPA2322S
D (SOIC)
DRG (SON)
DGK (VSSOP)
DGS
(VSSOP)
8 PINS
8 PINS
8 PINS
10 PINS
UNITS
RθJA
Junction-to-ambient thermal resistance
122.6
50.6
174.8
171.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
67.1
54.9
43.9
43
°C/W
RθJB
Junction-to-board thermal resistance
64
25.2
95
91.4
°C/W
ψJT
Junction-to-top characterization parameter
13.2
0.6
2
1.9
°C/W
ψJB
Junction-to-board characterization parameter
63.4
25.3
93.5
89.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
—
5.7
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4322, OPA4322S
THERMAL METRIC
(1)
OPA4322
OPA4322S
PW (TSSOP)
PW (TSSOP)
14 PINS
16 PINS
UNITS
RθJA
Junction-to-ambient thermal resistance
109.8
105.9
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
34.9
28.1
°C/W
RθJB
Junction-to-board thermal resistance
52.5
51.1
°C/W
ψJT
Junction-to-top characterization parameter
2.2
0.8
°C/W
ψJB
Junction-to-board characterization parameter
51.8
50.4
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
6.7 Electrical Characteristics
At VS = 1.8 V to 5.5 V, or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and
SHDN_x = VS+ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
2
mV
1.8
6
μV/°C
TA = 25°C
10
50
TA = –40°C to 125°C
20
65
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
vs temperature
VS = 5.5 V
PSR
vs power supply
VS = 1.8 V to 5.5 V
Channel separation
At 1 kHz
130
μV/V
dB
INPUT VOLTAGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = 25°C
90
TA = –40°C to 125°C
90
(V+) + 0.1
100
V
dB
INPUT BIAS CURRENT
TA = 25°C
±0.2
TA = –40°C to 85°C
IB
Input bias current
±50
OPA322 and OPA322S, TA = –40°C to 125°C
±800
OPA2322 and OPA2322S, TA = –40°C to 125°C
±400
OPA4322 and OPA4322S, TA = –40°C to 125°C
Input offset current
pA
±400
TA = 25°C
IOS
±10
±0.2
±10
TA = –40°C to 85°C
±50
TA = –40°C to 125°C
±400
pA
NOISE
Input voltage noise
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
2.8
f = 1 kHz
8.5
f = 10 kHz
7
f = 1 kHz
0.6
μVPP
nV/√Hz
fA/√Hz
INPUT CAPACITANCE
Differential
5
pF
Common-mode
4
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
PM
Phase margin
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
100
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
94
130
dB
VS = 5 V, CL = 50 pF
47
°
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V, CL = 50 pF, unity gain
20
MHz
SR
Slew rate
VS = 5 V, CL = 50 pF, G = +1
10
V/μs
tS
Settling time
Overload recovery time
THD+N
(1)
Total harmonic distortion +
noise (1)
VS = 5 V, CL = 50 pF, to 0.1%, 2-V step, G = +1
0.25
VS = 5 V, CL = 50 pF, to 0.01%, 2-V step, G = +1
0.32
VS = 5 V, CL = 50 pF, VIN × G > VS
100
VS = 5 V, CL = 50 pF, VO = 4 VPP, G = +1, f = 10 kHz,
RL = 10 kΩ
0.0005%
VS = 5 V, CL = 50 pF, VO = 2 VPP, G = +1, f = 10 kHz,
RL = 600 Ω
0.0011%
μs
ns
Third-order filter; bandwidth = 80 kHz at –3 dB
Copyright © 2011–2016, Texas Instruments Incorporated
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OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
Electrical Characteristics (continued)
At VS = 1.8 V to 5.5 V, or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and
SHDN_x = VS+ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
20
UNIT
OUTPUT
VO
Voltage output (swing from
both rails)
RL = 10 kΩ
ISC
Short-circuit current
VS = 5.5 V
CL
Capacitive load drive
RO
Open-loop output resistance
TA = 25°C
TA = –40°C to 125°C
30
±65
mV
mA
See Typical Characteristics
IO = 0 mA, f = 1 MHz
90
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per
amplifier
Power-on time
1.8
OPA322 and OPA322S,
IO = 0 mA, VS = 5.5 V
TA = 25°C
OPA2322 and OPA2322S,
IO = 0 mA, VS = 5.5 V
TA = 25°C
OPA4322 and OPA4322S,
IO = 0 mA, VS = 5.5 V
TA = 25°C
5.5
1.6
1.9
1.5
1.75
TA = –40°C to 125°C
V
2
TA = –40°C to 125°C
1.85
1.4
TA = –40°C to 125°C
mA
1.65
1.75
VS+ = 0 V to 5 V, to 90% IQ level
28
0.1
μs
SHUTDOWN (2)
IQSD
Quiescent current
(per amplifier)
VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS–
VIH
High voltage (enabled)
VS = 1.8 V to 5.5 V, amplifier enabled
VIL
Low voltage (disabled)
VS = 1.8 V to 5.5 V, amplifier disabled
Amplifier enable time
(full shutdown) (3)
VS = 1.8 V to 5.5 V, full shutdown; G = 1,
VOUT = 0.9 × VS/2 (4)
Amplifier enable time
(partial shutdown) (3)
VS = 1.8 V to 5.5 V, partial shutdown; G = 1,
VOUT = 0.9 × VS/2 (4)
tON
tOFF
Amplifier disable time
(3)
SHDN pin input bias current
(per pin)
(2)
(3)
(4)
10
0.5
(V+) – 0.1
µA
V
(V–) + 0.1
VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS/2
V
10
µs
6
µs
3
µs
VS = 1.8 V to 5.5 V, VIH = 5 V
0.13
VS = 1.8 V to 5.5 V, VIL = 0 V
0.04
µA
Ensured by design and characterization; not production tested.
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual OPA2322S having both channels A and B disabled (SHDN_A = SHDN_B = VS–) and the quad
OPA4322S having all channels A to D disabled (SHDN_A/B = SHDN_C/D = VS–). For partial shutdown, only one SHDN pin is exercised;
in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
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SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
6.8 Typical Characteristics
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
-20
125
-40
120
100
-60
115
80
-80
60
-100
40
-120
20
-140
RL = 10 kW, 50 pF
VS = ±2.5 V
Gain
Phase
0
-20
10
1
100
1k
10k
100k
1M
10M
10 kW Load
Phase (°)
Gain (dB)
120
Open-Loop Gain (dB)
140
110
2 kW Load
105
100
95
-160
90
-180
100M
85
-50
-25
0
25
0.8
5
100
125
150
4
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2
1
0
-1
-2
-3
IB+
IBIOS
-5
-6
2.9
2.7
3
-4
IBIB+
-0.8
-3 -2.5 -2 -1.5 -1 -0.5 0
Supply Voltage (±V)
0.5
1
1.5
2
3
2.5
Common-Mode Voltage (V)
Figure 3. Input Bias Current vs Supply Voltage
Figure 4. Input Bias Current
vs Common-Mode Voltage
1.6
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-100
IOS
IB+
IB-
IB
IOS
Quiescent Current (mA/Ch)
Input Bias Current (pA)
75
Figure 2. Open-Loop Gain vs Temperature
6
Input Bias Current (pA)
Input Bias Current (pA)
Figure 1. Open-Loop Gain and Phase vs Frequency
1
-1
50
Temperature (°C)
Frequency (Hz)
1.55
1.5
1.45
1.4
+125°C
+85°C
1.35
+25°C
-40°C
1.3
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 5. Input Bias Current vs Temperature
Copyright © 2011–2016, Texas Instruments Incorporated
150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Figure 6. Quiescent Current vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
1
14
0.8
0.6
Offset Voltage (mV)
Number of Amplifiers (%)
12
10
8
6
4
0.4
0.2
0
-0.2
-0.4
-0.6
2
Representative Units
VS = ±2.75 V
-0.8
-1
1.5
1.1
1.3
0.9
0.5
0.7
0.1
0.3
-0.1
-0.3
-0.5
-0.7
-1.1
-0.9
-1.3
-1.5
0
-3
-2
Offset Voltage (mV)
3
2
6
VS = 1.8 V to 5.5 V
5
4
3
100
Voltage (mV)
Voltage Noise (nV/ÖHz)
1
Figure 8. Offset Voltage vs Common-Mode Voltage
Figure 7. Offset Voltage Production Histogram
1000
0
-1
Common-Mode Voltage (V)
10
2
1
0
-1
-2
-3
1
-4
10
100
1k
10 k
1M
100 k
0
1
2
3
Frequency (Hz)
20
G = +10 V/V
0
-20
10 k
12
60
VS = +1.8 V
RL = 10 kW
CL = 50 pF
G = +100 V/V
40
1M
7
8
10
9
10 M
100 M
VS = +5.5 V
RL = 10 kW
CL = 50 pF
G = +100 V/V
20
G = +10 V/V
0
G = +1 V/V
100 k
6
Figure 10. 0.1-Hz to 10-Hz Input Voltage Noise
Gain (dB)
Gain (dB)
40
5
Time (s)
Figure 9. Input Voltage Noise Spectral Density
vs Frequency
60
4
-20
10 k
G = +1 V/V
100 k
1M
10 M
100 M
Frequency (Hz)
Frequency (Hz)
Figure 11. Closed-Loop Gain vs Frequency
Figure 12. Closed-Loop Gain vs Frequency
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SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
Typical Characteristics (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
6
3
5.5 VS
2
4
Output Voltage (V)
Output Voltage (VPP)
5
3.3 VS
3
2
1
-40°C
+25°C
+125°C
0
-1
1.8 VS
1
-2
RL = 10 kW
CL = 50 pF
VS = ±2.75 V
0
10 k
-3
100 k
10 M
1M
10
0
20
30
Frequency (Hz)
40
50
Figure 13. Maximum Output Voltage vs Frequency
70
80
Figure 14. Output Voltage Swing vs Output Current
1000
70
G = 1, VS = 1.8 V
VS = ±2.75 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
50
Overshoot (%)
Impedance (W)
60
Output Current (mA)
100
G = 10, VS = 5.5 V
40
30
20
10
0
10
1
10
100
1k
10 k
100 k
1M
10 M 100 M
500
0
1000
Frequency (Hz)
0.1
0.01
Load = 600 W
0.001
Frequency = 10 kHz
VS = ±2.5 V
G = +1 V/V
Load = 10 kW
0.1
2000
2500
3000
Figure 16. Small-Signal Overshoot
vs Load Capacitance
Total Harmonic Distortion and Noise (%)
Total Harmonic Distortion and Noise (%)
Figure 15. Open-Loop Output Impedance
vs Frequency
0.0001
0.01
1500
Capacitive Load (pF)
1
VIN (VPP)
Figure 17. THD+N vs Amplitude
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10
0.1
Frequency = 10 kHz
VIN = 2 VPP
VS = ±2.5 V
G = +1 V/V
0.01
Load = 600 W
0.001
Load = 10 kW
0.0001
10
100
1k
10 k
100 k
Frequency (Hz)
Figure 18. THD+N vs Frequency
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Typical Characteristics (continued)
0.1
0
Frequency = 10 kHz
VIN = 4 VPP
VS = ±2.5 V
G = +1 V/V
VS = ±2.75 V
-20
Channel Separation (dB)
Total Harmonic Distortion and Noise (%)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
0.01
Load = 600 W
0.001
-60
-80
-100
-120
Load = 10 kW
0.0001
-40
-140
10
100
1k
1k
100 k
10 k
10 k
100 k
Frequency (Hz)
Figure 19. THD+N vs Frequency
10 M
100 M
Figure 20. Channel Separation
vs Frequency (for Dual)
0.1
12
CL = 50 pF
0.075
11.5
0.05
11
Voltage (V)
Slew Rate (V/ms)
1M
Frequency (Hz)
Rise
10.5
Fall
10
Gain = +1
VS = ±2.75 V
VIN = 100 mVPP
0.025
0
-0.025
-0.05
9.5
VOUT
VIN
-0.075
9
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
-0.1
-0.8
5.6
-0.4
0
0.4
Supply Voltage (V)
Figure 21. Slew Rate vs Supply Voltage
1.5
0.075
VIN
Gain = -1
VS = ±2.75 V
VIN = 100 mVPP
Voltage (V)
Voltage (V)
Gain = +1
VS = ±2.75 V
VIN = 2 VPP
1
0.05
0
1.6
1.2
Figure 22. Small-Signal Step Response
0.1
0.025
0.8
Time (ms)
-0.025
0.5
VOUT
0
-0.5
-0.05
-0.1
-1.6
-1.2
-0.8
-0.4
0
0.4
Time (ms)
Figure 23. Small-Signal Step Response
14
-1
VOUT
VIN
-0.075
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0.8
-1.5
-0.4
0
0.4
0.8
1.2
1.6
Time (ms)
Figure 24. Large-Signal Step Response vs Time
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SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
Typical Characteristics (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
3
Shutdown Signal
Output Signal
2.4
100
1.8
1.2
80
Voltage (V)
Common-Mode Rejection Ratio,
Power-Supply Rejection Ratio (dB)
120
60
40
0.6
0
−0.6
−1.2
20
−1.8
PSRR
CMRR
−2.4
0
1k
100
10k
100k
−3
1M
0
2
4
6
8
Frequency (Hz)
Figure 25. CMRR and PSRR vs Frequency
3
1.8
Voltage (V)
Voltage (V)
1.2
0.6
0
−0.6
−1.2
−1.8
−3
Shutdown Signal
Output Signal
0
2
4
6
8
10
12
Time (µs)
14
16
18
20
G000
Figure 27. Turnon Transient
14
16
18
20
G000
Figure 26. Turnoff Transient
2.4
−2.4
10
12
Time (µs)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
−4.5
−5
Shutdown Signal
Output Signal
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
G000
5.5 V (High Supply)
Figure 28. Turnon and Turnoff Transient
2
1.5
Voltage (V)
1
0.5
0
−0.5
−1
Shutdown Signal
Output Signal
−1.5
−2
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
G000
1.8 V (Low Supply)
Figure 29. Turnon and Turnoff Transient
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7 Detailed Description
7.1 Overview
The OPA322 family of operational amplifiers (op amps) are high-speed, precision amplifiers perfectly suited to
drive 12-, 14-, and 16-bit analog-to-digital converters. Low-output impedance with flat frequency characteristics
and zero-crossover distortion circuitry enable high linearity over the full input common-mode range, achieving
true rail-to-rail input from a 1.8-V to 5.5-V single supply.
7.2 Functional Block Diagram
V+
Low Noise Charge
Pump
Bias Circuitry
+IN
-IN
OUT
Input Stage Load
Bias Circuitry
VCopyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Operating Voltage
The OPA322 series op amps are unity-gain stable and can operate on a single-supply voltage (1.8 V to 5.5 V), or
a split-supply voltage (±0.9 V to ±2.75 V), making them highly versatile and easy to use. The power-supply pins
must have local bypass ceramic capacitors (typically 0.001 μF to 0.1 μF). These amplifiers are fully specified
from 1.8 V to 5.5 V and over the extended temperature range of –40°C to 125°C. Parameters that can exhibit
variance with regard to operating voltage or temperature are presented in the Typical Characteristics.
7.3.2 Input and ESD Protection
The OPA322 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as
the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Many input signals are inherently
current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 30 shows how a series
input resistor (RS) may be added to the driven input to limit the input current. The added resistor contributes
thermal noise at the amplifier input and the value must be kept to the minimum in noise-sensitive applications.
16
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SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
Feature Description (continued)
V+
IOVERLOAD
10 mA, Max
VOUT
OPA322
VIN
RS
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Input Current Protection
7.3.3 Phase Reversal
The OPA322 op amps are designed to be immune to phase reversal when the input pins exceed the supply
voltages, therefore providing further in-system stability and predictability. Figure 31 shows the input voltage
exceeding the supply voltage without any phase reversal.
4
VIN
VS = ±2.5 V
3
Voltage (V)
2
VOUT
1
0
-1
-2
-3
-4
-500
-250
0
250
500
750
1000
Time (ms)
Figure 31. No Phase Reversal
7.3.4 Feedback Capacitor Improves Response
For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a
feedback capacitor across the feedback resistor, RF, as shown in Figure 32. This capacitor compensates for the
zero created by the feedback network impedance and the OPA322 input capacitance (and any parasitic layout
capacitance). The effect becomes more significant with higher impedance networks.
CF
RIN
RF
VIN
V+
CIN
RIN ´ CIN = RF ´ CF
OPA322
VOUT
CL
CIN
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NOTE: Where CIN is equal to the OPA322 input capacitance (approximately 9 pF) plus any parasitic layout capacitance.
Figure 32. Feedback Capacitor Improves Dynamic Performance
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Feature Description (continued)
For the circuit shown in Figure 32, the value of the variable feedback capacitor must be chosen so that the input
resistance times the input capacitance of the OPA322 (typically 9 pF) plus the estimated parasitic layout
capacitance equals the feedback capacitor times the feedback resistor with Equation 1.
RIN × CIN = RF × CF
where
•
CIN is equal to the OPA322 input capacitance (sum of differential and common-mode) plus the layout
capacitance
(1)
The capacitor value can be adjusted until optimum performance is obtained.
7.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
device, the DC offset observed at the amplifier output may shift from the nominal value while EMI is present. This
shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational
amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA322
operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to
EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a
cutoff frequency of approximately 580 MHz (–3 dB), with a roll-off of 20 dB per decade.
7.3.6 Output Impedance
The open-loop output impedance of the OPA322 common-source output stage is approximately 90 Ω. When the
op amp is connected with feedback, this value is reduced significantly by the loop gain. For each decade rise in
the closed-loop gain, the loop gain is reduced by the same amount, which results in a tenfold increase in
effective output impedance. While the OPA322 output impedance remains very flat over a wide frequency range,
at higher frequencies the output impedance rises as the open-loop gain of the op amp drops. However, at these
frequencies the output also becomes capacitive as a result of parasitic capacitance. This characteristic, in turn,
prevents the output impedance from becoming too high, which can cause stability problems when driving large
capacitive loads. As mentioned previously, the OPA322 has excellent capacitive load drive capability for an op
amp with its bandwidth.
7.3.7 Capacitive Load and Stability
The OPA322 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA322 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer configuration and driving a capacitive
load exhibits a greater tendency to become unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA322 remains stable with a pure capacitive load up to
approximately 1 nF.
The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains, as shown in Figure 33. One technique
for increasing the capacitive load drive capability of the amplifier operating in unity gain is to insert a small
resistor (RS), typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 34.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing. The error contributed by the voltage divider, however, may be insignificant. For
instance, with a load resistance, RL = 10 kΩ and RS = 20 Ω, the gain error is only about 0.2%. However, when RL
is decreased to 600 Ω, which the OPA322 is able to drive, the error increases to 7.5%.
18
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SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
Feature Description (continued)
70
G = 1, VS = 1.8 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
Overshoot (%)
50
G = 10, VS = 5.5 V
40
30
20
10
0
0
500
1000
1500
2000
3000
2500
Capacitive Load (pF)
Figure 33. Small-Signal Overshoot vs Capacitive Load (100-mVPP Output Step)
V+
RS
VOUT
OPA322
VIN
10 W to
20 W
RL
CL
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Improving Capacitive Load Drive
7.3.8 Overload Recovery Time
Overload recovery time is the time required for the output of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly important in applications where small signals must be
amplified in the presence of large transients. Figure 35 and Figure 36 show the positive and negative overload
recovery times of the OPA322, respectively. In both cases, the time elapsed before the OPA322 comes out of
saturation is less than 100 ns. In addition, the symmetry between the positive and negative recovery times allows
excellent signal rectification without distortion of the output signal.
spacer
3
2.5
Output
0.5
Input
2
0
1.5
-0.5
Voltage (V)
Voltage (V)
1
VS = ±2.75 V
G = -10
1
0.5
0
-1
-1.5
-2
Input
Output
-0.5
VS = ±2.75 V
G = -10
-2.5
-1
9.75
10
10.25
10.5
10.75
Time (250 ns/div)
Figure 35. Positive Recovery Time
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11
-3
9.75
10
10.25
10.5
10.75
11
Time (250 ns/div)
Figure 36. Negative Recovery Time
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Feature Description (continued)
7.3.9 Shutdown Function
The SHDN (enable) pin function of the OPAx322S is referenced to the negative supply voltage of the operational
amplifier. A logic level high enables the op amp. A valid logic high is defined as voltage [(V+) – 0.1 V], up to (V+),
applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–), applied to the enable pin.
The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative supply, independent of the
positive supply voltage. This pin must either be connected to a valid high or a low voltage or driven, and not left
as an open circuit.
The logic input is a high-impedance CMOS input. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown of
all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This architecture
allows the OPAx322S to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases with increased
load resistance. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required. If using the OPAx322S without a load, the resulting turnoff time is significantly
increased.
7.4 Device Functional Modes
The OPA322 family of operational amplifiers are operational when power-supply voltages between 1.8 V to 5.5 V
are applied. Devices with an S suffix have a shutdown capability. For a detailed description of the shutdown
function, refer to Shutdown Function.
20
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Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA322 family offers outstanding DC and AC performance. These devices operate up to a 5.5-V power
supply and offer ultra-low input bias current and 20-MHz bandwidth. These features make the OPA322 family a
robust operational amplifier for both battery-powered and industrial applications.
8.1.1 Active Filter
The OPA322 is well-suited for active filter applications that require a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. Figure 37 shows a 500-kHz, second-order, low-pass filter using the multiplefeedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth response.
Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is ideal for applications that require
predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of these options:
1. adding an inverting amplifier;
2. adding an additional second-order MFB stage; or
3. using a noninverting filter topology, such as the Sallen-Key (shown in Figure 38).
MFB, Sallen-Key, low-pass, and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™ program.
This software is available as a free download at www.ti.com.
R3
549 W
C2
150 pF
R1
549 W
R2
1.24 kW
V+
VIN
VOUT
OPA322
C1
1 nF
VCopyright © 2016, Texas Instruments Incorporated
Figure 37. Second-Order, Butterworth, 500-kHz Low-Pass Filter
220 pF
V+
1.8 kW
19.5 kW
150 kW
VIN = 1 VRMS
3.3 nF
47 pF
OPA322
VOUT
V-
Figure 38. OPA322 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
Copyright © 2011–2016, Texas Instruments Incorporated
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21
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
8.2 Typical Application
2.25 k
2.25 k
1.13 k
Input
1 nF
±
4 nF
Output
+
Copyright © 2016, Texas Instruments Incorporated
Figure 39. Second-Order, Low-Pass Filter Schematic
8.2.1 Design Requirements
•
Gain = 1 V/V
•
•
Low-pass cutoff frequency = 50 kHz
–40-db/dec filter response
•
Maintain less than 3-dB gain peaking in the gain versus frequency response
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in. Use Equation 2 to
calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(2)
This circuit produces a signal inversion. For this circuit, the gain at DC and the lowpass cutoff frequency are
calculated by Equation 3.
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(3)
®
Software tools are readily available to simplify filter design. WEBENCH Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
22
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Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
Typical Application (continued)
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 40. OPA322 Second-Order, 50-kHz, Low-Pass Filter
9 Power Supply Recommendations
The OPA322 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.
Copyright © 2011–2016, Texas Instruments Incorporated
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23
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
10 Layout
10.1 Layout Guidelines
The OPA322 is a wideband amplifier. To realize the full operational performance of the device, follow good highfrequency printed-circuit board (PCB) layout practices. The bypass capacitors must be connected between each
supply pin and ground as close to the device as possible. The bypass capacitor traces must be designed for
minimum inductance.
10.1.1 Leadless DFN Package
The OPA2322 uses the DFN style package (also known as SON), which is a QFN with contacts on only two
sides of the package bottom. This leadless package maximizes PCB space and offers enhanced thermal and
electrical characteristics through an exposed pad. One of the primary advantages of the DFN package is its low
height (0.8 mm).
DFN packages are physically small, and have a smaller routing area. Additionally, they offer improved thermal
performance, reduced electrical parasitics, and a pinout scheme that is consistent with other commonly-used
packages (such as SOIC and VSSOP). The absence of external leads also eliminates bent-lead issues.
The DFN package can easily be mounted using standard PCB assembly techniques. See the application reports,
QFN/SON PCB Attachment and Quad Flatpack No-Lead Logic Packages. The dimension of the exposed thermal
die pad is 2 mm × 1.2 mm and is centered.
NOTE
The exposed leadframe die pad on the bottom of the DFN package must be connected to
the most negative potential (V–).
10.2 Layout Example
VS+
VOUT
VS±
V+
OUT
GND
V±
Use a low-ESR,
ceramic bypass
capacitor.
Use a low-ESR,
ceramic bypass
capacitor.
RG
VIN
+IN
GND
±IN
GND
Run the input traces
as far away from
the supply lines
as possible.
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
Copyright © 2016, Texas Instruments Incorporated
Figure 41. Layout Example
24
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Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.2.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation
tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT23-5 and
SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
11.1.2.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.2.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.2.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
25
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
www.ti.com
Device Support (continued)
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPA322x, and recommended for reference. All are available
for download at www.ti.com unless otherwise noted.
• QFN/SON PCB Attachment (SLUA271)
• Quad Flatpack No-Lead Logic Packages (SCBA017)
• OPA322, OPA2322, OPA4322 EMIR Immunity Performance (SBOT005)
• FilterPro™ User's Guide (SBFA001)
• AFE for Transient Recorder and Digital Fault Recorder Using High-Speed ADCs and Differential Amplifiers
(TIDUAT7)
• Reference Design for Interfacing Current Output Hall Sensors and CTs With Differential ADCs/MCUs
(TIDUA57)
• Single-Ended Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
(TIDU583)
• Differential Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
(TIDU569)
11.3 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA322
Click here
Click here
Click here
Click here
Click here
OPA322S
Click here
Click here
Click here
Click here
Click here
OPA2322
Click here
Click here
Click here
Click here
Click here
OPA2322S
Click here
Click here
Click here
Click here
Click here
OPA4322
Click here
Click here
Click here
Click here
Click here
OPA4322S
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
26
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Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538F – JANUARY 2011 – REVISED DECEMBER 2016
11.6 Trademarks
FilterPro, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2016, Texas Instruments Incorporated
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Product Folder Links: OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2322AID
ACTIVE
SOIC
D
8
75
OPA2322AIDGKR
ACTIVE
VSSOP
DGK
8
2500
OPA2322AIDGKT
ACTIVE
VSSOP
DGK
8
OPA2322AIDR
ACTIVE
SOIC
D
OPA2322AIDRGR
ACTIVE
SON
OPA2322AIDRGT
ACTIVE
OPA2322SAIDGSR
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
O2322A
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OOZI
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OOZI
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2322A
DRG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
SON
DRG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPCI
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
OPA2322SAIDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPBI
OPA322AIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAD
OPA322AIDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAD
OPA322SAIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
OPA322SAIDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAF
OPA4322AIPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322A
OPA4322AIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322A
OPA4322SAIPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322SA
OPA4322SAIPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4322SA
(1)
NIPDAU
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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