OPA4830
¨
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
Quad, Low-Power, Single-Supply, Wideband Operational Amplifier
FEATURES
1
DESCRIPTION
• HIGH BANDWIDTH:
280MHz (G = +1)
120MHz (G = +2)
• LOW SUPPLY CURRENT:
3.9mA/ch (VS = +5V)
• FLEXIBLE SUPPLY RANGE:
±1.4V to ±5.5V Dual Supply
+2.8V to +11V Single Supply
• INPUT RANGE INCLUDES GROUND ON
SINGLE SUPPLY
• 4.91V OUTPUT SWING ON +5V SUPPLY
• HIGH SLEW RATE: 560V/µs
• LOW INPUT VOLTAGE NOISE: 9.2nV/√Hz
• AVAILABLE IN A TSSOP-14 PACKAGE
2
The OPA4830 is a quad, low-power, single-supply,
wideband, voltage-feedback amplifier designed to
operate on a single +3V or +5V supply. Operation on
±5V or +10V supplies is also supported. The input
range extends below the negative supply and to
within 1.8V of the positive supply. Using
complementary common-emitter outputs provides an
output swing to within 220mV of either supply while
driving 150Ω. High output drive current (±80mA) and
low differential gain and phase errors also make this
amplifier an excellent choice for single-supply
consumer video products.
Low distortion operation is ensured by the high gain
bandwidth product (110MHz) and slew rate
(560V/µs), making the OPA4830 an ideal input buffer
stage to 3V and 5V CMOS analog-to-digital
converters (ADCs). Unlike other low-power,
single-supply amplifiers, distortion performance
improves as the signal swing is decreased. A low
9.2nV/√Hz input voltage noise supports wide dynamic
range operation.
APPLICATIONS
•
•
•
•
•
•
SINGLE-SUPPLY ANALOG-TO-DIGITAL
CONVERTER (ADC) INPUT BUFFERS
SINGLE-SUPPLY VIDEO LINE DRIVERS
CCD IMAGING CHANNELS
ACTIVE FILTERS
PLL INTEGRATORS
PORTABLE CONSUMER ELECTRONICS
The OPA4830 is available in an industry-standard
quad pinout TSSOP-14 package.
RELATED PRODUCTS
DESCRIPTION
+3.3V
2.26kW
+3.3V
374W
VIN
1/4
OPA4830
1/4
100W
22pF
562W
ADS5240
12-Bit
40MSPS
SINGLES
DUALS
TRIPLES
QUADS
Rail-to-Rail
OPA830
OPA2830
—
—
Rail-to-Rail Fixed-Gain
OPA832
OPA2832
OPA3832
—
General-Purpose
(1800V/µs slew rate)
OPA690
OPA2690
OPA3690
—
Low-Noise,
High DC Precision
OPA820
OPA2822
—
OPA4820
750W
Figure 1. DC-Coupled, +3.3V ADC Driver
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008.................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
OPA4830
TSSOP-14
PW
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +85°C
OPA4830
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
OPA4830IPW
Rail, 90
OPA4830IPWR
Tape and Reel, 2000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Power Supply
12VDC
Internal Power Dissipation
See Thermal Analysis
Differential Input Voltage
±2.5V
Input Voltage Range (Single Supply)
–0.5V to +VS + 0.3V
Storage Temperature Range: D, PW
–65°C to +125°C
Lead Temperature (soldering, 10s)
+300°C
Maximum Junction Temperature (TJ):
Peak
+150°C
Continuous Operation, Long-Term Reliability
+140°C
ESD Rating:
Human Body Model (HBM)
2000V
Charge Device Model (CDM)
1500V
Machine Model (MM)
(1)
200V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress Ratings only, and functional operations of the device at these and any other conditions
beyond those specified is not supported.
PIN CONFIGURATION
Top View
TSSOP
Output A
1
-Input A
2
A
14
Output D
13
-Input D
D
+Input A
3
12
+Input D
+V
4
11
-V
+Input B
5
10
+Input C
B
C
-Input B
6
9
-Input C
Output B
7
8
Output C
OPA4830
2
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OPA4830
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
OPA4830IPW
TYP
MIN/MAX OVER TEMPERATURE
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
MIN/
MAX
TEST
LEVEL (1)
120
66
64
61
MHz
typ
C
MHz
min
G = +5, VO ≤ 0.2VPP
23
16
14
B
13
MHz
min
G = +10, VO ≤ 0.2VPP
11
8
B
7
6
MHz
min
Gain-Bandwidth Product
G ≥ +10
110
80
B
77
75
MHz
min
Peaking at a Gain of +1
VO ≤ 0.2VPP
6
B
dB
typ
C
Slew Rate
G = +2, 2V Step
560
275
265
255
Rise Time
0.5V Step
3.4
5.9
5.95
6.0
V/µs
min
B
ns
max
Fall Time
0.5V Step
3.6
6.0
6.05
B
6.1
ns
max
G = +2, 1V Step
43
64
B
66
67
ns
max
B
RL = 150Ω
–60
RL ≥ 500Ω
–68
–53
–51
–50
dBc
max
B
–58
–57
–56
dBc
max
RL = 150Ω
B
–59
–50
–49
–48
dBc
max
B
RL ≥ 500Ω
–77
–65
–62
–55
dBc
max
B
Input Voltage Noise
f > 1MHz
9.5
10.6
11.1
11.6
nV/√Hz
max
B
Input Current Noise
f > 1MHz
3.7
4.8
5.3
5.8
pA/√Hz
max
B
0.07
%
typ
C
0.17
°
typ
C
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.2VPP
280
G = +2, VO ≤ 0.2VPP
UNITS
AC PERFORMANCE (see Figure 74)
Small-Signal Bandwidth
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
VO = 2VPP, f = 5MHz
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE (4)
RL = 150Ω
Open-Loop Voltage Gain
74
66
65
64
dB
min
A
Input Offset Voltage
±2
±8
±9.4
±9.8
mV
max
A
±30
±30
µV/°C
max
B
+12
+13
µA
max
A
±44
±46
nA/°C
max
B
±1.3
±1.5
µA
max
A
±5
±5
nA/°C
max
B
Average Offset Voltage Drift
Input Bias Current
VCM = 0V
+5
+10
Input Bias Current Drift
Input Offset Current
VCM = 0V
±0.2
Input Offset Current Drift
±1.1
—
INPUT
Negative Input Voltage (5)
–5.5
–5.4
–5.3
–5.2
V
max
A
Positive Input Voltage (5)
3.2
3.1
3.0
2.9
V
min
A
80
76
74
71
dB
min
A
Common-Mode Rejection Ratio (CMRR)
Input-Referred
Input Impedance
Differential Mode
10 || 2.1
kΩ || pF
typ
C
Common-Mode
400 || 1.2
kΩ || pF
typ
C
OUTPUT
Output Voltage Swing
G = +2, RL = 1kΩ to GND
±4.88
±4.86
±4.85
±4.84
V
min
A
G = +2, RL = 150Ω to GND
±4.64
±4.60
±4.58
±4.56
V
min
A
±82
±63
±58
±53
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
(5)
Output Shorted to Ground
±150
mA
typ
C
G = +2, f ≤ 100kHz
0.06
Ω
typ
C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +19°C at high temperature limit for over
temperature specifications.
Current is considered positive out of pin.
Tested < 3dB below minimum specified CMRR at ± CMIR limits.
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OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
OPA4830IPW
TYP
PARAMETER
CONDITIONS
+25°C
MIN/MAX OVER TEMPERATURE
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
±5.5
±5.5
±5.5
MIN/
MAX
TEST
LEVEL (1)
V
typ
C
V
max
A
UNITS
POWER SUPPLY
Minimum Operating Voltage
±1.4
Maximum Operating Voltage
Maximum Quiescent Current
VS = ±5V, All Channels
17
19
21.4
23.8
mA
max
A
Minimum Quiescent Current
VS = ±5V, All Channels
17
16
14.4
13.2
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
95
°C/W
typ
C
Power-Supply Rejection Ratio (–PSRR)
THERMAL CHARACTERISTICS
Specification: IPW
Thermal Resistance, θJA
PW
4
TSSOP-14
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
OPA4830
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted.
OPA4830IPW
TYP
MIN/MAX OVER TEMPERATURE
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
MIN/
MAX
TEST
LEVEL (1)
100
70
68
66
MHz
typ
C
MHz
min
G = +5, VO ≤ 0.2VPP
21
15
14
B
13
MHz
min
G = +10, VO ≤ 0.2VPP
10
7
B
6
5
MHz
min
Gain-Bandwidth Product
G ≥ +10
100
75
B
65
59
MHz
min
Peaking at a Gain of +1
VO ≤ 0.2VPP
5
B
dB
typ
C
Slew Rate
G = +2, 2V Step
500
270
260
250
Rise Time
0.5V Step
3.4
5.8
5.9
6.0
V/µs
min
B
ns
max
Fall Time
0.5V Step
3.4
5.8
5.9
B
6.0
ns
max
G = +2, 1V Step
44
65
B
67
68
ns
max
B
RL = 150Ω
–56
RL ≥ 500Ω
–62
–50
–49
–48
dBc
max
B
–56
–55
–54
dBc
max
RL = 150Ω
B
–58
–50
–49
–48
dBc
max
B
RL ≥ 500Ω
–84
–65
–62
–60
dBc
max
B
Input Voltage Noise
f > 1MHz
9.2
10.3
10.8
11.3
nV/√Hz
max
B
Input Current Noise
f > 1MHz
3.5
4.6
5.1
5.6
pA/√Hz
max
B
%
typ
C
0.09
°
typ
C
–62
dB
typ
C
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.2VPP
230
G = +2, VO ≤ 0.2VPP
UNITS
AC PERFORMANCE (see Figure 72)
Small-Signal Bandwidth
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
VO = 2VPP, f = 5MHz
NTSC Differential Gain
0.08
NTSC Differential Phase
All Hostile Crosstalk, Input-Referred
DC PERFORMANCE (4)
3 Channels Driven at 5MHz,
1VPP, 4th Channel Measured
RL = 150Ω
Open-Loop Voltage Gain
Input Offset Voltage
72
66
65
64
dB
min
A
±0.5
±6
±7
±7.5
mV
max
A
±24
±24
µV/°C
max
B
+12
+13
µA
max
A
±44
±46
nA/°C
max
B
±1.1
±1.3
µA
max
A
±5
±6
nA/°C
max
B
Average Offset Voltage Drift
Input Bias Current
VCM = 2.5V
+5
+10
Input Bias Current Drift
Input Offset Current
VCM = 2.5V
±0.2
±0.9
Input Offset Current Drift
INPUT
Least Positive Input Voltage (5)
–0.5
–0.4
–0.3
–0.2
V
max
A
Most Positive Input Voltage (5)
3.2
3.1
3.0
2.8
V
min
A
80
76
74
71
dB
min
A
Common-Mode Rejection Ratio (CMRR)
Input-Referred
Input Impedance
Differential-Mode
10 || 2.1
kΩ || pF
typ
C
Common-Mode
400 || 1.2
kΩ || pF
typ
C
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
G = +5, RL = 1kΩ to 2.5V
0.09
0.11
0.12
0.13
V
max
A
G = +5, RL = 150Ω to 2.5V
0.21
0.24
0.25
0.26
V
max
A
G = +5, RL = 1kΩ to 2.5V
4.91
4.89
4.88
4.87
V
min
A
G = +5, RL = 150Ω to 2.5V
4.78
4.75
4.73
4.72
V
min
A
±75
±58
±53
±50
mA
min
A
Current Output, Sourcing and Sinking
Short-Circuit Output Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
(5)
Output Shorted to Either
Supply
±140
mA
typ
C
G = +2, f ≤ 100kHz
0.06
Ω
typ
C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over
temperature specifications.
Current considered positive out of pin.
Tested < 3dB below minimum specified CMRR at ± CMIR limits.
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Product Folder Link(s): OPA4830
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OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted.
OPA4830IPW
TYP
PARAMETER
CONDITIONS
+25°C
MIN/MAX OVER TEMPERATURE
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
+11
+11
+11
MIN/
MAX
TEST
LEVEL (1)
V
typ
C
V
max
A
UNITS
POWER SUPPLY
Minimum Operating Voltage
+2.8
Maximum Operating Voltage
Maximum Quiescent Current
VS = +5V, All Channels
15.6
16.6
19.4
22.2
mA
max
A
Minimum Quiescent Current
VS = +5V, All Channels
15.6
14.8
13.6
12.0
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
95
°C/W
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: IPW
Thermal Resistance, θJA
PW
6
TSSOP-14
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
OPA4830
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = +3V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted.
OPA4830IPW
TYP
MIN/MAX OVER TEMPERATURE
CONDITIONS
+25°C
+25°C (2)
0°C to
+70°C (3)
UNITS
MIN/
MAX
TEST LEVEL (1)
G = +2, VO ≤ 0.2VPP
100
70
66
MHz
min
B
G = +5, VO ≤ 0.2VPP
21
15
14
MHz
min
B
G = +10, VO ≤ 0.2VPP
10
7.5
6.5
MHz
min
B
Gain-Bandwidth Product
G ≥ +10
100
75
65
MHz
min
B
Slew Rate
1V Step
220
135
105
V/µs
min
B
Rise Time
0.5V Step
3.4
5.6
5.7
ns
max
B
Fall Time
0.5V Step
3.4
5.6
5.7
ns
max
B
1V Step
46
73
88
ns
max
B
RL = 150Ω
–60
–56
–54
dBc
max
B
RL ≥ 500Ω
–65
–59
–57
dBc
max
B
RL = 150Ω
–68
–59
–58
dBc
max
B
RL ≥ 500Ω
–76
–65
–64
dBc
max
B
Input Voltage Noise
f > 1MHz
9.2
10.3
10.8
nV/√Hz
max
B
Input Current Noise
f > 1MHz
3.5
4.6
5.1
pA/√Hz
max
B
PARAMETER
AC PERFORMANCE (see Figure 73)
Small-Signal Bandwidth
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
VO = 1VPP, f = 5MHz
DC PERFORMANCE (4)
Open-Loop Voltage Gain
Input Offset Voltage
72
66
65
dB
min
A
±1.5
±7.5
±8.7
mV
max
A
±27
µV/°C
max
B
+12
µA
max
A
±44
nA/°C
max
B
±1.3
µA
max
A
±5
nA/°C
max
B
Average Offset Voltage Drift
Input Bias Current
VCM = 1.0V
+5
+10
Input Bias Current Drift
Input Offset Current
VCM = 1.0V
±0.2
±1.1
Input Offset Current Drift
INPUT
Least Positive Input Voltage (5)
–0.45
–0.4
–0.27
V
max
A
Most Positive Input Voltage (5)
1.2
1.1
1.0
V
min
A
80
74
72
dB
min
A
Common-Mode Rejection Ratio (CMRR)
Input-Referred
Input Impedance
Differential-Mode
10 || 2.1
kΩ || pF
typ
C
Common-Mode
400 || 1.2
kΩ || pF
typ
C
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
G = +5, RL = 1kΩ to 1.5V
0.08
0.11
0.125
V
max
A
G = +5, RL = 150Ω to 1.5V
0.17
0.39
0.40
V
max
A
G = +5, RL = 1kΩ to 1.5V
2.91
2.88
2.85
V
min
A
G = +5, RL = 150Ω to 1.5V
2.82
2.74
2.70
V
min
A
±30
±20
±18
mA
min
A
Current Output, Sourcing and Sinking
Short-Circuit Output Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
(5)
Output Shorted to Either Supply
±45
mA
typ
C
See Figure 73, f < 100kHz
0.06
Ω
typ
C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over
temperature specifications.
Current considered positive out of pin.
Tested < 3dB below minimum specified CMRR at ± CMIR limits.
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
7
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +3V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted.
OPA4830IPW
TYP
PARAMETER
CONDITIONS
+25°C
MIN/MAX OVER TEMPERATURE
+25°C (2)
0°C to
+70°C (3)
+11
+11
MIN/
MAX
TEST LEVEL (1)
V
min
B
V
max
A
UNITS
POWER SUPPLY
Minimum Operating Voltage
+2.8
Maximum Operating Voltage
Maximum Quiescent Current
VS = +3V, All Channels
15
16.4
17.6
mA
max
A
Minimum Quiescent Current
VS = +3V, All Channels
15
13.2
12.4
mA
min
A
Input-Referred
64
60
58
dB
min
A
–40 to +85
°C
typ
C
95
°C/W
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: IPW
Thermal Resistance, θJA
PW
8
TSSOP-14
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TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 74).
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
6
3
G = +1V/V
RF = 0W
0
G = +2V/V
-3
G = +5V/V
-6
G = +10V/V
-9
-12
G = -1
-3
-6
G = -5
-9
G = -10
-12
VO = 0.2VPP
RL = 150W
-15
VO = 0.2VPP
RL = 150W
-15
G = -2
0
Normalized Gain (dB)
3
-18
-18
1
10
100
600
1
10
100
Frequency (MHz)
Figure 2.
Figure 3.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
9
3
6
0
-3
VO = 0.5VPP
Gain (dB)
Gain (dB)
3
0
-3
VO = 0.5VPP
-6
VO = 4VPP
-9
VO = 2VPP
VO = 4VPP
-6
-12
VO = 2VPP
-9
VO = 1VPP
-15
G = +2V/V
RL = 150W
VO = 1VPP
-12
G = -1V/V
RL = 150W
-18
10
100
400
10
Frequency (MHz)
Figure 4.
Figure 5.
NONINVERTING PULSE RESPONSE
0.2
1.5
1.0
0.1
0.5
Small-Signal ±100mV
Left Scale
0
0
-0.1
-0.5
-0.2
-1.0
-0.3
-1.5
G = +2V/V
-0.4
2.0
G = -1V/V
-2.0
Large-Signal Output Voltage (V)
Small-Signal Output Voltage (V)
Large-Signal ±1V
Right Scale
400
INVERTING PULSE RESPONSE
0.4
2.0
0.3
100
Frequency (MHz)
0.4
Small-Signal Output Voltage (V)
400
Frequency (MHz)
0.3
1.5
0.2
1.0
0.1
0.5
0
Small-Signal ±100mV
Left Scale
-0.1
-0.2
-0.3
0
-0.5
Large-Signal ±1V
Right Scale
-0.4
-1.0
-1.5
Large-Signal Output Voltage (V)
Normalized Gain (dB)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
-2.0
Time (10ns/div)
Time (10ns/div)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 74).
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
-40
-45
-55
Harmonic Distortion (dBc)
-60
2nd-Harmonic
-65
-70
-75
G = +2V/V
VO = 2VPP
f = 5MHz
-80
-50
-55
-60
2nd-Harmonic
-65
-70
-75
-80
3rd-Harmonic
-85
3rd-Harmonic
-85
100
-90
1k
2.0
2.5
3.5
Figure 9.
G = +2V/V
RL = 500W
f = 5MHz
-55
2nd-Harmonic
-70
-75
-80
3rd-Harmonic
-85
-60
G = +2V/V
VO = 2VPP
5.5
6.0
-65
2nd-Harmonic
RL = 150W
3rd-Harmonic
RL = 150W
-70
-75
-80
-85
3rd-Harmonic
RL = 500W
-90
2nd-Harmonic
RL = 500W
-95
-100
-105
-95
-110
0.1
1
10
0.1
1
Output Voltage (VPP)
Figure 11.
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-40
PI
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
20MHz
1/4
50W OPA4830
83
13
82
12
PO
500W
-50
10
Frequency (MHz)
Figure 10.
750W
Output Current (mA)
3rd-Order Spurious Level (dBc)
5.0
HARMONIC DISTORTION vs FREQUENCY
-50
-90
-55
750W
-60
10MHz
-65
-70
-75
5MHz
-80
81
11
Output Current (sourcing)
80
10
Output Current (sinking)
79
9
78
8
-85
Quiescent Current (total, both amplifiers)
77
-90
-26
-20
-14
-8
4
-2
6
7
-50
-25
Single-Tone Load Power (2dBm/div)
Figure 12.
10
4.5
Figure 8.
-65
-45
4.0
Supply Voltage (V)
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
3.0
Resistance (W)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-55
G = +2V/V
VO = 2VPP
RL = 500W
Input Limited for VCM = 0V
Supply Current (mA)
Harmonic Distortion (dBc)
-50
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 13.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 74).
RECOMMENDED RS vs CAPACITIVE LOAD
120
CL = 10pF
7
6
5
100
90
CL = 1000pF
4
80
3
2
1
VI
0
1/4
50W OPA4830
VO
1kW
750W
60
40
(1)
750W
-2
70
50
RS
CL
-1
0.1dB Peaking Targeted
110
CL = 100pF
RS (W)
Normalized Gain to Capacitive Load (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD
8
30
NOTE: (1) 1kW is optional.
20
10
-3
1
10
100
1
200
10
Figure 14.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
6
5
5
4
4
3
3
2
-1
Output
Current Limit
RL = 500W
0
-2
-3
-4
-4
-5
-5
100
1k
RL = 100W
-1
-3
10
RL = 50W
1
-2
-6
1W Internal Power Limit, One Channel Only
2
G = +5V/V
VS = ±5V
VO (V)
Output Voltage (V)
OUTPUT SWING vs LOAD RESISTANCE
0
1k
Figure 15.
6
1
100
Capacitive Load (pF)
Frequency (MHz)
Output
Current Limit
-6
-160
-120
1W Internal
Power Limit
-80
-40
0
40
Resistance (W)
IO (mA)
Figure 16.
Figure 17.
80
120
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TYPICAL CHARACTERISTICS: VS = ±5V, Differential Configuration
At TA = +25°C, RF = 604Ω (as shown in Figure 18), and RL = 500Ω, unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
3
+5V
1/4
OPA4830
20W
VI
RG
604W
RG
604W
604W
RG
RL
500W
GD = 1
0
Normalized Gain (dB)
GD =
VO
1/4
OPA4830
GD = 2
-3
-6
GD = 5
-9
GD = 10
-12
20W
VO = 200mVPP
RL = 500W
-15
-5V
1
10
100
200
Frequency (MHz)
Figure 18.
Figure 19.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
-45
9
-50
Harmonic Distortion (dBc)
6
VO = 5VPP
Gain (dB)
3
0
VO = 2VPP
-3
VO = 1VPP
-6
GD = 2
RL = 500W
VO = 200mVPP
-55
3rd-Harmonic
-60
GD = 2
VO = 4VPP
f = 5MHz
-65
-70
-75
-80
-85
-90
2nd-Harmonic
-95
-100
-9
1
10
100
100
200
150
Figure 20.
DIFFERENTIAL DISTORTION vs FREQUENCY
350
400
450
500
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
GD = 2
VO = 4VPP
RL = 500W
-60
3rd-Harmonic
-70
-80
-90
-65
-110
-75
-80
-85
2nd-Harmonic
-90
-95
-105
1
3rd-Harmonic
-70
-100
2nd-Harmonic
0.1
GD = 2
RL = 500W
f = 5MHz
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
300
-55
-100
10
100
1
10
Output Voltage Swing (VPP)
Frequency (MHz)
Figure 22.
12
250
Figure 21.
-40
-50
200
Resistance (W)
Frequency (MHz)
Figure 23.
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2V/V, RF = 750Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 72).
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
6
3
G = +1
RF = 0W
G = -2
0
Normalized Gain (dB)
3
Normalized Gain (dB)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
0
-3
G = +2V/V
G = +10V/V
-6
-9
-12
G = -1
-3
-6
G = -5
-9
G = -10
-12
G = +5V/V
-18
1
VO = 0.2VPP
RL = 150W
-15
VO = 0.2VPP
RL = 150W
-15
-18
10
100
500
1
10
100
300
Frequency (MHz)
Frequency (MHz)
Figure 24.
Figure 25.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
3
9
6
0
3
-3
VO = 0.5VPP
Gain (dB)
0
-3
VO = 1VPP
VO = 0.5VPP
-6
-9
-12
-6
-9
-15
G = +2V/V
RL = 150W
VO = 2VPP
VO = 2VPP
G = -1V/V
RL = 150W
-18
-12
10
100
10
400
Frequency (MHz)
Figure 26.
Figure 27.
NONINVERTING PULSE RESPONSE
3.5
2.7
3.0
2.6
Small-Signal 2.4V to 2.6V
Left Scale
2.5
2.5
2.4
2.0
2.3
1.5
2.2
1.0
G = +2V/V
0.5
2.1
Large-Signal Output Voltage (V)
4.0
2.9
4.5
G = -1V/V
Small-Signal Output Voltage (V)
Small-Signal Output Voltage (V)
Large-Signal 1.5V to 3.5V
Right Scale
300
INVERTING PULSE RESPONSE
4.5
2.9
2.8
100
Frequency (MHz)
2.8
4.0
2.7
3.5
2.6
2.5
3.0
Small-Signal 2.4V to 2.6V
Left Scale
2.4
2.0
2.3
2.2
2.5
1.5
Large-Signal 1.5V to 3.5V
Right Scale
2.1
1.0
Large-Signal Output Voltage (V)
Gain (dB)
VO = 1VPP
0.5
Time (10ns/div)
Time (10ns/div)
Figure 28.
Figure 29.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 72).
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
-55
-50
-55
-60
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
G = +2V/V
VO = 2VPP
-65
-70
3rd-Harmonic
-75
-80
G = +2V/V
VO = 2VPP
f = 5MHz
-85
-60
3rd-Harmonic
RL = 150W
-65
-70
2nd-Harmonic
RL = 150W
-75
-80
-85
-90
-95
3rd-Harmonic
RL = 500W
-100
-90
100
-105
1k
0.1
1
Load Resistance (W)
Figure 31.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs NONINVERTING GAIN
-55
G = +2V/V
RL = 500W
f = 5MHz
-50
-55
2nd-Harmonic
Input Limited
-60
Harmonic Distortion (dBc)
-45
2nd-Harmonic
-65
-70
-75
-80
-85
3rd-Harmonic
-90
-60
-65
-70
-75
-80
3rd-Harmonic
RL = 500W
VO = 2VPP
f = 5MHz
-85
-95
-90
-100
0.1
1
1
10
10
Gain (V/V)
Output Voltage Swing (VPP)
Figure 32.
Figure 33.
HARMONIC DISTORTION vs INVERTING GAIN
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-45
3rd-Order Spurious Level (dBc)
Harmonic Distortion (dBc)
-50
-55
-60
2nd-Harmonic
-65
-70
3rd-Harmonic
-75
RL = 500W
VO = 2VPP
f = 5MHz
1
-50
PI
50W
1/4
OPA4830
PO
20MHz
500W
-55
750W
-60
750W
-65
10MHz
-70
-75
-80
5MHz
-85
-90
-80
14
10
Frequency (MHz)
Figure 30.
Harmonic Distortion (dBc)
2nd-Harmonic
RL = 500W
10
-95
-26
-23
-20
-17
-14
-11
-8
Gain (V/V)
Single-Tone Load Power (dBm)
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 72).
INPUT VOLTAGE AND CURRENT NOISE DENSITY
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
100
Output Impedance (W)
Voltage Noise (nV/ÖHz)
Current Noise (pA/ÖHz)
100
Voltage Noise
(9.2nV/ÖHz)
10
Current Noise
(3.5pA/ÖHz)
10
1
0.1
0.01
1
10
100
1k
10k
100k
1M
1k
10M
10k
100k
Figure 36.
RECOMMENDED RS vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
0.1dB Peaking Targeted
100
RS (W)
90
80
70
60
50
40
30
20
10
10
100
1k
8
CL = 10pF
7
6
CL = 100pF
5
CL = 1000pF
4
3
2
1
VI
50W
0
1/4
OPA4830
RS
VO
CL
-1
-2
750W
NOTE: (1) 1kW is optional.
-3
1
10
VOLTAGE RANGES vs TEMPERATURE
0
5.0
70
-20
4.5
-60
-80
40
-100
Ð (AOL)
-120
Voltage Range (V)
-40
20 log (AOL)
3.5
2.5
2.0
1.0
0
-160
-10
-180
-0.5
-20
-200
-1.0
10k
100k
1M
10M
100M
1G
RL = 150W
1.5
-140
1k
Most Positive Input Voltage
3.0
10
100
Most Positive Output Voltage
4.0
Open-Loop Phase (dB)
Open-Loop Gain (dB)
OPEN-LOOP GAIN AND PHASE
20
300
Figure 39.
80
30
100
Frequency (MHz)
Figure 38.
50
(1)
1kW
750W
Capacitive Load (pF)
60
100M
FREQUENCY RESPONSE vs CAPACITIVE LOAD
110
1
10M
Figure 37.
130
120
1M
Frequency (Hz)
Frequency (Hz)
Least Positive Output Voltage
0.5
0
Least Positive Input Voltage
-50
0
50
110
Ambient Temperature (10°C/div)
Frequency (Hz)
Figure 40.
Figure 41.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 72).
TYPICAL DC DRIFT OVER TEMPERATURE
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
3
6
2
4
1
2
10 ´ Input Offset Current (IOS)
0
0
-1
-2
Input Offset Voltage (VOS)
-2
-4
-3
-6
-4
-25
0
25
50
75
100
90
9.5
85
9.0
Output Current, Sinking
80
8.5
75
8.0
Output Current, Sourcing
70
7.5
65
7.0
125
6.5
-50
-25
Ambient Temperature (°C)
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 42.
Figure 43.
CMRR AND PSRR vs FREQUENCY
OUTPUT SWING vs LOAD RESISTANCE
5.5
90
5.0
80
4.5
70
CMRR
60
50
40
30
4.0
Output Voltage (V)
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
10.0
Quiescent Current
60
-8
-50
10.5
95
Output Current (mA)
Input Offset Voltage (mV)
Input Bias Current (IB)
100
Supply Current (mA)
8
Input Bias and Offset Current (mA)
4
PSRR
3.5
G = +5V/V
3.0
2.5
2.0
1.5
1.0
20
0.5
10
0
0
1k
10k
100k
1M
10M
-0.5
100M
10
100
Frequency (Hz)
Load Resistance (W)
Figure 44.
Figure 45.
1k
CROSSTALK vs FREQUENCY
-30
Input-Referred
Crosstalk (dB)
-40
All Hostile Crosstalk
1VPP Output, 3 Channels
-50
-60
-70
Channel-to-Channel Crosstalk
1VPP Output, 1 Channel
-80
-90
1
10
100
Frequency (MHz)
Figure 46.
16
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TYPICAL CHARACTERISTICS: VS = +5V, Differential Configuration
At TA = +25°C, RF = 604Ω, and RL = 500Ω differential (as shown in Figure 47), unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
3
+5V
GD = 1
1.2kW
0
2.5V
GD = 2
1/4
0.1mF OPA4830
RG
604W
RL
VO
VI
RG
GD =
604W
RG
Normalized Gain (dB)
1.2kW
604W
-3
-6
GD = 5
-9
-12
1/4
OPA4830
GD = 10
VO = 200mVPP
RL = 500W
-15
2.5V
1
10
100
200
Frequency (MHz)
Figure 47.
Figure 48.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
-40
9
-45
Harmonic Distortion (dBc)
6
VO = 3VPP
Gain (dB)
3
VO = 2VPP
0
-3
VO = 1VPP
-6
GD = 2
RL = 500W
VO = 0.2VPP
3rd-Harmonic
-55
GD = 2
VO = 4VPP
f = 5MHz
-60
-65
-70
-75
-80
2nd-Harmonic
-85
-90
-9
1
-50
10
100
100
200
150
Figure 49.
Harmonic Distrtion (dBc)
Harmonic Distortion (dBc)
3rd-Harmonic
-60
2nd-Harmonic
-80
-90
-65
400
450
500
-75
-80
-85
-95
-100
100
2nd-Harmonic
-90
-110
10
3rd-Harmonic
-70
-100
1
350
GD = 2
RL = 500W
f = 5MHz
-60
-50
-70
300
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
-55
GD = 2
VO = 4VPP
RL = 500W
-40
250
Figure 50.
DIFFERENTIAL DISTORTION vs FREQUENCY
-30
200
Resistance (W)
Frequency (MHz)
1
10
Output Voltage Swing (VPP)
Frequency (MHz)
Figure 51.
Figure 52.
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TYPICAL CHARACTERISTICS: VS = +3V
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 73).
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
6
3
Normalized Gain (dB)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
6
G = +1V/V
RF = 0W
3
-3
G = +2V/V
G = +10V/V
-6
Normalized Gain (dB)
0
G = +5V/V
-9
-12
RL = 150W
VO = 0.2VPP
-15
-3
G = -2
-6
-9
G = -10
-12
10
100
G = -5
RL = 150W
VO = 0.2VPP
-15
-18
1
G = -1
0
-18
400
1
10
100
300
Frequency (MHz)
Frequency (MHz)
Figure 53.
Figure 54.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
9
3
VO = 0.5VPP
VO = 1VPP
6
0
3
-3
VO = 0.5VPP
0
Gain (dB)
-3
-6
-9
VO = 1.5VPP
-6
-9
-12
G = +2V/V
RL = 150W
-15
VO = 1.5VPP
-12
G = -1V/V
RL = 150W
-18
100
10
300
10
Frequency (MHz)
Figure 55.
Figure 56.
NONINVERTING PULSE RESPONSE
1.10
1.50
1.05
1.25
Small-Signal
0.95V to 1.05V
Left Scale
1.00
0.95
0.90
0.85
1.75
1.00
0.75
0.50
0.25
G = +2V/V
0.80
0
1.20
Small-Signal Output Voltage (V)
Large-Signal 0.5V to 1.5V
Right Scale
2.00
Large-Signal 0.5V to 1.5V
Right Scale
1.15
1.10
1.75
1.50
1.05
1.25
Small-Signal 0.95V to 1.05V
Left Scale
1.00
1.00
0.95
0.75
0.90
0.50
0.85
0.25
G = -1V/V
0.80
Time (10ns/div)
0
Time (10ns/div)
Figure 57.
18
300
INVERTING PULSE RESPONSE
2.00
Large-Signal Output Voltage (V)
Small-Signal Output Voltage (V)
1.20
1.15
100
Frequency (MHz)
Large-Signal Output Voltage (V)
Gain (dB)
VO = 1VPP
Figure 58.
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TYPICAL CHARACTERISTICS: VS = +3V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 73).
HARMONIC DISTORTION vs LOAD RESISTANCE
G = +2V/V
VO = 1VPP
f = 5MHz
-55
2nd-Harmonic
-60
-65
-70
3rd-Harmonic
-75
-50
-55
-60
Input Limited
-65
-70
2nd-Harmonic
-75
3rd-Harmonic
-80
-80
-85
-85
-90
100
Figure 59.
Figure 60.
HARMONIC DISTORTION vs FREQUENCY
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-40
3rd-Harmonic
RL = 150W
-70
2nd-Harmonic
RL = 150W
-75
-80
-85
-90
3rd-Harmonic
RL = 500W
-95
PI
-45
1/4
PO
50W OPA4830
-50
500W
750W
-55
20MHz
-60
750W
-65
-70
10MHz
-75
-80
5MHz
-85
-90
-100
0.1
1
-26
10
-23
Frequency (MHz)
-20
150
130
110
90
70
50
30
10
100
1k
Normalized Gain to Capacitive Load (dB)
0.1dB Peaking Targeted
10
-11
-8
FREQUENCY RESPONSE vs CAPACITIVE LOAD
170
1
-14
Figure 62.
RECOMMENDED RS vs CAPACITIVE LOAD
190
-17
Single-Tone Load Power (dBm)
Figure 61.
RS (W)
10
Output Voltage Swing (VPP)
2nd-Harmonic
RL = 500W
-65
1
Resistance (W)
G = +2V/V
VO = 1VPP
-60
0.1
1k
3rd-Order Spurious Level (dBc)
-55
Harmonic Distortion (dBc)
G = +2V/V
RL = 500W
f = 5MHz
-45
Normalized Gain (dB)
Harmonic Distortion (dBc)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-40
-50
8
CL = 10pF
7
CL = 100pF
6
5
CL = 1000pF
4
3
2
1
VI
50W
0
1/4
OPA4830
RS
VO
CL
1kW
(1)
750W
-1
750W
-2
NOTE: (1) 1kW is optional.
-3
1
Capacitive Load (pF)
10
100
200
Frequency (MHz)
Figure 63.
Figure 64.
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TYPICAL CHARACTERISTICS: VS = +3V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 73).
OUTPUT SWING vs LOAD RESISTANCE
3.5
3.0
Output Voltage (V)
2.5
2.0
G = +5V/V
1.5
1.0
0.5
0
-0.5
10
100
1k
Load Resistance (W)
Figure 65.
20
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TYPICAL CHARACTERISTICS: VS = +3V, Differential Configuration
At TA = +25°C, RF = 604Ω, and RL = 500Ω differential (as shown in Figure 66), unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
3
+3V
1V
1kW
0.1mF
RD
0
Normalized Gain (dB)
2kW
604W
GD =
RG
1/4
OPA4830
604W
RL
VO
VI
RD
604W
-3
GD = 2
-6
GD = 5
-9
GD = 10
-12
1/4
OPA4830
1V
GD = 1
-15
VO = 200mVPP
RL = 500W
1
10
100
200
Frequency (MHz)
Figure 66.
Figure 67.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
-40
9
-45
Gain (dB)
3
Harmonic Distortion (dBc)
6
VO = 2VPP
0
VO = 1VPP
-3
VO = 200mVPP
-6
-55
3rd-Harmonic
GD = 2
VO = 4VPP
f = 5MHz
-60
-65
-70
-75
-80
2nd-Harmonic
-85
GD = 2
-9
-50
-90
1
10
100
200
100
150
200
250
Figure 68.
-55
GD = 2
VO = 2VPP
RL = 500W
-65
400
450
500
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
-75
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-45
350
Figure 69.
DIFFERENTIAL DISTORTION vs FREQUENCY
-35
300
Resistance (W)
Frequency (MHz)
3rd-Harmonic
-75
-85
-95
2nd-Harmonic
-80
GD = 2
RL = 500W
f = 5MHz
3rd-Harmonic
-85
2nd-Harmonic
-90
-95
-105
-115
0.1
1
10
100
-100
0.50
0.75
1.00
1.25
1.50
Frequency (MHz)
Output Voltage Swing (VPP)
Figure 70.
Figure 71.
1.75
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OPA4830
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APPLICATION INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The OPA4830 is a unity-gain stable, very high-speed
voltage-feedback op amp designed for single-supply
operation (+3V to +10V). The input stage supports
input voltages below ground and to within 1.7V of the
positive supply. The complementary common-emitter
output stage provides an output swing to within 25mV
of ground and the positive supply. The OPA4830 is
compensated to provide stable operation with a wide
range of resistive loads.
Figure 72 shows the ac-coupled, gain of +2V/V
configuration
used
for
the
+5V
Electrical
Characteristics and Typical Characteristics. For test
purposes, the input impedance is set to 50Ω with a
resistor to ground. Voltage swings reported in the
Electrical Characteristics are taken directly at the
input and output pins. For the circuit of Figure 72, the
total effective load on the output at high frequencies
is 150Ω || 1500Ω. The 1.5kΩ resistors at the
noninverting input provide the common-mode bias
voltage. This parallel combination equals the dc
resistance at the inverting input (RF), reducing the dc
output offset because of input bias current.
Figure 73 shows the ac-coupled, gain of +2V/V
configuration
used
for
the
+3V
Electrical
Characteristics and Typical Characteristics. For test
purposes, the input impedance is set to 50Ω with a
resistor to ground. Voltage swings reported in the
Electrical Characteristics are taken directly at the
input and output pins. For the circuit of Figure 73, the
total effective load on the output at high frequencies
is 150Ω || 1500Ω. The 1.13kΩ and 2.26kΩ resistors
at the noninverting input provide the common-mode
bias voltage. The parallel combination equals the dc
resistance at the inverting input (RF), reducing the dc
output offset as a result of input bias current.
VS = +3V
6.8mF
+
2.26kW
0.1mF
VIN
53.6W
1.50kW
0.1mF
VIN
53.6W
+1V
1.13kW
RG
750W
+VS/3
0.1mF
1/4
OPA4830
VOUT
RL
150W
VS = +5V
6.8mF
+
0.1mF
RF
750W
+VS
3
Figure 73. AC-Coupled, G = +2V/V, +3V
Single-Supply Specification and Test Circuit
2.5V
1.50kW
1/4
OPA4830
VOUT
RL
150W
RG
750W
RF
750W
+VS/2
+VS
2
Figure 72. AC-Coupled, G = +2V/V, +5V
Single-Supply Specification and Test Circuit
22
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Figure 74 illustrates the dc-coupled, gain of +2V/V,
dual power-supply circuit configuration used as the
basis of the ±5V Electrical Characteristics and Typical
Characteristics. For test purposes, the input
impedance is set to 50Ω with a resistor to ground and
the output impedance is set to 150Ω with a series
output resistor. Voltage swings reported in the
specifications are taken directly at the input and
output pins. For the circuit of Figure 74, the total
effective load is 150Ω
1.5kΩ. Two optional
components are included in Figure 74. An additional
resistor (348Ω) is included in series with the
noninverting input. Combined with the 25Ω dc source
resistance looking back towards the signal generator,
this gives an input bias current cancelling resistance
that matches the 375Ω source resistance seen at the
inverting input (see the DC Accuracy and Offset
Control section). In addition to the usual power-supply
decoupling capacitors to ground, a 0.01µF capacitor
is included between the two power-supply pins. In
practical printed circuit board layouts, this optional
capacitor typically improves the 2nd-harmonic
distortion performance by 3dB to 6dB.
DC LEVEL-SHIFTING
Figure 75 shows a DC-coupled noninverting amplifier
that level-shifts the input up to accommodate the
desired output voltage range. Given the desired
signal gain (G), and the amount VOUT needs to be
shifted up (ΔVOUT) when VIN is at the center of its
range, Equation 1 and Equation 2 give the resistor
values that produce the desired performance.
Assume that R4 is between 200Ω and 1.5kΩ.
NG = G + VOUT/VS
R1 = R4/G
R2 = R4/(NG - G)
R3 = R4/(NG - 1)
(1)
where:
NG = 1 + R4/R3
VOUT = (G)VIN + (NG - G)VS
(2)
Make sure that VIN and VOUT stay within the specified
input and output voltage ranges.
+VS
+5V
0.1mF
R2
6.8mF
+
R1
VIN
50W Source
348W
1/4
OPA4830
VIN
VO
1/4
OPA4830
50W
0.01mF
R3
RF
750W
RG
750W
+
6.8mF
VOUT
150W
Figure 75. DC Level-Shifting
0.1mF
-5V
Figure 74. DC-Coupled, G = +2V/V, Bipolar Supply
Specification and Test Circuit
R4
The circuit on the front page is a good example of
this type of application. It was designed to take VIN
between 0V and 0.5V and produce VOUT between 1V
and 2V when using a +3V supply. This output means
G = 2.00, and ΔVOUT = 1.50V – G × 0.25V = 1.00V.
Plugging these values into Equation 1 and Equation 2
(with R4 = 750Ω) gives: NG = 2.33, R1 = 375Ω, R2 =
2.25kΩ, and R3 = 563Ω. The resistors were changed
to the nearest standard values for the front page
circuit.
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+5V
1.87kW
Video DAC
78.7W
47mF
1/4
OPA4830
75W
VO
75W Load
22mF
845W
325W
528W
650W
Figure 76. Video Line Driver with SAG Correction
Low-power and low-cost video line drivers often
buffer digital-to-analog converter (DAC) outputs with
a gain of 2V/V into a doubly-terminated line. Those
interfaces typically require a dc blocking capacitor.
For a simple solution, that interface often has used a
very large value blocking capacitor (220µF) to limit
tilt, or SAG, across the frames. One approach to
creating a very low high-pass pole location using
much lower capacitor values is shown in Figure 76.
This circuit gives a voltage gain of 2 at the output pin
with a high-pass pole at 8Hz. Given the 150Ω load, a
simple blocking capacitor approach would require a
133µF value. The two much lower valued capacitors
give this same low-pass pole using this simple SAG
correction circuit of Figure 76.
The input is shifted slightly positive in Figure 76 using
the voltage divider from the positive supply. This
configuration gives about a 200mV input dc offset
that shows up at the output pin as a 400mV dc offset
when the DAC output is at zero current during the
sync tip portion of the video signal. This offset acts to
hold the output in its linear operating region. This
circuit then passes on any power-supply noise to the
24
output with a gain of approximately –20dB, so good
supply decoupling is recommended on the
power-supply pin. Figure 77 shows the frequency
response for the circuit of Figure 76. This plot shows
the 8Hz low-frequency high-pass pole and a high-end
cutoff at approximately 100MHz.
3
0
Normalized Gain (dB)
AC-COUPLED OUTPUT VIDEO LINE DRIVER
-3
-6
-9
-12
-15
-18
-21
1
10
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
Frequency (Hz)
Figure 77. Video Line Driver Response to Matched
Load
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NONINVERTING AMPLIFIER WITH REDUCED
PEAKING
Figure 78 shows a noninverting amplifier that reduces
peaking at low gains. The resistor RC compensates
the OPA4830 to have higher noise gain (NG), which
reduces the ac response peaking (typically 5dB at G
= +1V/V without RC) without changing the dc gain.
VIN needs to be a low-impedance source, such as an
op amp. The resistor values are low in order to
reduce noise. Using both RT and RF helps minimize
the impact of parasitic impedances.
VIN
RC
1/4
OPA4830
RG
VOUT
RF
Figure 78. Compensated Noninverting Amplifier
The noise gain can be calculated as shown in
Equation 3, Equation 4, and Equation 5:
RF
G1 = 1 +
RG
(3)
G2 = 1 +
RT +
RF
G1
RC
(4)
NG = G1 ´ G2
The circuit in Figure 72 can be redesigned to have
less peaking by increasing the noise gain to 3. This
increase is accomplished by adding RC = 2.55kΩ
across the op amp inputs.
SINGLE-SUPPLY ACTIVE FILTER
The OPA4830, while operating on a single +3V or
+5V supply, lends itself well to high-frequency active
filter designs. Again, the key additional requirement is
to establish the dc operating point of the signal near
the supply midpoint for highest dynamic range.
Figure 79 shows an example design of a 1MHz
low-pass Butterworth filter using the Sallen-Key
topology.
+5V
RT
circuit gives a noise gain of 2V/V, so the response is
similar to the characteristics plots with G = +2V/V.
Decreasing RC to 20.0Ω increases the noise gain to
3V/V, which typically gives a flat frequency response,
but with less bandwidth.
(5)
A unity-gain buffer can be designed by selecting RT =
RF = 20.0Ω and RC = 40.2Ω (do not use RG). This
Both the input signal and the gain setting resistor are
ac-coupled using 0.1µF blocking capacitors (actually
giving bandpass response with the low-frequency
pole set to 32kHz for the component values shown).
As discussed for Figure 72, this configuration allows
the midpoint bias formed by the two 1.87kΩ resistors
to appear at both the input and output pins. The
midband signal gain is set to +4 (12dB) in this case.
The capacitor to ground on the noninverting input is
intentionally set larger to dominate input parasitic
terms. At a gain of +4, the OPA4830 on a single
supply shows 30MHz small- and large-signal
bandwidth. The resistor values have been slightly
adjusted to account for this limited bandwidth in the
amplifier stage. Tests of this circuit show a precise
1MHz, –3dB point with a maximally-flat passband
(above the 32kHz ac-coupling corner), and a
maximum stop band attenuation of 36dB at the
amplifier –3dB bandwidth of 30MHz.
+5V
100pF
1.87kW
0.1mF
137W
432W
VI
1.87kW
150pF
1/4
OPA4830
4VI
1MHz, 2nd-Order
Butterworth Filter
1.5kW
500W
0.1mF
Figure 79. Single-Supply, High-Frequency Active Filter
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DIFFERENTIAL INTERFACE APPLICATIONS
Dual and quad op amps are particularly suitable to
differential input to differential output applications.
Typically, these op amps fall into either ADC input
interface or line driver applications. Two basic
approaches to differential I/O are noninverting or
inverting configurations. Because the output is
differential, the signal polarity is somewhat
meaningless—the
noninverting
and
inverting
terminology applies here to where the input is brought
into the OPA4830. Each has its advantages and
disadvantages. Figure 80 shows a basic starting point
for noninverting differential I/O applications.
This approach provides for a source termination
impedance that is independent of the signal gain. For
instance, simple differential filters may be included in
the signal path right up to the noninverting inputs
without interacting with the amplifier gain. The
differential signal gain for the circuit of Figure 80 is
shown in Equation 6:
VO
R
= AD = 1 + 2 ´ F
VI
RG
(6)
Various combinations of single-supply or ac-coupled
gains can also be delivered using the basic circuit of
Figure 80. Common-mode bias voltages on the two
noninverting inputs pass on to the output with a gain
of 1V/V because an equal dc voltage at each
inverting node creates no current through RG, giving
that voltage a common-mode gain of 1 to the output.
Figure 81 shows a differential I/O stage configured as
an inverting amplifier. In this case, the gain resistors
(RG) become the input resistance for the source. This
configuration provides a better noise performance
than the noninverting configuration, but does limit the
flexibility in setting the input impedance separately
from the gain.
+VCC
VCM
1/4
OPA4830
Figure 80 shows the recommended value of 750Ω.
However, the gain may be adjusted using just the RG
resistor.
VI
RG
RF
750W
RG
RF
750W
+VCC
VO
1/4
OPA4830
VCM
1/4
OPA4830
-VCC
Figure 81. Inverting Differential I/O Amplifier
RF
750W
VI
RG
RF
750W
VO
1/4
OPA4830
-VCC
Figure 80. Noninverting Differential I/O Amplifier
26
The two noninverting inputs provide an easy
common-mode control input. This control is
particularly useful if the source is ac-coupled through
either blocking caps or a transformer. In either case,
the common-mode input voltages on the two
noninverting inputs again have a gain of 1 to the
output pins, giving an easy common-mode control for
single-supply operation. The input resistors may be
adjusted to the desired gain but also change the input
impedance as well. The differential gain for this circuit
is shown in Equation 7:
R
VO
=- F
RG
VI
(7)
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DC-COUPLED SINGLE-TO-DIFFERENTIAL
CONVERSION
common-mode voltage, VCM, is cut in half and applied
to the noninverting input of the second stage. The
signal path in this stage sees a gain of –1V/V while
this (1/2 × VCM) voltage sees a gain of +2V/V. The
output of this second stage is then the original
common-mode voltage plus the inverted signal from
the output of the first stage. The 2nd stage output
appears directly at the output of the noninverting final
stage. The inverting node of the inverting output
stage is also biased to the common-mode voltage,
equal to the common-mode voltage appearing at the
output of the second stage, creating no current flow
and placing the desired VCM at the output of this
stage as well.
The previous differential output circuits were set up to
receive a differential input as well as provide a
differential output. Figure 82 illustrates one way to
provide a single-to-differential conversion, with dc
coupling, and independent output common-mode
control using a quad op amp.
The circuit of Figure 82 provides several useful
features for isolating the input signal from the final
outputs. Using the first amplifier as a simple
noninverting stage gives an independent adjustment
on RI (to set the source loading) while the gain can
be easily adjusting in this stage using the RG resistor.
The next stage allows a separate output
common-mode level to be set up. The desired output
+5V
1.5V
VCM
200W
1/4
OPA4830
750W VCM
2
VI
RI
1/4
OPA4830
402W
0.1mF
750W
750W
RG
1/4
OPA4830
750W
402W
402W
+VOUT = VCM + VI (1 +
402W
)
RG
-VOUT = VCM - VI (1 +
402W
)
RG
50W
200W
1/4
OPA4830
250W
-5V
Figure 82. Wideband, DC-Coupled, Single-to-Differential Conversion
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100pF
100pF
+5V
161W
77W
121W
100pF
294W
1/4
OPA4830
VO/VI = 4V/V
100pF
1/4
OPA4830
250W
500W
250W
100pF
161W
121W
1/4
OPA4830
PD = 225mW
250W
500W
VI
f-3dB = 10MHz
VO
250W
100pF
77W
294W
100pF
1/4
OPA4830
100pF
-5V
GD = 2, wO = 2p 10MHz, Q = 0.54
GD = 2, wO = 2p 10MHz, Q = 1.31
Figure 83. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter
LOW-POWER, DIFFERENTIAL I/O,
4th-ORDER ACTIVE FILTER
15
While this circuit is bipolar, using ±5V supplies, it can
easily be adapted to single-supply operation. This
configuration adds two real zeroes in the response,
transforming this circuit into a bandpass. The
frequency response for the filter of Figure 83 is
illustrated in Figure 84.
28
Differential Gain (dB)
12
The OPA4830 can give a very capable gain block for
active filters. The quad design lends itself very well to
differential active filters. Where the filter topology is
looking for a simple gain function to implement the
filter, the noninverting configuration is preferred to
isolate the filter elements from the gain elements in
the design. See Figure 83 for an example of a
10MHz, 4th-order Butterworth, low-pass Sallen-Key
filter. The design places the higher Q stage first to
allow the lower Q 2nd stage to roll off the peaked
noise of the first stage. The resistor values have been
adjusted slightly to account for the amplifier group
delay.
9
6
3
0
-3
-6
-9
1
10
Frequency (MHz)
100
Figure 84. Differential 4th-Order, 10MHz
Butterworth Filter
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DUAL-CHANNEL, DIFFERENTIAL ADC
DRIVER
Where a low-noise, single-supply, interface to a
differential input +5V ADC is required, the circuit of
Figure 85 can provide a high dynamic range, medium
gain interface for dual high-performance ADCs. The
circuit of Figure 85 uses two amplifiers in the
differential inverting configuration. The common-mode
voltage is set on the noninverting inputs to the supply
midscale. In this example, the input signal is coupled
in through a 1:2 transformer. This design provides
both signal gain, single to differential conversion, and
a reduction in noise figure. To show a 50Ω input
impedance at the input to the transformer, two 200Ω
resistors are required on the transformer secondary.
These two resistors are also the amplifier gain
elements. Because the same dc voltage appears on
both inverting nodes in the circuit of Figure 85, no dc
current will flow through the transformer, giving a dc
gain of 1 to the output for this common-mode voltage,
VCM.
The circuit of Figure 85 is particularly suitable for a
moderate resolution dual ADC used as I/Q samplers.
The optional 500Ω resistors to ground on each
amplifier output can be added to improve the 2ndand 3rd-harmonic distortion by >15dB if higher
dynamic range is required.
The 5mA added output stage current significantly
improves linearity if that is required. The measured
2nd-harmonic distortion is consistently lower than the
3rd-harmonics for this balanced differential design. It
is particularly helpful for this low-power design if there
are no grounds in the signal path after the low-level
signal at the transformer input. The two pull-down
resistors do show a signal path ground and should be
connected at the same physical point to ground, in
order to eliminate imbalanced ground return currents
from degrading 2nd-harmonic distortion.
VIDEO LINE DRIVING
Most video distribution systems are designed with
75Ω series resistors to drive a matched 75Ω cable. In
order to deliver a net gain of 1 to the 75Ω matched
load, the amplifier is typically set up for a voltage gain
of +2V/V, compensating for the 6dB attenuation of the
voltage divider formed by the series and shunt 75Ω
resistors at either end of the cable.
The circuit of Figure 72 applies to this requirement if
all references to 50Ω resistors are replaced by 75Ω
values. Often, the amplifier gain is further increased
to 2.2, which recovers the additional dc loss of a
typical long cable run. This change would require the
gain resistor (RG) in Figure 72 to be reduced from
750Ω to 625Ω. In either case, both the gain flatness
and the differential gain/phase performance of the
OPA4830 provide exceptional results in video
distribution applications. Differential gain and phase
measure the change in overall small-signal gain and
phase for the color sub-carrier frequency (3.58MHz in
NTSC systems) versus changes in the large-signal
output level (which represents luminance information
in a composite video signal). The OPA4830, with the
typical 150Ω load of a single matched video cable,
shows less than 0.07%/0.17° differential gain/phase
errors over the standard luminance range for a
positive video (negative sync) signal. Similar
performance would be observed for multiple video
signals (see Figure 86).
+5V
1kW
VCM
0.1mF
1kW
1/4
OPA4830
Dual ADC
500W
1:2
50W
Source
200W
800W
RS
200W
800W
RS
16.7dB
Noise Figure
Gain = 8V/V
18dB
CL
1 of 2
Channels
1/4
OPA4830
500W
VCM
Figure 85. Single-Supply Differential ADC Driver (1 of 2 channels)
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625W
750W
75W Transmission Line
1/4
OPA4830
75W
VOUT
Video
Input
75W
75W
75W
VOUT
75W
High output current drive capability allows three
back-terminated 75W transmission lines to be simultaneously driven.
75W
VOUT
75W
Figure 86. Video Distribution Amplifier
4-CHANNEL DAC TRANSIMPEDANCE
AMPLIFIER
High-frequency Digital-to-Analog Converters (DACs)
require a low-distortion output amplifier to retain the
SFDR performance into real-world loads. Figure 87
illustrates
a
single-ended
output
drive
implementation. In this circuit, only one side of the
complementary output drive signal is used. The
diagram shows the signal output current connected
into the virtual ground-summing junction of the
OPA4830, which is set up as a transimpedance stage
or I-V converter. The unused current output of the
DAC is connected to ground. If the DAC requires its
outputs to be terminated to a compliance voltage
other than ground for operation, then the appropriate
voltage level may be applied to the noninverting input
of the OPA4830.
1/4
OPA4830
High-Speed
DAC
VO = ID RF
RF
CF
ID
CD
GBP ® Gain Bandwidth
Product (Hz) for the OPA4830.
ID
Figure 87. Wideband, Low-Distortion DAC
Transimpedance Amplifier
30
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The dc gain for this circuit is equal to RF. At high
frequencies, the DAC output capacitance (CD)
produces a zero in the noise gain for the OPA4830
that may cause peaking in the closed-loop frequency
response. CF is added across RF to compensate for
this noise-gain peaking. To achieve a flat
transimpedance frequency response, this pole in the
feedback network should be set to:
1
GBP
=
2pRFCF
4pRFCD
which gives a
approximately:
GBP
f-3dB =
2pRFCD
corner
frequency
f–3dB
of
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Because the OPA4830 is a unity-gain stable,
voltage-feedback op amp, a wide range of resistor
values may be used for the feedback and gain setting
resistors. The primary limits on these values are set
by dynamic range (noise and distortion) and parasitic
capacitance considerations. For a noninverting
unity-gain follower application, the feedback
connection should be made with a direct short.
Below 200Ω, the feedback network presents
additional output loading that can degrade the
harmonic distortion performance of the OPA4830.
Above 1kΩ, the typical parasitic capacitance
(approximately 0.2pF) across the feedback resistor
may cause unintentional band limiting in the amplifier
response.
DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
A printed circuit board (PCB) is available to assist in
the initial evaluation of circuit performance using the
OPA4830. The fixture is offered free of charge as
unpopulated PCB, delivered with a user’s guide. The
summary information for this fixture is shown in
Table 2.
Table 2. Demonstration Fixture
PRODUCT
PACKAGE
ORDERING NUMBER
LITERATURE
NUMBER
OPA4830IPW
TSSOP-14
DEM-OPA-TSSOP-4A
SBOU017
The demonstration fixture can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA4830 product folder.
MACROMODELS AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using
SPICE is often a quick way to analyze the
performance of the OPA4830 and its circuit designs.
This approach is particularly true for video and RF
amplifier circuits where parasitic capacitance and
inductance can play a major role on circuit
performance. A SPICE model for the OPA4830 is
available through the TI web page (www.ti.com). Note
that this model is the OPA830 model applied to the
OPA4830 quad version. The applications department
is also available for design assistance. These models
predict typical small-signal ac, transient steps, dc
performance, and noise under a wide variety of
operating conditions. The models include the noise
terms found in the electrical specifications of the data
sheet. This model does not attempt to distinguish
between the package types in their small-signal ac
performance.
A good rule of thumb is to target the parallel
combination of RF and RG (see Figure 74) to be less
than about 400Ω. The combined impedance RF || RG
interacts with the inverting input capacitance, placing
an additional pole in the feedback network, and thus
a zero in the forward response. Assuming a 2pF total
parasitic on the inverting node, holding RF || RG <
400Ω keeps this pole above 200MHz. By itself, this
constraint implies that the feedback resistor RF can
increase to several kΩ at high gains. This increase is
acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out
of the frequency range of interest.
In the inverting configuration, an additional design
consideration must be noted. RG becomes the input
resistor and therefore the load impedance to the
driving source. If impedance matching is desired, RG
may be set equal to the required termination value.
However, at low inverting gains, the resulting
feedback resistor value can present a significant load
to the amplifier output. For example, an inverting gain
of 2 with a 50Ω input matching resistor (= RG) would
require a 100Ω feedback resistor, which would
contribute to output loading in parallel with the
external load. In such a case, it would be preferable
to increase both the RF and RG values, and then
achieve the input matching impedance with a third
resistor to ground (see Figure 88). The total input
impedance becomes the parallel combination of RG
and the additional shunt resistor.
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BANDWIDTH VS GAIN:
NONINVERTING OPERATION
Voltage-feedback op amps exhibit decreasing
closed-loop bandwidth as the signal gain is
increased. In theory, this relationship is described by
the gain bandwidth product (GBP) shown in the
Electrical Characteristics. Ideally, dividing GBP by the
noninverting signal gain (also called the noise gain, or
NG) predicts the closed-loop bandwidth. In practice,
this calculation only holds true when the phase
margin approaches 90°, as it does in high-gain
configurations. At low gains (increased feedback
factors), most amplifiers exhibit a more complex
response with lower phase margin. The OPA4830 is
compensated to give a slightly peaked response in a
noninverting gain of 2V/V (see Figure 74). This
compensation results in a typical gain of +2V/V
bandwidth of 110MHz, far exceeding that predicted
by dividing the 110MHz GBP by 2V/V. Increasing the
gain causes the phase margin to approach 90° and
the bandwidth to more closely approach the predicted
value of (GBP/NG). At a gain of +10V/V, the 11MHz
bandwidth illustrated in the Electrical Characteristics
agrees with that predicted using the simple formula
and the typical GBP of 110MHz.
Frequency response in a gain of +2V/V may be
modified to achieve exceptional flatness simply by
increasing the noise gain to 3V/V. One way to do this,
without affecting the +2V/V signal gain, is to add a
2.55kΩ resistor across the two inputs (see Figure 78).
A similar technique may be used to reduce peaking in
unity-gain (voltage follower) applications. For
example, by using a 750Ω feedback resistor along
with a 750Ω resistor across the two op amp inputs,
the voltage follower response is similar to the gain of
+2V/V response of Figure 73. Further reducing the
value of the resistor across the op amp inputs further
dampens the frequency response because of
increased noise gain. The OPA4830 exhibits minimal
bandwidth reduction going to single-supply (+5V)
operation as compared with ±5V. This minimal
reduction is because the internal bias control circuitry
retains nearly constant quiescent current as the total
supply voltage between the supply pins changes.
INVERTING AMPLIFIER OPERATION
All of the familiar op amp application circuits are
available with the OPA4830 to the designer. See
Figure 88 for a typical inverting configuration where
the I/O impedances and signal gain from Figure 72
are retained in an inverting circuit configuration.
Inverting operation is one of the more common
requirements and offers several performance
32
benefits. It also allows the input to be biased at VS/2
without any headroom issues. The output voltage can
be independently moved to be within the output
voltage range with coupling capacitors, or bias
adjustment resistors.
+5V
0.1mF
+
6.8mF
2RT
1.5kW
0.1mF
50W Source
0.1mF
2RT
1.5kW
RG
374W
1/4
OPA4830
150W
+VS
2
RF
750W
RM
57.6W
Figure 88. AC-Coupled, G = –2V/V Example Circuit
In the inverting configuration, three key design
considerations must be noted. The first consideration
is that the gain resistor (RG) becomes part of the
signal channel input impedance. If input impedance
matching is desired (which is beneficial whenever the
signal is coupled through a cable, twisted pair, long
PCB trace, or other transmission line conductor), RG
may be set equal to the required termination value
and RF adjusted to give the desired gain. This
approach is the simplest and results in optimum
bandwidth and noise performance.
However, at low inverting gains, the resulting
feedback resistor value can present a significant load
to the amplifier output. For an inverting gain of 2,
setting RG to 50Ω for input matching eliminates the
need for RM but requires a 100Ω feedback resistor.
This configuration has the interesting advantage of
the noise gain becoming equal to 2 for a 50Ω source
impedance—the same as the noninverting circuits
considered above. The amplifier output now sees the
100Ω feedback resistor in parallel with the external
load. In general, the feedback resistor should be
limited to the 200Ω to 1.5kΩ range. In this case, it is
preferable to increase both the RF and RG values, as
shown in Figure 88, and then achieve the input
matching impedance with a third resistor (RM) to
ground. The total input impedance becomes the
parallel combination of RG and RM.
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The second major consideration, touched on in the
previous paragraph, is that the signal source
impedance becomes part of the noise gain equation
and thus influences the bandwidth. For the example
in Figure 88, the RM value combines in parallel with
the external 50Ω source impedance (at high
frequencies), yielding an effective driving impedance
of 50Ω || 57.6Ω = 26.8Ω. This impedance is added in
series with RG for calculating the noise gain. The
resulting noise gain is 2.87 for Figure 88, as opposed
to only 2 if RM could be eliminated as discussed
above. The bandwidth is therefore lower for the gain
of –2 circuit of Figure 88 (NG = +2.87) than for the
gain of +2 circuit of Figure 72.
The third important consideration in inverting amplifier
design is setting the bias current cancellation
resistors on the noninverting input (a parallel
combination of RT = 750Ω). If this resistor is set equal
to the total dc resistance looking out of the inverting
node, the output dc error (as a result of the input bias
currents) is reduced to (input offset current) times RF.
With the dc blocking capacitor in series with RG, the
dc source impedance looking out of the inverting
mode is simply RF = 750Ω for Figure 88. To reduce
the additional high-frequency noise introduced by this
resistor and power-supply feed-through, RT is
bypassed with a capacitor.
OUTPUT CURRENT AND VOLTAGES
The OPA4830 provides outstanding output voltage
capability. For the +5V supply, under no-load
conditions at +25°C, the output voltage typically
swings closer than 90mV to either supply rail.
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at
cold startup does the output current and voltage
decrease to the numbers shown in the specification
tables. As the output transistors deliver power, the
junction temperatures increase, decreasing the VBEs
(increasing the available output voltage swing), and
increasing the current gains (increasing the available
output current). In steady-state operation, the
available output voltage and current is always greater
than
that
shown
in
the
over-temperature
specifications, because the output stage junction
temperatures are higher than the minimum specified
operating ambient temperature.
To maintain maximum output stage linearity, no
output short-circuit protection is provided. This
absence of protection is not normally a problem,
because most applications include a series matching
resistor at the output that limits the internal power
dissipation if the output side of this resistor is shorted
to ground. However, shorting the output pin directly to
the adjacent positive power-supply pin (8-pin
packages), in most cases, destroys the amplifier. If
additional short-circuit protection is required, consider
a small series resistor in the power-supply leads. This
resistor reduces the available output voltage swing
under heavy output loads.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance that
may be recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier such as the
OPA4830 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series isolation resistor between the
amplifier output and the capacitive load.
The Typical Characteristics show the recommended
RS versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads
greater than 2pF can begin to degrade the
performance of the OPA4830. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the output pin (see the Board Layout Guidelines
section).
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a
gain of +2, the frequency response at the output pin
is already slightly peaked without the capacitive load,
requiring relatively high values of RS to flatten the
response at the load. Increasing the noise gain also
reduces the peaking (see Figure 78).
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DISTORTION PERFORMANCE
ENI
The OPA4830 provides good distortion performance
into a 150Ω load. Relative to alternative solutions, it
provides exceptional performance into lighter loads
and/or operating on a single +3V supply. Generally,
until the fundamental signal reaches very high
frequency or power levels, the 2nd-harmonic
dominates the distortion with a negligible
3rd-harmonic component. Focusing then on the
2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total
load includes the feedback network; in the
noninverting configuration (see Figure 74) this is sum
of RF + RG, while in the inverting configuration, only
RF needs to be included in parallel with the actual
load.
Running
differential
suppresses
the
2nd-harmonic, as shown in the Differential Typical
Characteristics.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve their slew rate at the expense
of a higher input noise voltage. The 9.2nV/√Hz input
voltage noise for the OPA4830 however, is much
lower than comparable amplifiers. The input-referred
voltage noise and the two input-referred current noise
terms (2.8pA/√Hz) combine to give low output noise
under a wide variety of operating conditions.
Figure 89 shows the op amp noise analysis model
with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current
density terms in either nV/√Hz or pA/√Hz.
1/4
OPA4830
RS
EO
IBN
ERS
RF
4kTRS
RG
4kT
RG
4kTRF
IBI
4kT = 1.6E - 20J
at 290°K
Figure 89. Noise Analysis Model
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 8 shows the
general form for the output noise voltage using the
terms shown in Figure 89:
EO =
2
2
2
2
(ENI + (IBNRS) + 4kTRS)NG + (IBIRF) + 4kTRFNG
(8)
Dividing this expression by the noise gain [ NG = (1 +
RF/RG) ] gives the equivalent input-referred spot noise
voltage at the noninverting input; this result is shown
in Equation 9:
EN =
2
2
ENI + (IBNRS) + 4kTRS +
IBIRF
NG
2
+
4kTRF
NG
(9)
Evaluating these two equations for the circuit and
component values shown in Figure 72 gives a total
output spot noise voltage of 19.3nV/√Hz and a total
equivalent input spot noise voltage of 9.65nV/√Hz.
This value is including the noise added by the
resistors. This total input-referred spot noise voltage
is not much higher than the 9.2nV/√Hz specification
for the op amp voltage noise alone.
34
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DC ACCURACY AND OFFSET CONTROL
THERMAL ANALYSIS
The balanced input stage of a wideband
voltage-feedback op amp allows good output dc
accuracy in a wide variety of applications. The
power-supply current trim for the OPA4830 gives
even tighter control than comparable products.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output dc error
caused by this current. This reduction is achieved by
matching the dc source resistances appearing at the
two inputs. Evaluating the configuration of Figure 74
(which has matched dc input resistances), using
worst-case +25°C input offset voltage and current
specifications, gives a worst-case output offset
voltage equal to Equation 10:
Maximum desired junction temperature sets the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
(NG = noninverting signal gain at dc)
±(NG ´ VOS(MAX)) + (RF ´ IOS(MAX))
= ±(2 ´ 8mV) ´ (375W ´ 1.1mA)
= ±16.41mV
Operating junction temperature (TJ) is given by TA +
PD × θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load; though, for resistive loads connected
to mid-supply (VS/2), PDL is at a maximum when the
output is fixed at a voltage equal to VS/4 or 3VS/4.
Under this condition, PDL = VS2/(16 × RL), where RL
includes feedback network loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
(10)
A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques are based
on adding a dc current through the feedback resistor.
In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
be noninverting, the offset control is best applied as
an inverting summing signal to avoid interaction with
the signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. Bring the dc
offsetting current into the inverting input node through
resistor values that are much larger than the signal
path resistors. This configuration ensures that the
adjustment circuit has minimal effect on the loop gain
and therefore the frequency response.
As a worst-case example, compute the maximum TJ
using an OPA4830 (TSSOP-14 package) in the circuit
of Figure 72 operating at the maximum specified
ambient temperature of +85°C and driving a 150Ω
load at mid-supply.
2
PD = 5V ´ 19mA + 4 ´ 5 /(4 ´ (150W || 750W)) = 295mW
Maximum TJ = +85°C + (0.295W ´ 95°C/W) = +113°C
Although this value is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
dissipation occurs if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
puts a high current through a large internal voltage
drop in the output transistors.
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BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the OPA4830 requires
careful attention to board layout parasitics and
external component types. Recommendations that
optimize performance include:
a) Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
b) Minimize the distance ( < 0.25”) from the
power-supply
pins
to
high-frequency
0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each
power-supply
connection
should
always
be
decoupled with one of these capacitors. An optional
supply decoupling capacitor (0.1µF) across the two
power supplies (for bipolar operation) improves
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components
preserve
the
high-frequency
performance. Resistors should be a very low
reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal film or carbon
composition axially-leaded resistors can also provide
good high-frequency performance. Again, keep the
leads and PCB traces as short as possible. Never
use wire-wound type resistors in a high-frequency
application. Because the output pin and inverting
input pin are the most sensitive to parasitic
capacitance, always position the feedback and series
output resistor, if any, as close as possible to the
output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side
of the board between the output and inverting input
pins. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor values
can create significant time constants that can
degrade performance. Good axial metal film or
surface-mount resistors have approximately 0.2pF in
36
shunt with the resistor. For resistor values > 1.5kΩ,
this parasitic capacitance can add a pole and/or zero
below 500MHz that can effect circuit operation. Keep
resistor values as low as possible consistent with
load driving considerations. The 750Ω feedback used
in the Typical Characteristics is a good starting point
for design.
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the typical characteristic curve
Recommended RS vs Capacitive Load (Figure 15,
Figure 38, or Figure 63). Low parasitic capacitive
loads (< 5pF) may not need an RS because the
OPA4830 is nominally compensated to operate with a
2pF parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and
in fact, a higher impedance environment improves
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
(based on board material and trace dimensions), a
matching series resistor into the trace from the output
of the OPA4830 is used as well as a terminating
shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the
input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in this
case and set the series resistor value as shown in the
typical characteristic curve Recommended RS vs
Capacitive Load (Figure 15, Figure 38, or Figure 63).
This configuration does not preserve signal integrity
as well as a doubly-terminated line. If the input
impedance of the destination device is low, there will
be some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
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Product Folder Link(s): OPA4830
OPA4830
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
e) Socketing a high-speed part is not
recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA4830 directly onto the
board.
+VCC
External
Pin
Internal
Circuitry
-VCC
Figure 90. Internal ESD Protection
INPUT AND ESD PROTECTION
The OPA4830 is built using a very high-speed,
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 90.
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (that is, in systems with ±15V supply parts
driving into the OPA4830), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible, because
high values degrade both noise performance and
frequency response.
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
37
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008.................................................................................................................................................... www.ti.com
Revision History
Changes from Original (December 2006) to Revision A ................................................................................................ Page
•
38
Changed rating for storage temperature range in Absolute Maximum Ratings table from –40°C to +125°C to –65°C
to +125°C............................................................................................................................................................................... 2
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA4830IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4830
OPA4830IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4830
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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