OPA549-HiRel
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SLOS744 – MAY 2012
HIGH-VOLTAGE, HIGH-CURRENT OPERATIONAL AMPLIFIER
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FEATURES
1
•
•
•
•
•
•
•
•
•
High Output Current:
– 8-A Continuous
– 10-A Peak
Wide Power Supply Range:
– Single Supply: 8 V to 60 V
– Dual Supply: ±4 V to ±30 V
Wide Output Voltage Swing
Fully Protected:
– Thermal Shutdown
– Adjustable Current
Output Disable Control
Thermal Shutdown Indicator
High Slew Rate: 9 V/µs
Control Reference Pin
11-Lead Power Package
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C),
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
V+
OPA549
VO
ILIM
Ref
APPLICATIONS
•
•
•
•
•
•
Valve, Actuator Drivers
Synchro, Servo Drivers
Power Supplies
Test Equipment
Transducer Excitation
Audio Power Amplifiers
RCL
RCL sets the current limit
value from 0A to 10A.
(Very Low Power Dissipation)
ES Pin
E/S
Forced Low: Output disabled.
Indicates Low: Thermal shutdown.
V–
(1)
Additional temperature ranges available - contact factory
DESCRIPTION
The OPA549 is a low-cost, high-voltage and high-current operational amplifier ideal for driving a wide variety of
loads. This laser-trimmed monolithic integrated circuit provides excellent low-level signal accuracy and high
output voltage and current.
The OPA549 operates from either single or dual supplies for design flexibility. The input common-mode range
extends below the negative supply.
The OPA549 is internally protected against over-temperature conditions and current overloads. In addition, the
OPA549 provides an accurate, user-selected current limit. Unlike other designs which use a power resistor in
series with the output current path, the OPA549 senses the load indirectly. This allows the current limit to be
adjusted from 0 A to 10 A with a resistor or potentiometer, or controlled digitally with a voltage-out or current-out
digital-to-analog converter (DAC).
The enable/status (E/S) pin provides two functions. It can be monitored to determine if the device is in thermal
shutdown, and it can be forced low to disable the output stage and effectively disconnect the load.
The OPA549 is available in an 11-lead power package. Its copper tab allows easy mounting to a heat sink for
excellent thermal performance. Operation is specified over the temperature range of −55°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
OPA549-HiRel
SLOS744 – MAY 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TCASE
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 125°C
KVC
OPA549MKVC
OPA549M
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Tab connected to V–. Do not use to conduct current.
2
1
3
4
6
8
+In
Ref
ILIM
5
7
–In
VO
10
11
9
E/S
V–
V+
Connect both pins 1 and 2 to output.
Connect both pins 5 and 7 to V–.
Connect both pins 10 and 11 to V+.
Figure 1. Connection Diagram
ABSOLUTE MAXIMUM RATINGS (1)
Output current
See Figure 8
V+ to V-
Supply voltage
60 V
VI
Input voltage range
(V−) − 0.5 V to (V+) + 0.5 V
Input voltage reference maximum
(V+) - 8
Input shutdown voltage
Ref - 0.5 V to V+
TOP
Operating temperature
−55°C to 125°C
Tstg
Storage temperature
−55°C to 125°C
TJ
Junction temperature
ESD
(1)
2
150°C
Lead temperature
Soldering, 10 s
300°C
Electrostatic discharge rating
Human Body Model
2000 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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THERMAL INFORMATION
OPA549
THERMAL METRIC (1)
KVC
UNITS
11 PINS
Junction-to-ambient thermal resistance (2)
θJA
21.5
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
9.2
ψJT
Junction-to-top characterization parameter (5)
1.5
ψJB
Junction-to-board characterization parameter (6)
9.2
θJCbot
Junction-to-case (bottom) thermal resistance (7)
0.1
17.4
°C/W
xxx
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ELECTRICAL CHARACTERISTICS
At TCASE = 25°C, VS = ±30V, Ref = 0V, and and E/S pin open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±1
±5
mV
±7
mV
OFFSET VOLTAGE
VCM = 0 V, IO = 0 A, TCASE = 25°C
VOS
Input offset voltage
dVOS/ dT
Input offset voltage drift
VCM = 0 V, IO = 0 A,
TCASE = -55°C to 125°C
PSRR
Input offset voltage vs power
supply
VS = ±4 V to ±30 V, Ref = V–,
TCASE = -55°C to 125°C
VCM = 0 V, IO = 0 A,
TCASE = -55°C to 125°C
±20
25
µV/°C
100
µV/V
INPUT BIAS CURRENT
IB
Input bias current (1)
VCM = 0 V, TCASE = -55°C to 125°C
-100
-500
nA
IOS
Input offset current
VCM = 0 V, TCASE = -55°C to 125°C
±5
±100
nA
en
Input voltage noise density
f = 1 kHz
705
nV/√Hz
in
Input current noise density
f = 1 kHz
1
pA/√Hz
NOISE
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
Linear operation; Positive,
TCASE = -55°C to 125°C
(V+) – 3
(V+) - 2.3
Linear operation; Negative,
TCASE = -55°C to 125°C
(V-) – 0.1
(V-) – 0.2
78
95
VCM = (V-) - 0.1 V to (V+) - 3 V,
TCASE = -55°C to 125°C
V
dB
INPUT IMPEDANCE
(1)
Differential
107 || 6
Ω || pF
Common-mode
109 || 4
Ω || pF
Positive conventional current is defined as flowing into the terminal.
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ELECTRICAL CHARACTERISTICS (continued)
At TCASE = 25°C, VS = ±30V, Ref = 0V, and and E/S pin open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
100
110
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VO = ±25 V, RL = 1 kΩ,
TCASE = -55°C to 125°C
VO = ±25 V, RL = 4 Ω
dB
100
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
G = 1, 50-Vp-p step, RL = 4 Ω
Full-power bandwidth
0.9
MHz
9
V/µs
See Typical Characteristics
tS
Settling time
±0.1%, G = -10, 50-V step
THD+N
Total harmonic distortion +
noise (2)
f = 1 kHz, RL = 4 Ω, G = 3, Power = 25 W
20
µs
0.015
%
OUTPUT
Voltage output
Maximum continuous current
output (3)
IO = 2 A, TCASE = -55°C to 125°C
(V+) - 3.7
(V+) - 2.7
IO = -2 A, TCASE = -55°C to 125°C
(V-) + 1.8
(V-) + 1.4
IO = 8 A, TCASE = -55°C to 125°C
(V+) - 5.0
(V+) - 4.3
IO = -8 A, TCASE = -55°C to 125°C
(V-) + 4.9
(V-) + 3.9
RL = 8 Ω to V-, TCASE = -55°C to 125°C
(V-) + 0.4
(V-) + 0.1
dc
±8
ac; Waveform cannot exceed 10-A peak
0 to ±10
RCL = 7.5 kΩ (ILIM = ±5 A), RL = 4 Ω
Capacitive load drive
(stable operation)
Output disabled leakage
current
A rms
A
ILIM = 15800 x 4.75 V/(7500 Ω + RCL)
Output current limit equation
CLOAD
A
8
Output current limit range
Output current limit
tolerance (4)
V
±200
A
±600
mA
2000
µA
See Typical Characteristics
VO = 0 V, TCASE = -55°C to 125°C
-2000
Output disabled capacitance
±200
750
pF
OUTPUT ENABLE/STATUS (E/S) PIN
Shutdown input mode VE/S
high (output enabled)
E/S pin open or forced high
(Ref) + 2.4
V
Shutdown input mode VE/S low
E/S pin forced low
(output disabled)
4
V
Shutdown input mode IE/S high
E/S pin indicates high
(output enabled)
-50
µA
Shutdown input mode IE/S low
(output disabled)
-55
µA
Ouput disable time
1
µs
Output enable time
3
µs
(Ref) + 3.5
V
(Ref) + 0.2 (Ref) + 0.8
V
E/S pin indicates low
Thermal shutdown status
output (normal operation)
Sourcing 20 µA
Thermal shutdown status
output (thermally shutdown)
Sinking 5 µA, TJ > 160°C
Junction temperature
(2)
(3)
(4)
(Ref) + 0.8
(Ref) + 2.4
Shutdown
160
Reset from shutdown
140
°C
See Total Harmonic Distortion + Noise vs Frequency in the Typical Characteristics section for additional power levels.
See Safe Operating Area (SOA) in the Typical Characteristics section.
High-speed test at TJ = 25°C
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ELECTRICAL CHARACTERISTICS (continued)
At TCASE = 25°C, VS = ±30V, Ref = 0V, and and E/S pin open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ref (REFERENCE PIN FOR CONTROL SIGNALS)
Voltage range
V-
V
Current (5)
-3.5
mA
POWER SUPPLY
VS
IQ
Specified voltage range
TCASE = -55°C to 125°C
Operating voltage range
(V+) - (V-)
Quiescent current
ILIM connected to Ref IO = 0,
TCASE = -55°C to 125°C
±30
60
±26
Shutdown mode; ILIM connected to Ref
(5)
V
8
±35
V
mA
±6
Positive conventional current is defined as flowing into the terminal.
xxx
Estimated Life (Hours)
1000000
100000
10000
1000
55
65
75
85
95
105
115
125
135
145
155
Continuous T J (°C)
A.
See datasheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
C.
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
D.
This curve represents operation with 8-A continuous output current.
Figure 2. OPA549MKVC Operating Life Derating Chart
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TYPICAL CHARACTERISTICS
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
OPEN-LOOP AND PHASE
vs
FREQUENCY
INPUT BIAS CURRENT
vs
TEMPERATURE
120
0
-130
100
-20
-120
80
-40
60
-60
40
-80
20
-100
0
-120
-20
-140
–IB
+I B
-40
1
10
100
1k
10k
f - Frequency - Hz
100k
1M
Input Bias Current - nA
Phase (°)
Gain - dB
-110
-100
-90
-80
-70
-60
-50
-40
-60
-160
10M
-40
-20
CURRENT LIMIT
vs
TEMPERATURE
0
20
40
60
Temperature - °C
80
100
120
140
CURRENT LIMIT
vs
SUPPLY VOLTAGE
9
9
8
8
+ILIM, 8A
–I LIM, 8A
8A
7
6
Current Limit - A
Current Limit - A
7
5A
5
4
3
6
+ILIM, 5A
5
–ILIM, 5A
4
3
2A
+ILIM, 2A
2
2
1
1
0
-75
–ILIM, 2A
0
-50
-25
0
25
50
Temperature - °C
75
100
125
0
5
10
INPUT BIAS CURRENT
vs
COMMON-MODE VOLTAGE
15
20
Supply Voltage - V
25
30
QUIESCENT CURRENT
vs
TEMPERATURE
30
-200
VS = ±30 V
-180
25
Quiescent Current - mA
Input Bias Current - nA
-160
-140
-120
-100
-80
-60
20
VS = ±5 V
15
10
IQ Shutdown (output disabled)
-40
5
-20
-0
-30
6
-20
-10
0
10
Common-Mode Voltage - V
20
30
0
-75
-50
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-25
0
25
50
Temperature - °C
75
100
125
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY
120
PSRR - Power-Supply Rejection Ratio - dB
CMRR - Common-Mode Rejection - dB
100
90
80
70
60
50
40
10
100
1k
Frequency - Hz
10k
100
60
40
+PSRR
20
0
10
100k
-PSRR
80
100
1k
10k
Frequency - Hz
100k
1M
OPEN-LOOP GAIN, COMMON-MODE REJECTION RATIO
AND POWER-SUPPLY REJECTION RATIO
vs
TEMPERATURE
VOLTAGE NOISE DENSITY
vs
FREQUENCY
300
120
250
AOL - CMRR, PSRR - dB
Voltage Noise (nV/√ Hz)
110
200
150
100
AOL
100
PSRR
90
CMRR
50
0
1
10
100
1k
Frequency - Hz
10k
100k
80
-75
-50
0
50
Temperature - °C
100
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
GAIN-BANDWIDTH PRODUCT AND SLEW RATE
vs
TEMPERATURE
1
16
0.9
15
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1
G = +3
RL = 4 W
75W
0.7
13
0.6
12
0.5
11
SR+
0.4
10
0.3
9
0.2
10W
0.1
THD+N - %
14
Slew Rate - V/ms
Gain-Bandwidth Product - MHz
GBW
0.8
1W
0.1W
0.01
8
SR–
0.1
7
0
-75
-50
-25
0
25
50
Temperature - °C
75
100
6
125
0.001
20
100
OUTPUT VOLTAGE SWING
vs
OUTPUT CURRENT
1k
Frequency - Hz
5
IO = +8 A
(V+) – VO
4
4
IO = -8 A
(V–) – VO
|VSUPPLY| - |VOUT| - V
|VSUPPLY| - |VOUT| - V
20k
OUTPUT VOLTAGE SWING
vs
TEMPERATURE
5
3
2
3
IO = +2 A
2
IO = -2 A
1
1
0
0
2
4
6
IO - Output Current - A
8
0
-75
10
-50
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREQUENCY
-25
0
25
50
Temperature - °C
75
100
125
30
40
OUTPUT LEAKAGE CURRENT
vs
APPLIED OUTPUT VOLTAGE
5
30
Leakage current with output disabled.
Maximum output
voltage without
slew rate-induced
distortion.
4
3
Leakage Current - mA
25
VO - Output Voltage - Vp
10k
20
15
10
2
1
RCL =
∞
0
RCL = 0
–1
–2
–3
5
–4
0
1k
100k
10k
1M
–5
-40
-30
Frequency - Hz
8
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-20
-10
0
10
VO - Output Voltage - V
20
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
25
20
20
Offset Voltage - mV
84
76
80
68
72
60
64
52
56
44
48
36
40
24
28
32
0
4.7
3.76
4.23
2.82
3.29
1.88
2.35
0.94
1.41
0
0.47
-0.94
-0.47
-1.88
-1.41
-2.82
-2.35
0
-3.76
0
-3.29
5
-4.7
-4.23
5
16
10
20
10
15
8
12
15
4
Percent of Amplifiers - %
Percent of Amplifiers - %
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
25
Offset Voltage - mV/°C
SMALL-SIGNAL OVERSHOOT
vs
LOAD CAPACITANCE
LARGE-SIGNAL STEP RESPONSE
G = 3, CL = 1000pF
70
60
G = +1
10 V/div
Overshoot - %
50
40
30
20
G = –1
10
0
0
5k
10k
15k
20k
25k
30k
5 µs/div
35k
Load Capacitance - pF
SMALL-SIGNAL STEP RESPONSE
G = 3, CL = 1000pF
50 mV/div
100 mV/div
SMALL-SIGNAL STEP RESPONSE
G = 1, CL = 1000pF
25 ms/div
2.5 ms/div
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APPLICATION INFORMATION
Figure 3 shows the OPA549 connected as a basic noninverting amplifier. The OPA549 can be used in virtually
any operational amplifier configuration.
Power-supply terminals should be bypassed with low series impedance capacitors. The technique shown in
Figure 3, using a ceramic and tantalum type in parallel, is recommended. Power-supply wiring should have low
series impedance.
Be sure to connect both output pins (pins 1 and 2).
V+
10 mF
+
0.1 mF(2)
R2
R1
10, 11
E/S
9
3
1, 2
VO
OPA549
8
VIN
Ref
4
6
ILIM (1)
ZL
5, 7
G = 1+
R2
R1
0.1 mF(2)
10 mF
+
V–
NOTES: (1) ILIM connected to Ref gives the maximum
current limit, 10A (peak). (2) Connect capacitors directly to
package power-supply pins.
Figure 3. Basic Circuit Connections
Power Supplies
The OPA549 operates from single (8-V to 60-V) or dual (±4-V to ±30-V) supplies with excellent performance.
Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly
with operating voltage are shown in the Typical Characteristics. Some applications do not require equal positive
and negative output voltage swing. Power-supply voltages do not need to be equal. The OPA549 can operate
with as little as 8 V between the supplies and with up to 60 V between the supplies. For example, the positive
supply could be set to 55 V with the negative supply at –5 V. Be sure to connect both V– pins (pins 5 and 7) to
the negative power supply, and both V+ pins (pins 10 and 11) to the positive power supply. Package tab is
internally connected to V–; however, do not use the tab to conduct current.
Control Reference (Ref) Pin
The OPA549 features a reference (Ref) pin to which the ILIM and the E/S pin are referred. Ref simply provides a
reference point accessible to the user that can be set to V–, ground, or any reference of the user’s choice. Ref
cannot be set below the negative supply or above (V+) – 8 V. If the minimum VS is used, Ref must be set at V–.
Adjustable Current Limit
The OPA549’s accurate, user-defined current limit can be set from 0 A to 10 A by controlling the input to the ILIM
pin. Unlike other designs, which use a power resistor in series with the output current path, the OPA549 senses
the load indirectly. This allows the current limit to be set with a 0-μA to 633-μA control signal. In contrast, other
designs require a limiting resistor to handle the full output current (up to 10 A in this case).
10
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Although the design of the OPA549 allows output currents up to 10 A, it is not recommended that the device be
operated continuously at that level. The highest rated continuous current capability is 8 A. Continuously running
the OPA549 at output currents greater than 8 A will degrade long-term reliability.
Operation of the OPA549 with current limit less than 1 A results in reduced current limit accuracy. Applications
requiring lower output current may be better suited to the OPA547 or OPA548.
Resistor-Controlled Current Limit
See Figure 4(a) for a simplified schematic of the internal circuitry used to set the current limit. Leaving the ILIM pin
open programs the output current to zero, while connecting ILIM directly to Ref programs the maximum output
current limit, typically 10 A.
With the OPA549, the simplest method for adjusting the current limit uses a resistor or potentiometer connected
between the ILIM pin and Ref according to Equation 1:
75kV
RCL =
- 7.5k W
ILIM
(1)
Refer to Figure 4 for commonly used values.
Digitally-Controlled Current Limit
The low-level control signal (0 μA to 633 μA) also allows the current limit to be digitally controlled by setting
either a current (ISET) or voltage (VSET). The output current ILIM can be adjusted by varying ISET according to
Equation 2:
ILIM
ISET =
15800
(2)
Figure 4(b) demonstrates a circuit configuration implementing this feature.
The output current ILIM can be adjusted by varying VSET according to Equation 3:
(7500W )( ILIM )
VSET = (Re f) + 4.75V 15800
(3)
demonstrates a circuit configuration implementing this feature.
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(b) DAC METHOD (Current or Voltage)
(a) RESISTOR METHOD
Max IO = ILIM
±ILIM =
7500 Ω
4.75 V
(4.75) (15800)
Max IO = ILIM
7500Ω + RCL
±ILIM =15800 ISET
8
6
RCL =
=
Ref
8
RCL
0.01 mF
(optional, for noisy
environments)
6
15800 (4.75 V)
– 7500 Ω
ILIM
75 kΩ
ILIM
7500Ω
4.75 V
ISET
Ref
D/A
ISET = ILIM/15800
VSET = (Ref) + 4.75 V– (7500 Ω) (ILIM)/15800
– 7.5 k Ω
OPA549 CURRENT LIMIT: 0 A to 10 A
DESIRED
CURRENT LIMIT
RESISTOR(1)
(RCL)
CURRENT
(ISET)
VOLTAGE
(VSET)
0A(2)
2.5 A
3A
4A
5A
6A
7A
8A
9A
10 A
ILIM Open
22.6 k Ω
17.4 k Ω
11.3 k Ω
7.5 k Ω
4.99 kΩ
3.24 kΩ
1.87 kΩ
845 Ω
ILIM Connected to Ref
0 mA
158 mA
190 mA
253 mA
316 mA
380 mA
443 mA
506 mA
570 mA
633 mA
(Ref) + 4.75 V
(Ref) + 3.56 V
(Ref) + 3.33 V
(Ref) + 2.85 V
(Ref) + 2.38 V
(Ref) + 1.90 V
(Ref) + 1.43 V
(Ref) + 0.95 V
(Ref) + 0.48 V
(Ref)
NOTES: (1) Resistors are nearest standard 1% values. (2) Offset in the current limit circuitry
may introduce approximately ±0.25 A variation at low current limit values.
Figure 4. Adjustable Current Limit
Enable/Status (E/S) Pin
The enable/status pin provides two unique functions: 1) output disable by forcing the pin low, and 2) thermal
shutdown indication by monitoring the voltage level at the pin. Either or both of these functions can be utilized in
an application. For normal operation (output enabled), the E/S pin can be left open or driven high (at least 2.4 V
above Ref). A small value capacitor connected between the E/S pin and CREF may be required for noisy
applications.
Output Disable
To disable the output, the E/S pin is pulled to a logic low (no greater than 0.8 V above Ref). Typically the output
is shut down in 1 μs. To return the output to an enabled state, the E/S pin should be disconnected (open) or
pulled to at least 2.4 V above Ref. It should be noted that driving the E/S pin high (output enabled) does not
defeat internal thermal shutdown; however, it does prevent the user from monitoring the thermal shutdown
status. Figure 5 shows an example implementing this function.
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This function not only conserves power during idle periods (quiescent current drops to approximately 6 mA) but
also allows multiplexing in multi-channel applications. See Figure 14 for two OPA549s in a switched amplifier
configuration. The on/off state of the two amplifiers is controlled by the voltage on the E/S pin. Under these
conditions, the disabled device will behave like a 750-pF load. Slewing faster than 3 V/μs will cause leakage
current to rapidly increase in devices that are disabled, and will contribute additional load. At high temperature
(125°C), the slewing threshold drops to approximately 2 V/μs. Input signals must be limited to avoid excessive
slewing in multiplexed applications.
OPA549
E/S
Ref
CMOS or TTL
Logic
Ground
Figure 5. Output Disable
Thermal Shutdown Status
The OPA549 has thermal shutdown circuitry that protects the amplifier from damage. The thermal protection
circuitry disables the output when the junction temperature reaches approximately 160°C and allows the device
to cool. When the junction temperature cools to approximately 140°C, the output circuitry is automatically reenabled. Depending on load and signal conditions, the thermal protection circuit may cycle on and off. The E/S
pin can be monitored to determine if the device is in shutdown. During normal operation, the voltage on the E/S
pin is typically 3.5V above Ref. Once shutdown has occurred, this voltage drops to approximately 200 mV above
Ref. Figure 6 shows an example implementing this function.
OPA549
Ref
E/S
HCT
Logic
Ground
E/S pin can interface
with standard HCT logic
inputs. Logic ground is
referred to Ref.
Figure 6. Thermal Shutdown Status
External logic circuitry or an LED can be used to indicate if the output has been thermally shutdown, see
Figure 12.
Output Disable and Thermal Shutdown Status
As mentioned earlier, the OPA549’s output can be disabled and the disable status can be monitored
simultaneously. Figure 7 provides an example of interfacing to the E/S pin.
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Open-drain logic output can disable
the amplifier's output with a logic low.
HCT logic input monitors thermal
shutdown status during normal
operation.
OPA549
E/S
Ref
Open Drain
(Output Disable)
HCT
(Thermal Status
Shutdown)
Logic
Ground
Figure 7. Output Disable and Thermal Shutdown Status
Safe Operating Area
Stress on the output transistors is determined both by the output current and by the output voltage across the
conducting output transistor, VS – VO. The power dissipated by the output transistor is equal to the product of the
output current and the voltage across the conducting transistor, VS – VO. The safe operating area (SOA curve,
Figure 8) shows the permissible range of voltage and current.
20
IO - Output Current - A
10
PD
PD
Output current can
be limited to less
than 8A—see text.
PD
1
=4
=1
=9
0W
T C = 25°C
7W
8W
T C = 85°C
T C = 125°C
Pulse Operation Only
0.1
1
(Limit rms current to ≤ 8A)
2
5
10
20
|VS| - |VO| V
50
100
Figure 8. Safe Operating Area
The safe output current decreases as VS – VO increases. Output short circuits are a very demanding case for
SOA. A short circuit to ground forces the full power-supply voltage (V+ or V–) across the conducting transistor.
Increasing the case temperature reduces the safe output current that can be tolerated without activating the
thermal shutdown circuit of the OPA549. For further insight on SOA, consult Application Bulletin (SBOA022).
Power Dissipation
Power dissipation depends on power supply, signal, and load conditions. For dc signals, power dissipation is
equal to the product of output current times the voltage across the conducting output transistor. Power
dissipation can be minimized by using the lowest possible power-supply voltage necessary to assure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a dc output voltage of one-half the power-supply
voltage. Dissipation with ac signals is lower. Application Bulletin (SBOA022) explains how to calculate or
measure power dissipation with unusual signals and loads.
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Thermal Protection
Power dissipated in the OPA549 will cause the junction temperature to rise. Internal thermal shutdown circuitry
shuts down the output when the die temperature reaches approximately 160°C and resets when the die has
cooled to 140°C. Depending on load and signal conditions, the thermal protection circuit may cycle on and off.
This limits the dissipation of the amplifier but may have an undesirable effect on the load.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heat sink) increase the ambient temperature until the thermal
protection is triggered.
Use worst-case load and signal conditions. For good reliability, thermal protection should trigger more than 35°C
above the maximum expected ambient condition of your application. This produces a junction temperature of
125°C at the maximum expected ambient condition.
The internal protection circuitry of the OPA549 was designed to protect against overload conditions. It was not
intended to replace proper heat sinking. Continuously running the OPA549 into thermal shutdown will degrade
reliability.
Amplifier Mounting and Heat Sinking
Most applications require a heat sink to assure that the maximum operating junction temperature (125°C) is not
exceeded. In addition, the junction temperature should be kept as low as possible for increased reliability.
Junction temperature can be determined according to the Equations:
TJ = TA + PDθJA
θJA = θJC + θCH + θHA
(4)
(5)
Where:
TJ = Junction Temperature (°C)
TA = Ambient Temperature (°C)
PD = Power Dissipated (W)
θJC = Junction-to-Case Thermal Resistance (°C/W)
θCH = Case-to-Heat Sink Thermal Resistance (°C/W)
θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W)
θJA = Junction-to-Air Thermal Resistance (°C/W)
Figure 9 shows maximum power dissipation versus ambient temperature with and without the use of a heat sink.
Using a heat sink significantly increases the maximum power dissipation at a given ambient temperature, as
shown in Figure 9.
The challenge in selecting the heat sink required lies in determining the power dissipated by the OPA549. For dc
output, power dissipation is simply the load current times the voltage developed across the conducting output
transistor, PD = IL (VS – VO). Other loads are not as simple. Consult the SBOA022 Application Report for further
insight on calculating power dissipation. Once power dissipation for an application is known, the proper heat sink
can be selected.
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Heat Sink Selection Example
An 11-lead power ZIP package is dissipating 10 Watts. The maximum expected ambient temperature is 40°C.
Find the proper heat sink to keep the junction temperature below 125°C (150°C minus 25°C safety margin).
Combining Equation 4 and Equation 5 gives:
TJ = TA + PD (θJC + θCH + θHA)
(6)
TJ, TA, and PD are given. θJC is provided in the Specifications Table, 0.1°C/W (dc). θCH can be obtained from the
heat sink manufacturer. Its value depends on heat sink size, area, and material used. Semiconductor package
type, mounting screw torque, insulating material used (if any), and thermal joint compound used (if any) also
affect θCH. A typical θCH for a mounted 11-lead power ZIP package is 0.5°C/W. Now we can solve for θHA:
θHA = [(TJ - TA)/PD] - θJC - θCH
θHA = [(125°C - 55°C)/10 W] - 0.1°C/W - 0.5°C/W
θHA = 6.4°C/W
To maintain junction temperature below 125°C, the heat sink selected must have a θHA less than 6.4°C/W. In
other words, the heat sink temperature rise above ambient must be less than 64°C (6.4°C/W • 10 W). For
example, at 10 W, Thermalloy model number 6396B has a heat sink temperature rise of 56°C (θHA = 56°C/10 W
= 5.6°C/W), which is below the required 66°C required in this example. Thermalloy model number 6399B has a
sink temperature rise of 33°C (θHA = 33°C/10 W = 3.3°C/W), which is also below the required 66°C required in
this example. Figure 9 shows power dissipation versus ambient temperature for a 11-lead power ZIP package
with the Thermalloy 6396B and 6399B heat sinks.
30
PD = (TJ (max) – TA )/ θ JA
Power Dissipation - W
(TJ (max) – 150°C)
with Thermalloy 6399B
20
Heat Sink, θ JA = 3.9°C/W
with Thermalloy 6396B
Heat Sink, θJA = 6.2°C/W
10
with No Heat Sink,
θ JA = 30°C/W
0
0
25
50
75
TA - Temperature - °C
Thermalloy 6396B
assume
OPA549
Thermalloy 6399B
assume
OPA549
θ HA = 5.6
θ CH = 0.5
θ JC = 0.1
θ JA = 6.2
100
125
°C/W
°C/W
°C/W
°C/W
θ HA = 3.3 °C/W
θ CH = 0.5 °C/W
θ JC = 0.1 °C/W
θ JA = 3.9 °C/W
Figure 9. Maximum Power Dissipation vs Ambient Temperature
Another variable to consider is natural convection versus forced convection air flow. Forced-air cooling by a small
fan can lower θCA (θCH + θHA) dramatically. Some heat sink manufacturers provide thermal data for both of these
cases. Heat sink performance is generally specified under idealized conditions that may be difficult to achieve in
an actual application. For additional information on determining heat sink requirements, consult Application
Report (SBOA021).
As mentioned earlier, once a heat sink has been selected, the complete design should be tested under worstcase load and signal conditions to ensure proper thermal protection. Any tendency to activate the thermal
protection circuitry may indicate inadequate heat sinking.
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The tab of the 11-lead power ZIP package is electrically connected to the negative supply, V–. It may be
desirable to isolate the tab of the 11-lead power ZIP package from its mounting surface with a mica (or other
film) insulator. For lowest overall thermal resistance, it is best to isolate the entire heat sink/OPA549 structure
from the mounting surface rather than to use an insulator between the semiconductor and heat sink.
Output Stage Compensation
The complex load impedances common in power op amp applications can cause output stage instability. For
normal operation, output compensation circuitry is typically not required. However, for difficult loads or if the
OPA549 is intended to be driven into current limit, an R/C network may be required. Figure 10 shows an output
R/C compensation (snubber) network which generally provides excellent stability.
V+
R1
5 kΩ
R2
20 kΩ
G=–
R2
= –4
R1
VIN
D1
OPA549
D2
10 Ω
(Carbon)
Motor
0.01 mF
V–
D1, D2 : Schottky Diodes
Figure 10. Motor Drive Circuit
A snubber circuit may also enhance stability when driving large capacitive loads (> 1000 pF) or inductive loads
(motors, loads separated from the amplifier by long cables). Typically, 3-Ω to 10-Ω resistors in series with
0.01-μF to 0.1-μF capacitors is adequate. Some variations in circuit values may be required with certain loads.
Output Protection
Reactive and EMF-generating loads can return load current to the amplifier, causing the output voltage to exceed
the power-supply voltage. This damaging condition can be avoided with clamp diodes from the output terminal to
the power supplies, as shown in Figure 10. Schottky rectifier diodes with an 8-A or greater continuous rating are
recommended.
Voltage Source Application
Figure 11 illustrates how to use the OPA549 to provide an accurate voltage source with only three external
resistors. First, the current limit resistor, RCL, is chosen according to the desired output current. The resulting
voltage at the ILIM pin is constant and stable over temperature. This voltage, VCL, is connected to the noninverting
input of the op amp and used as a voltage reference, thus eliminating the need for an external reference. The
feedback resistors are selected to gain VCL to the desired output voltage level.
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R1
R2
V+
VO = VCL (1 + R2/R1)
4.75 V
7500 Ω
Ref
IO =
VCL
15800 (4.75 V)
7500 Ω + RCL
ILIM
V–
0.01 mF
(Optional, for noisy
environments)
RCL
Uses voltage developed at ILIM pin
as a moderately accurate reference
voltage.
For Example:
If ILIM = 7.9 A, RCL= 2 kΩ
2 kΩ • 4.75 V
=1V
(2k Ω + 7500 Ω)
10
= 10
Desired VO = 10 V, G =
1
VCL =
R1 = 1 kΩ and R2 = 9 kΩ
Figure 11. Voltage Source
Programmable Power Supply
A programmable source and sink power supply can easily be built using the OPA549. Both the output voltage
and output current are user-controlled. See Figure 12 for a circuit using potentiometers to adjust the output
voltage and current while Figure 13 uses DACs. An LED connected to the E/S pin through a logic gate indicates
if the OPA549 is in thermal shutdown.
1 kΩ
9 kΩ
G=1+
+5 V
10.5 kΩ
Output
Adjust
3
VO = 1 V to 25 V
IO = 0 to 10 A
OPA549
0.12 V to 2.5 V
10 kΩ
9 kΩ
= 10
1 kΩ
V+ = +30 V
V– = 0 V
4
6
9 E/S
ILIM 8 Ref
74HCT04
499 Ω
R ≥ 250 Ω
+5 V
V–
0 V to 4.75 V
1 kΩ
Current
Limit
Adjust
20 kΩ
Thermal
Shutdown Status
(LED)
0.01 mF
Figure 12. Resistor-Controlled Programmable Power Supply
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1 kΩ
V+ = +30 V
V– = 0 V
9 kΩ
–5 V
OUTPUT ADJUST
VREF
G = 10
+5 V
VREF A
3
+5 V
R FB A
1, 2
1/2 DAC7800/1/2(3)
VO = 7 V to 25 V
OPA549
10 pF
9
4
1/2
OPA2336
I OUT A
E/S
6
Ref
DAC A
AGND A
ILIM
IO = 0 A to 10 A
74HCT04
R ≥ 250 Ω
8
Thermal
Shutdown Status
(LED)
VREF B
R FB B
10 pF
1/2 DAC7800/1/2
1/2
OPA2336
I OUT B
DAC B
0.01 mF
DGND
AGND B
CURRENT LIMIT ADJUST
Choose DAC780X based on digital interface: DAC7800—12-bit
interface, DAC7801—8-bit interface + 4 bits, DAC7802—serial interface.
Figure 13. Digitally-Controlled Programmable Power Supply
R1
R2
VIN1
OPA549
E/S
R3
VE/S
R4
VO
VIN2
OPA549
E/S
Limit output slew rates to ≤ 3 V/ ms (see text).
Figure 14. Switched Amplifier
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OPA549
ILIM
Ref
RCL2
RCL1
Close for high current
(could be open drain
output of a logic gate).
Figure 15. Multiple Current Limit Values
R2
4 kΩ
R1
1 kΩ
Master
0.1 Ω
OPA549
VIN
ILIM
Ref
20 A Peak
VO
G=5
Slave
0.1 Ω
OPA549
ILIM
Ref
Figure 16. Parallel Output for Increased Output Current
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA549MKVC
ACTIVE Power Package
KVC
11
25
RoHS & Green
SN
N / A for Pkg Type
-55 to 125
OPA549M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
