OPA620SG

OPA ® 620 OPA620 OPA 620 OPA 620 Wideband Precision OPERATIONAL AMPLIFIER FEATURES q LOW NOISE: 2.3nV/√Hz q HIGH OUTPUT CURRENT: 100mA q FAST SETTLING: 25ns (0.01%) q GAIN-BANDWIDTH PRODUCT: 200MHz q UNITY-GAIN STABLE q LOW OFFSET VOLTAGE: ±200µV q LOW DIFFERENTIAL GAIN/PHASE ERROR q 8-PIN DIP, SO-8 PACKAGES APPLICATIONS q LOW NOISE PREAMPLIFIER q LOW NOISE DIFFERENTIAL AMPLIFIER q HIGH-RESOLUTION VIDEO q HIGH-SPEED SIGNAL PROCESSING q LINE DRIVER q ADC/DAC BUFFER q ULTRASOUND q PULSE/RF AMPLIFIERS q ACTIVE FILTERS DESCRIPTION The OPA620 is a precision wideband monolithic operational amplifier featuring very fast settling time, low differential gain and phase error, and high output current drive capability. The OPA620 is internally compensated for unity-gain stability. This amplifier has a very low offset, fully symmetrical differential input due to its “classical” operational amplifier circuit architecture. Unlike “current-feedback” amplifier designs, the OPA620 may be used in all op amp applications requiring high speed and precision. Low noise and distortion, wide bandwidth, and high linearity make this amplifier suitable for RF and video applications. Short-circuit protection is provided by an internal current-limiting circuit. The OPA620 is available in plastic and ceramic DIP and SO-8 packages. Two temperature ranges are offered: –40°C to +85°C and –55°C to +125°C. +VCC 7 Non-Inverting Input Inverting Input 3 Output Stage Current Mirror CC 6 Output 2 4 –VCC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1988 Burr-Brown Corporation PDS-872G Printed in U.S.A. September, 1993 SPECIFICATIONS ELECTRICAL At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. OPA620KP, KU PARAMETER INPUT NOISE Voltage: fO = 100Hz fO = 1kHz fO = 10kHz fO = 100kHz fO = 1MHz to 100MHz fB = 100Hz to 10MHz Current: fO = 10kHz to 100MHz OFFSET VOLTAGE(1) Input Offset Voltage Average Drift Supply Rejection BIAS CURRENT Input Bias Current OFFSET CURRENT Input Offset Current INPUT IMPEDANCE Differential Common-Mode INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Closed-Loop Bandwidth (–3dB) VCM = 0VDC TA = TMIN to TMAX ±VCC = 4.5V to 5.5V VCM = 0VDC VCM = 0VDC Open-Loop ±200 ±8 60 15 0.2 15 || 1 1 || 1 ±3.0 65 50 48 ±3.5 75 60 58 300 100 40 20 200 0.05 0.05 –61 –65 16 40 250 10 13 25 60 2 22 ±3.0 ±2.5 ±3.5 ±3.0 0.015 20 ±150 5 4.0 21 –40 6.0 23 +85 T T T –55 –55 125 90 100 T T –50 –55 T T T T T T T ±1000 T 30 2 T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T +125 +125 T T T µV µV/°C dB µA µA kΩ || pF MΩ || pF V dB dB dB MHz MHz MHz MHz MHz % Degrees dBc(3) dBc MHz MHz V/µs % ns ns Degrees ns ns V V Ω pF mA VDC VDC mA °C °C °C °C °C/W °C/W °C/W CONDITIONS RS = 0Ω MIN TYP 10 5.5 3.3 2.5 2.3 8.0 2.3 MAX MIN OPA620SG TYP T T T T T T T MAX UNITS nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVr ms pA/√Hz 50 T T VIN = ±2.5VDC, VO = 0VDC RL = 100Ω RL = 50Ω Gain = +1V/V Gain = +2V/V Gain = +5V/V Gain = +10V/V Gain ≥ +5V/V 3.58MHz, G = +1V/V 3.58MHz, G = +1V/V G = +2V/V, f = 10MHz, VO = 2Vp-p Second Harmonic Third Harmonic VO = 5Vp-p, Gain = +1V/V VO = 2Vp-p, Gain = +1V/V 2V Step, Gain = –1V/V 2V Step, Gain = –1V/V 2V Step, Gain = –1V/V Gain = +1V/V Gain = +1V/V, 10% to 90% VO = 100mVp-p; Small Signal VO = 6Vp-p; Large Signal RL = 100Ω RL = 50Ω 1MHz, Gain = +1V/V Gain = +1V/V Continuous ±VCC ±VCC IO = 0mA Ambient Temperature Ambient Temperature Gain-Bandwidth Product Differential Gain Differential Phase Harmonic Distortion(2) Full Power Bandwidth(2) Slew Rate(2) Overshoot Settling Time: 0.1% 0.01% Phase Margin Rise Time 11 27 175 RATED OUTPUT Voltage Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Derated Performance Current, Quiescent TEMPERATURE RANGE Specification: KP, KU SG Operating: SG KP, KU θJA: SG KP KU –40 +85 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA620 2 SPECIFICATIONS (CONT) ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At VCC = ±5VDC, RL = 100Ω, and TA = TMIN to TMAX, unless otherwise noted. OPA620KP, KU PARAMETER TEMPERATURE RANGE Specification: KP, KU SG OFFSET VOLTAGE(1) Average Drift Supply Rejection BIAS CURRENT Input Bias Current OFFSET CURRENT Input Offset Current INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN LOOP GAIN, DC Open-Loop Voltage Gain RATED OUTPUT Voltage Output CONDITIONS Ambient Temperature MIN –40 TYP MAX +85 MIN T –55 T T T T T T T T T T T T T 25 T T T T T T T T T T T T OPA620SG TYP MAX T +125 UNITS °C °C µV/° C dB dB µA µA V dB dB dB V V V V mA Full Temp. 0°C to +70° C ±VCC = 4.5V to 5.5V Full Temp., ±VCC = 4.5 to 5.5V Full Temp., VCM = 0VDC Full Temp., VCM = 0VDC 45 40 ±8 60 55 15 0.2 40 5 T T VIN = ±2.5VDC, VO = 0VDC RL = 100Ω RL = 50Ω 0°C to +70°C, RL = 100Ω –40°C to +85° C, RL = 100Ω 0°C to +70°C, RL = 50Ω –40°C to +85°C, RL = 50Ω IO = 0mA ±2.5 60 46 44 ±3.0 ±2.75 ±2.5 ±2.25 ±3.0 75 60 58 ±3.5 ±3.25 ±3.0 ±2.7 21 POWER SUPPLY Current, Quiescent T Same specifications as for KP, KU. NOTES: (1) Offset Voltage specifications are also guaranteed with units fully warmed up. (2) Parameter is guaranteed by characterization. (3) dBc = dB referred to carrier-input signal. PIN CONFIGURATION Top View No Internal Connection Inverting Input Non-Inverting Input Negative Supply (–VCC ) 1 2 3 4 8 7 6 5 No Internal Connection Positive Supply (+VCC ) Output No Internal Connection DIP/SO-8 ORDERING INFORMATION OPA620 Basic Model Number Performance Grade Code K = –40°C to +85°C S = –55°C to +125°C Package Code G = 8-pin Ceramic DIP P = 8-pin Plastic DIP U = SO-8 Surface Mount ( ) ( ) PACKAGE INFORMATION PRODUCT OPA620KP OPA620KU OPA620SG PACKAGE 8-Pin Plastic DIP SO-8 Surface Mount 8-Pin Ceramic DIP PACKAGE DRAWING NUMBER(1) 006 182 157 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS Supply ............................................................................................. ±7VDC Internal Power Dissipation(1) ....................... See Applications Information Differential Input Voltage ............................................................ Total VCC Input Voltage Range .................................... See Applications Information Storage Temperature Range: SG ................................. –65°C to +150°C KP, KU .......................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C (soldering, SO-8, 3s) ...................................... +260°C Output Short Circuit to Ground (+25°C) ............... Continuous to Ground Junction Temperature (TJ ) ............................................................ +175°C NOTE: (1) Packages must be derated based on specified θ must be observed. JA. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® Maximum TJ 3 OPA620 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. Phase Shift (°) +4 AOL +2 0 Gain (dB) Open-Loop Voltage Gain (dB) 80 60 40 20 0 -20 1k 10k 100k 1M Frequency (Hz) Gain Phase Margin ≈ 60° 10M 100M 0 –45 –90 –135 –180 Gain 0 –45 Open-Loop Phase –90 –135 –180 1M 10M 100M 1G Frequency (Hz) Phase –2 –4 –6 –8 PM ≈ 60° 1G Phase Shift (°) +10 AOL +8 +6 Gain +24 +22 +20 AOL Gain 0 –45 Open-Loop Phase –90 –135 –180 1M 10M 100M 1G Frequency (Hz) 0 –45 –90 PM ≈ 90° –135 –180 1M 10M 100M 1G Frequency (Hz) Gain (dB) +4 +2 0 –2 Gain (dB) +18 +16 +14 +12 Open-Loop Phase PM ≈ 70° A V = +1V/V CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING 8 RL = 50Ω Output Voltage (Vp-p) Output Voltage (Vp-p) 6 6 8 A V = +2V/V CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING RL = 50Ω 4 4 2 2 0 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) 0 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) ® OPA620 4 Phase Shift (°) A V = +2V/V CLOSED-LOOP SMALL-SIGNAL BANDWIDTH AV = +10V/V CLOSED-LOOP SMALL-SIGNAL BANDWIDTH Phase Shift (°) OPEN-LOOP FREQUENCY RESPONSE A V = +1V/V CLOSED-LOOP SMALL-SIGNAL BANDWIDTH TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. A V = +10V/V CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING 8 R L = 50Ω Output Voltage (Vp-p) 6 TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE 100 RS = 1kΩ 10 RS = 500Ω 4 Voltage Noise (nV/ Hz) RS = 100 Ω 1 RS = 0Ω 2 0 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) 0.1 100 1k 10k 100k Frequency (Hz) 1M 10M 100M INPUT CURRENT NOISE SPECTRAL DENSITY 100 INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE 3.1 fO = 100kHz Voltage Noise (nV/√Hz) 2.9 Current Noise (pA/√Hz) 2.8 10 Current Noise 2.6 2.5 Voltage Noise 2.2 2.3 1 2.0 0.1 100 1k 10k 100k Frequency (Hz) 1M 10M 100M 1.9 –75 –50 –25 0 +25 +50 +75 +100 Ambient Temperature (°C) 1.7 +125 INPUT OFFSET VOLTAGE WARM-UP DRIFT +100 +1000 INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK Offset Voltage Change (µV) +50 Offset Voltage Change (µV) +500 SG TA = 25°C to TA = 125°C Air Environment K Grade T = 25°C to 70°C A Air Environment 0 0 25°C –50 –500 –100 0 1 2 3 4 5 6 Time from Power Turn-on (min) –1000 –1 0 +1 +2 +3 +4 +5 Time from Thermal Shock (min) Current Noise (pA/√Hz) ® 5 OPA620 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 25 0.8 21 BIAS AND OFFSET CURRENT vs TEMPERATURE 0.8 Offset Current (µA) Bias Current (µA) Bias Current 15 0.4 Bias Current (µA) Bias Current 15 0.4 10 Offset Current 9 –4 –3 –2 –1 0 +1 +2 +3 +4 Common-Mode Voltage (V) 0.2 12 Offset Current 0.2 0 9 –75 –50 –25 0 +25 +50 +75 Ambient Temperature (°C) 0 +100 +125 COMMON-MODE REJECTION vs FREQUENCY POWER SUPPLY REJECTION vs FREQUENCY Common-Mode Rejection (dB) 60 VO = 0VDC 40 20 0 -20 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) Power Supply Rejection (dB) 80 80 60 40 20 – PSR 0 -20 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) + PSR COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 80 Common-Mode Rejection (dB) SUPPLY CURRENT vs TEMPERATURE 25 V = 0VDC O 70 Supply Current (mA) 75 23 21 65 19 60 –5 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 Common-Mode Voltage (V) 17 –75 –50 –25 0 +25 +50 +75 +100 +125 Ambient Temperature (°C) ® OPA620 6 Offset Current (µA) 20 0.6 18 0.6 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. SMALL-SIGNAL TRANSIENT RESPONSE LARGE-SIGNAL TRANSIENT RESPONSE +3 +50 Output Voltage (mV) 0 G = +1V/V RL= 50Ω CL = 15pF Output Voltage (mV) 0 G = +1V/V RL= 50Ω CL = 15pF –50 –3 0 25 Time (ns) 50 0 100 Time (ns) 200 SETTLING TIME vs CLOSED-LOOP GAIN 100 VO = 2V Step 80 Settling Time (ns) SETTLING TIME vs OUTPUT VOLTAGE CHANGE 160 140 G = –1V/V 120 Settling Time (ns) 60 0.01% 100 80 60 40 20 0.1% 0.01% 40 20 0.1% 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 Closed-Loop Amplifier Gain (V/V) 0 0 2 4 Output Voltage Change (V) 6 8 80 A OL , PSR, AND CMR vs TEMPERATURE FREQUENCY CHARACTERISTICS vs TEMPERATURE 2.0 A OL , PSR, CMR (dB) 70 CMR PSR Relative Value 1.5 Settling Time 60 AOL 50 1.0 Gain-Bandwidth 0.5 Slew Rate 40 –75 –50 –25 0 +25 +50 +75 +100 +125 Temperature (°C) 0 –75 –50 –25 0 +25 +50 +75 +100 +125 Temperature (°C) ® 7 OPA620 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. NTSC DIFFERENTIAL GAIN vs CLOSED-LOOP GAIN 0.5 f = 3.58MHz 0.4 Differential Gain (%) NTSC DIFFERENTIAL PHASE vs CLOSED-LOOP GAIN 1.0 f = 3.58MHz Differential Phase (Degrees) RL = 75Ω (Two Back-Terminated Outputs) 0.8 RL = 75Ω (Two Back-Terminated Outputs) 0.3 VO = 0V to 2.1V VO = 0V to 1.4V 0.6 VO = 0V to 2.1V VO = 0V to 1.4V VO = 0V to 0.7V 0.2 VO = 0V to 0.7V 0.1 0.4 0.2 0 1 2 3 4 5 6 7 8 9 10 Closed-Loop Amplifier Gain (V/V) 0 1 2 3 4 5 6 7 8 9 10 Closed-Loop Amplifier Gain (V/V) SMALL-SIGNAL HARMONIC DISTORTION vs FREQUENCY –30 G = +2V/V V O = 0.5Vp-p RL = 50Ω LARGE-SIGNAL HARMONIC DISTORTION vs FREQUENCY –30 G = +2V/V V O = 2Vp-p RL = 50Ω Harmonic Distortion (dBc) –40 Harmonic Distortion (dBc) –40 –50 2f –50 2f –60 –60 –70 3f –70 3f 1M Frequency (Hz) 10M 100M –80 100k 1M Frequency (Hz) 10M 100M –80 100k 1MHz HARMONIC DISTORTION vs POWER OUTPUT –30 –40 –50 –60 –70 –80 0.125Vp-p –90 –20 –15 –10 –5 0 +5 +10 +15 Power Output (dBm) 0.25Vp-p 0.5Vp-p 3f 1Vp-p 2Vp-p –90 –20 –15 2f G = +2V/V RL = 50 Ω f C = 1MHz –30 –40 –50 –60 –70 –80 10MHz HARMONIC DISTORTION vs POWER OUTPUT G = +2V/V RL = 50 Ω f C = 10MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) 2f 3f 0.125Vp-p 0.25Vp-p –10 –5 0.5Vp-p 0 1Vp-p +5 2Vp-p +10 +15 Power Output (dBm) ® OPA620 8 APPLICATIONS INFORMATION DISCUSSION OF PERFORMANCE The OPA620 provides a level of speed and precision not previously attainable in monolithic form. Unlike current feedback amplifiers, the OPA620’s design uses a “classical” operational amplifier architecture and can therefore be used in all traditional operational amplifier applications. While it is true that current feedback amplifiers can provide wider bandwidth at higher gains, they offer many disadvantages. The asymmetrical input characteristics of current feedback amplifiers (i.e., one input is a low impedance) prevents them from being used in a variety of applications. In addition, unbalanced inputs make input bias current errors difficult to correct. Bias current cancellation through matching of inverting and non-inverting input resistors is impossible because the input bias currents are uncorrelated. Current noise is also asymmetrical and is usually significantly higher on the inverting input. Perhaps most important, settling time to 0.01% is often extremely poor due to internal design tradeoffs. Many current feedback designs exhibit settling times to 0.01% in excess of 10 microseconds even though 0.1% settling times are reasonable. Such amplifiers are completely inadequate for fast settling 12-bit applications. The OPA620’s “classical” operational amplifier architecture employs true differential and fully symmetrical inputs to eliminate these troublesome problems. All traditional circuit configurations and op amp theory apply to the OPA620. The use of low-drift thin-film resistors allows internal operating currents to be laser-trimmed at wafer-level to optimize AC performance such as bandwidth and settling time, as well as DC parameters such as input offset voltage and drift. The result is a wideband, high-frequency monolithic operational amplifier with a gain-bandwidth product of 200MHz, a 0.01% settling time of 25ns, and an input offset voltage of 200µV. WIRING PRECAUTIONS Maximizing the OPA620’s capability requires some wiring precautions and high-frequency layout techniques. Oscillation, ringing, poor bandwidth and settling, gain peaking, and instability are typical problems plaguing all high-speed amplifiers when they are improperly used. In general, all printed circuit board conductors should be wide to provide low resistance, low impedance signal paths. They should also be as short as possible. The entire physical circuit should be as small as practical. Stray capacitances should be minimized, especially at high impedance nodes, such as the amplifier’s input terminals. Stray signal coupling from the output or power supplies to the inputs should be minimized. All circuit element leads should be no longer than 1/4 inch (6mm) to minimize lead inductance, and low values of resistance should be used. This will minimize time constants formed with the circuit capacitances and will eliminate stray, parasitic circuits. Grounding is the most important application consideration for the OPA620, as it is with all high-frequency circuits. Oscillations at frequencies of 200MHz and above can easily occur if good grounding techniques are not used. A heavy ground plane (2 oz. copper recommended) should connect all unused areas on the component side. Good ground planes can reduce stray signal pickup, provide a low resistance, low inductance common return path for signal and power, and can conduct heat from active circuit package pins into ambient air by convection. Supply bypassing is extremely critical and must always be used, especially when driving high current loads. Both power supply leads should be bypassed to ground as close as possible to the amplifier pins. Tantalum capacitors (1µF to 10µF) with very short leads are recommended. A parallel 0.1µF ceramic should be added at the supply pins. Surface mount bypass capacitors will produce excellent results due to their low lead inductance. Additionally, suppression filters can be used to isolate noisy supply lines. Properly bypassed and modulation-free power supply lines allow full amplifier output and optimum settling time performance. Points to Remember 1) Don’t use point-to-point wiring as the increase in wiring inductance will be detrimental to AC performance. However, if it must be used, very short, direct signal paths are required. The input signal ground return, the load ground return, and the power supply common should all be connected to the same physical point to eliminate ground loops, which can cause unwanted feedback. 2) Good component selection is essential. Capacitors used in critical locations should be a low inductance type with a high quality dielectric material. Likewise, diodes used in critical locations should be Schottky barrier types, such as HP50822835 for fast recovery and minimum charge storage. Ordinary diodes will not be suitable in RF circuits. 3) Whenever possible, solder the OPA620 directly into the PC board without using a socket. Sockets add parasitic capacitance and inductance, which can seriously degrade AC performance or produce oscillations. If sockets must be used, consider using zero-profile solderless sockets such as Augat part number 8134-HC-5P2. Alternately, Teflon® standoffs located close to the amplifier’s pins can be used to mount feedback components. 4) Resistors used in feedback networks should have values of a few hundred ohms for best performance. Shunt capacitance problems limit the acceptable resistance range to about 1kΩ on the high end and to a value that is within the amplifier’s output drive limits on the low end. Metal film and carbon resistors will be satisfactory, but wirewound resistors (even “non-inductive” types) are absolutely unacceptable in high-frequency circuits. 5) Surface-mount components (chip resistors, capacitors, etc) have low lead inductance and are therefore strongly recommended. Circuits using all surface-mount components with the OPA620KU (SO-8 package) will offer the best AC performance. The parasitic package inductance and capacitance for the SO-8 is lower than the both the Cerdip and 8-lead Plastic DIP. Teflon® E. I. Du Pont de Nemours & Co. ® 9 OPA620 6) Avoid overloading the output. Remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its load. Lowest distortion is achieved with high impedance loads. 7) Don’t forget that these amplifiers use ±5V supplies. Although they will operate perfectly well with +5V and –5.2V, use of ±15V supplies will destroy the part. 8) Standard commercial test equipment has not been designed to test devices in the OPA620’s speed range. Benchtop op amp testers and ATE systems will require a special test head to successfully test these amplifiers. 9) Terminate transmission line loads. Unterminated lines, such as coaxial cable, can appear to the amplifier to be a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the amplifier’s load then appears purely resistive. 10) Plug-in prototype boards and wire-wrap boards will not be satisfactory. A clean layout using RF techniques is essential; there are no shortcuts. OFFSET VOLTAGE ADJUSTMENT The OPA620’s input offset voltage is laser-trimmed and will require no further adjustment for most applications. However, if additional adjustment is needed, the circuit in Figure 1 can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier’s inverting input terminal. Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce input bias current errors to the amplifier’s offset current, which is typically only 0.2µA. INPUT PROTECTION Static damage has been well recognized for MOSFET devices, but any semiconductor device deserves protection from this potentially damaging source. The OPA620 incorporates on-chip ESD protection diodes as shown in Figure 2. This eliminates the need for the user to add external protection diodes, which can add capacitance and degrade AC performance. All pins on the OPA620 are internally protected from ESD by means of a pair of back-to-back reverse-biased diodes to either power supply as shown. These diodes will begin to conduct when the input voltage exceeds either power supply by about 0.7V. This situation can occur with loss of the amplifier’s power supplies while a signal source is still present. The diodes can typically withstand a continuous current of 30mA without destruction. To insure long term reliability, however, diode current should be externally limited to 10mA or so whenever possible. +VCC ESD Protection diodes internally connected to all pins. External Pin Internal Circuitry –VCC FIGURE 2. Internal ESD Protection. The internal protection diodes are designed to withstand 2.5kV (using Human Body Model) and will provide adequate ESD protection for most normal handling procedures. However, static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, static protection is strongly recommended when handling the OPA620. OUTPUT DRIVE CAPABILITY The OPA620’s design uses large output devices and has been optimized to drive 50Ω and 75Ω resistive loads. The device can easily drive 6Vp-p into a 50Ω load. This highoutput drive capability makes the OPA620 an ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded. Internal current-limiting circuitry limits output current to about 150mA at 25°C. This prevents destruction from accidental shorts to common and eliminates the need for external current-limiting circuitry. Although the device can withstand momentary shorts to either power supply, it is not recommended. +VCC RTrim 47kΩ –VCC R1 (1)R R2 20kΩ OPA620 3 = R1 || R 2 VIN or Ground Output Trim Range ≅ +V CC ( R 2 ) to –V CC ( R2 ) RTrim RTrim NOTE: (1) R3 is optional and can be used to cancel offset errors due to input bias currents. FIGURE 1. Offset Voltage Trim. ® OPA620 10 Many demanding high-speed applications such as ADC/ DAC buffers require op amps with low wideband output impedance. For example, low output impedance is essential when driving the signal-dependent capacitances at the inputs of flash A/D converters. As shown in Figure 3, the OPA620 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. When the output is shorted to ground, PDL = 5V x 150mA = 750mW. Thus, PD = 230mW + 750mW ≈ 1W. Note that the short-circuit condition represents the maximum amount of internal power dissipation that can be generated. Thus, the “Maximum Power Dissipation” curve starts at 1W and is derated based on a 175°C maximum junction temperature and the junction-to-ambient thermal resistance, θJA, of each package. The variation of short-circuit current with temperature is shown in Figure 5. 10 Small-Signal Output Impedance (Ω ) 250 Short-Circuit Current (mA) 1 G = +10V/V 200 +ISC 0.1 G = +1V/V 150 – ISC 100 G = +2V/V 0.01 100 1k 10k 100k Frequency (Hz) 1M 10M 100M 50 –75 –50 –25 0 +25 +50 +75 +100 +125 Ambient Temperature (°C) FIGURE 3. Small-Signal Output Impedance vs Frequency. THERMAL CONSIDERATIONS The OPA620 does not require a heat sink for operation in most environments. The use of a heat sink, however, will reduce the internal thermal rise and will result in cooler, more reliable operation. At extreme temperatures and under full load conditions a heat sink is necessary. See “Maximum Power Dissipation” curve, Figure 4. 1.2 FIGURE 5. Short-Circuit Current vs Temperature. CAPACITIVE LOADS The OPA620’s output stage has been optimized to drive resistive loads as low as 50Ω. Capacitive loads, however, will decrease the amplifier’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than 20pF should be buffered by connecting a small resistance, usually 5Ω to 25Ω, in series with the output as shown in Figure 6. This is particularly important when driving high capacitance loads such as flash A/D converters. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance. Internal Power Dissipation (W) 1.0 0.8 0.6 0.4 0.2 0 0 +25 +50 +75 Plastic DIP, SO-8 Packages Cerdip Package +100 +125 +150 Ambient Temperature (°C) (RS typically 5Ω to 25Ω ) FIGURE 4. Maximum Power Dissipation. The internal power dissipation is given by the equation PD = PDQ + PDL, where PDQ is the quiescent power dissipation and PDL is the power dissipation in the output stage due to the load. (For ±VCC = ±5V, PDQ = 10V x 23mA = 230mW, max). For the case where the amplifier is driving a grounded load (RL) with a DC voltage (±VOUT) the maximum value of PDL occurs at ±VOUT = ±VCC/2, and is equal to PDL, max = (±VCC)2/4RL. Note that it is the voltage across the output transistor, and not the load, that determines the power dissipated in the output stage. 11 RS OPA620 RL CL FIGURE 6. Driving Capacitive Loads. ® OPA620 COMPENSATION The OPA620 is internally compensated and is stable in unity gain with a phase margin of approximately 60°. However, the unity gain buffer is the most demanding circuit configuration for loop stability and oscillations are most likely to occur in this gain. If possible, use the device in a noise gain of two or greater to improve phase margin and reduce the susceptibility to oscillation. (Note that, from a stability standpoint, an inverting gain of –1V/V is equivalent to a noise gain of 2.) Gain and phase response for other gains are shown in the Typical Performance Curves. The high-frequency response of the OPA620 in a good layout is very flat with frequency. However, some circuit configurations such as those where large feedback resistances are used, can produce high-frequency gain peaking. This peaking can be minimized by connecting a small capacitor in parallel with the feedback resistor. This capacitor compensates for the closed-loop, high frequency, transfer function zero that results from the time constant formed by the input capacitance of the amplifier (typically 2pF after PC board mounting), and the input and feedback resistors. The selected compensation capacitor may be a trimmer, a fixed capacitor, or a planned PC board capacitance. The capacitance value is strongly dependent on circuit layout and closed-loop gain. Using small resistor values will preserve the phase margin and avoid peaking by keeping the break frequency of this zero sufficiently high. When high closedloop gains are required, a three-resistor attenuator (tee network) is recommended to avoid using large value resistors with large time constants. SETTLING TIME Settling time is defined as the total time required, from the input signal step, for the output to settle to within the specified error band around the final value. This error band is expressed as a percentage of the value of the output transition, a 2V step. Thus, settling time to 0.01% requires an error band of ±200µV centered around the final value of 2V. Settling time, specified in an inverting gain of one, occurs in only 25ns to 0.01% for a 2V step, making the OPA620 one of the fastest settling monolithic amplifiers commercially available. Settling time increases with closed-loop gain and output voltage change as described in the Typical Performance Curves. Preserving settling time requires critical attention to the details as mentioned under “Wiring Precautions.” The amplifier also recovers quickly from input overloads. Overload recovery time to linear operation from a 50% overload is typically only 30ns. In practice, settling time measurements on the OPA620 prove to be very difficult to perform. Accurate measurement is next to impossible in all but the very best equipped labs. Among other things, a fast flat-top generator and high speed oscilloscope are needed. Unfortunately, fast flat-top genera- tors, which settle to 0.01% in sufficient time, are scarce and expensive. Fast oscilloscopes, however, are more commonly available. For best results, a sampling oscilloscope is recommended. Sampling scopes typically have bandwidths that are greater than 1GHz and very low capacitance inputs. They also exhibit faster settling times in response to signals that would tend to overload a real-time oscilloscope. Figure 7 shows the test circuit used to measure settling time for the OPA620. This approach uses a 16-bit sampling oscilloscope to monitor the input and output pulses. These waveforms are captured by the sampling scope, averaged, and then subtracted from each other in software to produce the error signal. This technique eliminates the need for the traditional “false-summing junction,” which adds extra parasitic capacitance. Note that instead of an additional flat-top generator, this technique uses the scope’s built-in calibration source as the input signal. 2pF to 5pF (Adjust for Optimum Settling) 0 to +2V, f = 1.25MHz 100 Ω VIN +5VDC 0 to –2V VOUT 100 Ω OPA620 –5VDC To Active Probe (Channel 2) on sampling scope. NOTE: Test fixture built using all surface-mount components. Ground plane used on component side and entire fixture enclosed in metal case. Both power supplies bypassed with 10µF Tantalum || 0.01µF ceramic capacitors. It is directly connected (without cable) to TIME CAL trigger source on Sampling Scope (Data Precision's Data 6100 with Model 640-1 plug-in). Input monitored with Active Probe (Channel 1). FIGURE 7. Settling Time Test Circuit. DIFFERENTIAL GAIN AND PHASE Differential Gain (DG) and Differential Phase (DP) are among the more important specifications for video applications. DG is defined as the percent change in closed-loop gain over a specified change in output voltage level. DP is defined as the change in degrees of the closed-loop phase over the same output voltage change. Both DG and DP are specified at the NTSC sub-carrier frequency of 3.58MHz. DG and DP increase with closed-loop gain and output voltage transition as shown in the Typical Performance Curves. All measurements were performed using a Tektronix model VM700 Video Measurement Set. ® OPA620 12 DISTORTION The OPA620’s harmonic distortion characteristics into a 50Ω load are shown vs frequency and power output in the Typical Performance Curves. Distortion can be further improved by increasing the load resistance as illustrated in Figure 8. Remember to include the contribution of the feedback resistance when calculating the effective load resistance seen by the amplifier. For this case OPI3P = 40dBm, PO = 4dBm, and the thirdorder IMD = 2(40 – 10) = 72dB below either 4dBm tone. The OPA620’s low IMD makes the device an excellent choice for a variety of RF signal processing applications. 2-TONE, 3RD ORDER INTERMODULATION INTERCEPT vs FREQUENCY 60 55 250Ω – + G = +1V/V POUT RL 250Ω – + G = +2V/V POUT RL 50 45 40 35 30 25 20 15 G = +1V/V RL = 50Ω G = +2V/V RL = 400Ω RL = 100 Ω RL = 50 Ω RL = 100Ω 40 RL = 400Ω 50 60 70 80 90 100 10MHz HARMONIC DISTORTION vs LOAD RESISTANCE –40 VO = 2Vp-p Harmonic Distortion (dBc) –50 G = +1V/V –60 G = +2V/V 2f Intercept Point (+dBm) –70 10 0 10 20 30 Frequency (MHz) –80 3f –90 0 100 200 300 400 500 Load Resistance (Ω) FIGURE 9. 2-Tone, 3rd Order Intermodulation Intercept vs Frequency. NOISE FIGURE FIGURE 8. 10MHz Harmonic Distortion vs Load Resistance. Two-tone third-order intermodulation distortion (IM) is an important parameter for many RF amplifier applications. Figure 9 shows the OPA620’s two-tone third-order IM intercept vs frequency. For these measurements, tones were spaced 1MHz apart. This curve is particularly useful for determining the magnitude of the third-order IM products as a function of frequency, load resistance, and gain. For example, assume that the application requires the OPA620 to operate in a gain of +2V/V and drive 2Vp-p (4dBm for each tone) into 50Ω at a frequency of 10MHz. Referring to Figure 9 we find that the intercept point is +40dBm. The magnitude of the third-order IM products can now be easily calculated from the expression: Third IMD = 2(OPI3P – PO) where OPI3P = third-order output intercept, dBm PO = output level/tone, dBm/tone Third IMD = third-order intermodulation ratio below each output tone, dB The OPA620’s voltage and current noise spectral densities are specified in the Typical Performance Curves. For RF applications, however, Noise Figure (NF) is often the preferred noise specification since it allows system noise performance to be more easily calculated. The OPA620’s Noise Figure vs Source Resistance is shown in Figure 10. NOISE FIGURE vs SOURCE RESISTANCE 25 NFdB = 10log 1 + en2 + (inRS)2 4kTRS 20 NF (dB) 15 10 5 0 10 100 1k Source Resistance (Ω ) 10k 100k FIGURE 10. Noise Figure vs Source Resistance. ® 13 OPA620 SPICE MODELS Computer simulation using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model using MicroSim Corporation’s PSpice is available for the OPA620. This simulation model is available through the Burr-Brown web site at www.burr-brown.com or by contacting the BurrBrown Applications Department. RELIABILITY DATA Extensive reliability testing has been performed on the OPA620. Accelerated life testing (2000 hours) at maximum operating temperature was used to calculate MTTF at an ambient temperature of 25°C. These test results yield MTTF of: Cerdip package = 1.31E+9 Hours, Plastic DIP = 5.02E+7 Hours, and SO-8 = 2.94E+7 Hours. Additional tests such as PCT have also been performed. Reliability reports are available upon request for each of the package options offered. DEMONSTRATION BOARDS Demonstration boards are available to speed protyping. The 8-pin DIP packaged parts may be evaluated using the DEMOPA65XP board while the SO-8 packaged part may be evaluated using the DEM-OPA65XU board. Both of these boards come partially assembled from your local distributor (the external resistors and the amplifier are not included). APPLICATIONS 390 Ω 390 Ω 75Ω Transmission Line 75Ω OPA620 Video Input 75Ω 75Ω VOUT 75Ω 75Ω VOUT High output current drive capability (6Vp-p into 50Ω) allows three back-terminated 75Ω transmission lines to be simultaneously driven. VOUT 75Ω 75Ω FIGURE 11. Video Distribution Amplifier. R3 OPA620 2kΩ R4 2kΩ +5V (–) (+) D D *J1 *J2 S S 2N5911 2 7 OPA620 4 6 VOUT C2 1000pF R1 VIN 15.8kΩ C1 1000pF R2 158Ω R5 158Ω VOUT 3 *R1 2kΩ *R2 2kΩ OPA620 –5V Feedback from pin 6 to the (–) FET input required for stability. fC = 1MHz BW = 20kHz at –3dB Q = 50 * Select J1, J2 and R1, R2 to set input stage current for optimum performance. IB eN Gain-Bandwidth Slew Rate Settling Time : 1pA : 6nV/√Hz at 1MHz : 200MHz : 250 V/µs : 15ns to 0.1% FIGURE 12. High-Q 1MHz Bandpass Filter. ® FIGURE 13. Low Noise, Wideband FET Input Op Amp. 14 OPA620 50Ω or 75Ω 50Ω or 75Ω OPA620 50Ω or 75Ω Transmission Line RF 249 Ω RG 499Ω RF 249 Ω 50Ω or 75Ω Transmission Line 50Ω or 75Ω 50Ω or 75Ω 50Ω or 75Ω Differential Input Differential Output OPA620 50Ω or 75Ω 1 Differential Voltage Gain = 1V/V = (1 + 2RF/RG) 2 Bandwidth, –3dB = 125MHz 500V/µs Slew Rate = FIGURE 14. Differential Line Driver for 50Ω or 75Ω Systems. OPA620 RF 249 Ω RG 499Ω RF 249 Ω 249Ω 249Ω 249Ω OPA620 249Ω OPA620 Differential Voltage Gain = 2V/V = 1 + 2RF/RG FIGURE 15. Wideband, Fast-Settling Instrumentation Amplifier. 249 Ω 249 Ω Differential Input SingleEnded Output 150 Ω 75 Ω 5Ω OPA620 ADS805 12-Bit, 10MHz A/D Converter Signal Input 249 Ω OPA620 75Ω Triax Input 249 Ω 10 Ω Analog Common FIGURE 16. Unity Gain Difference Amplifier. FIGURE 17. Differential Input Buffer Amplifier (G = –2V/V). ® 15 OPA620