®
OPA
631
OPA631 OPA632
For most current data sheet and other product information, visit www.burr-brown.com
Low Power, Single-Supply OPERATIONAL AMPLIFIERS
TM
FEATURES
q HIGH BANDWIDTH: 75MHz (G = +2) q LOW SUPPLY CURRENT: 6mA q ZERO POWER DISABLE (OPA632) q +3V AND +5V OPERATION q INPUT RANGE INCLUDES GROUND q 4.8V OUTPUT SWING ON +5V SUPPLY q HIGH SLEW RATE: 100V/µs q LOW INPUT VOLTAGE NOISE: 6nV/√HZ q AVAILABLE IN SOT23 PACKAGE
DESCRIPTION
The OPA631 and OPA632 are low power, high-speed, voltage-feedback amplifiers designed to operate on a single +3V or +5V supply. Operation on ±5V or +10V supplies is also supported. The input range extends below ground and to within 1V of the positive supply. Using complementary common-emitter outputs provides an output swing to within 30mV of ground and 130mV of the positive supply. The high output drive current and low differential gain and phase errors also make them ideal for single-supply consumer video products. Low distortion operation is ensured by the high gain bandwidth (68MHz) and slew rate (100V/µs), making the OPA631 and OPA632 ideal input buffer stages to 3V and 5V CMOS converters. Unlike other low power, single-supply amplifiers, distortion performance improves as the signal swing is decreased. A low 6nV input voltage noise supports wide dynamic range operation. Channel multiplexing or system power reduction can be achieved using the high speed disable line. Power dissipation can be reduced to zero by taking the disable line High. The OPA631 and OPA632 are available in an industrystandard SO-8 package. The OPA631 is also available in an ultra-small SOT23-5 package, while the OPA632 is available in the SOT23-6. Where higher full-power bandwidth and lower distortion are required in a singlesupply operational amplifier, consider the OPA634 and OPA635. RELATED PRODUCTS
SINGLES Medium Speed, No Disable With Disable High Speed, No Disable With Disable OPA631 OPA632 OPA634 OPA635 DUALS OPA2631 — OPA2634 —
APPLICATIONS
q SINGLE SUPPLY ADC INPUT BUFFER q SINGLE SUPPLY VIDEO LINE DRIVER q CCD IMAGING CHANNELS q LOW POWER ULTRASOUND q PLL INTEGRATORS q PORTABLE CONSUMER ELECTRONICS
+3V 2.26kΩ 374Ω VIN
OPA632
Disable
+3V Pwrdn ADS901 10-Bit 20Msps 22pF
DIS
100Ω
562Ω
750Ω
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1377A
Printed in U.S.A. June, 1999
SPECIFICATIONS: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1). OPA631U, N OPA632U, N TYP +25°C 75 16 7.6 68 5 100 5.3 5.4 17 42 6.0 1.9 0.5 1.2 62 2.5 — 11 0.3 — –0.5 4.0 74 10 || 2.1 400 || 1.2 RL = 1kΩ to 2.5V R L = 150Ω to 2.5V RL = 1kΩ to 2.5V R L = 150Ω to 2.5V 0.03 0.16 4.87 4.60 80 90 100 0.2 1.0 3.7 70 0 0 100 60 70 — — 6 6 59 –40 to +85 125 150 +25°C 50 12 5.6 51 — 64 8.0 7.5 28 40 6.8 2.6 — — 56 6 — 21 1 — –0.1 3.7 70 — — 0.06 0.17 4.8 4.4 25 38 — — 1.0 3.8 110 — 20 — — — 2.7 10.5 6.4 5.8 52 GUARANTEED 0°C to 70°C 40 10 4.2 40 — 52 11 10 38 38 7.6 2.9 — — 50 8 — 27 1.3 — –0.1 3.7 68 — — 0.09 0.20 4.7 4.4 20 24 — — 1.0 4.0 120 — 25 — — — 2.7 10.5 6.7 5.5 49 –40°C to +85°C 32 8.5 3.7 36 — 47 12.8 11.6 42 35 7.9 3.6 — — 46 11 50 40 2 7 –0.1 3.5 60 — — 0.12 1.7 4.6 3.1 5 10 — — 1.0 4.2 120 — 30 — — — 2.7 10.5 6.9 4.8 48 MIN/ MAX TEST LEVEL(1)
PARAMETER AC PERFORMANCE (Figure 1) Small-Signal Bandwidth
CONDITIONS G = +2, VO ≤ 0.5Vp-p G = +5, VO ≤ 0.5Vp-p G = +10, VO ≤ 0.5Vp-p G ≥ +10 VO ≤ 0.5Vp-p G = +2, 2V Step 0.5V Step 0.5V Step G = +2, 1V Step VO = 2Vp-p, f = 5MHz f > 1MHz f > 1MHz
UNITS
Gain Bandwidth Product Peaking at a Gain of +1 Slew Rate Rise Time Fall Time Settling Time to 0.1% Spurious Free Dynamic Range Input Voltage Noise Input Current Noise NTSC Differential Gain NTSC Differential Phase DC PERFORMANCE Open-Loop Voltage Gain Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Offset Current Input Offset Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Least Positive Output Voltage Most Positive Output Voltage
MHz MHz MHz MHz dB V/µs ns ns ns dBc nV/√Hz pA/√Hz % degrees dB mV µV/°C µA µA nA/°C V V dB kΩ || pF kΩ || pF V V V V mA mA mA Ω V V µA µA µA ns ns dB V V mA mA dB °C °C/W °C/W
min min min min typ min max max max min max max typ typ min max max max max max max min min typ typ max max min min min min typ typ min max max typ max typ typ typ min max max min min typ typ typ
B B B B C B B B B B B B C C A A B B B B B A A C C B A B A A A C C A A A C A C C C A A A A A C C C
VCM = 2.0V VCM = 2.0V
Input Referred
Current Output, Sourcing Current Output, Sinking Short-Circuit Current (output shorted to either supply) Closed-Loop Output Impedance G = +2, f ≤ 100kHz DISABLE (OPA632 only) On Voltage (device enabled Low) Off Voltage (device disabled High) On Disable Current (DIS pin) Off Disable Current (DIS pin) Disabled Quiescent Current Disable Time Enable Time Off Isolation POWER SUPPLY Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: U, N Thermal Resistance U SO-8 N SOT23-5, SOT23-6
f = 5MHz, Input to Output
VS = +5V VS = +5V Input Referred
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.
®
OPA631, OPA632
2
SPECIFICATIONS: VS = +3V
At TA = 25°C, G = +2 and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2). OPA631U, N OPA632U, N TYP +25°C GUARANTEED +25°C 0°C to 70°C MIN/ TEST MAX LEVEL(1)
PARAMETER AC PERFORMANCE (Figure 2) Small-Signal Bandwidth
CONDITIONS G = +2, VO ≤ 0.5Vp-p G = +5, VO ≤ 0.5Vp-p G = +10, VO ≤ 0.5Vp-p G ≥ +10 VO ≤ 0.5Vp-p 1V Step 0.5V Step 0.5V Step 1V Step VO = 1Vp-p, f = 5MHz f > 1MHz f > 1MHz
UNITS
Gain Bandwidth Product Peaking at a Gain of +1 Slew Rate Rise Time Fall Time Settling Time to 0.1% Spurious Free Dynamic Range Input Voltage Noise Input Current Noise DC PERFORMANCE Open-Loop Voltage Gain Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Offset Current Input Offset Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Least Positive Output Voltage Most Positive Output Voltage Current Output, Sourcing Current Output, Sinking Short Circuit Current (output shorted to either supply) Closed-Loop Output Impedance DISABLE (OPA632 only) On Voltage (device enabled Low) Off Voltage (device disabled High) On Disable Current (DIS pin) Off Disable Current (DIS pin) Disabled Quiescent Current Disable Time Enable Time Off Isolation POWER SUPPLY Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: U, N Thermal Resistance U SO-8 N SOT23-5, SOT23-6
61 15 7.7 63 5 95 5.6 5.6 40 44 6.2 2.0 60 0.5 — 12 0.3 — –0.5 2 72 10 || 2.1 400 || 1.2
45 11 4.6 47 — 52 9 9 63 37 7.0 2.6 54 3.5 — 21 1 — –0.3 1.75 66 — — 0.05 0.15 2.85 2.66 21 21 — — 1.0 1.8 100 — 20 — — — 2.7 10.5 5.7 5.0 50
35 9 4.0 34 — 46 11.3 11.3 85 34 7.8 2.9 50 4 45 26 1.3 2 –0.1 1.3 65 — — 0.05 0.16 2.84 2.60 14 14 — — 1.0 1.8 110 — 25 — — — 2.7 10.5 6.2 4.8 48
MHz MHz MHz MHz dB V/µs ns ns ns dBc nV/√Hz pA/√Hz dB mV µV/°C µA µA nA/°C V V dB kΩ || p kΩ || p V V V V mA mA mA Ω V V µA µA µA ns ns dB V V mA mA dB °C °C/W °C/W
min min min min typ min max max max min max max min max max max max max max min min typ typ max max min min min min typ typ min max max typ max typ typ typ min max max min min typ typ typ
B B B B C B B B B B B B A A B B B B B A A C C A A A A A A C C A A A C A C C C A A A A A C C C
VCM = 1.0V VCM = 1.0V
Input Referred
RL = 1kΩ to 1.5V RL = 150Ω to 1.5V RL = 1kΩ to 1.5V RL = 150Ω to 1.5V
Figure 2, f < 100kHz
0.03 0.05 2.95 2.85 55 55 80 0.2 1.0 1.7 66 0 0 100 60 70 — — 5.3 5.3 57 –40 to +85 125 150
f = 5MHz, Input to Output
VS = +3V VS = +3V Input Referred
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
OPA631, OPA632
ABSOLUTE MAXIMUM RATINGS
Power Supply ................................................................................ +11VDC Internal Power Dissipation .................................... See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range .................................................... –0.5 to +VS + 0.3V Storage Temperature Range: P, U, N ........................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C
ELECTROSTATIC DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications.
PIN CONFIGURATIONS
Top View—OPA631, OPA632 SO-8
NC Inverting Input Non-Inverting Input GND
1 2 3 4
8 7 6 5
DIS (OPA632 only) +VS Output NC
Top View—OPA631
SOT23-5
Top View—OPA632
SOT23-6
Output
1
6
+VS
Output
1
6
+VS
GND
2
GND
2
5
DIS
Non-Inverting Input
3
4
Inverting Input
Non-Inverting Input
3
4
Inverting Input
6
5
6
4
A31
1 2 3
A32
1 2
Pin Orientation/Package Marking
Pin Orientation/Package Marking
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER(1) 182 SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING OPA631U ORDERING NUMBER(2) OPA631U OPA631U/2K5 OPA631N/250 OPA631N/3K OPA632U OPA632U/2K5 OPA632N/250 OPA632N/3K TRANSPORT MEDIA Rails Tape and Reel Tape and Reel Tape and Reel Rails Tape and Reel Tape and Reel Tape and Reel
PRODUCT OPA631U
PACKAGE SO-8 Surface-Mount
"
OPA631N
"
5-Lead SOT23-5
"
331
"
–40°C to +85°C
"
A31
"
OPA632U
"
SO-8 Surface-Mount
"
182
"
–40°C to +85°C
"
OPA632U
"
OPA632N
"
6-Lead SOT23-6
"
332
"
–40°C to +85°C
"
A32
"
"
"
"
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /3K indicates 3000 devices per reel). Ordering 3000 pieces of “OPA632N/3K” will get a single 3000piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
OPA631, OPA632
4
3
4
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
SMALL-SIGNAL FREQUENCY RESPONSE 6 3 VO = 200mVp-p G = +2 12 9 6 3
LARGE-SIGNAL FREQUENCY RESPONSE VO = 0.2Vp-p
Normalized Gain (dB)
0 –3
Gain (dB)
–6 –9 –12 –15 –18 –21 –24 1 10 Frequency (MHz) 100 300 G = +10 G = +5
0 –3 –6 –9 –12 –15 –18 1 10 Frequency (MHz) 100 300 VO = 1Vp-p VO = 2Vp-p VO = 4Vp-p
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Input and Output Voltage (500mV/div)
Input and Output Voltage (50mV/div)
VO = 200mVp-p VO
VO = 4Vp-p VO
VIN
VIN
Time (10ns/div)
Time (10ns/div)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
DISABLE FEEDTHROUGH vs FREQUENCY –35 –40 –45
Feedthrough (dB)
Disable Voltage (1V/div)
VDIS
OPA632 Only VDIS = +5V
–50 –55 –60 –65 –70 –75 –80 –85 1 10 100 Frequency (MHz) 1000
VIN = 0.5V OPA632 Only Time (50ns/div)
VO
Output Voltage (250mV/div)
®
5
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
(Cont.)
1MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –30
2nd Harmonic Distortion (dBc)
–30
1MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE RL = 500Ω RL = 250Ω –50 RL = 150Ω –60 –70 –80 –90
–40 –50 –60 –70 –80 –90 0.1 1 Output Voltage (Vp-p) 4
3rd Harmonic Distortion (dBc)
–40
RL = 250Ω RL = 150Ω
0.1
1 Output Voltage (Vp-p)
4
5MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –30 –30 RL = 500Ω RL = 250Ω –50 RL = 150Ω –60 –70 –80 –90 0.1 1 Output Voltage (Vp-p) 4
5MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE RL = 250Ω –40 –50 –60 –70 RL = 500Ω –80 –90 0.1 1 Output Voltage (Vp-p) 4 RL = 150Ω
2nd Harmonic Distortion (dBc)
–40
10MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –30 RL = 500Ω
2nd Harmonic Distortion (dBc)
3rd Harmonic Distortion (dBc)
10MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –30
3rd Harmonic Distortion (dBc)
–40 –50 –60 –70 –80 –90 0.1 1 Output Voltage (Vp-p) 4 RL = 250Ω RL = 150Ω
–40 –50 –60 –70 –80 –90 0.1 1 Output Voltage (Vp-p) 4
RL = 500Ω RL = 250Ω RL = 150Ω
®
OPA631, OPA632
6
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
(Cont.)
2nd HARMONIC DISTORTION vs FREQUENCY –30
2nd Harmonic Distortion (dBc)
3rd HARMONIC DISTORTION vs FREQUENCY –30
3rd Harmonic Distortion (dBc)
–40 –50
VO = 2Vp-p RL = 150Ω G = +2 G = +5
–40 –50 –60 –70
VO = 2Vp-p RL = 150Ω
–60 –70 –80 –90 0.1
G = +10
G = +2 G = +5
–80 G = +10 –90
1 Frequency (MHz)
10
0.1
1 Frequency (MHz)
10
HARMONIC DISTORTION vs LOAD RESISTANCE –30
3rd-Order Spurious Level (dBc)
TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS –30 fO = 10MHz –40 –50 –60 –70 –80 –90 fO = 5MHz fO = 1MHz –16 –14 –12 –10 –8 Load Power at Matched 50Ω Load –6 –4 –2 0
Harmonic Distortion (dBc)
–40 –50 –60 –70 2nd Harmonic Distortion –80 –90 100 200 RL (Ω) 300 3rd Harmonic Distortion
VO = 2Vp-p fO = 5MHz
400
500
Single-Tone Load Power (dBm)
CMRR AND PSRR vs FREQUENCY 80
Rejection Ratio, Input Referred (dB)
INPUT NOISE DENSITY vs FREQUENCY 100
75 70 65 60 55 50 45 40 35 30 100 1k
CMRR
Voltage Noise (nV/√Hz) Current Noise (pA/√Hz)
PSRR
10
Voltage Noise, eni = 6.0nV/√Hz
Current Noise, ini = 1.9pA/√Hz
1 10k 100k 1M 10M 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz)
®
7
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
(Cont.)
1000
RS vs CAPACITIVE LOAD 2 1 0
Normalized Gain (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD CL = 1000pF CL = 10pF
100
RS (Ω)
–1 –2 –3 –4 –5 –6 –7
OPA63x CL 1kΩ +VS/2 RS VO
CL = 100pF
10
1 1 10 100 1000 Capacitive Load (pF)
–8 1 10 Frequency (MHz) 100 300
OPEN-LOOP GAIN AND PHASE 100 90 80 70 60 50 40 30 20 10 0 –10 –20 0 –30 –60 –90 –120 –150 –180 –210 –240 –270 –300 –330 –360 1G
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 100 G = +1 RF = 25Ω
Open-Loop Phase Open-Loop Gain
Output Impedance (Ω)
Open-Loop Gain (dB)
Open-Loop Phase (°)
10
1
0.1 1k 10k 100k 1M 10M 100M Frequency (Hz)
1k
10k
100k
1M
10M
100M
Frequency (Hz)
INPUT DC ERRORS vs TEMPERATURE 5.0 4.5 20
POWER SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 12 120 Sinking Output Current 10 8 6 Quiescent Supply Current 4 2 0 –40 –20 0 20 40 60 80 100 Temperature (°C) 40 20 0 Sourcing Output Current 100 80 60
18 16
Input Offset Voltage (mV)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 –40 –20 0 20 40 60 80 100 Temperature (°C) 10X Input Offset Current Input Bias Current Input Offset Voltage
Quiescent Supply Current (mA)
Input Bias Current (µA) 10x Input Offset Current (µA)
14 12 10 8 6 4 2 0
®
OPA631, OPA632
8
Output Current (mA)
TYPICAL PERFORMANCE CURVES: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
SMALL-SIGNAL FREQUENCY RESPONSE 6 3 VO = 200mVp-p G = +2 12 9 6 G = +5 3
LARGE-SIGNAL FREQUENCY RESPONSE
Normalized Gain (dB)
0 –3 –6 –9 –12 –15 –18 –21 –24 1 10 Frequency (MHz) 100 300 G = +10
VO = 200mVp-p
Gain (dB)
0 –3 –6 –9 –12 –15 –18 1 10 Frequency (MHz) 100 300 VO = 2Vp-p VO = 1Vp-p
2nd HARMONIC DISTORTION vs FREQUENCY –30 –30 VO = 1Vp-p RL = 150Ω G = +2 –50 –60 –70 G = +10 –80 –90 0.1 1 Frequency (MHz) 10
3rd HARMONIC DISTORTION vs FREQUENCY VO = 1Vp-p RL = 150Ω
2nd Harmonic Distortion (dBc)
3rd Harmonic Distortion (dBc)
–40
–40 –50 –60
G = +5
G = +2 –70 G = +10 –80 –90 0.1 1 Frequency (MHz) 10 G = +5
HARMONIC DISTORTION vs LOAD RESISTANCE –30 –40 3rd Harmonic Distortion –50 –60 –70 2nd Harmonic Distortion –80 –90 100 200 RL (Ω) 300 400 500 –30 VO = 1Vp-p fO = 5MHz
TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS fO = 10MHz
3rd-Order Spurious Level (dBc)
Harmonic Distortion (dBc)
–40 –50 –60 –70 –80 –90 –16 –14 –12 –10 –8 –6 –4 Single-Tone Load Power (dBm) fO = 5MHz fO = 1MHz
Load Power at Matched 50Ω Load
®
9
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
(Cont.)
1000
RS vs CAPACITIVE LOAD
6 3 0
FREQUENCY RESPONSE vs CAPACITIVE LOAD VO = 0.2Vp-p CL = 1000pF CL = 10pF
Normalized Gain (dB)
100
RS (Ω)
–3 –6 –9 –12 –15 –18 –21
OPA63x CL 1kΩ +VS/2 RS VO
CL = 100pF
10
1 1 10 100 1000 Capacitive Load (pF)
–24 1 10 Frequency (MHz) 100 300
OUTPUT SWING vs LOAD RESISTANCE 3.0 2.9 1.0
Quiescent Supply Current (mA)
10 9 8 7 6 5 4 3 2 1 0 3 4
SUPPLY AND OUTPUT CURRENTS vs SUPPLY VOLTAGE 200 180
Maximum Output Voltage (V)
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 50 100
0.8 0.7 0.6 0.5 0.4 0.3 0.2
Minimum Output Voltage (V)
Maximum VO
0.9
140 120 100 Output Current, Sinking 80 60 40 20 0
Minimum VO
0.1 0.0 1000
Output Current, Sourcing
5
6
7
8
9
10
RL (Ω)
Supply Voltage (V)
SLEW RATE AND GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 120 Slew Rate 100
Slew Rate (V/µs)
120 100 80 Gain Bandwidth Product 60 40 20 0 3 4 5 6 7 8 9 10 Supply Voltage (V)
Gain Bandwidth Product (MHz)
80 60 40 20 0
®
OPA631, OPA632
10
Output Current (mA)
Quiescent Supply Current
160
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK OPERATION The OPA631 and OPA632 are unity-gain stable, very highspeed, voltage-feedback op amps designed for single-supply operation (+3V to +5V). The input stage supports input voltages below ground, and within 1.0V of the positive supply. The complementary common-emitter output stage provides an output swing to within 30mV of ground and 130mV of the positive supply. They are compensated to provide stable operation with a wide range of resistive loads. The OPA632’s internal disable circuitry is intended to minimize system power when disabled. Figure 1 shows the AC-coupled, gain of +2 configuration used for the +5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground. Voltage swings reported in the Specifications are taken directly at the input and output pins. For the circuit of Figure 1, the total effective load on the output at high frequencies is 150Ω || 1500Ω. The disable pin (OPA635 only) needs to be driven by a low impedance source, such as a CMOS inverter. The 1.50kΩ resistors at the non-inverting input provide the common-mode bias voltage. Their parallel combination equals the DC resistance at the inverting input, minimizing the output DC offset.
+VS = 3V 6.8µF + 2.26kΩ 374Ω VIN 57.6Ω DIS (OPA632 only) 0.1µF +
OPA63x
RL 150Ω
VOUT
562Ω
750Ω
+VS 2
FIGURE 2. DC-Coupled Signal—Resistive Load to Supply Midpoint. SINGLE-SUPPLY ADC CONVERTER INTERFACE The front page shows a DC-coupled, single-supply ADC driver circuit. Many systems are now requiring +3V supply capability of both the ADC and its driver. The OPA632 provides excellent performance in this demanding application. Its large input and output voltage ranges, and low distortion, support converters such as the ADS901 shown in this figure. The input level-shifting circuitry was designed so that VIN can be between 0V and 0.5V, while delivering an output voltage of 1V to 2V for the ADS901. Both the OPA632 and ADS901 have power reduction pins with the same polarity for those systems that need to conserve power. DC LEVEL SHIFTING Figure 3 shows a DC-coupled non-inverting amplifier that level-shifts the input up to accommodate the desired output voltage range. Given the desired signal gain (G), and the amount VOUT needs to be shifted up (∆VOUT) when VIN is at the center of its range, the following equations give the resistor values that produce the best DC offset. NG = G + ∆VOUT/VS R1 = R4/G R2 = R4/(NG – G) R3 = R4/(NG –1) where: NG = 1 + R4/R3 (Noise Gain) VOUT = (G)VIN + (NG – G)VS Make sure that VIN and VOUT stay within the specified input and output voltage ranges.
+VS = 5V 6.8µF + 1.50kΩ 0.1µF VIN 53.6Ω 1.50kΩ DIS (OPA632 only) 0.1µF +
OPA63x
RL 150Ω
VOUT
0.1µF
750Ω
750Ω
+VS 2
FIGURE 1. AC-Coupled Signal—Resistive Load to Supply Midpoint. Figure 2 shows the DC-coupled, gain of +2 configuration used for the +3V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground. Though not strictly a “rail-to-rail” design, these parts come very close, while maintaining excellent performance. They will deliver ≈ 2.9Vp-p on a single +3V supply with 61MHz bandwidth. The 374Ω and 2.26kΩ resistors at the input level-shift VIN so that VOUT is within the allowed output voltage range when VIN = 0. See the Typical Performance Curves for information on driving capacitive loads.
®
11
OPA631, OPA632
+VS R2 R1 VIN
A unity gain buffer can be designed by selecting RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG ). This gives a Noise Gain of 2, so its response will be similar to the Characteristics Plots with G = +2 which typically gives a flat frequency response, but with less bandwidth.
OPA63x
VOUT
DESIGN-IN TOOLS
DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA631 and OPA632 in their three package styles. These are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown below:
BOARD PART NUMBER DEM-OPA68xU DEM-OPA6xxN LITERATURE REQUEST NUMBER MKT-351 MKT-348
R3
R4
FIGURE 3. DC Level-Shifting Circuit. The front page circuit is a good example of this type of application. It was designed to take VIN between 0V and 0.5V, and produce VOUT between 1V and 2V, when using a +3V supply. This means G = 2.00, and ∆VOUT = 1.50V – G • 0.25V = 1.00V. Plugging into the above equations gives: NG = 2.33, R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The resistors were changed to the nearest standard values. NON-INVERTING AMPLIFIER WITH REDUCED PEAKING Figure 4 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the OPA631 or OPA632 to have higher Noise Gain (NG), which reduces the AC response peaking (typically 5dB at G = +1 without RC) without changing the DC gain. VIN needs to be a low impedance source, such as an op amp. The resistor values are low to reduce noise. Using both RT and RF helps minimize the impact of parasitic impedances.
PRODUCT OPA63xU OPA63xN PACKAGE 8-Pin SO-8 5-Pin SOT23-5 6-Pin SOT23-6
Contact the Burr-Brown Applications support line to request any of these boards.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES Since the OPA631 and OPA632 are voltage feedback op amps, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a non-inverting unity gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short (see Figure 4). This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, for G > 1 application, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (Figure 1) to be less than approximately 400Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 3pF total parasitic on the inverting node, holding RF || RG
