OPA634

® OPA 634 OPA634 OPA635 For most current data sheet and other product information, visit www.burr-brown.com Wideband, Single Supply OPERATIONAL AMPLIFIERS TM FEATURES q q q q q q q q q HIGH BANDWIDTH: 150MHz (G = +2) +3V AND +5V OPERATION ZERO POWER DISABLE (OPA635) INPUT RANGE INCLUDES GROUND 4.8V OUTPUT SWING ON +5V SUPPLY HIGH OUTPUT CURRENT: 80mA HIGH SLEW RATE: 250V/µs LOW INPUT VOLTAGE NOISE: 5.6nV/√HZ AVAILABLE IN SOT23 PACKAGES APPLICATIONS q q q q q SINGLE SUPPLY ADC INPUT BUFFER SINGLE SUPPLY VIDEO LINE DRIVER WIRELESS LAN IF AMPLIFIER CCD IMAGING CHANNELS LOW POWER ULTRASOUND DESCRIPTION The OPA634 and OPA635 are low power, voltagefeedback, high-speed amplifiers designed to operate on +3V or +5V single-supply voltages. Operation on ±5V or +10V supplies is also supported. The input range extends below ground and to within 1.2V of the positive supply. Using complementary common-emitter outputs provides an output swing to within 30mV of ground and 140mV of positive supply. The high output drive current, low differential gain and phase errors make them ideal for single-supply composite video line driving. Low distortion operation is ensured by the high gain bandwidth (140MHz) and slew rate (250V/µs). This makes the OPA634 and OPA635 ideal input buffer stages to 3V and 5V CMOS converters. Unlike other low power, single-supply operational amplifiers, distortion performance improves as the signal swing is decreased. +3V 2.26kΩ 374Ω VIN OPA635 A low 5.6nV input voltage noise supports wide dynamic range operation. Multiplexing or system power reduction can be achieved using the high-speed disable line with the OPA635. Power dissipation can be reduced to zero by taking the disable line High. The OPA634 and OPA635 are available in an industry standard SO-8 package. The OPA634 is also available in an ultra-small SOT23-5 package, while the OPA635 is available in the SOT23-6. Where lower supply current and speed are required, consider the OPA631 and OPA632. RELATED PRODUCTS SINGLES Medium Speed, No Disable With Disable High Speed, No Disable With Disable OPA631 OPA632 OPA634 OPA635 DUALS OPA2631 — OPA2634 — Disable +3V Pwrdn ADS900 10-Bit 20Msps 22pF DIS 100Ω 562Ω 750Ω International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1999 Burr-Brown Corporation PDS-1465A Printed in U.S.A. June, 1999 SPECIFICATIONS: VS = +5V At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1). OPA634U, N OPA635U, N TYP +25°C 150 36 16 140 5 250 2.4 2.4 15 63 5.6 2.8 0.10 0.16 66 3 — 25 0.6 — –0.24 3.8 78 10 || 2.1 400 || 1.2 RL = 1kΩ to 2.5V R L = 150Ω to 2.5V RL = 1kΩ to 2.5V R L = 150Ω to 2.5V 0.03 0.1 4.86 4.65 80 100 100 0.2 1.0 4.0 70 0 0 100 60 70 — — 12 12 55 –40 to +85 125 150 +25°C 100 24 11 100 — 170 3.4 3.5 19 56 6.2 3.8 — — 63 7 — 45 2 — –0.1 3.5 75 — — 0.05 0.14 4.8 4.55 50 80 — — 1.0 4.1 110 — 30 — — — 2.7 10.5 12.5 11.3 52 GUARANTEED 0°C to 70°C 84 20 10 82 — 125 4.7 4.5 22 51 7.3 4.2 — — 60 8 — 55 2.3 — –0.05 3.45 73 — — 0.06 0.15 4.75 4.5 45 65 — — 1.0 4.2 120 — 40 — — — 2.7 10.5 13 9.75 50 –40°C to +85°C 78 18 8 75 — 115 5.2 4.8 23 50 7.7 5 — — 53 10 4.6 80 4 15 –0.01 3.4 65 — — 0.07 0.22 4.7 4.4 20 20 — — 1.0 4.3 120 — 50 — — — 2.7 10.5 13.25 8.5 49 MIN/ MAX TEST LEVEL(1) PARAMETER AC PERFORMANCE (Figure 1) Small-Signal Bandwidth CONDITIONS G = +2, VO ≤ 0.5Vp-p G = +5, VO ≤ 0.5Vp-p G = +10, VO ≤ 0.5Vp-p G ≥ +10 VO ≤ 0.5Vp-p G = +2, 2V Step 0.5V Step 0.5V Step G = +2, 1V Step VO = 2Vp-p, f = 5MHz f > 1MHz f > 1MHz UNITS Gain Bandwidth Product Peaking at a Gain of +1 Slew Rate Rise Time Fall Time Settling Time to 0.1% Spurious Free Dynamic Range Input Voltage Noise Input Current Noise NTSC Differential Gain NTSC Differential Phase DC PERFORMANCE Open-Loop Voltage Gain Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Offset Current Input Offset Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Common-Mode Rejection (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Least Positive Output Voltage Most Positive Output Voltage MHz MHz MHz MHz dB V/µs ns ns ns dBc nV/√Hz pA/√Hz % degrees dB mV µV/°C µA µA nA/°C V V dB kΩ || pF kΩ || pF V V V V mA mA mA Ω V V µA µA µA ns ns dB V V mA mA dB °C °C/W °C/W min min min min typ min max max max min max max typ typ min max max max max max max min min typ typ max max min min min min typ typ min max max typ max typ typ typ min max max min min typ typ typ B B B B C B B B B B B B C C A A B B B B B A A C C B A B A A A C C A A A C A C C C A A A A A C C C VCM = 2.0V VCM = 2.0V Input Referred Current Output, Sourcing Current Output, Sinking Short-Circuit Current (output shorted to either supply) Closed-Loop Output Impedance G = +2, f ≤ 100kHz DISABLE (OPA635 only) On Voltage (device enabled Low) Off Voltage (device disabled High) On Disable Current (DIS pin) Off Disable Current (DIS pin) Disabled Quiescent Current Disable Time Enable Time Off Isolation POWER SUPPLY Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: U, N Thermal Resistance U SO-8 N SOT23-5, SOT23-6 f = 5MHz, Input to Output Input Referred NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. ® OPA634, OPA635 2 SPECIFICATIONS: VS = +3V At TA = 25°C, G = +2 and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2). OPA634U, N OPA635U, N TYP +25°C +25°C GUARANTEED 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(1) PARAMETER AC PERFORMANCE (Figure 2) Small-Signal Bandwidth CONDITIONS G = +2, VO ≤ 0.5Vp-p G = +5, VO ≤ 0.5Vp-p G = +10, VO ≤ 0.5Vp-p G ≥ +10 VO ≤ 0.5Vp-p 1V Step 0.5V Step 0.5V Step 1V Step VO = 1Vp-p, f = 5MHz f > 1MHz f > 1MHz UNITS Gain Bandwidth Product Peaking at a Gain of +1 Slew Rate Rise Time Fall Time Settling Time to 0.1% Spurious Free Dynamic Range Input Voltage Noise Input Current Noise DC PERFORMANCE Open-Loop Voltage Gain Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Offset Current Input Offset Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Common-Mode Rejection (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Least Positive Output Voltage Most Positive Output Voltage 110 39 16 150 5 215 2.8 3.0 14 65 5.6 2.8 67 1.5 — 25 0.6 — –0.25 1.8 75 10 || 2.1 400 || 1.2 77 24 12 100 — 160 4.3 4.4 30 56 6.2 3.7 64 4 — 42 2 — –0.1 1.6 67 — — 0.043 0.08 2.86 2.70 35 30 — — 0.5 1.9 100 — 30 — — — 2.7 10.5 11.1 10.1 49 65 20 10 85 — 123 4.5 4.6 32 52 7.3 4.2 60 5 — 55 2.3 — –0.05 1.55 64 — — 0.045 0.09 2.85 2.69 30 27 — — 0.5 2.1 110 — 40 — — — 2.7 10.5 11.4 8.6 45 58 19 8 80 — 82 6.3 6.0 38 47 7.7 4.4 56 6 46 60 4 40 –0.01 1.5 61 — — 0.06 0.13 2.45 2.65 12 10 — — 0.5 2.2 110 — 50 — — — 2.7 10.5 11.6 8.0 44 MHz MHz MHz MHz dB V/µs ns ns ns dBc nV/√Hz pA/√Hz dB mV µV/°C µA µA nA/°C V V dB k Ω || p k Ω || p V V V V mA mA mA Ω V V µA µA µA ns ns dB V V mA mA dB °C °C/W °C/W min min min min typ min max max max min max max min max max max max max max min min typ typ max max min min min min typ typ min max max typ max typ typ typ min max max min min typ typ typ B B B B C B B B B B B B A A B B B B B A A C C A A A A A A C C A A A C A C C C A A A A A C C C VCM = 1.0V VCM = 1.0V Input Referred RL = 1kΩ to 1.5V RL = 150Ω to 1.5V RL = 1kΩ to 1.5V RL = 150Ω to 1.5V Current Output, Sourcing Current Output, Sinking Short Circuit Current (output shorted to either supply) Closed-Loop Output Impedance Figure 2, f < 100kHz DISABLE (OPA635 only) On Voltage (device enabled Low) Off Voltage (device disabled High) On Disable Current (DIS pin) Off Disable Current (DIS pin) Disabled Quiescent Current Disable Time Enable Time Off Isolation POWER SUPPLY Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: U, N Thermal Resistance U SO-8 N SOT23-5, SOT23-6 0.035 0.06 2.9 2.8 45 65 100 0.2 1.0 1.8 66 0 0 100 60 70 — — 10.8 10.8 50 –40 to +85 125 150 f = 5MHz, Input to Output Input Referred NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA634, OPA635 ABSOLUTE MAXIMUM RATINGS Power Supply ................................................................................ +11VDC Internal Power Dissipation .................................... See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................... –0.5 to +VS Storage Temperature Range: P, U, N ........................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATIONS Top View—OPA634, OPA635 SO-8 NC Inverting Input Non-Inverting Input GND 1 2 3 4 8 7 6 5 DIS (OPA635 only) +VS Output NC Top View—OPA634 SOT23-5 Top View—OPA635 SOT23-6 Output 1 6 +VS Output 1 6 +VS GND 2 GND 2 5 DIS Non-Inverting Input 3 4 Inverting Input Non-Inverting Input 3 4 Inverting Input 6 5 6 4 B34 1 2 3 A35 1 2 Pin Orientation/Package Marking Pin Orientation/Package Marking PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 182 SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING OPA635U ORDERING NUMBER(2) OPA635U OPA635U/2K5 OPA635N/250 OPA635N/3K OPA634U OPA634U/2K5 OPA634N/250 OPA634N/3K TRANSPORT MEDIA Rails Tape and Reel Tape and Reel Tape and Reel Rails Tape and Reel Tape and Reel Tape and Reel PRODUCT OPA635U PACKAGE SO-8 Surface-Mount " OPA635N " 6-Lead SOT23-6 " 332 " –40°C to +85°C " A35 " OPA634U " SO-8 Surface-Mount " 182 " –40°C to +85°C " OPA634U " OPA634N " 5-Lead SOT23-5 " 331 " –40°C to +85°C " B34 " " " " " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 3000 pieces of “OPA635N/3K” will get a single 3000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® OPA634, OPA635 4 3 4 TYPICAL PERFORMANCE CURVES: VS = +5V At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1). SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.2Vp-p 3 G = +2 9 G = +5 6 12 LARGE-SIGNAL FREQUENCY RESPONSE VO = 0.2Vp-p Normalized Gain (dB) 0 –6 –9 –12 –15 –18 1 10 Frequency (MHz) 100 300 G = +10 Gain (dB) –3 3 0 VO = 1Vp-p –3 –6 VO = 4Vp-p –9 –12 1 10 Frequency (MHz) 100 300 VO = 2Vp-p SMALL-SIGNAL PULSE RESPONSE Input and Output Voltage (500mV/div) Input and Output Voltage (50mV/div) LARGE-SIGNAL DISABLE/ENABLE RESPONSE VO = 2Vp-p VO VO = 200mVp-p VO VIN VIN Time (10ns/div) Time (10ns/div) LARGE-SIGNAL DISABLE/ENABLE RESPONSE VDIS DISABLE FEEDTHROUGH vs FREQUENCY –35 –40 Output Voltage (250mV/div) –45 Feedthrough (dB) OPA635 only VDIS = +5V Disable Voltage (1V/div) –50 –55 –60 –65 –70 –75 –80 –85 1 10 100 Frequency (MHz) 1000 VO VIN = 0.5V OPA635 only Time (50ns/div) ® 5 OPA634, OPA635 TYPICAL PERFORMANCE CURVES: VS = +5V At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1). (CONT) 5MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –40 –45 –40 –45 5MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 0.1 1 Output Voltage (Vp-p) RL = 150Ω RL = 250Ω RL = 500Ω 4 3rd Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 0.1 RL = 150Ω RL = 250Ω RL = 500Ω 1 Output Voltage (Vp-p) 4 10MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –40 –45 –40 –45 10MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 0.1 1 Output Voltage (Vp-p) 4 RL = 500Ω RL = 150Ω RL = 250Ω 3rd Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 0.1 RL = 150Ω RL = 500Ω RL = 250Ω 1 Output Voltage (Vp-p) 4 20MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –40 –45 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) 20MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –50 –55 –60 –65 –70 –75 –80 –85 –90 0.1 RL = 250Ω RL = 150Ω RL = 500Ω RL = 500Ω RL = 250Ω RL = 150Ω 1 Output Voltage (Vp-p) 4 0.1 1 Output Voltage (Vp-p) 4 ® OPA634, OPA635 6 TYPICAL PERFORMANCE CURVES: VS = +5V At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1). (CONT) 2nd HARMONIC DISTORTION vs FREQUENCY –40 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 1 Frequency (MHz) 10 20 G = +10 G = +5 G = +2 VO = 2Vp-p RL = 100Ω –45 3rd HARMONIC DISTORTION vs FREQUENCY VO = 2Vp-p RL = 100Ω 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 1 Frequency (MHz) 10 20 G = +10 G = +2 G = +5 HARMONIC DISTORTION vs LOAD RESISTANCE –40 3rd-Order Spurious Level (dBc) –40 TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –16 –14 –12 –10 –8 fO = 5MHz Load Power at Matched 50Ω Load –6 –4 –2 0 fO = 20MHz fO = 10MHz –45 Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 100 VO = 2Vp-p fO = 5MHz 3rd Harmonic Distortion 2nd Harmonic Distortion 200 RL (Ω) 300 400 500 Single-Tone Load Power (dBm) CMRR AND PSRR vs FREQUENCY 80 Rejection Ratio, Input Referred (dB) INPUT NOISE DENSITY vs FREQUENCY 100 75 70 65 60 55 50 45 40 35 30 100 1k CMRR Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) PSRR 10 Voltage Noise, eni = 5.6nV/√Hz Current Noise, ini = 2.8pA/√Hz 1 10k 100k 1M 10M 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) ® 7 OPA634, OPA635 TYPICAL PERFORMANCE CURVES: VS = +5V At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1). (CONT) 1000 RS vs CAPACITIVE LOAD 2 1 0 Normalized Gain (dB) FREQUENCY RESPONSE vs CAPACITIVE LOAD VO = 0.2Vp-p CL = 1000pF CL = 10pF 100 RS (Ω) –1 –2 –3 –4 –5 –6 –7 OPA63x CL 1kΩ +VS/2 RS VO CL = 100pF 10 1 1 10 100 1000 Capacitive Load (pF) –8 1 10 Frequency (MHz) 100 300 OPEN-LOOP GAIN AND PHASE 100 90 80 70 60 50 40 30 20 10 0 –10 –20 0 –30 –60 –90 –120 –150 –180 –210 –240 –270 –300 –330 –360 1G CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 100 G = +1 RF = 25Ω Open-Loop Phase Open-Loop Gain Output Impedance (Ω) Open-Loop Gain (dB) Open-Loop Phase (°) 10 1 0.1 1k 10k 100k 1M 10M 100M Frequency (Hz) 1k 10k 100k 1M 10M 100M Frequency (Hz) INPUT DC ERRORS vs TEMPERATURE 5.0 4.5 Input Offset Voltage 50 45 16 14 Power Supply Current (mA) SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 160 Sinking Output Current Quiescent Supply Current 10 8 6 4 2 0 –40 –20 0 20 40 60 80 100 Temperature (°C) 100 80 60 40 20 0 Output Current (mA) Input Offset Voltage (mV) Input Bias Current (µA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 –40 –20 0 40 35 30 10X Input Offset Current (µA) 140 120 12 Sourcing Output Current Input Bias Current 25 20 15 10X Input Offset Current 10 5 0 20 40 60 80 100 Temperature (°C) ® OPA634, OPA635 8 TYPICAL PERFORMANCE CURVES: VS = +3V At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2). SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.2Vp-p 3 G = +2 9 6 G = +5 12 LARGE-SIGNAL FREQUENCY RESPONSE VO = 0.2Vp-p Normalized Gain (dB) 0 Gain (dB) –3 –6 –9 –12 –15 –18 1 10 Frequency (MHz) 100 300 G = +10 3 0 –3 –6 –9 –12 1 10 Frequency (MHz) 100 300 VO = 1Vp-p VO = 2Vp-p 2nd HARMONIC DISTORTION vs FREQUENCY –40 –45 –40 VO = 1Vp-p RL = 100Ω –45 3rd HARMONIC DISTORTION vs FREQUENCY VO = 1Vp-p RL = 100Ω 2nd Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 1 3rd Harmonic Distortion (dBc) –50 –55 –60 –65 –70 –75 –80 –85 –90 G = +2 G = +5 G = +10 G = +2 G = +5 G = +10 10 Frequency (MHz) 20 1 Frequency (MHz) 10 20 HARMONIC DISTORTION vs LOAD RESISTANCE –40 –40 –45 Harmonic Distortion (dBc) TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –16 fO = 5MHz –14 –12 –10 Load Power at Matched 50Ω Load –8 –6 –4 fO = 10MHz fO = 20MHz –50 –55 –60 –65 –70 –75 –80 –85 –90 100 3rd Harmonic Distortion 2nd Harmonic Distortion 200 RL (Ω) 300 400 500 3rd-Order Spurious Level (dBc) VO = 1Vp-p fO = 5MHz Single-Tone Load Power (dBm) ® 9 OPA634, OPA635 TYPICAL PERFORMANCE CURVES: VS = +3V At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2). (CONT) 1000 RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 2 1 0 Normalized Gain (dB) VO = 0.2Vp-p CL = 1000pF CL = 10pF 100 RS (Ω) –1 –2 –3 –4 –5 –6 –7 OPA63x CL 1kΩ +VS/2 RS VO CL = 100pF 10 1 1 10 100 1000 Capacitive Load (pF) –8 1 10 Frequency (MHz) 100 300 OUTPUT SWING vs LOAD RESISTANCE 3.0 2.9 Maximum VO 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Minimum VO 0.2 0.1 50 100 R L (Ω) 0.0 1000 Maximum Output Voltage (V) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 ® OPA634, OPA635 10 Minimum Output Voltage (V) APPLICATIONS INFORMATION WIDEBAND VOLTAGE FEEDBACK OPERATION The OPA634 and OPA635 are unity-gain stable, very high speed voltage feedback op amps designed for single supply operation (+3V to +5V). The input stage supports input voltages below ground, and within 1.2V of the positive supply. The complementary common-emitter output stage provides an output swing to within 30mV of ground and 140mV of the positive supply. They are compensated to provide stable operation with a wide range of resistive loads. The OPA635’s internal disable circuitry is designed to minimize supply current when disabled. Figure 1 shows the AC-coupled, gain of +2 configuration used for the +5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground. Voltage swings reported in the Specifications are taken directly at the input and output pins. For the circuit of Figure 1, the total effective load on the output at high frequencies is 150Ω || 1500Ω. The disable pin needs to be driven by a low impedance source, such as a CMOS inverter. The 1.50kΩ resistors at the non-inverting input provide the common-mode bias voltage. Their parallel combination equals the DC resistance at the inverting input, minimizing the DC offset. +VS = 3V 6.8µF + 2.26kΩ 374Ω VIN 57.6Ω DIS (OPA635 only) 0.1µF + OPA63x RL 150Ω VOUT 562Ω 750Ω +VS 2 FIGURE 2. DC-Coupled Signal—Resistive Load to Supply Midpoint. SINGLE SUPPLY ADC CONVERTER INTERFACE The front page shows a DC-coupled, single supply ADC driver circuit. Many systems are now requiring +3V supply capability of both the ADC and its driver. The OPA635 provides excellent performance in this demanding application. Its large input and output voltage ranges, and low distortion, support converters such as the ADS900 shown in this figure. The input level-shifting circuitry was designed so that VIN can be between 0V and 0.5V, while delivering an output voltage of 1V to 2V for the ADS900. Both the OPA635 and ADS900 have power reduction pins with the same polarity for those systems that need to conserve power. DC LEVEL SHIFTING +VS = 5V 6.8µF + 1.50kΩ 0.1µF VIN 53.6Ω 1.50kΩ DIS (OPA635 only) 0.1µF + OPA63x RL 150Ω VOUT 0.1µF 750Ω 750Ω +VS 2 FIGURE 1. AC-Coupled Signal—Resistive Load to Supply Midpoint. Figure 2 shows the DC-coupled, gain of +2 configuration used for the +3V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground. Though not strictly a “rail-to-rail” design, these parts come very close, while maintaining excellent performance. They will deliver ≤ 2.8Vp-p on a single +3V supply with 110MHz bandwidth. The 374Ω and 2.26kΩ resistors at the input level-shift VIN so that VOUT is within the allowed output voltage range when VIN = 0. See the Typical Performance Curves for information on driving capacitive loads. Figure 3 shows a DC-coupled non-inverting amplifier that level-shifts the input up to accommodate the desired output voltage range. Given the desired signal gain (G), and the amount VOUT needs to be shifted up (∆VOUT) when VIN is at the center of its range, the following equations give the resistor values that produce the best DC offset. NG = G + ∆VOUT/VS R1 = R4/G R2 = R4/(NG – G) R3 = R4/(NG –1) where: NG = 1 + R4/R3 VOUT = (G)VIN + (NG – G)VS Make sure that VIN and VOUT stay within the specified input and output voltage ranges. ® 11 OPA634, OPA635 +VS R2 R1 VIN A unity gain buffer can be designed by selecting RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG ). This gives a Noise Gain of 2, so its response will be similar to the Characteristics Plots with G = +2. Decreasing RC to 20.0Ω will increase the Noise Gain to 3, which typically gives a flat frequency response, but with less bandwidth. VOUT OPA63x The circuit in Figure 1 can be redesigned to have less peaking by increasing the noise gain to 3. This is accomplished by adding RC = 2.55kΩ between the op amps inputs. R3 R4 DESIGN-IN TOOLS DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA634 and OPA635 in their three package styles. These are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown below: BOARD PART NUMBER DEM-OPA68xU DEM-OPA6xxN LITERATURE REQUEST NUMBER MKT-351 MKT-348 FIGURE 3. DC Level-Shifting Circuit. The front page circuit is a good example of this type of application. It was designed to take VIN between 0V and 0.5V, and produce VOUT between 1V and 2V, when using a +3V supply. This means G = 2.00, and ∆VOUT = 1.50V – G • 0.25V = 1.00V. Plugging into the above equations gives: NG = 2.33, R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The resistors were changed to the nearest standard values. NON-INVERTING AMPLIFIER WITH REDUCED PEAKING Figure 4 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the OPA634 or OPA635 to have higher Noise Gain (NG), which reduces the AC response peaking (typically 5dB at G = +1 without RC) without changing the DC gain. VIN needs to be a low impedance source, such as an op amp. The resistor values are low to reduce noise. Using both RT and RF helps minimize the impact of parasitic impedances. PRODUCT OPA63xU OPA63xN PACKAGE 8-Pin SO-8 5-Pin SOT23-5 6-Pin SOT23-6 Contact the Burr-Brown Applications support line to request any of these boards. OPERATING SUGGESTIONS OPTIMIZING RESISTOR VALUES Since the OPA634 and OPA635 are voltage feedback op amps, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a non-inverting unity gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short (see Figure 4). This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, for G > 1 application, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (Figure 1) to be less than approximately 400Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 3pF total parasitic on the inverting node, holding RF || RG 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 750Ω feedback used in the typical performance specifications is a good starting point for design. See Figure 4 for the unity gain follower application. d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (