OPA680U

® OPA 680 OPA680 OPA 680 OPA6 80 Wideband, Voltage Feedback OPERATIONAL AMPLIFIER With Disable TM FEATURES q q q q q q q q WIDEBAND +5V OPERATION: 220MHz (G = 2) UNITY GAIN STABLE: 400MHz (G = 1) HIGH OUTPUT CURRENT: 150mA OUTPUT VOLTAGE SWING: ±4.0V HIGH SLEW RATE: 1800V/µs LOW SUPPLY CURRENT: 6.4mA LOW DISABLED CURRENT: 300µA ENABLE/DISABLE TIME: 25ns/100ns APPLICATIONS q q q q q q q VIDEO LINE DRIVER xDSL LINE DRIVER/RECEIVER HIGH SPEED IMAGING CHANNELS ADC BUFFERS PORTABLE INSTRUMENTS TRANSIMPEDANCE AMPLIFIERS ACTIVE FILTERS DESCRIPTION The OPA680 represents a major step forward in unity gain stable, voltage feedback op amps. A new internal architecture provides slew rate and full power bandwidth previously found only in wideband current feedback op amps. A new output stage architecture delivers high currents with a minimal headroom requirement. These combine to give exceptional single supply operation. Using a single +5V supply, the OPA680 can deliver a 1V to 4V output swing with over 100mA drive current and 150MHz bandwidth. This combination of features makes the OPA680 an ideal RGB line driver or single supply ADC input driver. The OPA680’s low 6.4mA supply current is precisely trimmed at 25°C. This trim, along with low temperature +5V 1.2kΩ drift, guarantees lower maximum supply current than competing products. System power may be reduced further using the optional disable control pin. Leaving this disable pin open, or holding it high, will operate the OPA680 normally. If pulled low, the OPA680 supply current drops to less than 300µA while the output goes to a high impedance state. This feature may be used for either power savings or to implement video MUX applications. OPA680 RELATED PRODUCTS SINGLES Voltage Feedback Current Feedback Fixed Gain OPA680 OPA681 OPA682 DUALS OPA2680 OPA2681 OPA2682 TRIPLES OPA3680 OPA3681 OPA3682 +5V 3kΩ +3.5V Clock 0.1µF 400Ω 50Ω DIS 40Ω 0.5Vp-p 0.1µF VIN OPA680 2Vp-p Analog Input 22pF +2.5V 0.1µF Gnd 3kΩ REFB +1.5V 0.1µF ADS822 10-Bit 40MSPS CM +VS REFT 0.1µF 1.15kΩ Single-Supply, High Speed, 10-Bit Digitzer International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation PDS-1426E 1 Printed in U.S.A. OPA680 October, 1999 SPECIFICATIONS: VS = ±5V RF = 402Ω, RL = 100Ω, and G = +2, (Figure 1 for AC performance only), unless otherwise noted. OPA680P, U, N TYP +25°C 400 220 30 300 30 4 175 1800 1.4 2.8 12 8 –68 –80 –80 –88 4.8 2.5 0.05 0.03 58 ±1.0 +8 ±0.1 +25°C(2) GUARANTEED 0°C to 70°C(3) –40°C to +85°C(3) MIN/ TEST MAX LEVEL(1) typ min min min typ typ typ min typ typ typ typ max max max max max max typ typ min max max max max max max min min typ typ min min min min typ typ typ typ typ typ typ typ min max max typ max max min min typ typ typ typ C B B B C C C B C C C C B B B B B B C C A A B A B A B A A C C A A A A C C C C C C C C A A A C A A A A C C C C PARAMETER AC PERFORMANCE (Figure 1) Small Signal Bandwidth CONDITIONS G = +1, VO = 0.5Vp-p, RF = 25Ω G = +2, VO = 0.5Vp-p G = +10, VO = 0.5Vp-p G ≥ 10 G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 5Vp-p G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, VO = 5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 G = +2, NTSC, VO = 1.4Vp, RL = 150 VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V UNITS MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz % deg dB mV µV/°C µA nA/°C µA nA/°C V dB kΩ || pF MΩ || pF Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL ) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled Low) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (+PSRR) THERMAL CHARACTERISTICS Specified Operating Range P, U, N Package Thermal Resistance, θJA P 8-Pin DIP U SO-8 N SOT23-6 210 20 200 200 20 200 190 20 200 1400 1200 900 –63 –70 –75 –85 5.3 2.8 –62 –68 –73 –83 5.9 3.0 –60 –65 –70 –80 6.1 3.6 ±4.5 +14 54 ±0.7 ±3.4 56 52 ±5.2 ±10 +19 –70 ±1.0 ±1 ±3.3 53 50 ±6.0 ±10 +32 –150 ±1.2 ±1.5 ±3.2 52 VCM = ±1V VCM = 0 VCM = 0 No Load 100Ω Load VO = 0 VO = 0 G = +2, f = 100kHz VDIS = 0 ±3.5 59 190 || 0.6 3.2 || 0.9 ±4.0 ±3.9 +190 –150 0.03 –300 100 25 70 4 ±50 ±20 3.3 1.8 100 ±5 ±3.8 ±3.7 +160 –135 ±3.7 ±3.6 +140 –130 ±3.6 ±3.3 +80 –80 V V mA mA Ω µA ns ns dB pF mV mV V V µA V V mA mA dB °C °C/W °C/W °C/W G = +2, 5MHz G = +2, RL = 150Ω, VIN = 0 G = +2, RL = 150Ω, VIN = 0 VDIS = 0 3.5 1.7 160 3.6 1.6 160 3.7 1.5 160 VS = ±5V VS = ±5V Input Referred ±6 6.8 6.0 60 6.4 6.4 65 –40 to +85 ±6 7.0 6.0 58 ±6 7.2 5.3 56 Junction-to-Ambient 100 125 150 NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction Temperature = Ambient for 25°C guaranteed specifications. (3) Junction Temperature = Ambient at low temperature limit: Junction Temperature = Ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits. ® OPA680 2 SPECIFICATIONS: VS = +5V RF = 402Ω, RL = 100Ω to VS /2, G = +2, (Figure 2 for AC performance only), unless otherwise noted. OPA680P, U, N TYP +25°C 300 220 25 250 20 5 200 1000 1.6 2.0 12 8 –60 –70 –72 –80 5 2.5 0.06 0.03 58 ±2.0 +8 ±0.1 +25°C(2) GUARANTEED 0°C to 70°C(3) –40°C to +85°C(3) MIN/ TEST MAX LEVEL(1) typ min min min typ typ typ min typ typ typ typ max max max max max max typ typ min max max max max max max max min min typ typ min min min max max min typ typ typ typ typ typ typ typ min max typ typ max max min typ typ typ typ typ C B B B C C C B C C C C B B B B B B C C A A B A B A B A A A C C A A A A A A C C C C C C C C A A C C B A A C C C C C PARAMETER AC PERFORMANCE (Figure 2) Small Signal Bandwidth CONDITIONS G = +1, VO < 0.5Vp-p, RF = ±25Ω G = +2, VO < 0.5Vp-p G = +10, VO < 0.5Vp-p G ≥ 10 G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2 G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2 VO = 2.5V, RL = 100Ω to 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V UNITS MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz % deg dB mV µV/°C µA nA/°C µA nA/°C V V dB kΩ || pF MΩ || pF Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise Time/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Most Positive Output Voltage Least Positive Output Voltage 160 20 200 160 19 190 140 18 180 700 670 550 –55 –66 –66 –76 5.3 2.8 –54 –63 –64 –74 6.0 3.0 –51 –59 –62 –71 6.2 3.4 ±6.0 +15 54 ±0.6 1.6 3.4 56 52 ±7 –10 +18 –52 ±1.0 ±0.5 1.7 3.3 53 50 ±8.5 –12 +32 –80 ±1.2 ±1.0 1.8 3.2 52 VCM = 2.5V ±0.5V VCM = 2.5V VCM = 2.5V No Load RL = 100Ω to 2.5V No Load RL = 100Ω to 2.5V G =+2, f = 100kHz VDIS = 0 G = +2, 5MHz G = +2, RL = 150Ω, VIN = VS /2 G = +2, RL = 150Ω, VIN = VS /2 VDIS = 0 1.5 3.5 59 92 || 1.4 2.2 || 1.5 4 3.9 1 1.1 +150 –110 0.03 –250 100 25 65 4 ±50 ±20 3.3 1.8 100 5 Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disable Low) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) POWER SUPPLY Specified Single Supply Operating Voltage Maximum Single Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: P, U, N Thermal Resistance, θJA P 8-Pin DIP U SO-8 N SOT23-6 3.8 3.7 1.2 1.3 +110 –80 3.6 3.5 1.4 1.5 +110 –70 3.5 3.4 1.5 1.7 +60 –50 V V V V mA mA Ω µA ns ns dB pF mV mV V V µA V V mA mA dB °C °C/W °C/W °C/W 3.5 1.7 3.6 1.6 3.7 1.5 VS = +5V VS = +5V Input Referred 5.1 5.1 55 –40 to +85 12 6.0 4.0 12 6.0 4.0 12 6.0 3.8 Junction-to-Ambient 100 125 150 NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction Temperature = Ambient for 25°C guaranteed specifications. (3) Junction Temperature = Ambient at low temperature limit: Junction Temperature = Ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits. ® 3 OPA680 ABSOLUTE MAXIMUM RATINGS Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ..................................... See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: P, U, N ........................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATIONS Top View DIP/SO-8 Top View SOT23-6 Output 1 6 +VS –VS 2 5 DIS NC Inverting Input Non-Inverting Input –VS 1 2 3 4 8 7 6 5 DIS Non-Inverting Input 3 4 Inverting Input +VS Output 6 5 NC 4 3 A80 1 Pin Orientation/Package Marking PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 006 182 " 332 " SPECIFIED TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C " –40°C to +85°C " PACKAGE MARKING OPA680P OPA680U " A80 " ORDERING NUMBER(2) OPA680P OPA680U OPA680U/2K5 OPA680N/250 OPA680N/3K TRANSPORT MEDIA Rails Rails Tape and Reel Tape and Reel Tape and Reel PRODUCT OPA680P OPA680U " OPA680N " PACKAGE 8-Pin Plastic DIP SO-8 Surface-Mount " 6-Pin SOT23-6 " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 3000 pieces of “OPA680N/3K” will get a single 3000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA680 4 2 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. SMALL-SIGNAL FREQUENCY RESPONSE 6 3 Normalized Gain (3dB/div) LARGE-SIGNAL FREQUENCY RESPONSE 15 12 9 Gain (3dB/div) VO = 0.5Vp-p G = +1 RF = 25Ω G = +2 VO = 1Vp-p VO = 2Vp-p 0 –3 –6 –9 –12 –15 –18 –21 –24 0.5 10 Frequency (MHz) 100 500 G = +10 G = +5 6 3 0 –3 –6 –9 –12 –15 0.5 10 Frequency (MHz) 100 500 VO = 7Vp-p VO = 4Vp-p SMALL-SIGNAL PULSE RESPONSE 400 +4 G = +2 VO = 0.5Vp-p +3 LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 5Vp-p Output Voltage (100mV/div) 300 200 100 0 –100 –200 –300 –400 Time (5ns/div) Output Voltage (1V/div) +2 +1 0 –1 –2 –3 –4 Time (5ns/div) LARGE-SIGNAL DISABLE/ENABLE RESPONSE VDIS DISABLED FEEDTHROUGH vs FREQUENCY VDIS (2V/div) 6.0 4.0 2.0 0 Output Voltage 2.0 –45 –50 VDIS = 0 Feedthrough (5dB/div) –55 –60 –65 –70 –75 –80 –85 –90 –95 Forward Reverse VO (0.4V/div) 1.6 0.8 0.4 0 G = +2 VIN = +1V Time (50ns/div) 1 10 Frequency (MHz) 100 ® 5 OPA680 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. 5MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 –60 (CONT) 5MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) –65 –70 –75 3rd Harmonic Distortion (dBc) RL = 100Ω RL = 200Ω –65 –70 –75 –80 –85 RL = 500Ω –90 RL = 100Ω RL = 200Ω RL = 500Ω –80 –85 –90 0.1 1 Output Voltage Swing (Vp-p) 10 0.1 1 Output Voltage Swing (Vp-p) 10 10MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 10MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) –65 –70 –75 RL = 100Ω RL = 200Ω –65 RL = 100Ω –70 –75 –80 –85 –90 RL = 200Ω RL = 500Ω –80 –85 –90 0.1 1 Output Voltage Swing (Vp-p) 10 RL = 500Ω 0.1 1 Output Voltage Swing (Vp-p) 10 20MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 RL = 100Ω –50 20MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) –55 –60 –65 –70 –75 –80 0.1 3rd Harmonic Distortion (dBc) RL = 200Ω –55 RL = 100Ω –60 –65 –70 –75 –80 RL = 200Ω RL = 500Ω RL = 500Ω 1 Output Voltage Swing (Vp-p) 10 0.1 1 Output Voltage Swing (Vp-p) 10 ® OPA680 6 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. (CONT) 2nd HARMONIC DISTORTION vs FREQUENCY –40 2nd Harmonic Distortion (dBc) 3rd HARMONIC DISTORTION vs FREQUENCY –40 3rd Harmonic Distortion (dBc) –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 0.1 VO = 2Vp-p RL = 100Ω G = +10 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 1 Frequency (MHz) 10 20 0.1 VO = 2Vp-p RL = 100Ω G = +10 G = +5 G = +5 G = +2 G = +2 1 Frequency (MHz) 10 20 INPUT VOLTAGE AND CURRENT NOISE DENSITY 100 –40 TWO-TONE, 3rd-ORDER SPURIOUS LEVEL 50MHz 3rd-Order Spurious Level (dBc) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) –50 –60 20MHz –70 10MHz –80 Load Power at matched 50Ω load –90 10 Voltage Noise 4.8nV/√Hz Current Noise 1 100 1k 10k 100k 2.5pA/√Hz 1M 10M –8 –6 –4 –2 0 2 4 6 8 10 Frequency (Hz) Single-Tone Load Power (dBm) RECOMMENDED RS vs CAPACITIVE LOAD 80 12 FREQUENCY RESPONSE vs CAPACITIVE LOAD Gain-to-Capacitive Load (3dB/div) 70 60 50 9 6 3 0 –3 –6 –9 –12 –15 –18 0 VIN G = +2 CL = 10pF CL = 22pF CL = 47pF RS OPA680 RS (Ω) 40 30 20 10 0 10 Capacitive Load (pF) 100 VO 402Ω 402Ω CL 1kΩ CL = 100pF 1kΩ is optional 100MHz Frequency (20MHz/div) 200MHz ® 7 OPA680 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. (CONT) CMRR AND PSRR vs FREQUENCY 100 OPEN-LOOP GAIN AND PHASE 70 60 Open-Loop Phase Open-Loop Gain (dB) 0 –30 Open-Loop Gain –60 –90 –120 –150 –180 –210 –240 –270 10k 100k 1M 10M 100M 1G Frequency (Hz) Open-Loop Phase (degrees) Supply Current (2.5mA/div) Power Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 90 80 70 60 50 40 30 20 10 0 10k 100k 1M Frequency (Hz) 10M 100M +PSRR CMRR –PSRR 50 40 30 20 10 0 –10 –20 COMPOSITE VIDEO dG/dP 0.2 0.175 dG/dP (%/degrees) Video In +5V DIS Video Loads Optional 1.3kΩ Pulldown TYPICAL DC DRIFT OVER TEMPERATURE 15 With 1.3kΩ Pulldown Input Offset Voltage (mV) Input Bias and Offset Current (µA) No Pulldown 10 0.15 0.125 0.1 0.075 0.05 0.025 0 1 OPA680 75Ω 402Ω 402Ω –5V IB 5 0 dP dG VIO IOS –5 –10 –15 dG dP 2 3 4 –40 –20 0 20 40 60 80 100 120 140 Number of 150Ω Loads Ambient Temperature (°C) OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 4 3 2 VO (Volts) 1 0 –1 –2 –3 –4 –5 –300 –200 –100 0 IO (mA) 100 200 300 Output Current Limit 1W Internal Power Limit 0 25Ω Load Line 50Ω Load Line 100Ω Load Line 1W Internal Power Limit Output Current Limited Output Current (50mA/div) SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 200 Sourcing Output Current Sinking Output Current 10 150 7.5 100 Quiescent Supply Current 5.0 50 2.5 0 –40 –20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) ® OPA680 8 TYPICAL PERFORMANCE CURVES: VS = +5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 2. SMALL-SIGNAL FREQUENCY RESPONSE 6 3 VO = 0.5Vp-p G = +1 RF = 25Ω G = +2 12 9 6 LARGE-SIGNAL FREQUENCY RESPONSE VO = 0.5Vp-p VO = 1Vp-p VO = 2Vp-p VO = 3Vp-p Normalized Gain (3dB/div) 0 –6 –9 –12 –15 –18 –21 –24 0.5 10 Frequency (MHz) 100 500 G = +10 G = +5 Gain (3dB/div) –3 3 0 –3 –6 –9 –12 –15 –18 0.5 10 100 500 Frequency (MHz) SMALL-SIGNAL PULSE RESPONSE 2.9 4.1 G = +2 VO = 0.5Vp-p LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 2Vp-p Output Voltage (100mV/div) 2.7 2.6 2.5 2.4 2.3 2.2 2.1 Time (5ns/div) Output Voltage (400mV/div) 2.8 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD 70 60 50 12 FREQUENCY RESPONSE vs CAPACITIVE LOAD Gain-to-Capacitive Load (3dB/div) Noise Gain = 2.6 9 6 3 0 –3 Signal Gain = +2 Noise Gain = 2.6 CL = 100pF +5V 714Ω CL = 47pF CL = 10pF CL = 22pF RS (Ω) 40 30 20 10 0 1 10 Capacitive Load (pF) 100 0.1µF VI RS 58Ω 714Ω 714Ω –6 –9 –12 –15 –18 0 OPA680 CL 402Ω VO 402Ω 0.1µF 100MHz Frequency (20MHz/div) 200MHz ® 9 OPA680 TYPICAL PERFORMANCE CURVES: VS = +5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω to VS /2, unless otherwise noted. See Figure 2. (CONT) 2nd HARMONIC DISTORTION vs FREQUENCY –40 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) 3rd HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 100Ω to VS/2 –45 –50 –55 –60 –65 –70 –75 0.1 VO = 2Vp-p RL = 100Ω to VS/2 G = +10 –45 –50 –55 –60 –65 –70 –75 G = +10 G = +5 G = +5 G = +2 G = +2 –80 1 Frequency (MHz) 10 20 0.1 1 Frequency (MHz) 10 20 2nd HARMONIC DISTORTION vs FREQUENCY –40 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) –40 3rd HARMONIC DISTORTION vs FREQUENCY VO = 2Vp-p –45 –50 –55 –60 RL = 200 –65 –70 –75 –80 RL = 100 RL = 500 –45 –50 –55 –60 –65 –70 –75 –80 0.1 VO = 2Vp-p RL = 100Ω RL = 200Ω RL = 500Ω 1 Frequency (MHz) 10 20 0.1 1 Frequency (MHz) 10 20 TWO-TONE, 3RD-ORDER SPURIOUS LEVEL –40 3rd-Order Spurious Level (dBc) CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10 +5V –45 –50 –55 –60 –65 –70 –75 –80 –14 –12 –10 50MHz Output Impedance (Ω) 200Ω OPA680 ZO –5V 402Ω 402Ω 1 20MHz 0.1 10MHz Load Power at Matched 50Ω Load 0.01 –8 –6 –4 –2 0 2 10k 100k 1M Frequency (Hz) 10M 100M Single-Tone Load Power (dBm) ® OPA680 10 APPLICATIONS INFORMATION WIDEBAND VOLTAGE FEEDBACK OPERATION The OPA680 provides an exceptional combination of high output power capability with a wideband, unity gain stable voltage feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA680 uses a new input stage which places the transconductance element between two input buffers, using their output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This provides very high slew rate (1800V/µs) while consuming relatively low quiescent current (6.4mA). This exceptional full power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 4.8nV/√Hz input voltage noise for the OPA680 is exceptionally low for this type of input stage. Figure 1 shows the DC-coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω. The disable control line is typically left open to guarantee normal amplifier operation. Two optional components are included in Figure 1. An additional resistor (175Ω) is included in series with the non-inverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 200Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power supply decoupling capacitors to ground, a 0.1µF capacitor is included between the two power supply pins. In practical PC board layouts, this optionaladded capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. Figure 2 shows the AC-coupled, gain of +2, single supply circuit configuration which is the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA680 requires minimal input and output voltage headroom compared to other very wideband voltage feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with >150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 698Ω resistors). The input signal is then AC-coupled into the midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (59Ω) used for testing is adjusted to give a 50Ω input load when the parallel combination of the biasing divider network is included. Again, an additional resistor (50Ω in this case) is included directly in series with the non-inverting input. This minimum recommended value provides part of the DC source resistance matching for the non-inverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies (>500MHz) using the input parasitic capacitance to form a bandlimiting pole. The gain resistor (RG) is ACcoupled, giving the circuit a DC gain of +1, which puts the input DC bias voltage (2.5V) at the output as well. The +5V 0.1µF 6.8µF + +5V +VS 0.1µF 50Ω Source 175Ω 50Ω + 6.8µF 50Ω Source DIS VO 50Ω 50Ω Load 698Ω 50Ω 698Ω DIS VO 100Ω VS/2 0.1µF VI 59Ω VI OPA680 OPA680 RF 402Ω 0.1µF RF 402Ω RG 402Ω + –5V 6.8µF 0.1µF RG 402Ω 0.1µF FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. FIGURE 2. AC-Coupled, G = +2, Single Supply, Specification and Test Circuit. ® 11 OPA680 SFDR output voltage can swing to within 1V of either supply pin while delivering >100mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage circuit used in the OPA680 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown in the +5V supply, 3rd harmonic distortion plots. SINGLE SUPPLY A/D CONVERTER INTERFACE Most modern, high performance analog-to-digital converters (such as the Burr-Brown ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output swing and high linearity of the OPA680 make it an ideal single supply ADC driver. The circuit on the front page shows one possible interface. Figure 3 shows the test circuit of Figure 2 modified for a capacitive (A/D) load and with an optional output pull-down resistor (RB). The OPA680 in the circuit of Figure 3 provides >200MHz bandwidth for a 2Vp-p output swing. Minimal 3rd harmonic distortion or two-tone, 3rd-order intermodulation distortion will be observed due to the very low crossover distortion in the OPA680 output stage. The limit of output Spurious Free Dynamic Range (SFDR) will be set by the 2nd harmonic distortion. Without RB, the circuit of Figure 3 measured at 10MHz shows an SFDR of 65dBc. This may be improved by pulling additional DC bias current (IB) out of the output stage through the optional RB resistor to ground (the output midpoint is at 2.5V for Figure 3). Adjusting IB gives the improvement in SFDR shown in Figure 4. SFDR improvement is achieved for IB values up to 6mA, with worse performance for higher values. 73 VO = 2Vp-p, 10MHz 72 71 70 69 68 67 66 65 0 1 2 3 4 5 6 7 8 9 10 Output Pull-Down Current (mA) FIGURE 4. SFDR vs IB. HIGH PERFORMANCE DAC TRANSIMPEDANCE AMPLIFIER High frequency DDS DACs require a low distortion output amplifier to retain their SFDR performance into real-world loads. A single-ended output drive implementation is shown in Figure 5. In this circuit, only one side of the complementary output drive signal is used. The diagram shows the signal output current connected into the virtual ground summing junction of the OPA680, which is set up as a transimpedance stage or “I-V converter”. The unused current output of the DAC is connected to ground. If the DAC requires its outputs terminated to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the non-inverting input of the OPA680. The +5V 698Ω 0.1µF VI 1Vp-p 59Ω 698Ω 50Ω Power supply decoupling not shown DIS RS 30Ω 2.5V DC ±1V AC 50pF 402Ω ADC Input OPA680 402Ω 0.1µF RB IB FIGURE 3. Single-Supply ADC Input Driver. ® OPA680 12 DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance will produce a zero in the noise gain for the OPA680 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in the feedback network should be set to: 1/2πRFCF = √GBP/4πRFCD which will give a closed-loop transimpedance bandwidth f–3dB, of approximately: f–3dB = √GBP/(2πRFCD) WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers which include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple “Wired-OR Video Multiplexer” can be easily implemented using the OP680 as shown in Figure 6. Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The “make-before-break” disable characteristic of the OPA680 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that shown in Figure 6. Since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75Ω output impedance to the cable. The video multiplexer connection (Figure 6) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated ±1.2V maximum for standard video signal levels. The section on Disable Operation shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than ±50mV. Where two outputs are switched (as shown in Figure 6), the output line is always under the control of one amplifier or the other due to the “make-before-break” disable timing. In this case, the switching glitches for two 0V inputs drop to 1 application, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA680. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (Figure 1) to be less than approximately 300Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 300Ω will keep this pole above 250MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. BANDWIDTH VS GAIN: NON-INVERTING OPERATION Voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most amplifiers will exhibit a more complex response with lower phase margin. The OPA680 is compensated to give a slightly peaked response in a noninverting gain of 2 (Figure 1). This results in a typical gain of +2 bandwidth of 220MHz, far exceeding that predicted by dividing the 300MHz GBP by 2. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 30MHz bandwidth shown in the Typical Specifications agrees with that predicted using the simple formula and the typical GBP of 300MHz. Frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5. One way to do this, without affecting the +2 signal gain, is to add an 804Ω resistor across the two inputs in the circuit of Figure 1. A similar technique may be used to reduce peaking in unity gain (voltage follower) applications. For example, by using a 402Ω feedback resistor along with a 402Ω resistor across the two op amp inputs, the voltage follower response will be similar to the gain of +2 response of Figure 2. Further reducing the value of the resistor across the op amp inputs will further dampen the frequency response due to increased noise gain. The OPA680 exhibits minimal bandwidth reduction going to single supply (+5V) operation as compared with ±5V. This is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. INVERTING AMPLIFIER OPERATION Since the OPA680 is a general purpose, wideband voltage feedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. Figure 8 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration. +5V + 0.1µF 0.1µF DIS RG 146Ω RO 50Ω 50Ω Load 6.8µF OPA680 50Ω Source RG 200Ω RF 402Ω RM 67Ω 0.1µF + 6.8µF –5V FIGURE 8. Gain of –2 Example Circuit. In the inverting configuration, three key design consideration must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the ® 15 OPA680 amplifier output. For an inverting gain of 2, setting RG to 50Ω for input matching eliminates the need for RM but requires a 100Ω feedback resistor. This has the interesting advantage that the noise gain becomes equal to 2 for a 50Ω source impedance—the same as the non-inverting circuits considered above. However, the amplifier output will now see the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values as shown in Figure 8, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and hence influences the bandwidth. For the example in Figure 8, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50 Ω || 67Ω = 28.6Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 2.8 for Figure 8, as opposed to only 2 if RM could be eliminated as discussed above. The bandwidth will therefore be slightly lower for the gain of –2 circuit of Figure 8 than for the gain of +2 circuit of Figure 1. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the non-inverting input (RB). If this resistor is set equal to the total DC resistance looking out of the inverting node, the output DC error, due to the input bias currents, will be reduced to (Input Offset Current) • RF. If the 50Ω source impedance is DC-coupled in Figure 8, the total resistance to ground on the inverting input will be 228Ω. Combining this in parallel with the feedback resistor gives the RB = 146Ω used in this example. To reduce the additional high frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB 4Vp-p). This also shows up in the two-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Performance Curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For 2 tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2Vp-p for each tone at the load, which requires 8Vp-p for the overall twotone envelope at the output pin), the Typical Performance Curves show 57dBc difference between the test tone powers and the 3rd-order intermodulation spurious powers. This exceptional performance improves further when operating at lower frequencies. 50Ω +5V 175Ω Power supply decoupling not shown. R 50Ω RNG OPA680 402Ω 402Ω CL VO –5V FIGURE 9. Capacitive Load Driving with Noise Gain Tuning. This gain of +2 circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique will reduce the required RS resistor for a given capacitive load, it does increase the noise at the output. It also will decrease the loop gain, nominally decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high RS value, significant dynamic range improvement can be achieved using this technique. Figure 10 shows the required RS versus CLOAD parametric on noise gain using this technique. This is the circuit of Figure 9 with RNG adjusted to increase the noise gain (increasing the phase margin) then sweeping CLOAD and finding the required RS to get a flat frequency response. This plot also gives the required RS versus CLOAD for the OPA680 operated at higher signal gains. ® 17 OPA680 NOISE PERFORMANCE High slew rate, unity gain stable, voltage feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. The 4.8nV/√Hz input voltage noise for the OPA680 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 11 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 300Ω. Keeping both (RF || RG) and the non-inverting input source impedance less than 300Ω will satisfy both noise and frequency response flatness considerations. Since the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 8 is not required. DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage feedback op amp allows good output DC accuracy in a wide variety of applications. The power supply current trim for the OPA680 gives even tighter control than comparable products. Although the high speed input stage does require relatively high input bias current (typically 14µA out of each input terminal), the close matching between them may be used to reduce the output DC error caused by this current. The total output offset voltage may be considerably reduced by matching the DC source resistances appearing at the two inputs. This reduces the output DC error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: – (NG = noninverting signal gain) ±(NG • VOS(MAX)) ± (RF • IOS(MAX)) = ±(2 • 4.5mV) ± (402Ω • 0.7µA) = ±9.3mV A fine scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques eventually reduce to adding a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the non-inverting input may be considered. However, the DC offset voltage on the summing junction will set up a DC current back into the source which must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, Figure 12 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. ENI RS OPA680 IBN EO ERS √ 4kTRS RF √ 4kTRF 4kT = 1.6E –20J at 290°K 4kT RG RG IBI FIGURE 11. Op Amp Noise Analysis Model. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 11. Equation 1: EO = (E NI 2 + ( I BN R S ) + 4 kTR S NG 2 + ( I BI R F ) + 4 kTR F NG 2 2 ) Dividing this expression by the noise gain (NG = (1+RF /RG)) will give the equivalent input-referred spot noise voltage at the non-inverting input, as shown in Equation 2. Equation 2: I R 2 4 kTR F 2 E N = E NI 2 + ( I BN R S ) + 4 kTR S +  BI F  +  NG  NG Evaluating these two equations for the OPA680 circuit and component values shown in Figure 1 will give a total output spot noise voltage of 11nV/√Hz and a total equivalent input spot noise voltage of 5.5nV/√Hz. This is including the noise added by the bias current cancellation resistor (175Ω) on the non-inverting input. This total input-referred spot noise voltage is only slightly higher than the 4.8nV/√Hz specification for the op amp voltage noise alone. This will be the case ® OPA680 18 +5V Supply Decoupling Not Shown 328Ω 0.1µF OPA680 VO –5V +5V 5kΩ 10kΩ 0.1µF 5kΩ VO VI –5V RF RG VI 20kΩ ±200mV Output Adjustment RG 500Ω RF 1kΩ eventually turning on those two diodes (≈100µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 13. Additional circuitry ensures that turnon time occurs faster than turn-off time (make-beforebreak). When disabled, the output and input nodes go to a high impedance state. If the OPA680 is operating in a gain of +1, this will show a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) and the isolation will be very poor as a result. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 14 shows these glitches for the circuit of Figure 1 with the input signal at 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. =– = –2 FIGURE 12. DC-Coupled, Inverting Gain of –2, with Offset Adjustment. DISABLE OPERATION The OPA680 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA680 will operate normally. To disable, the control pin must be asserted LOW. Figure 13 shows a simplified internal circuit for the disable control feature. 40 Output Voltage (20mV/div) 20 0 –20 –40 Output Voltage (0V Input) +VS 4.8V VDIS 0.2V 15kΩ Time (20ns/div) Q1 FIGURE 14. Disable/Enable Glitch. The transition edge rate (dv/dt) of the DIS control line will influence this glitch. For the plot of Figure 14, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 1kΩ series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring adequate logic level swing. 25kΩ VDIS IS Control 110kΩ –VS FIGURE 13. Simplified Disable Control Circuit. In normal operation, base current to Q1 is provided through the 110kΩ resistor, while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled LOW, additional current is pulled through the 15kΩ resistor ® 19 OPA680 THERMAL ANALYSIS Due to the high output power capability of the OPA680, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD•θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4•RL) where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA680N (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load. PD = 10V•7.2mA + 52/(4•(20Ω || 804Ω)) = 392mW Maximum TJ = +85°C + (0.39W•150°C/W) = 144°C. Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower guaranteed junction temperatures. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The output V-I plot shown in the Typical Performance Curves include a boundary for 1W maximum internal power dissipation under these conditions. b) Minimize the distance (