OPA681N

® OPA 681 OPA681 OPA 681 OPA6 81 Wideband, Current Feedback OPERATIONAL AMPLIFIER With Disable TM FEATURES q WIDEBAND +5V OPERATION: 225MHz (G = +2) q UNITY GAIN STABLE: 280MHz (G = 1) q q q q q q HIGH OUTPUT CURRENT: 150mA OUTPUT VOLTAGE SWING: ±4.0V HIGH SLEW RATE: 2100V/µs LOW dG/dφ: .001%/.01° LOW SUPPLY CURRENT: 6mA LOW DISABLED CURRENT: 320µA APPLICATIONS q q q q q q q q xDSL LINE DRIVER BROADBAND VIDEO BUFFERS HIGH SPEED IMAGING CHANNELS PORTABLE INSTRUMENTS ADC BUFFERS ACTIVE FILTERS WIDEBAND INVERTING SUMMING HIGH SFDR IF AMPLIFIER DESCRIPTION The OPA681 sets a new level of performance for broadband current feedback op amps. Operating on a very low 6mA supply current, the OPA681 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers a high output current with minimal voltage headroom and crossover distortion. This gives exceptional single-supply operation. Using a single +5V supply, the OPA681 can deliver a 1V to 4V output swing with over 100mA drive current and 150MHz bandwidth. This combination of features makes the OPA681 an ideal RGB line driver or single-supply ADC input driver. The OPA681’s low 6mA supply current is precisely trimmed at 25°C. This trim, along with low drift over temperature, +5V DIS 50Ω V1 50Ω V2 50Ω V3 50Ω V4 50Ω V5 –5V 23.7Ω 100Ω 100MHz, –1dB Compression = 15dBm 50Ω VO = – (V1 + V2 + V3 + V4 + V5) RG-58 50Ω guarantees lower guaranteed maximum supply current than competing products. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it high, gives normal operation. If pulled low, the OPA681 supply current drops to less than 320µA while the output goes into a high impedance state. This feature may be used for either power savings or for video MUX applications. OPA681 RELATED PRODUCTS SINGLES Voltage Feedback Current Feedback Fixed Gain OPA680 OPA681 OPA682 DUALS OPA2680 OPA2681 OPA2682 TRIPLES OPA3680 OPA3681 OPA3682 OPA681 200MHz RF Summing Amplifier International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1427C Printed in U.S.A. March, 1999 SPECIFICATIONS: VS = ±5V RF = 402Ω, RL = 100Ω, and G = +2, (Figure 1 for AC performance only), unless otherwise noted. OPA681P, U, N TYP +25°C 280 220 185 180 90 0.4 150 2100 1.7 2.0 12 8 –79 –85 –74 –77 2.5 12 15 0.001 0.008 0.01 0.05 100 ± 1.3 +30 ± 10 +25°C(2) GUARANTEED 0°C to 70°C(3) –40°C to +85°C(3) MIN/ TEST MAX LEVEL(1) typ min typ typ min max typ min typ typ typ typ max max max max max max max typ typ typ typ min max max max max max max min min typ min max min min min min typ typ typ typ typ typ typ typ min max max typ max max min min typ typ typ typ C B C C B B C B C C C C B B B B B B B C C C C A A B A B A B A A C A A A A A A C C C C C C C C A A A C A A A A C C C C PARAMETER AC PERFORMANCE (Figure 1) Small-Signal Bandwidth (VO = 0.5Vp-p) CONDITIONS G = +1, RF = 453Ω G = +2, RF = 402Ω G = +5, RF = 261Ω G = +10, RF = 180Ω G = +2, VO = 0.5Vp-p RF = 453, VO = 0.5Vp-p G = +2, VO = 5Vp-p G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, 5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p R L = 100Ω RL ≥ 500Ω R L = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150Ω RL = 37.5Ω G = +2, NTSC, VO = 1.4Vp, RL = 150Ω RL = 37.5Ω VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V UNITS MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz % % deg deg kΩ mV µV/°C µA nA/°C µA nA°/C V dB kΩ || pF Ω Ω V V mA mA Ω µA ns ns dB pF mV mV V V µA V V mA mA dB °C °C/W °C/W °C/W 220 210 190 Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase 50 2 1600 45 4 1600 45 1200 –73 –77 –71 –75 3.0 14 18 –70 –70 –71 –74 3.4 15 18 –68 –69 –68 –72 3.6 15 19 DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range(5) Common-Mode Rejection Non-Inverting Input Impedance Min Inverting Input Resistance (RI) Max Inverting Input Resistance (RI) OUTPUT™ Voltage Output Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled Low) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: P, U, N Thermal Resistance, θJA P 8-Pin DIP U SO-8 N SOT23-6 ±5 56 +55 ±40 ±3.4 47 33 48 56 ± 6.5 +35 ± 65 –400 ± 50 –125 ± 3.3 46 31 50 ± 3.7 ± 3.6 +140 –130 56 ± 7.5 +40 ± 85 –450 ± 55 –150 ± 3.2 45 30 55 ± 3.6 ± 3.3 +80 –80 VCM = 0V Open-Loop Open-Loop No Load 100Ω Load VO = 0 VO = 0 G = +2, f = 100kHz VDIS = 0 G = +2, 5MHz G = +2, RL = 150Ω, VIN = 0 G = +2, RL = 150Ω, VIN = 0 VDIS = 0 ± 3.5 52 100 || 2 41 41 ± 4.0 ± 3.9 +190 –150 0.03 –320 100 25 70 4 ± 50 ± 20 3.3 1.8 100 ±5 ±3.8 ±3.7 +160 –135 3.5 1.7 160 3.6 1.6 160 3.7 1.5 160 VS = ±5V VS = ±5V Input Referred ±6 6.4 5.6 52 6 6 58 –40 to +85 ±6 6.5 5.5 50 ±6 6.6 5.0 49 Junction-to-Ambient 100 125 150 NOTES: (1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits. ® OPA681 2 SPECIFICATIONS: VS = +5V RF = 499Ω, RL = 100Ω to VS /2, and G = +2, (Figure 2 for AC performance only), unless otherwise noted. OPA681P, U, N TYP +25°C 250 225 180 165 100 0.4 200 830 1.5 2.0 14 9 –70 –72 –72 –73 2.2 12 15 100 ±1 +40 ±5 +25°C(2) GUARANTEED 0°C to 70°C(3) –40°C to +85°C(3) MIN/ TEST MAX LEVEL(1) typ min typ typ min max typ min typ typ typ typ max max max max max max max min max max max max max max max min min typ min max min min max max min min typ typ typ typ typ typ typ typ min max typ typ max max min typ typ typ typ typ C B C C B B C B C C C C B B B B B B B A A B A B A B A A A C A A A A A A A A C C C C C C C C A A C C A A A C C C C C PARAMETER AC PERFORMANCE (Figure 2) Small-Signal Bandwidth (VO = 0.5Vp-p) CONDITIONS G = +1, RF = 649Ω G = +2, RF = 499Ω G = +5, RF = 360Ω G = +10, RF = 200Ω G = +2, VO < 0.5Vp-p RF = 649Ω, VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 f > 1MHz f > 1MHz f > 1MHz VO = VS /2, RL = 100Ω to VS /2 VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V UNITS MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz kΩ mV µV/°C µA nA/°C µA nA / °C V V dB kΩ || pF Ω Ω V V V V mA mA Ω µA ns ns dB pF mV mV V V µA V V mA mA dB °C °C/W °C/W °C/W 180 140 110 Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Non-Inverting Input Impedance Min Inverting Input Resistance (RI ) Max Inverting Input Resistance (RI ) OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disable Low) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Single-Supply Operating Voltage Max Single-Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: P, U, N Thermal Resistance, θJA P 8-Pin DIP U SO-8 N SOT23-6 50 2 700 35 4 680 23 570 –68 –70 –65 –68 3 14 18 60 ±5 +65 –67 –70 –65 –67 3.4 14 18 53 ±6.0 +15 +75 –300 ±25 –125 1.7 3.3 44 36 55 3.7 3.6 1.3 1.4 110 –70 –63 –68 –62 –67 3.6 15 19 51 ±7 +20 +95 –350 ±35 –175 1.8 3.2 44 35 60 3.5 3.4 1.5 1.6 60 –50 ±20 1.6 3.4 45 38 53 3.8 3.7 1.2 1.3 110 –75 VCM = VS /2 Open-Loop Open-Loop No Load RL = 100Ω to V S /2 No Load RL = 100Ω to VS /2 VO = VS /2 VO = VS /2 G = +2, f = 100kHz VDIS = 0 G = +2, 5MHz G = +2, RL = 150Ω, VIN = VS /2 G = +2, RL = 150Ω, VIN = VS /2 VDIS = 0 1.5 3.5 51 100 || 2 46 46 4 3.9 1 1.1 150 –110 0.03 –270 100 25 65 4 ±50 ±20 3.3 1.8 100 5 3.5 1.7 3.6 1.6 3.7 1.5 VS = +5V VS = +5V Input Referred 10.0 10.0 48 –40 to +85 12 5.3 4.1 12 5.4 3.7 12 5.4 3.6 Junction-to-Ambient 100 125 150 NOTES: (1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ±CMIR limits. ® 3 OPA681 ABSOLUTE MAXIMUM RATINGS Power Supply .............................................................................. ±6.5VDC Internal Power Dissipation(1) ............................ See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: P, U, N ........................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C NOTE:: (1) Packages must be derated based on specified θJA. Maximum TJ must be observed. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION Top View DIP/SO-8 Top View SOT23-6 Output 1 6 +VS –VS 2 5 DIS NC Inverting Input Non-Inverting Input –VS 1 2 3 4 8 7 6 5 DIS +VS Output 6 5 4 Non-Inverting Input 3 4 Inverting Input NC NC = No Connection A81 1 2 3 Pin Orientation/Package Marking PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 006 182 " 332 " SPECIFIED TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C " –40°C to +85°C " PACKAGE MARKING OPA681P OPA681U " A81 " ORDERING NUMBER OPA681P OPA681U OPA681U/2K5 OPA681N/250 OPA681N/3K TRANSPORT MEDIA Rails Rails Tape and Reel Tape and Reel Tape and Reel PRODUCT OPA681P OPA681U " OPA681N " PACKAGE 8-Pin Plastic DIP SO-8 Surface Mount " 6-Lead SOT23-6 " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only as Tape and Reel in the quantity indicated after the slash (e.g. /2K5 indicates 2500 devices per reel). Ordering 3000 pieces of the OPA681N/3K will get a single 3000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of the Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA681 4 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1). SMALL-SIGNAL FREQUENCY RESPONSE 2 1 Normalized Gain (1dB/div) LARGE-SIGNAL FREQUENCY RESPONSE 8 7 6 G = +2, RL = 100Ω G = +1, RF = 453Ω G = +2, RF = 402Ω 0 Gain (1dB/div) –1 –2 –3 –4 –5 –6 –7 –8 0 125MHz Frequency (25MHz/div) 250MHz G = +10, RF = 180Ω G = +5, RF = 261Ω 5 4 3 2 1 0 –1 –2 0 125MHz Frequency (25MHz/div) 7Vp-p 4Vp-p 2Vp-p 1Vp-p 250MHz SMALL-SIGNAL PULSE RESPONSE 400 +4 G = +2 VO = 0.5Vp-p +3 LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 5Vp-p Output Voltage (100mV/div) 300 200 100 0 –100 –200 –300 –400 Time (5ns/div) Output Voltage (1V/div) +2 +1 0 –1 –2 –3 –4 Time (5ns/div) LARGE-SIGNAL DISABLE/ENABLE RESPONSE VDIS (2V/div) DISABLED FEEDTHROUGH vs FREQUENCY 6.0 –45 –50 Feedthrough (5dB/div) VDIS Output Voltage (400mV/div) 4.0 2.0 0 VDIS = 0 –55 –60 –65 –70 –75 –80 –85 –90 –95 Forward Reverse 2.0 1.6 1.2 0.8 0.4 0 G = +2 VIN = +1V Output Voltage Time (50ns/div) 1 10 Frequency (MHz) 100 ® 5 OPA681 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1). 5MHz 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 –60 (CONT) 5MHz 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) –65 –70 –75 –80 –85 –90 0.1 1 3rd Harmonic Distortion (dBc) RL = 100Ω RL = 200Ω –65 –70 RL = 100Ω –75 –80 –85 –90 RL = 500Ω RL = 200Ω RL = 500Ω 10 0.1 1 Output Voltage Swing (Vp-p) 10 Output Voltage Swing (Vp-p) 10MHz 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 2nd Harmonic Distortion (dBc) 10MHz 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 3rd Harmonic Distortion (dBc) –65 RL = 200Ω –70 –75 RL = 100Ω –65 –70 –75 –80 RL = 500Ω –85 –90 RL = 100Ω RL = 200Ω RL = 500Ω –80 –85 –90 0.1 1 Output Voltage Swing (Vp-p) 10 0.1 1 Output Voltage Swing (Vp-p) 10 20MHz 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 20MHz 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –55 RL = 200Ω –60 –65 RL = 100Ω –55 –60 –65 –70 –75 –80 RL = 100Ω RL = 500Ω –70 –75 –80 0.1 1 Output Voltage Swing (Vp-p) 10 RL = 200Ω RL = 500Ω 0.1 1 Output Voltage Swing (Vp-p) 10 ® OPA681 6 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1). (CONT) 2ND HARMONIC DISTORTION vs FREQUENCY –40 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) –40 3RD HARMONIC DISTORTION vs FREQUENCY VO = 2Vp-p RL = 100Ω –50 G = +10, RF = 180Ω –50 VO = 2Vp-p RL = 100Ω G = +10, RF = 180Ω –60 G = +5, RF = 261Ω –60 G = +5, RF = 261Ω –70 –70 G = +2, RF = 402Ω –80 –80 G = +2, RF = 402Ω 0.1 1 Frequency (MHz) 10 20 –90 0.1 1 Frequency (MHz) 10 20 –90 INPUT VOLTAGE AND CURRENT NOISE DENSITY 100 TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –8 –6 –4 –2 10MHz Load Power at Matched 50Ω Load 0 2 4 6 8 10 20MHz dBc = dB below carriers 50MHz Inverting Input Current Noise 15.1pA/√Hz 12.2pA/√Hz 10 Non-Inverting Input Current Noise Voltage Noise 1 100 1k 10k 2.2nV/√Hz 100k 1M 10M Frequency (Hz) 3rd-Order Spurious Level (dBc) Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) Single-Tone Load Power (dBm) RECOMMENDED RS vs CAPACITIVE LOAD 60 50 40 RS (Ω) FREQUENCY RESPONSE vs CAPACITIVE LOAD 15 Gain to Capacitive Load (3dB/div) 12 9 6 3 0 –3 –6 –9 –12 –15 0 VIN OPA681 CL = 10pF CL = 22pF CL = 47pF RS 402Ω 402Ω 30 20 10 0 1 10 Capacitive Load (pF) 100 VO CL 1kΩ 1kΩ is optional. CL = 100pF 300MHz 150MHz Frequency (30MHz/div) ® 7 OPA681 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1). (CONT) CMRR AND PSRR vs FREQUENCY 70 65 60 Rejection Ratio (dB) Transimpedance Gain (20dBΩ/div) OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE 120 Transimpedance Phase (40°/div) +PSRR –PSRR CMRR ∠ ZOL | ZOL| 0 –40 –80 –120 –160 –200 –240 109 100 80 60 40 20 0 55 50 45 40 35 30 25 20 102 103 104 105 Frequency (Hz) 106 107 108 104 105 106 107 108 Frequency (Hz) COMPOSITE VIDEO dG/dφ 0.05 Positive Video Negative Sync Input Offset Voltage (mV) TYPICAL DC DRIFT OVER TEMPERATURE 5 4 3 2 1 0 –1 –2 –3 –4 –5 Inverting Input Bias Current 50 Non-Inverting Input Bias Current 40 Input Bias Currents (µA) 0.04 dφ dG/dφ (%/°) 30 20 10 0 0.03 0.02 VIO –10 –20 –30 –40 –50 –40 –20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) 0.01 dG 0 1 2 3 4 Number of 150Ω Loads OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 4 3 2 1W Internal Power Limit Output Current Limited Supply Current (2.5mA/div) 10 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 200 Sourcing Output Current Sinking Output Current VO (Volts) 1 0 –1 –2 –3 –4 –5 –300 –200 –100 0 IO (mA) 100 200 Output Current Limit 25Ω Load Line 50Ω Load Line 100Ω Load Line 5 Quiescent Supply Current 100 2.5 50 1W Internal Power Limit 0 0 –40 –20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) 300 ® OPA681 8 Output Current (mA) 7.5 150 TYPICAL PERFORMANCE CURVES: VS = +5V G = +2, RF = 499Ω, and RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2). SMALL-SIGNAL FREQUENCY RESPONSE 2 1 Normalized Gain (1dB/div) LARGE-SIGNAL FREQUENCY RESPONSE 8 7 G = +2 RL = 100Ω to 2.5V VO = 0.5Vp-p 0 –1 –2 –3 –4 –5 –6 –7 –8 0 125 G = +2, RF = 499Ω Gain (1dB/div) G = +1, RF = 649Ω 6 5 4 3 2 1 0 –1 –2 VO = 2Vp-p VO = 1Vp-p G = +5, RF = 360Ω G = +10, RF = 200Ω 250 0 125 Frequency (25MHz/div) 250 Frequency (25MHz/div) SMALL-SIGNAL PULSE RESPONSE 2.10 2.9 4.5 G = +2 VO = 0.5Vp-p 4.1 LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 2Vp-p Output Voltage (100mV/div) Output Voltage (400mV/div) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 Time (5ns/div) 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 0.5 Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD 70 60 50 RS (Ω) Gain to Capacitive Load (3dB/div) 15 12 9 6 3 0 VI FREQUENCY RESPONSE vs CAPACITIVE LOAD CL = 47pF CL = 10pF CL = 22pF +5V 806Ω 806Ω OPA681 RS C L 499Ω 499Ω 0.1µF 1kΩ is optional. VO 1kΩ 40 30 20 10 0 1 10 Capacitive Load (pF) 100 0.1µF 57.6Ω –3 –6 –9 –12 –15 0 CL = 100pF 200MHz 100MHz Frequency (20MHz/div) ® 9 OPA681 TYPICAL PERFORMANCE CURVES: VS = +5V G = +2, RF = 499Ω, and RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2). (CONT) 2ND HARMONIC DISTORTION vs FREQUENCY –40 2nd Harmonic Distortion (dBc) 3RD HARMONIC DISTORTION vs FREQUENCY –40 3rd Harmonic Distortion (dBc) VO = 2Vp-p RL = 100Ω to 2.5V –50 G = +10, RF = 200Ω VO = 2Vp-p RL = 100Ω to 2.5V –50 G = +10, RF = 200Ω G = +5, RF = 360Ω G = +5, RF = 360Ω –60 G = +2, RF = 499Ω –60 –70 –70 G = +2, RF = 499Ω –80 0.1 1 Frequency (MHz) 10 20 –80 0.1 1 Frequency (MHz) 10 20 2ND HARMONIC DISTORTION vs FREQUENCY –50 2nd Harmonic Distortion (dBc) 3RD HARMONIC DISTORTION vs FREQUENCY –50 VO = 2Vp-p G = +2 –60 RL = 100Ω –70 RL = 200Ω RL = 100Ω RL = 200Ω –60 –70 –80 Loads to 2.5V –90 0.1 1 Frequency (MHz) RL = 500Ω 3rd Harmonic Distortion (dBc) VO = 2Vp-p G = +2 –80 RL = 500Ω Loads to 2.5V –90 10 20 0.1 1 Frequency (MHz) 10 20 TWO-TONE, 3RD ORDER SPURIOUS LEVEL –45 dBc = dB below carriers –50 CLOSED-LOOP OUTPUT IMPEDANCE 10 +5 3rd Order Spurious (dBc) 50MHz Output Impedance (Ω) –55 –60 –65 20MHz –70 –75 –80 –85 –14 –12 –10 –8 10MHz 1 50Ω OPA681 402Ω ZO 402Ω 0.1 –5 Load Power at Matched 50Ω Load 0.01 –6 –4 –2 0 2 10k 100k 1M Frequency (Hz) 10M 100M Single-Tone Load Power (dBm) ® OPA681 10 APPLICATIONS INFORMATION WIDEBAND CURRENT FEEDBACK OPERATION The OPA681 gives the exceptional AC performance of a wideband current feedback op amp with a highly linear, high power output stage. Requiring only 6mA quiescent current, the OPA681 will swing to within 1V of either supply rail and deliver in excess of 135mA guaranteed at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA681 will deliver greater than 200MHz bandwidth driving a 2Vp-p output into 100Ω on a single +5V supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA681 achieves a comparable power gain with much better linearity. The primary advantage of a current feedback op amp over a voltage feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. For similar AC performance at low gain, with improved DC accuracy, consider the high slew rate, unity gain stable, voltage feedback OPA680. Figure 1 shows the DC coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω = 89Ω. The disable control line (DIS) is typically left open to guarantee normal amplifier operation. One optional component is included in Figure 1. In addition to the usual power supply de-coupling capacitors to ground, a 0.1µF capacitor is included between the two power supply pins. In +5V +VS 0.1µF 6.8µF + practical PC board layouts, this optional added capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. Figure 2 shows the AC-coupled, gain of +2, single supply circuit configuration used as the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA681 requires minimal input and output voltage headroom compared to other very wideband current feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with greater than 150MHz bandwidth. The key requirement of broadband single supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC coupled into this midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1—which puts the input DC bias voltage (2.5V) on the output as well. The feedback resistor value has been adjusted from the bipolar supply condition to re-optimize for a flat frequency response in +5V, gain of +2, operation (see Setting Resistor Values to Optimize Bandwidth). Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 80mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA681 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, 3rd harmonic distortion plots. +5V +VS 0.1µF 50Ω Source DIS VI 50Ω VO 50Ω 50Ω Load + 6.8µF 806Ω 0.1µF VI 57.6Ω 806Ω DIS VO 100Ω VS/2 OPA681 OPA681 0.1µF RF 402Ω RF 499Ω RG 402Ω + –VS –5V 6.8µF 0.1µF RG 499Ω 0.1µF FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. 11 FIGURE 2. AC-Coupled, G = +2, Single Supply Specification and Test Circuit. ® OPA681 SINGLE-SUPPLY A/D CONVERTER INTERFACE Most modern, high performance A/D converters (such as the Burr-Brown ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output swing and high linearity of the OPA681 make it an ideal single-supply ADC driver. Figure 3 shows an example input interface to a very high performance 10-bit, 60MSPS CMOS converter. The OPA681 in the circuit of Figure 3 provides > 180MHz bandwidth operating at a signal gain of +4 with a 2Vp-p output swing. One of the primary advantages of the current feedback internal architecture used in the OPA681 is that high bandwidth can be maintained as the signal gain is increased. The non-inverting input bias voltage is referenced to the mid-point of the ADC signal range by dividing off the top and bottom of the internal ADC reference ladder. With the gain resistor (RG) AC-coupled, this bias voltage has a gain of +1 to the output, centering the output voltage swing as well. Tested performance at a 20MHz analog input frequency and a 60MSPS clock rate on the converter gives > 58dBc SFDR. WIDEBAND INVERTING SUMMING AMPLIFIER Since the signal bandwidth for a current feedback op amp may be controlled independently of the noise gain (NG, which is normally the same as the non-inverting signal gain), very broadband inverting summing stages may be implemented using the OPA681. The circuit on the front page of this data sheet shows an example inverting summing amplifier where the resistor values have been adjusted to maintain both maximum bandwidth and input impedance matching. If each RF signal is assumed to be driven from a 50Ω source, the NG for this circuit will be (1 + 100Ω /(100Ω /5)) = 6. The total feedback impedance (from VO to the inverting error current) is the sum of RF + (RI x NG) where RI is the +5V impedance looking into the inverting input from the summing junction (see Setting Resistor Values to Optimize Performance section). Using 100Ω feedback (to get a signal gain of –2 from each input to the output pin) requires an additional 20Ω in series with the inverting input to increase the feedback impedance. With this resistor added to the typical internal RI = 41Ω, the total feedback impedance is 100Ω + (65Ω x 6) = 490Ω, which is equal to the required value to get a maximum bandwidth flat frequency response for NG = 6. Tested performance shows more than 200MHz small signal bandwidth and a –1dBm compression of 15dBm at the matched 50Ω load through 100MHz. WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers which include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple “Wired-OR Video Multiplexer” can be easily implemented using the OPA681 as shown in Figure 4. Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The “make-before-break” disable characteristic of the OPA681 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that shown in Figure 4. Since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75Ω output impedance to the cable. The video multiplexer connection (Figure 4) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated ±1.2V maximum for standard video signal levels. RF 360Ω Clock 50Ω +5V 0.1µF RG 120Ω OPA681 ADS823 10-Bit 60MSPS Input 22pF Input CM 0.5Vp-p 0.1µF 2Vp-p DIS 2kΩ +3.5V REFT 0.1µF +2.5V DC Bias 2kΩ +1.5V REFB 0.1µF FIGURE 3. Wideband, AC-Coupled, Single-Supply A/D Driver. ® OPA681 12 +5V 2kΩ VDIS +5V Video 1 DIS 75Ω OPA681 340Ω –5V 82.5Ω 402Ω 75Ω Cable 340Ω +5V 402Ω 82.5Ω RG-59 Video 2 OPA681 DIS 75Ω –5V 2kΩ FIGURE 4. Two-Channel Video Multiplexer. The section on Disable Operation shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than ±50mV. Where two outputs are switched (as shown in Figure 6), the output line is always under the control of one amplifier or the other due to the “make-before-break” disable timing. In this case, the switching glitches for two 0V inputs drop to 150MHz signal bandwidth. +5V Dividing this expression by the noise gain (NG = (1+RF/RG)) will give the equivalent input-referred spot noise voltage at the non-inverting input as shown in Equation 5. Eq. 5 IR 4kTR F 2 E N = E NI 2 + ( I BN R S ) + 4kTR S +  BI F  +  NG  NG 2 Power supply de-coupling not shown VI DIS OPA681 1.8kΩ +5V VO 2.86kΩ –5V 180Ω Evaluating these two equations for the OPA681 circuit and component values shown in Figure 1 will give a total output spot noise voltage of 8.4nV/√Hz and a total equivalent input spot noise voltage of 4.2nV/√Hz. This total input-referred spot noise voltage is higher than the 2.2nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high gain configurations (as suggested previously), the total input-referred voltage noise given by Equation 5 will approach just the 2.2nV/√Hz of the op amp itself. For example, going to a gain of +10 using RF = 180Ω will give a total input-referred noise of 2.4nV/√Hz . DC ACCURACY AND OFFSET CONTROL A current feedback op amp like the OPA681 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Typical Specifications show an input offset voltage comparable to high speed voltage feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage feedback op amps, they do not generally reduce the output DC offset for wideband current feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worstcase output offset range equal to: ± (NG x VOS(MAX)) + (IBN x RS /2 x NG) ± (IBI x RF) where NG = non-inverting signal gain = ± (2 x 5.0mV) + (55µA x 25Ω x 2) ± (402Ω x 40µA) = ±10mV + 2.75mV ± 16mV = –23.25mV → +28.25mV ® OPA237 20Ω –5V 18kΩ 2kΩ FIGURE 10. Wideband, Precision, G = +10 Composite Amplifier. This DC-coupled circuit provides very high signal bandwidth using the OPA681. At lower frequencies, the output voltage is attenuated by the signal gain and compared to the original input voltage at the inputs of the OPA237 (this is a low cost, precision voltage feedback op amp with 1.5MHz gain bandwidth product). If these two don’t agree (due to DC offsets introduced by the OPA681), the OPA237 sums in a correction current through the 2.86kΩ inverting summing path. Several design considerations will allow this circuit to be optimized. First, the feedback to the OPA237’s non-inverting input must be precisely matched to the high speed signal gain. Making the 2kΩ resistor to ground an adjustable resistor would allow the low and high frequency gains to be precisely matched. Secondly, the crossover frequency region where the OPA237 passes control to the OPA681 must occur with exceptional phase linearity. These two issues reduce to designing for pole/zero cancellation in the overall transfer function. Using the 2.86kΩ resistor will nominally satisfy this requirement for the circuit in Figure 10. Perfect cancellation over process and temperature is not possible. However, this initial resistor setting and precise gain matching will minimize long term pulse settling tails. DISABLE OPERATION The OPA681 provides an optional disable feature that may be used either to reduce system power or to implement a OPA681 18 simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA681 will operate normally. To disable, the control pin must be asserted low. Figure 11 shows a simplified internal circuit for the disable control feature. was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the VDIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2kΩ series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring an adequate logic level swing. +VS 40 Output Voltage (20mV/div) 15kΩ 20 0 –20 –40 Output Voltage (0V Input) Q1 4.8V VDIS 0.2V 25kΩ VDIS IS Control 110kΩ –VS Time (20ns/div) FIGURE 11. Simplified Disable Control Circuit. In normal operation, base current to Q1 is provided through the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled low, additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 100µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 11. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high impedance state. If the OPA681 is operating in a gain of +1, this will show a very high impedance (4pF || 1MΩ) at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 12 shows these glitches for the circuit of Figure 1 with the input signal set to zero volts. The glitch waveform at the output pin is plotted along with the DIS pin voltage. The transition edge rate (dV/dT) of the DIS control line will influence this glitch. For the plot of Figure 12, the edge rate was reduced until no further reduction in glitch amplitude FIGURE 12. Disable/Enable Glitch. THERMAL ANALYSIS Due to the high output power capability of the OPA681, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD x θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 x RL) where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA681N (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load to +2.5V DC: PD = 10V x 7.2mA + 5 2 /(4 x (20Ω || 804Ω)) = 392mW Maximum TJ = +85°C + (0.39W (150°C/W) = 144°C Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower guaranteed junction temperatures. Remember, this is a worst-case internal power dissipation—use your actual signal and load to compute PDL. The highest possible ® 19 OPA681 internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The Output Voltage and Current Limitations plot shown in the Typical Performance Curves include a boundary for 1W maximum internal power dissipation under these conditions. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier like the OPA681 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA681. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing its value ® will reduce the bandwidth, while decreasing it will give a more peaked frequency response. The 402Ω feedback resistor used in the typical performance specifications at a gain of +2 on ±5V supplies is a good starting point for design. Note that a 453Ω feedback resistor, rather than a direct short, is recommended for the unity gain follower application. A current feedback op amp requires a feedback resistor even in the unity gain follower configuration to control stability. d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS versus Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA681 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the Distortion vs Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA681 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA681 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high speed part like the OPA681 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA681 onto the board. If socketing for the DIP package is desired, high frequency flush-mount pins (e.g., McKenzie Technology #710C) can give good results. OPA681 20 INPUT AND ESD PROTECTION The OPA681 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 13. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA681), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +V CC External Pin Internal Circuitry –V CC FIGURE 13. Internal ESD Protection. ® 21 OPA681