OPA682U

® OPA 682 OPA682 OPA 682 OPA6 82 Wideband, Fixed Gain BUFFER AMPLIFIER With Disable TM FEATURES q q q q q q q q INTERNALLY FIXED GAIN: +2 OR ±1 HIGH BANDWIDTH (G = +2): 240MHz LOW SUPPLY CURRENT: 6mA LOW DISABLED CURRENT: 320µA HIGH OUTPUT CURRENT: 150mA OUTPUT VOLTAGE SWING: ±4.0V ±5V OR SINGLE +5V OPERATION SOT23-6 AVAILABLE APPLICATIONS q q q q q q BROADBAND VIDEO LINE DRIVERS VIDEO MULTIPLEXERS MULTIPLE LINE VIDEO DA PORTABLE INSTRUMENTS ADC BUFFERS ACTIVE FILTERS DESCRIPTION The OPA682 provides an easy to use, broadband fixed gain buffer amplifier. Depending on the external connections, the internal resistor network may be used to provide either a fixed gain of +2 video buffer or a gain of +1 or –1 voltage buffer. Operating on a very low 6mA supply current, the OPA682 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers high output current with a minimal headroom and crossover distortion. This gives exceptional single supply operation. Using a single +5V supply, the OPA682 can deliver a 1V to 4V output swing with over 100mA drive current and 200MHz bandwidth. This combination of features makes the OPA682 an ideal RGB line driver or single supply ADC input driver. The OPA682’s low 6mA supply current is precisely trimmed at 25°C. This trim, along with low drift over temperature, guarantees lower maximum supply current than competing products that report only a room temperature nominal supply current. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it high, gives normal operation. If pulled low, the OPA682 supply current drops to less than 320µA while the output goes into a high impedance state. This feature may be used for either power savings or for video MUX applications. OPA682 RELATED PRODUCTS SINGLES Voltage Feedback Current Feedback Fixed Gain OPA680 OPA681 OPA682 DUALS OPA2680 OPA2681 OPA2682 TRIPLES OPA3680 OPA3681 OPA3682 75Ω OPA682 1 2 Video In 75Ω –5V 3 4 8-Pin DIP, SO-8 G = +2 75Ω RG-59 75Ω 8 DIS 7 6 5 75Ω RG-59 75Ω +5V RG-59 75Ω RG-59 75Ω 75Ω Video Out 240MHz, 4-Output Component Video D/A nternational Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1999 Burr-Brown Corporation PDS-1428C Printed in U.S.A. September, 1999 SPECIFICATIONS: VS = ±5V G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted. OPA682P, U, N TYP +25°C +25°C GUARANTEED(1) 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2 ) PARAMETER AC PERFORMANCE (Figure 1) Small-Signal Bandwidth (VO < 0.5Vp-p) CONDITIONS UNITS G = +1 G = +2 G = –1 330 240 220 150 0.8 210 2100 1.7 2.0 12 8 –69 –79 –84 –95 2.2 12 15 0.001 0.008 0.01 0.05 ±0.2 ±0.3 ±0.2 400 400 –62 –70 –75 –82 3.0 14 18 –59 –67 –71 –76 3.4 15 18 –57 –65 –69 –74 3.6 15 19 1600 1600 1200 50 2 45 4 45 220 210 190 MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz % % deg deg typ min typ min max typ min typ typ typ typ max max max max max max max typ typ typ typ C B C B B C B C C C C B B B B B B B C C C C Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(3) Gain Error G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 5Vp-p G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, VO = 5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz f > 1MHz NTSC, RL = 150Ω NTSC, RL = 37.5Ω NTSC, RL = 150Ω NTSC, RL = 37.5Ω G = +1 G = +2 G = –1 % typ max max max min max max max max max max max C A B A A B A B A B A B ±1.5 ±1.5 480 320 0.13 510 310 0.13 ±6.5 +35 ±65 –400 ±50 –125 520 290 0.13 ±7.5 +40 ±85 –450 ±55 –150 ±3.2 % % Ω Ω %/C° mV µV/°C µA nA/°C µA nA°C V kΩ || pF Internal RF and RG Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range Non-Inverting Input Impedance OUTPUT Voltage Output Swing Current Output, Sourcing Sinking Closed-Loop Output Impedance G = +2, f = 100kHz No Load 100Ω Load ±4.0 ±3.9 +190 –150 0.03 ±3.5 100 || 2 VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V ±10 +30 +55 ±1.3 ±5 ±40 ±3.4 ±3.3 min typ A C ±3.8 ±3.7 +160 –135 ±3.7 ±3.6 +140 –130 ±3.6 ±3.3 +80 –80 V V mA mA Ω min min min min typ A A A A C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA682 2 SPECIFICATIONS: VS = ±5V (Cont.) G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted. OPA682P, U, N TYP +25°C –320 100 25 G = +2, 5MHz G = +2, RL = 150Ω G = +2, RL= 150Ω 70 4 ±50 ±20 3.3 1.8 VDIS = 0 100 ±5 3.5 1.7 160 3.6 1.6 160 3.7 1.5 160 +25°C GUARANTEED(1) 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2) typ typ typ typ typ typ typ min max max C C C C C C C A A A PARAMETER DISABLE/POWER DOWN (DIS Pin) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: P, U, N Thermal Resistance, θJA P 8-Pin DIP CONDITIONS VDIS = 0 UNITS µA ns ns dB pF mV mV V V µA V typ max max min min C A A A A ±6 VS = ±5V VS = ±5V Input Referred 6 6 58 6.4 5.6 52 ±6 6.5 5.5 50 ±6 6.6 5.0 49 V mA mA dB °C °C/W °C/W °C/W –40 to +85 100 125 150 typ typ typ typ C C C C U SO-8 N SOT23-6 NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature +23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input commonmode voltage. ® 3 OPA682 SPECIFICATIONS: VS = +5V G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (Figure 2 for AC performance only), unless otherwise noted. OPA682P, U, N TYP +25°C +25°C GUARANTEED(1) 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2) PARAMETER AC PERFORMANCE (Figure 2) Small-Signal Bandwidth (VO < 0.5Vp-p) CONDITIONS UNITS Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise DC PERFORMANCE(3) Gain Error G = +1 G = +2 G = –1 G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 f > 1MHz f > 1MHz f > 1MHz 290 220 200 100 0.4 210 830 1.5 2.0 14 9 –62 –69 –71 –73 2.2 12 15 ±0.2 ±0.3 ±0.2 400 400 180 50 2 700 140 35 4 680 110 23 570 MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz typ min typ min max typ min typ typ typ typ max max max max max max max C B C B B C B C C C C B B B B B B B –56 –62 –64 –68 3.0 14 18 –55 –61 –63 –67 3.4 14 18 –53 –59 –61 –65 3.6 15 19 G = +1 G = +2 G = –1 % typ max max max min max max max max max max max max min typ min min max max min min typ C A B B B B A B A B A B B B C A A A A A A C ±1.5 ±1.5 480 320 0.13 ±5 +65 510 310 0.13 ±6 +15 +75 –300 ±25 –125 1.7 3.3 520 290 0.13 ±7 +20 +95 –350 ±35 –175 1.8 3.2 % % Ω Ω %/C° mV µV/°C µA nA/°C µA nA°C V V kΩ || pF V V V V mA mA Ω Internal RF and RG Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Non-Inverting Input Impedance OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Sinking Output Impedance No Load RL = 100Ω No Load RL = 100Ω VCM VCM VCM VCM VCM VCM = = = = = = 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V ±1 +40 ±5 ±20 1.5 3.5 100 || 2 4.0 3.9 1.0 1.1 +150 –110 0.03 1.6 3.4 3.8 3.7 1.2 1.3 +110 –75 3.7 3.6 1.3 1.4 +110 –70 3.5 3.4 1.5 1.6 +60 –50 G = +2, f = 100kHz ® OPA682 4 SPECIFICATIONS: VS = +5V (Cont.) G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (Figure 2 for AC performance only), unless otherwise noted. OPA682P, U, N TYP +25°C –270 100 25 65 4 ±50 ±20 3.3 1.8 100 5 VS = +5V VS = +5V Input Referred 4.8 4.8 50 –40 to +85 100 125 150 12 5.3 4.1 12 5.4 3.7 12 5.4 3.6 +25°C GUARANTEED(1) 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2) typ typ typ typ typ typ typ min max typ typ max max min typ typ typ typ typ C C C C C B B B B C C A A A C C C C C PARAMETER DISABLE/POWER DOWN (DIS Pin) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Single Supply Operating Voltage Maximum Single Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: P, U, N Thermal Resistance, θJA P 8-Pin DIP U SO-8 N SOT23-6 CONDITIONS VDIS = 0 UNITS µA ns ns dB pF mV mV V V µA V V mA mA dB °C °C/W °C/W °C/W G = +2, 5MHz G = +2, RL = 150Ω, VIN = 2.5V G = +2, RL = 150Ω, VIN = 2.5V 3.5 1.7 3.6 1.6 3.7 1.5 VDIS = 0 NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature +23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input commonmode voltage. ® 5 OPA682 ABSOLUTE MAXIMUM RATINGS Power Supply .............................................................................. ±6.5VDC Internal Power Dissipation(1) ............................ See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: P, U, N ........................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C NOTE:: (1) Packages must be derated based on specified θJA. Maximum TJ must be observed. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION Top View DIP/SO-8 Top View SOT23-6 Output 1 RF 400Ω 6 +VS –VS NC –IN +IN –VS 1 RG RF 400Ω 2 RG 400Ω 5 DIS 8 7 6 5 DIS +IN +VS Output NC 3 4 –IN 2 3 4 400Ω 6 5 4 NC: No Connection A82 1 2 3 Pin Orientation/Package Marking PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 006 182 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C PACKAGE MARKING OPA682P OPA682U ORDERING NUMBER(2) OPA682P OPA682U OPA682U/2K5 OPA682N/250 OPA682N/3K TRANSPORT MEDIA Rails Rails Tape and Reel Tape and Reel Tape and Reel PRODUCT OPA682P OPA682U PACKAGE 8-Pin Plastic DIP SO-8 Surface Mount " OPA682N " 6-Lead SOT23 " 332 " –40°C to +85°C " A82 " " " " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA682U/2K5” will get a single 2500-piece Tape and Reel. ® OPA682 6 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). SMALL-SIGNAL FREQUENCY RESPONSE 2 1 G = +1 8 7 6 LARGE-SIGNAL FREQUENCY RESPONSE RL = 100Ω Normalized Gain (1dB/div) 0 –1 –2 –3 –4 –5 –6 –7 –8 0 G = –1 Gain (1dB/div) 5 4 3 2 1 0 –1 –2 7Vp-p 4Vp-p 2Vp-p G = +2 1Vp-p 250MHz Frequency (50MHz/div) 500MHz 0 125MHz Frequency (25MHz/div) 250MHz SMALL-SIGNAL PULSE RESPONSE 400 Output Voltage (100mV/div) LARGE-SIGNAL PULSE RESPONSE +4 +3 VO = 5Vp-p 300 200 100 0 –100 –200 –300 –400 Time (5ns/div) VO = 0.5Vp-p Output Voltage (1V/div) +2 +1 0 –1 –2 –3 –4 Time (5ns/div) LARGE-SIGNAL DISABLE/ENABLE RESPONSE VDIS (2V/div) 6.0 VDIS Output Voltage (400mV/div) 4.0 2.0 0 2.0 1.6 1.2 0.8 0.4 0 Time (50ns/div) VIN = +1V Output Voltage –45 –50 DISABLED FEEDTHROUGH vs FREQUENCY VDIS = 0 Feedthrough (5dB/div) –55 –60 –65 –70 –75 –80 –85 –90 –95 1 10 Frequency (MHz) 100 Forward Reverse ® 7 OPA682 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). 5MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 RL = 100Ω –60 5MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) –65 –70 –75 –80 3rd Harmonic Distortion (dBc) RL = 200Ω –65 –70 –75 –80 RL = 200Ω –85 –90 RL = 500Ω 0.1 1 Output Voltage Swing (Vp-p) 10 RL = 100Ω RL = 500Ω –85 –90 0.1 1 Output Voltage Swing (Vp-p) 10 10MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 RL = 100Ω –60 10MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) –65 RL = 200Ω –70 –75 RL = 500Ω –80 –85 –90 0.1 1 Output Voltage Swing (Vp-p) 10 3rd Harmonic Distortion (dBc) –65 –70 –75 –80 RL = 200Ω –85 RL = 500Ω –90 0.1 1 Output Voltage Swing (Vp-p) 10 RL = 100Ω 20MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 RL = 100Ω –50 20MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) –55 RL = 200Ω –60 –65 RL = 500Ω –70 –75 –80 0.1 1 Output Voltage Swing (Vp-p) 10 –55 –60 –65 –70 –75 RL = 500Ω –80 0.1 1 Output Voltage Swing (Vp-p) 10 RL = 100Ω RL = 200Ω ® OPA682 8 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). (Cont.) 2nd HARMONIC DISTORTION vs FREQUENCY –40 –40 VO = 2Vp-p RL = 100Ω G = –1 –60 G = +2 3rd HARMONIC DISTORTION vs FREQUENCY VO = 2Vp-p RL = 100Ω –50 2nd Harmonic Distortion (dBc) –50 3rd Harmonic Distortion (dBc) –60 G = –1 –70 G = +1 –70 G = +2 G = +1 –80 –80 –90 0.1 1 Frequency (MHz) 10 20 –90 0.1 1 Frequency (MHz) 10 20 INPUT VOLTAGE AND CURRENT NOISE DENSITY 100 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –8 –6 TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS dBc = dB below carriers 50MHz Inverting Input Current Noise 15pA/√Hz 12pA/√Hz 10 Non-Inverting Input Current Noise 3rd-Order Spurious Level (dBc) Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) 20MHz Voltage Noise 1 100 1k 10k 2.2nV/√Hz 100k 1M 10M 10MHz Load Power at Matched 50Ω Load –4 –2 0 2 4 6 8 10 Frequency (Hz) Single-Tone Load Power (dBm) RECOMMENDED RS vs CAPACITIVE LOAD 60 50 40 RS (Ω) 30 20 10 0 1 10 Capacitive Load (pF) 100 15 FREQUENCY RESPONSE vs CAPACITIVE LOAD Gain to Capacitive Load (3dB/div) 12 9 6 3 0 –3 –6 –9 –12 –15 0 VIN RS OPA682 CL = 10pF CL = 22pF CL = 47pF VO 400Ω 400Ω CL 1kΩ 1kΩ is optional. CL = 100pF 300MHz 150MHz Frequency (30MHz/div) ® 9 OPA682 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). (Cont.) POWER SUPPLY REJECTION RATIO vs FREQUENCY 70 65 60 +PSRR SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 10 Supply Current (2.5mA/div) 200 Sourcing Output Current Sinking Output Current Output Current (mA) –PSRR Rejection Ratio (dB) 55 50 45 40 35 30 25 20 102 103 104 105 Frequency (Hz) 106 107 108 7.5 150 5 Quiescent Supply Current 100 2.5 50 0 –40 –20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) 0 COMPOSITE VIDEO dG/dP 0.05 Positive Video Negative Sync 5 4 TYPICAL DC DRIFT OVER TEMPERATURE 50 Non-Inverting Input Bias Current 40 Input Offset Voltage (mV) dP 2 1 0 –1 –2 –3 –4 –5 Inverting Input Bias Current VIO 20 10 0 0.03 0.02 –10 –20 –30 –40 –50 –40 –20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) 0.01 dG 0 1 2 3 4 Number of 150Ω Loads OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 4 3 2 1W Internal Power Limit Output Current Limited 10 CLOSED-LOOP OUTPUT IMPEDANCE +5 Output Impedance (Ω) 1 50Ω OPA682 ZO 400Ω VO (Volts) 1 0 –1 –2 –3 –4 –5 –300 –200 –100 0 IO (mA) 100 200 Output Current Limit 25Ω Load Line 50Ω Load Line 100Ω Load Line 400Ω 0.1 –5 1W Internal Power Limit 0.01 300 10k 100k 1M Frequency (Hz) 10M 100M ® OPA682 10 Input Bias Currents (µA) 0.04 3 30 dG/dP (%/°) TYPICAL PERFORMANCE CURVES: VS = +5V G = +2 and RL = 100Ω to VCM = +2.5V, unless otherwise noted (see Figure 2). SMALL-SIGNAL FREQUENCY RESPONSE 2 1 LARGE-SIGNAL FREQUENCY RESPONSE 8 7 6 RL = 100Ω to 2.5V VO = 0.5Vp-p Normalized Gain (1dB/div) 0 Gain (1dB/div) –1 –2 –3 –4 –5 –6 –7 –8 0 G = –1 G = +2 5 4 3 2 1 0 –1 –2 VO = 2Vp-p VO = 1Vp-p G = +1 250MHz Frequency (50MHz/div) 500MHz 0 125 Frequency (25MHz/div) 250 SMALL-SIGNAL PULSE RESPONSE 2.10 2.9 VO = 0.5Vp-p Output Voltage (400mV/div) LARGE-SIGNAL PULSE RESPONSE 4.5 4.1 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 0.5 VO = 2Vp-p Output Voltage (100mV/div) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 Time (5ns/div) Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD 70 60 50 Gain to Capacitive Load (3dB/div) 15 12 9 6 3 0 –3 –6 –9 –12 –15 1 10 Capacitive Load (pF) 100 0 VIN FREQUENCY RESPONSE vs CAPACITIVE LOAD CL = 47pF CL = 10pF CL = 22pF +5V 806Ω RS (Ω) 40 30 20 10 0 0.1µF 57.6Ω 806Ω OPA682 RS C L 400Ω 400Ω (1kΩ is optional) VO 1kΩ 0.1µF CL = 100pF 100MHz Frequency (20MHz/div) 200MHz ® 11 OPA682 TYPICAL PERFORMANCE CURVES: VS = +5V G = +2 and RL = 100Ω to VCM = +2.5V, unless otherwise noted (see Figure 2). (Cont.) 2nd HARMONIC DISTORTION vs FREQUENCY –40 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) 3rd HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 100Ω G = –1 –60 G = +2 –50 VO = 2Vp-p RL = 100Ω G = +2 G = –1 –50 –60 G = +1 –70 –70 G = +1 –80 –80 –90 0.1 1 Frequency (MHz) 10 20 –90 0.1 1 Frequency (MHz) 10 20 2nd HARMONIC DISTORTION vs FREQUENCY –40 –40 3rd HARMONIC DISTORTION vs FREQUENCY VO = 2Vp-p –50 2nd Harmonic Distortion (dBc) –50 RL = 200Ω RL = 100Ω 3rd Harmonic Distortion (dBc) VO = 2Vp-p –60 –60 RL = 200Ω RL = 100Ω –70 RL = 500Ω Loads to 2.5V –90 0.1 1 Frequency (MHz) 10 20 –70 –80 –80 Loads to 2.5V –90 0.1 1 Frequency (MHz) 10 20 RL = 500Ω TWO-TONE, 3rd-ORDER SPURIOUS LEVEL –40 dBc = dB Below Carriers 3rd-Order Spurious (dBc) –50 50MHz –60 20MHz –70 10MHz –80 Load Power at Matched 50Ω Load –90 –14 –12 –10 –8 –6 –4 –2 0 2 Single-Tone Load Power (dBm) ® OPA682 12 APPLICATIONS INFORMATION WIDEBAND BUFFER OPERATION The OPA682 gives the exceptional AC performance of a wideband current feedback op amp with a highly linear, high power output stage. It features internal RF and RG resistors which make it easy to select a gain of +2, +1 or –1 without any external resistors. Requiring only 6mA quiescent current, the OPA682 will swing to within 1V of either supply rail and deliver in excess of 135mA guaranteed at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA682 will deliver greater than 200MHz bandwidth driving a 2Vp-p output into 100Ω on a single +5V supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA682 achieves a comparable power gain with much better linearity. The primary advantage of a current feedback op amp over a voltage feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. Figure 1 shows the DC coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 800Ω = 89Ω. The disable control line (DIS) is typically left open to guarantee normal amplifier operation. In addition to the usual power supply decoupling capacitors to ground, a 0.1µF capacitor can be included between the two power supply pins. This optional added capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. +5V DIS 0.1µF + 6.8µF Figure 2 shows the AC coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA682 requires minimal input and output voltage headroom compared to other very wideband current feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with greater than 150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1—which puts the input DC bias voltage (2.5V) on the output as well. Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 80mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA682 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, 3rd harmonic distortion plots. +VS +5V 0.1µF 50Ω Source 0.1µF VIN 57.6Ω 806Ω VO 806Ω + 6.8µF DIS 100Ω VS/2 OPA682 RF 400Ω RG 400Ω 0.1µF 50Ω Source VIN 50Ω 50Ω 50Ω Load OPA682 RF 400Ω FIGURE 2. AC-Coupled, G = +2, Single Supply Specification and Test Circuit. SINGLE-SUPPLY A/D CONVERTER INTERFACE 0.1µF + 6.8µF RG 400Ω –5V FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. 13 Most modern, high performance A/D converters (such as the Burr-Brown ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequen® OPA682 cies exceeding 5MHz. The high slew rate, exceptional output swing and high linearity of the OPA682 make it an ideal single-supply ADC driver. Figure 3 shows an example input interface to a very high performance 10-bit, 60MSPS CMOS converter. The OPA682 in the circuit of Figure 3 provides 240MHz bandwidth operating at a signal gain of +2 with a 2Vp-p output swing. The non-inverting input bias voltage is referenced to the midpoint of the ADC signal range by dividing off the top and bottom of the internal ADC reference ladder. With the gain resistor (RG) AC-coupled, this bias voltage has a gain of +1 to the output, centering the output voltage swing as well. Tested performance at a 20MHz analog input frequency and a 60MSPS clock rate on the converter gives > 58dBc SFDR. WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers which include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple “Wired-OR Video Multiplexer” can be easily implemented using the OPA682 as shown in Figure 4. +5V +5V RF 400Ω 0.1µF RG 400Ω 50Ω OPA682 1Vp-p 0.1µF CM DIS +2.5V DC Bias 2kΩ 2kΩ +3.5V REFT 0.1µF +1.5V REFB 0.1µF 2Vp-p 22pF Input Input Clock ADS823 10-Bit 60MSPS FIGURE 3. Wideband, AC-Coupled, Single-Supply A/D Driver. +5V 2kΩ VDIS +5V |VOUT| < 2.6V Video 1 75Ω DIS OPA682 400Ω –5V 400Ω 68.1Ω 75Ω Cable VOUT 400Ω +5V 400Ω 68.1Ω RG-59 Video 2 75Ω 2kΩ OPA682 DIS –5V FIGURE 4. Two-Channel Video Multiplexer. ® OPA682 14 Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The “make-before-break” disable characteristic of the OPA682 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that shown in Figure 4. Since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (68.1Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The matching resistors have been set to get a signal gain of +1 at the load while providing > 20dB return loss at the load. The video multiplexer connection (Figure 4) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated ±1.2V maximum for standard video signal levels. In any case, VOUT must be < ±2.6Vp-p in order to not exceed the absolute maximum differential input voltage (±1.2V) on the disabled part. The section on Disable Operation shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than ±50mV. Where two outputs are switched (as shown in Figure 4), the output line is always under the control of one amplifier or the other due to the “make-before-break” disable timing. In this case, the switching glitches for two 0V inputs drop to < 20mV. DELAY-EQUALIZED LOWPASS FILTER The circuit in Figure 5 realizes a 5th-order Butterworth lowpass filter with a –3dB bandwidth of 20MHz and group delay equalization. This filter is based on the KRC active filter topology using amplifiers with a fixed positive gain ≥ 1. The OPA682 makes a good amplifier for this type of filter. The first stage is the group delay equalizer, which is based on a gain of –1. The second stage has a high-Q pole, and uses a gain of +2 for minimum component sensitivity. The second stage also produces a real pole. The last stage has a low-Q pole, and uses a gain of +1 for minimum component sensitivity. The component values have been pre-distorted to compensate for the op amps’s parasitic effects. The low-Q pole section was placed last to minimize noise peaking in the passband, while maintaining good dynamic range performance. 56pF 400Ω VIN 220pF 115Ω 27pF 400Ω 49.9Ω 105Ω 226Ω OPA682 OPA682 100pF 400Ω 400Ω 68pF 95.3Ω 226Ω VOUT 39pF OPA682 400Ω 400Ω (Open) FIGURE 5. Butterworth LP Filter with Delay Equalization. ® 15 OPA682 PRECISION VOLTAGE BUFFER The precision buffer in Figure 6 combines the DC precision and low 1/f noise of the OPA227 with the high speed performance of the OPA682. The 80.6kΩ resistor makes the high frequency and low frequency nominal gains equal. The OPA682 takes over from the OPA227 at approximately 32kHz. OPERATING SUGGESTIONS GAIN SETTING Setting the gain with the OPA682 is very easy. For a gain of +2, ground the –IN pin and drive the +IN pin with the signal. For a gain of +1, leave the –IN pin open and drive the +IN pin with the signal. For a gain of –1, ground the +IN pin and drive the –IN pin with the signal. Since the internal resistor values (but not their ratio) change significantly over temperature and process, external resistors should not be used to modify the gain. OUTPUT CURRENT AND VOLTAGE The OPA682 provides output voltage and current capabilities that are unsurpassed in a low cost monolithic op amp. Under no-load conditions at 25°C, the output voltage typically swings closer than 1V to either supply rail; the guaranteed swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is guaranteed to deliver more than ±135mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage x current, or V-I product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Performance Curves. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA682’s output drive capabilities, noting that the graph is bounded by a “Safe Operating Area” of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA682 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability, as shown in the Typical Specifications. The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the guaranteed tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBE’s (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally be a problem since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power supply pin will, in most cases, destroy the amplifier. If additional short-circuit protection is required, consider a small series resistor in the power supply 16 +5V VIN 200Ω +5V 80.6kΩ 400Ω OPA682 400Ω VOUT 2.7nF OPA227 –5V 200Ω –5V 2.7nF FIGURE 6. Precision Wideband, Unity Gain Buffer. DESIGN-IN TOOLS DEMONSTRATION BOARDS Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA682 in its three package styles. All of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below. BOARD PART NUMBER DEM-OPA68xP DEM-OPA68xU DEM-OPA68xN LITERATURE REQUEST NUMBER MKT-350 MKT-351 MKT-348 PRODUCT OPA682P OPA682U OPA682N PACKAGE 8-Pin DIP 8-Lead SO-8 6-Lead SOT23-6 Contact the Burr-Brown applications support line to request any of these boards. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA682 is available through the BurrBrown Internet web page (http://www.burr-brown.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortions, temperature or dG/dφ characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. ® OPA682 leads. This will, under heavy output loads, reduce the available output voltage swing. A 5Ω series resistor in each power supply lead will limit the internal power dissipation to less than 1W for an output short circuit while decreasing the available output voltage swing only 0.5V for up to 100mA desired load currents. Always place the 0.1µF power supply decoupling capacitors after these supply current limiting resistors directly on the supply pins. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter—including additional external capacitance which may be recommended to improve A/D linearity. A high-speed amplifier like the OPA682 can be very susceptible to decreased stability and frequency response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Performance Curves show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA682. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA682 output pin (see Board Layout Guidelines). DISTORTION PERFORMANCE The OPA682 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback networkin the non-inverting configuration (Figure 1) this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Performance Curves show the 2nd harmonic increasing at a little less than the expected 2X rate while the 3rd harmonic increases at a little less than the expected 3X rate. Where the test power doubles, the difference between it and the 2nd harmonic decreases less than the expected 6dB while the difference between it and the 3rd decreases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rdorder spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Performance Curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2Vp-p for each tone at the load, which requires 8Vp-p for the overall 2-tone envelope at the output pin), the Typical Performance Curves show 62dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies. NOISE PERFORMANCE The OPA682 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (15pA/√Hz) is significantly lower than earlier solutions while the input voltage noise (2.2nV√Hz) is lower than most unity gain stable, wideband, voltage feedback op amps. This low input voltage noise was achieved at the price of higher non-inverting input current noise (12pA/√Hz). As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise for the gain settings, available using the OPA682. Figure 7 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 7. ENI RS OPA682 IBN EO ERS √4kTRS RF √4kTRF 4kT = 1.6E –20J at 290°K 4kT RG RG IBI FIGURE 7. Noise Model. ® 17 OPA682 Eq.1 EO = (E 2 NI + ( I BN R S ) + 4kTR S NG 2 + ( I BI R F ) + 4kTR F NG 2 2 ) pin is left unconnected, the OPA682 will operate normally. To disable, the control pin must be asserted low. Figure 8 shows a simplified internal circuit for the disable control feature. Dividing this expression by the noise gain (NG = (1+RF/RG)) will give the equivalent input-referred spot noise voltage at the non-inverting input as shown in Equation 2. Eq. 2 +VS I R 2 4kTR F 2 E N = E NI 2 + ( I BN R S ) + 4kTR S +  BI F  +  NG  NG 15kΩ Q1 Evaluating these two equations for the OPA682 circuit and component values shown in Figure 1 will give a total output spot noise voltage of 8.4nV/√Hz and a total equivalent input spot noise voltage of 4.2nV/√Hz. This total input-referred spot noise voltage is higher than the 2.2nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. DC ACCURACY The OPA682 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Typical Specifications show an input offset voltage comparable to high speed voltage feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Bias current cancellation techniques will not reduce the output DC offset for OPA682. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: ±(NG • VOS(max)) + (IBN • RS/2 • NG) ± (IBI • RF) where NG = non-inverting signal gain = ±(2 • 5.0mV) + (55µA • 25Ω • 2) ± (480Ω • 40µA) = ±10mV + 2.8mV ± 19.2mV = –26.4mV → +32.0mV Minimizing the resistance seen by the non-inverting input will give the best DC offset performance. For significantly improved DC accuracy, consider the precision buffer circuit shown in Figure 6. DISABLE OPERATION The OPA682 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control 25kΩ VDIS IS Control 110kΩ –VS FIGURE 8. Simplified Disable Control Circuit. In normal operation, base current to Q1 is provided through the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled low, additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 100µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode is only that required to operate the circuit of Figure 8. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high impedance state. If the OPA682 is operating in a gain of +1, this will show a very high impedance (4pF || 1MΩ) at the output and exceptional signal isolation. If operating at a gain of +2, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured at a gain of –1 the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 9 shows these glitches for the circuit of Figure 1 with the input signal set to zero volts. The glitch waveform at the output pin is plotted along with the DIS pin voltage. ® OPA682 18 40 Output Voltage (20mV/div) 20 0 –20 –40 Output Voltage (0V Input) 4.8V VDIS 0.2V Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower guaranteed junction temperatures. Remember, this is a worst-case internal power dissipation-use your actual signal and load to compute PDL. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The Output Voltage and Current Limitations plot shown in the Typical Performance Curves include a boundary for 1W maximum internal power dissipation under these conditions. BOARD LAYOUT GUIDELINES Time (20ns/div) FIGURE 9. Disable/Enable Glitch. The transition edge rate (dV/dt) of the DIS control line will influence this glitch. For the plot of Figure 9, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the VDIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2kΩ series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring an adequate logic level swing. THERMAL ANALYSIS Due to the high output power capability of the OPA682, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA682N (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load to +2.5V DC: PD = 10V • 7.2mA + 52/(4 • (20Ω || 800Ω)) = 392mW Maximum TJ = +85°C + (0.39W • 150°C/W) = 144°C Achieving optimum performance with a high frequency amplifier like the OPA682 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pin can cause instability: on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA682. Any external resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. All external components should also be placed close to the package. ® 19 OPA682 d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA682 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the Distortion vs Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA682 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA682 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high speed part like the OPA682 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA682 onto the board. If socketing for the DIP package is desired, high frequency flush-mount pins (e.g., McKenzie Technology #710C) can give good results. INPUT AND ESD PROTECTION The OPA682 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 10. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA682), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +V CC External Pin Internal Circuitry –V CC FIGURE 10. Internal ESD Protection. ® OPA682 20