OPA686

® OPA 686 OPA686 OPA 686 For most current data sheet and other product information, visit www.burr-brown.com Wideband, Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER TM FEATURES q HIGH BANDWIDTH: 250MHz (G = +10) q LOW INPUT VOLTAGE NOISE: 1.3nV/√Hz q VERY LOW DISTORTION: –90dBc (5MHz) q HIGH SLEW RATE: 600V/µs q HIGH DC ACCURACY q LOW SUPPLY CURRENT: 12mA q HIGH GAIN BANDWIDTH PRODUCT: 1600MHz q STABLE FOR GAINS ≥ 7 APPLICATIONS q HIGH DYNAMIC RANGE ADC PREAMP q LOW NOISE, WIDEBAND, TRANSIMPEDANCE AMPLIFIER q WIDEBAND, HIGH GAIN AMPLIFIER q LOW NOISE DIFFERENTIAL RECEIVER q VDSL LINE RECEIVER q ULTRASOUND CHANNEL AMPLIFIER q IMPROVED REPLACEMENT FOR THE CLC425 A new external compensation technique can be used to give a very flat frequency response below the minimum stable gain for the OPA686, further improving its already exceptional distortion performance. Using this compensation makes the OPA686 one of the premier 12- to 14-bit analog-to-digital converter input drivers. The supply current for the OPA686 is precisely trimmed to 12.4mA at +25°C. This, along with carefully defined supply current tempcos in the input and output stages, combine to provide exceptional performance over the full specified temperature range. OPA686 RELATED PRODUCTS SINGLES OPA643 OPA2686 OPA687 DUALS INPUT NOISE VOLTAGE (nV/√Hz) 2.3 1.3 0.95 GAIN BANDWIDTH PRODUCT (MHz) 800 1600 3600 DESCRIPTION The OPA686 combines very high gain bandwidth and large signal performance with very low input voltage noise while dissipating a low 12mA supply current. The classical differential input stage, along with two stages of forward gain and a high power output stage, combine to make the OPA686 an exceptionally low distortion amplifier with excellent DC accuracy and output drive. The voltage feedback architecture allows all standard op amp applications to be implemented with very high performance. The combination of low input voltage and current noise, along with a 1.6GHz gain bandwidth product, make the OPA686 an ideal amplifier for wideband transimpedance stages. As a voltage gain stage, the OPA686 is optimized for a flat response at a gain of +10 and is guaranteed stable down to a noise gain of +7. +5V Supply decoupling not shown. 100pF 0.1µF 50kΩ 100 95 20log (50kΩ) = 94dBΩ 20•log (ZT) 5dB/div OPA686 VO 90 85 80 75 70 65 λ IS 10pF Photodiode –5V 50kΩ 0.2pF –VB 60 0.1 1 10 Frequency (MHz) 100 High Gain, 20MHz Transimpedance Amplifier International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation 1 PDS-1370D OPA686 May, 2000 Printed in U.S.A. SPECIFICATIONS: VS = ±5V RF = 453Ω, RL = 100Ω, and G =+10, unless otherwise noted. Figure 1 for AC performance. OPA686U, N TYP +25°C +25°C(2) GUARANTEED 0°C to 70°C (3) –40°C to +85°C (3) MIN/ TEST MAX LEVEL(1) PARAMETER AC PERFORMANCE (Figure 1) Closed-Loop Bandwidth CONDITIONS G = +7, RG = 50Ω, VO = 200mVp-p G = +10, RG = 50Ω, VO = 200mVp-p G = +20, RG = 50Ω, VO = 200mVp-p G ≥ +40 G = +10, RL = 100Ω, VO = 200mVp-p G = +10, f = 5MHz, VO = 2Vp-p R L = 100Ω R L = 500Ω R L = 100Ω R L = 500Ω G = +10, f = 10MHz f > 1MHz f > 1MHz 0.2V Step 2V Step 2V Step 2V Step 2V Step G = +10, NTSC, RL = 150Ω G = +10, NTSC, RL = 150Ω VO = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V UNITS Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +7 Harmonic Distortion 2nd Harmonic 3rd Harmonic Two-Tone, 3rd-Order Intercept Input Voltage Noise Input Current Noise Rise/Fall Time Slew Rate Settling Time to 0.01% 0.1% 1% Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection (CMR) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio +PSRR, –PSRR THERMAL CHARACTERISTICS Specified Operating Range: U, N Package Thermal Resistance, θJA U 8-Pin, SO-8 N 5-Pin, SOT23 425 250 100 1600 40 2 –72 –90 –95 –110 43 1.3 1.8 1.4 600 18 16 11 0.02 0.02 80 ±0.35 –10 ±0.5 200 80 1250 35 170 65 1100 30 140 55 1000 25 MHz MHz MHz MHz MHz dB dBc dBc dBc dBc dBm nV/√Hz pA/√Hz ns V/µs ns ns ns % deg typ min min min min typ max max max max min max max max min typ max max typ typ min max max max max max max min min typ typ min min min min typ typ max max min min typ typ typ C B B B B C B B B B B B B B B C B B C C A A B A B A B A A C C A A A A C C A A A A C C C –67 –85 –90 –105 40 1.5 2.3 1.75 500 14 12 –65 –80 –85 –100 39 1.6 2.4 2 400 21 14 –60 –75 –80 –95 37 1.7 2.5 2.5 310 25 18 ±1.0 –17 75 ±1.0 ±3.0 90 70 ±1.2 5 –18 50 ±1.5 5 ±2.9 85 70 ±1.5 10 –20 100 ±1.8 10 ±2.8 75 dB mV µV/°C µA nA/°C µA nA/°C V dB kΩ || pF MΩ || pF VCM = ±1V, Input Referred VCM = 0V VCM = 0V ≥ 400Ω Load 100Ω Load VO = 0V VO = 0V G = +10, f = 100kHz ±3.2 100 6 || 2 2.9 || 1 ±3.5 ±3.3 80 –80 0.008 ±5 ±3.2 ±3.0 60 –60 ±3.1 ±2.8 55 –55 ±3.0 ±2.8 50 –40 V V mA mA Ω V V mA mA dB °C °C/W °C/W VS = ±5V VS = ±5V |VS| = 4.5 to 5.5, Input Referred ±6 12.9 11.9 70 12.4 12.4 78 –40 to +85 ±6 13 11.9 70 ±6 13.9 11 65 Junction-to-Ambient 125 150 NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ±CMIR limits. ® OPA686 2 PIN CONFIGURATIONS Top View SOT23-5 Top View SO-8 Output 1 5 +VS –VS 2 Non-Inverting Input 3 4 Inverting Input NC Inverting Input Non-Inverting Input 1 2 3 4 8 7 6 5 DNC: Do Not Connect NC: No Connection DNC +VS Output NC 5 4 –VS A86 1 2 Pin Orientation/Package Marking 3 ABSOLUTE MAXIMUM RATINGS Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ...................................... See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: U, N ................................ –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 182 " 331 TEMPERATURE RANGE –40°C to +85°C " –40°C to +85°C " PACKAGE MARKING OPA686U " A86 " ORDERING NUMBER(2) OPA686U OPA686U/2K5 OPA686N/250 OPA686N/3K TRANSPORT MEDIA Rails Tape and Reel Tape and Reel Tape and Reel PRODUCT OPA686U " OPA686N " PACKAGE SO-8 Surface Mount " 5-Lead SOT23-5 " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA686U/2K5” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA686 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 3 Normalized Gain (3dB/div) INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 3 RG = RS = 50Ω VO = 0.2Vp-p G = –12 0 –3 –6 –9 –12 –15 –18 –21 –24 0.5 10 Frequency (MHz) 100 500 See Figure 1 G = +20 G = +50 G = +10 Normalized Gain (3dB/div) RG = 50Ω VO = 0.2Vp-p G = +7 0 –3 –6 –9 –12 –15 –18 –21 –24 0.5 10 Frequency (MHz) 100 500 See Figure 2 G = –50 G = –20 NON-INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 26 23 20 Gain (3dB/div) INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 30 29 26 RG = RS = 50Ω G = –20V/V RG = 50Ω G = +10V/V VO = 0.2Vp-p VO = 0.2Vp-p 14 11 8 5 2 –1 –4 0.5 10 See Figure 1 Gain (3dB/div) 17 VO = 1Vp-p VO = 2Vp-p VO = 5Vp-p 23 20 17 14 11 8 5 2 See Figure 2 0.1 10 Frequency (MHz) 100 500 VO = 1Vp-p VO = 2Vp-p VO = 5Vp-p 100 500 Frequency (MHz) NON-INVERTING PULSE RESPONSE G = +10V/V Output Voltage (100mV/div) Output Voltage (500mV/div) INVERTING PULSE RESPONSE G = –20V/V Output Voltage (100mV/div) Large Signal ±1V 100 0 –100 Right Scale Small Signal ±100mV Left Scale 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 Large Signal ±1V 100 0 –100 Right Scale Small Signal ±100mV Left Scale 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 See Figure 1 Time (5ns/div) See Figure 2 Time (5ns/div) ® OPA686 4 Output Voltage (500mV/div) TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +10, RG = 50Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. (CONT) 5MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –70 RL = 100Ω 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) 5MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –70 –80 RL = 200Ω –90 RL = 500Ω –80 –90 RL = 100Ω –100 RL = 200Ω RL = 500Ω 0.1 1 Output Voltage (Vp-p) 10 –100 –110 0.1 1 Output Voltage (Vp-p) 10 –110 10MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) 10MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 RL = 100Ω –70 RL = 200Ω –70 RL = 500Ω –80 RL = 500Ω RL = 200Ω –100 0.1 1 Output Voltage (Vp-p) 10 –80 RL = 500Ω –90 –90 –100 0.1 1 Output Voltage (Vp-p) 10 20MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 2nd Harmonic Distortion (dBc) 20MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 –60 RL = 200Ω –70 RL = 500Ω –80 3rd Harmonic Distortion (dBc) RL = 100Ω –60 –70 RL = 100Ω –80 RL = 500Ω –90 RL = 200Ω –90 0.1 1 Output Voltage (Vp-p) 10 0.1 1 Output Voltage (Vp-p) 10 ® 5 OPA686 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. 2nd HARMONIC DISTORTION vs FREQUENCY –50 2nd Harmonic Distortion (dBc) 3rd Harmonic Distortion (dBc) 3rd HARMONIC DISTORTION vs FREQUENCY –50 VO = 2Vp-p RL = 100Ω –60 VO = 2Vp-p RL = 100Ω –60 G = +50 G = +50 –70 –70 G = +20 –80 G = +10 –80 G = +20 G = +10 –90 1 Frequency (MHz) 10 20 –90 1 Frequency (MHz) 10 20 INPUT VOLTAGE and CURRENT NOISE DENSITY 10 50 45 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) TWO-TONE, 3rd-0RDER INTERMODULATION INTERCEPT vs FREQUENCY 40 Intercept (dBm) 35 30 25 20 15 0 PI 50Ω OPA686 50Ω PO 50Ω Current Noise 1.8pA/√Hz 1.3nV/√Hz 453Ω 50Ω Voltage Noise 1 100 1k 10k 100k 1M 10M Frequency (Hz) 0 5 10 15 20 25 30 35 40 45 50 Frequency (MHz) RS vs CAPACITIVE LOAD 60 50 40 RS (Ω) Gain to Capacitive Load (1dB/div) FREQUENCY RESPONSE vs CAPACITIVE LOAD 22 21 20 19 18 17 16 15 14 13 12 1 50Ω VIN OPA686 CL = 10pF CL = 20pF CL = 50pF CL = 100pF RS 453Ω VO 1kΩ 30 20 10 0 1 10 Capacitive Load (pF) 100 CL 1kΩ is optional 10 Frequency (MHz) 100 500 ® OPA686 6 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. (CONT) OPEN-LOOP GAIN and PHASE 90 80 Open-Loop Gain (10dB/div) POWER SUPPLY and OUTPUT CURRENT vs TEMPERATURE 0 Power Supply Current (mA) Open-Loop Phase (30°/div) 14 12 Power Supply Current Output Current Sourcing 140 120 100 Output Current Sinking 80 60 40 20 0 Output Current (mA) Input Bias and Input Offset Current (µA) ® | AOL| ∠ AOL –30 –60 –90 –120 –150 –180 –210 –240 –270 70 60 50 40 30 20 10 0 100 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) 10 8 6 4 2 0 –50 –25 0 25 50 75 100 125 Temperature (°C) CMRR and PSRR 110 INPUT DC ERRORS vs TEMPERATURE 1.3 1.1 Input Bias Current 13 11 9 7 5 Offset Voltage 0.3 0.1 –0.1 Input Offset Current 3 1 –1 –50 –25 0 25 50 75 100 125 Temperature (°C) Power Supply Rejection Ratio (dB) CMRR +PSRR 100 90 80 0.9 VOS (mV) 100k Frequency (Hz) 1M 10M 100M 70 60 50 40 30 20 10 100 1k –PSRR 0.7 0.5 10k CLOSED-LOOP OUTPUT IMPEDANCE 10 107 DIFFERENTIAL and COMMON-MODE INPUT IMPEDANCE Common-Mode Output Impedance (Ω) ZO 450Ω Input Impedance (Ω) 1.0 50Ω OPA686 106 0.1 50Ω 105 0.01 104 Differential 0.001 10k 103 100k 1M Frequency (Hz) 10M 100M 100 1k 10k 100k Frequency (Hz) 1M 10M 10M 7 OPA686 APPLICATIONS INFORMATION WIDEBAND, NON-INVERTING OPERATION The OPA686 provides a unique combination of features— low input voltage noise along with a very low distortion output stage—to give one of the highest dynamic range op amps available. Its very high Gain Bandwidth Product (GBP) can be used either to deliver high signal bandwidths at high gains, or to deliver very low distortion signals at moderate frequencies and lower gains. To achieve the full performance of the OPA686, careful attention to PC board layout and component selection is required as discussed in the remaining sections of this data sheet. Figure 1 shows the non-inverting gain of +10 circuit used as the basis of the Electrical Specifications and most of the Typical Performance Curves. Most of the curves were characterized using signal sources with 50Ω driving impedance, and with measurement equipment presenting a 50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the VI terminal matches the source impedance of the test generator, while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet voltage swing specifications are at the output pin (VO in Figure 1), while output power (dBm) specifications are at the matched 50Ω load. The total 100Ω load at the output, combined with the 503Ω total feedback network load, presents the OPA686 with an effective output load of 83Ω for the circuit of Figure 1. Voltage feedback op amps, unlike current feedback designs, can use a wide range of resistor values to set their gain. The circuit of Figure 1, and the specifications at other gains, use the constraint that RG should always be set to 50Ω and RF adjusted to get the desired gain. Using this guideline will guarantee that the noise added at the output due to Johnson noise of the resistors will not significantly increase the total noise over that due to the 1.3nV/√Hz input voltage noise for the op amp itself. WIDEBAND, INVERTING GAIN OPERATION Operating the OPA686 as an inverting amplifier has several benefits and is particularly appropriate when a matched input impedance is required. Figure 2 shows the inverting gain circuit used as the basis of the inverting mode Typical Performance Curves. +5V +VS + 0.1µF 6.8µF 50Ω Load 0.1µF 91Ω VO 50Ω OPA686 RF 1kΩ 50Ω Source VI RG 50Ω 0.1µF + 6.8µF –VS –5V FIGURE 2. Inverting, G = –20 Characterization Circuit. Driving this circuit from a 50Ω source, and constraining the gain resistor (RG) to equal 50Ω, will give both a signal bandwidth and noise advantage. R G acts as both the input termination resistor and the gain setting resistor for the circuit. Although the signal gain (VO/VI) for the circuit of Figure 2 is double that for Figure 1, the noise gains are in fact equal when the 50Ω source resistor is included. This has the interesting effect of doubling the equivalent GBP of the amplifier. This can be seen in comparing the G = +10 and G = –20 small-signal frequency response curves. Both show approximately 250MHz bandwidth, but the inverting configuration of Figure 2 gives 6dB higher signal gain. If the signal source is actually the low impedance output of another amplifier, RG should be increased to the minimum load resistance value allowed for that amplifier and R F should be adjusted to achieve the desired gain. For stable operation of the OPA686, it is critical that this driving amplifier show a very low output impedance at frequencies beyond the expected closed-loop bandwidth for the OPA686. WIDEBAND, HIGH SENSITIVITY, TRANSIMPEDANCE DESIGN +5V +VS 0.1µF 6.8µF + 50Ω Source 50Ω Load VI 50Ω VO 50Ω OPA686 RF 453Ω RG 50Ω + –VS –5V 6.8µF 0.1µF FIGURE 1. Non-Inverting, G = +10 Specification and Test Circuit. ® The high Gain Bandwidth Product (GBP) and the low input voltage and current noise for the OPA686 make it an ideal wideband transimpedance amplifier for low to moderate transimpedance gains. Very high transimpedance gains (> 100kΩ) will benefit from the low input noise current of a FET-input op amp such as the OPA655. Unity gain stability in the op amp is not required for application as a 8 OPA686 transimpedance amplifier. One transimpedance design example is shown on the front page of the data sheet. Designs that require high bandwidth from a large area (high capacitance) detector with relatively low transimpedance gain will benefit from the low input voltage noise offered by the OPA686. This input voltage noise will be peaked up over frequency at the output by the diode source capacitance, and can, in many cases, become the limiting factor to input sensitivity. The key elements of the design are the expected diode capacitance (CD) with the reverse bias voltage (–VB) applied, the desired transimpedance gain, RF, and the GBP of the OPA686 (1600MHz). Figure 3 shows a design using a 50pF source capacitance diode and a 10kΩ transimpedance gain. With these three variables set (and including the parasitic input capacitance for the OPA686 added to CD), the feedback capacitor value (CF) may be set to control the frequency response. +5V Supply Decoupling Not Shown Where: IEQ = Equivalent input noise current if the output noise is bandlimited to F < 1/(2πRFCD) IN = Input current noise for the op amp inverting input EN = Input voltage noise for the op amp CD = Diode capacitance F = Bandlimiting frequency in Hz (usually a post filter prior to further signal processing) Evaluating this expression up to the feedback pole frequency at 15.5MHz for the circuit of Figure 3, gives an equivalent input noise current of 6.4pA/√Hz. This is much higher than the 1.8pA/√Hz for just the op amp itself. This result is being dominated by the last term in the equivalent input noise expression. It is essential in this case to use a low voltage noise op amp. For example, if a slightly higher input noise voltage, but otherwise identical op amp were used instead of the OPA686 in this application (say 2.0nV/√Hz ), the total input-referred current noise would increase to 9.5pA/√Hz. LOW GAIN COMPENSATION FOR IMPROVED SFDR Where a low gain is desired, and inverting operation is acceptable, a new external compensation technique may be used to retain the full slew rate and noise benefits of the OPA686 while giving increased loop gain and the associated improvement in distortion offered by the decompensated architecture. This technique shapes the loop gain for good stability while giving an easily controlled secondorder low pass frequency response. Considering only the noise gain (non-inverting signal gain) for the circuit of Figure 4, the low frequency noise gain, (NG1) will be set by the resistor ratios while the high frequency noise gain (NG2) will be set by the capacitor ratios. The capacitor values set both the transition frequencies and the high frequency noise gain. If this noise gain, determined by NG2 = 1+CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp and the noise gain pole, set by 1/RFCF, is placed correctly, a very well controlled, 2nd-order low pass frequency response will result. OPA686 RF 10kΩ ID CD 50pF CF 0.8pF VO = ID RF λ –5V –VB FIGURE 3. Wideband, Low Noise, Transimpendance Amplifier. To achieve a maximally flat 2nd-order Butterworth frequency response, the feedback pole should be set to: 1/(2πRFCF) = √(GBP/(4πRFCD)) Adding the common-mode and differential mode input capacitance (1.0 + 2.0)pF to the 50pF diode source capacitance of Figure 3, and targeting a 10kΩ transimpedance gain using the 1600MHz GBP for the OPA686, will require a feedback pole set to 15.5MHz. This will require a total feedback capacitance of 1.0pF. Typical surface-mount resistors have a parasitic capacitance of 0.2pF, leaving the required 0.8pF value shown in Figure 3 to get the required feedback pole. This will give an approximate –3dB bandwidth equal to: f–3dB = √(GBP/2πRFCD)Hz The example of Figure 3 will give approximately 23MHz flat bandwidth using the 0.8pF feedback compensation. If the total output noise is bandlimited to a frequency less than the feedback pole frequency, a very simple expression for the equivalent input noise current can be derived as: I EQ = I 2 + N +5V OPA686 RG 250Ω VI CS 27pF –5V CF 2.9pF RF 500Ω VO ( E N 2πC D F ) 4 kT  E N  + + 3 RF  RF  2 2 FIGURE 4. Broadband Low Gain Inverting External Compensation. ® 9 OPA686 To choose the values for both CS and CF, two parameters and only three equations need to be solved. The first parameter is the target high frequency noise gain NG2, which should be greater than the minimum stable gain for the OPA686. Here, a target NG2 of 10.5 will be used. The second parameter is the desired low frequency signal gain, which also sets the low frequency noise gain NG1. To simplify this discussion, we will target a maximally flat second-order low pass Butterworth frequency response (Q = 0.707). The signal gain of –2 shown in Figure 4 will set the low frequency noise gain to NG1 = 1 + RF/RG (= 3 in this example). Then, using only these two gains and the GBP for the OPA686 (1600MHz), the key frequency in the compensation can be determined as: ZO = GBP NG12  NG1  NG1  1 –  – 1– 2 NG 2  NG 2       12 9 6 Gain (3dB/div) 3 0 –3 –6 –9 –12 –15 –18 1 10 Frequency (MHz) 100 500 170MHz FIGURE 5. G = –2 Frequency Response with External Compensation. LOW NOISE FIGURE, HIGH DYNAMIC RANGE “IF” AMPLIFIER The low input noise voltage of the OPA686 and its high two-tone intercept can be used to good advantage as a fixed gain IF amplifier. While input noise figures in the 10dB range (for a matched 50Ω input) are easily achieved with just OPA686 alone, Figure 6 shows a technique which reduces the noise figure even further while providing a broadband, low gain IF amplifier stage using the OPA686. +5V 50Ω Load Physically, this Z0 (10.6MHz for the values shown above) is set by 1/(2π • RF(CF + CS)) and is the frequency at which the rising portion of the noise gain would intersect unity gain if projected back to 0dB gain. The actual zero in the noise gain occurs at NG1 • Z0 and the pole in the noise gain occurs at NG2 • Z0. Since GBP is expressed in Hz, multiply Z0 by 2π and use this to get CF by solving: CF = 1 (= 2.86pF) 2π • R F Z O NG 2 Finally, since CS and CF set the high frequency noise gain, determine CS by [Using NG2 = 10.5]: C S = ( NG 2 – 1) C F (= 27.2pF) OPA686 VO 50Ω The resulting closed-loop bandwidth will be approximately equal to: (= 130MHz) f –3 dB ≅ Z O GBP For the values shown in Figure 4, the f –3dB will be approximately 130MHz. This is less than that predicted by simply dividing the GBP product by NG1. The compensation network controls the bandwidth to a lower value while providing the full slew rate at the output and an exceptional distortion performance due to increased loop gain at frequencies below NG1 • Z0. The capacitor values shown in Figure 4 are calculated for NG1 = 3 and NG2 = 10.5 with no adjustment for parasitics. Figure 5 shows the measured frequency response for the circuit of Figure 4. This shows the expected gain of –2 (6dB) with exceptional flatness through 70MHz and a –3dB bandwidth of 170MHz. Measured distortion into a 100Ω load shows > 5dB improvement through 20MHz over the performance shown in the Typical Performance Curves. Into a 500Ω load, the 5MHz, 2Vp-p, 2nd harmonic improves from –90dBc to –96dBc. 50Ω Source 1:2 RG 200Ω –5V RF 1kΩ 20pF 2pF FIGURE 6. Low Noise Figure IF Amplifier. Bringing the signal in through a step-up transformer to the inverting input gain resistor has several advantages for the OPA686. First, grounding the non-inverting input eliminates the contribution of the non-inverting input current noise to the output noise. Secondly, the non-inverting input voltage noise of the op amp is actually attenuated if reflected to the input side of RG. Using the 1:2 (turns ratio) step up transformer reflects the 50Ω source impedance at ® OPA686 10 the primary through to the secondary as a 200 Ω source impedance and likewise, the 200Ω RG resistor is reflected through to the transformer primary as a 50 Ω input matching impedance. The noise gain (NG) to the amplifier output is then 1+ 1000/400 = 3.5V/V. Taking the op amp’s 1.3nV/√Hz input voltage noise times this noise gain to the output, then reflecting this noise term to the input side of the RG resistor, divides it by 5. This gives a net gain of 0.7 for the non-inverting input voltage noise when reflected to the input point for the op amp circuit. This is further reduced when referred back to the transformer primary. The 14dB gain to the matched load for the circuit of Figure 6 is precisely controlled (±0.2dB) and gives a 6dB noise figure at the input of the transformer. The DC noise gain for this circuit (3.5) is below the specified minimum stable gain. This will improve the distortion performance at frequencies below 20MHz from those shown in the Typical Performance Curves. Adding the inverting compensation capacitors holds this configuration stable as described in the previous section. Measured results show 140MHz small-signal bandwidth for the circuit of Figure 6 with ±0.1dB flatness through 50MHz. The OPA686 will easily deliver a 2Vp-p ADC full-scale input at the matched 50Ω load. Two-tone testing at 20MHz for the circuit of Figure 6 (1Vp-p for each test tone) shows that the two-tone intermodulation intercept has improved to 40dBm versus the 35dBm shown in the Typical Performance Curves, giving a 72dBc SFDR for the two 4dBm test tones at the load . is also available for design assistance at this number. These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. OPERATING SUGGESTIONS SETTING RESISTOR VALUES TO MINIMIZE NOISE The OPA686 provides a very low input noise voltage while requiring a low 12mA quiescent current. To take full advantage of this low input noise, careful attention to the other possible noise contributors is required. Figure 7 shows the op amp noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI RS OPA686 IBN EO ERS DESIGN-IN TOOLS DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA686 in its two package styles. Both of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below. BOARD PART NUMBER DEM-OPA68xU DEM-OPA6xxN LITERATURE REQUEST NUMBER MKT-351 MKT-348 √ 4kTRS RF √ 4kTRF 4kT = 1.6E –20J at 290°K 4kT RG RG IBI FIGURE 7. Op Amp Noise Analysis Model. The total output spot noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. This computation adds all the contributing noise powers at the output by superposition, then takes the square root to get back to a spot noise voltage. Equation 1 shows the general form for this output noise voltage using the terms shown in Figure 7. Equation 1 EO = PRODUCT OPA686U OPA686N PACKAGE 8-Pin SO-8 5-Lead SOT23-5 Contact the Burr-Brown applications support line to request any of these boards. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA686 is available through either the Burr-Brown Internet web page (http://www.burr-brown.com) or as one model on a disk from the Burr-Brown Applications department (1-800-548-6132). The Applications department 11 (E NI 2 + ( I BN R S ) + 4 kTR S NG 2 + ( I BI R F ) + 4 kTR F NG 2 2 ) Dividing this expression by the noise gain (NG = 1+RF/RG) will give the equivalent input-referred spot noise voltage at the non-inverting input as shown in Equation 2. Equation 2 I R 2 4 kTR F 2 E N = E NI 2 + ( I BN R S ) + 4 kTR S +  BI F  +  NG  NG ® OPA686 Inserting high resistor values into Eq. 2 can quickly dominate the total equivalent input referred noise. A 105Ω source impedance on the non-inverting input will add a Johnson voltage noise term equal to that of the amplifier itself. As a simplifying constraint, set RG = RS in Eq. 2 and assume an RS/2 source impedance at the non-inverting input (where RS is the signal’s source impedance with another matching RS to ground on the non-inverting input). This results in Eq. 3, where NG > 10 has been assumed to further simplify the expression. Equation 3 EN = 5 ( E NI )2 + 4 ( I BR S )2 + 4 kT   3R S  2 Evaluating this expression for RS = 50Ω will give a total equivalent input noise of 1.7nV/√Hz. Note that the NG has dropped out of this expression. This is valid only for NG > 10 as will typically be required by stability considerations. FREQUENCY RESPONSE CONTROL Voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factor), most high speed amplifiers will exhibit a more complex response with lower phase margin. The OPA686 is compensated to give a maximally flat 2nd-order Butterworth closed-loop response at a non-inverting gain of +10 (Figure 1). This results in a typical gain of +10 bandwidth of 250MHz, far exceeding that predicted by dividing the 1600MHz GBP by 10. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +40, the OPA686 will show the 40MHz bandwidth predicted using the simple formula and the typical GBP of 1600MHz. Inverting operation offers some interesting opportunities to increase the available GBP. When the source impedance is matched by the gain resistor (Figure 2), the signal gain is (1+RF/RG) while the noise gain for bandwidth purposes is (1 + RF/2RG). This cuts the noise gain almost in half, increasing the minimum stable gain for inverting operation under these condition to –12 and the equivalent GBP to 3.2GHz. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance which may be recommended to improve A/D linearity. A high speed, high open-loop gain amplifier like the OPA686 can be very susceptible to decreased stability and closed-loop response peaking when a ® capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Performance Curves show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA686. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA686 output pin (see Board Layout Guidelines). The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA686 operating in a gain of +10, the frequency response at the output pin is very flat to begin with, allowing relatively small values of RS to be used for low capacitive loads. As the signal gain is increased, the unloaded phase margin will also increase. Driving capacitive loads at higher gains will require lower RS values than those shown for a gain of +10. DISTORTION PERFORMANCE The OPA686 is capable of delivering an exceptionally low distortion signal at high frequencies over a wide range of gains. The distortion plots in the Typical Performance Curves show the typical distortion under a wide variety of conditions. Most of these plots are limited to 110dB dynamic range. The OPA686’s distortion, driving a 500Ω, load does not rise above –90dBc until either the signal level exceeds 2.0Vp-p and/or the fundamental frequency exceeds 5MHz. Distortion in the audio band is < –120dBc. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd harmonic will dominate the distortion with negligible a 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the non-inverting configuration, this is sum of RF + RG, while in the inverting configuration, it is just RF (Figures 1 and 2). Increasing output voltage swing increases harmonic distortion directly. A 6dB increase in output swing will generally increase the 2nd harmonic 12dB and the 3rd harmonic 18dB. Increasing the signal gain will also increase the 2nd harmonic distortion. Again, a 6dB increase in gain will increase the 2nd and 3rd harmonic by approximately 6dB even with constant 12 OPA686 output power and frequency. Finally, the distortion increases as the fundamental frequency increases due to the rolloff in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 100kHz. Starting from the –82dBc 2nd harmonic for a 5MHz, 2Vp-p fundamental into a 200Ω load at G = +10 (from the Typical Performance Curves), the 2nd harmonic distortion for frequencies lower than 100kHz will be approximately –82dBc – 20log(5MHz/ 100kHz) = –116dBc. The OPA686 has extremely low 3rd-order harmonic distortion. This also gives a high two-tone, 3rd-order intermodulation intercept as shown in the Typical Performance Curves. This intercept curve is defined at the 50Ω load when driven through a 50Ω matching resistor to allow direct comparisons to RF MMIC devices. This matching network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA686 drives directly into the input of a high impedance device, such as an ADC, the 6dB attenuation is not taken. Under these conditions, the intercept will increase by a minimum 6dBm. The intercept is used to predict the intermodulation spurious for two, closelyspaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and ∆f = |f2 – f1|/2, the two 3rd-order, close-in spurious tones will appear at fO ±3 • ∆f. The difference between two equal test-tone power levels and these intermodulation spurious power levels is given by ∆dBc = 2 • (IM3 – PO) where IM3 is the intercept taken from the Typical Performance Curve and PO is the power level in dBm at the 50Ω load for one of the two closely-spaced test frequencies. For instance, at 5MHz the OPA686 at a gain of +10 has an intercept of 48dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2Vp-p, this requires each tone to be 4dBm. The 3rd-order intermodulation spurious tones will then be 2 • (48 – 4) = 88dBc below the test-tone power level (–84dBm). If this same 2Vp-p, twotone envelope were delivered directly into the input of an ADC—without the matching loss or the loading of the 50Ω network—the intercept would increase to at least 54dBm. With the same signal and gain conditions, but now driving directly into a light load, the spurious tones will then be at least 2 • (54 – 4) = 100dBc below the 4dBm test-tone power levels centered on 5MHz. DC ACCURACY AND OFFSET CONTROL bias current cancellation to the circuit of Figure 1 would be to insert a 20Ω series resistor into the non-inverting input from the 50Ω terminating resistor. When the 50Ω source resistor is DC-coupled, this will increase the source resistances for the non-inverting input bias current to 45Ω. Since this is now equal to the resistance looking out of the inverting input (RF || RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using the 453Ω feedback resistor, this output error will now be less than ±0.9µA • 453Ω = ±0.4mV over the full temperature range. A fine-scale, output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing a DC offset control into an op amp circuit. Most of these techniques eventually reduce to setting up a DC current through the feedback resistor. One key consideration to selecting a technique is to insure that it has a minimal impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the non-inverting input can be considered. For a DC-coupled inverting input signal, this DC offset signal will set up a DC current back into the source that must be considered. An offset adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. Figure 8 shows one example of an offset adjustment for a DC-coupled signal path that will have minimum impact on the signal frequency response. In this case, the input is brought into an inverting gain resistor with the DC adjustment an additional current summed into the inverting node. The resistor values setting this offset adjustment are much larger than the signal path resistors. This will insure that this adjustment has minimal impact on the loop gain and hence, the frequency response. +5V Supply Decoupling Not Shown 48Ω 0.1µF OPA686 VO –5V +5V RG 50Ω 5kΩ VI ±200mV Output Adjustment RF 1kΩ The OPA686 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of its low ±1.5mV input offset voltage, careful attention to input bias current cancellation is also required. The low noise input stage of the OPA686 has a relatively high input bias current (10µA typical into the pins) but with a very close match between the two input currents—typically ±100nA input offset current. The total output offset voltage may be reduced considerably by matching the source impedances looking out of the two inputs. For example, one way to add 13 20kΩ 10kΩ 0.1µF 5kΩ VO VI =– RF RG = –20 –5V FIGURE 8. DC-Coupled, Inverting Gain of –20, with Output Offset Adjustment. ® OPA686 THERMAL ANALYSIS The OPA686 will not require heatsinking or airflow in most applications. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +175°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 • RL) where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA686N (SOT23-5 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 100Ω load at +2.5VDC. PD = 10V (13.9mA) + 52/(4 • (100Ω || 500Ω)) = 214mW Maximum TJ = +85°C + (0.21W • 150°C/W) = 117°C Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or a zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. It has been suggested here that a good starting point for design would be set the RG be set to 50Ω. Doing this will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA686 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doublyterminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA686 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot 14 BOARD LAYOUT Achieving optimum performance with a high frequency amplifier like the OPA686 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA686. Resistors should be a very low reactance type. ® OPA686 of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high speed part like the OPA686 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA686 onto the board. INPUT AND ESD PROTECTION The OPA686 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 9. +V CC External Pin Internal Circuitry –V CC FIGURE 9. Internal ESD Protection. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA686), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. ® 15 OPA686