OPA690IDBVR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 OPA690 Wideband, Voltage-Feedback Operational Amplifier With Disable 1 Features 3 Description • The OPA690 device represents a major step forward in unity-gain stable, voltage-feedback op amps. A new internal architecture provides slew rate and fullpower bandwidth previously found only in wideband, current-feedback op amps. A new output stage architecture delivers high currents with a minimal headroom requirement. These combine to give exceptional single-supply operation. Using a single 5V supply, the OPA690 can deliver a 1-V to 4-V output swing with over 150 mA drive current and 150 MHz bandwidth. This combination of features makes the OPA690 an ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver. 1 • • • • • • • Flexible Supply Range: – 5-V to 12-V Single Supply – ±2.5-V to ±5-V Dual Supply Unity-Gain Stable: 500 MHz (G = 1) High Output Current: 190 mA Output Voltage Swing: ±4 V High Slew Rate: 1800 V/µs Low Supply Current: 5.5 mA Low Disable Current: 100 µA Wideband 5-V Operation: 220 MHz (G = 2) The low 5.5-mA supply current of the OPA690 is precisely trimmed at 25°C. This trim, along with low temperature drift, gives lower maximum supply current than competing products. System power may be reduced further using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, operates the OPA690 normally. If pulled LOW, the OPA690 supply current drops to less than 100 µA while the output goes to a high-impedance state. This feature may be used for power savings. 2 Applications • • • • • • • Video Line Drivers xDSL Line Drivers and Receivers High-Speed Imaging Channels ADC Buffers Portable Instruments Transimpedance Amplifiers Active Filters Device Information(1) PART NUMBER OPA690 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.90 mm SOT-23 (6) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Single-Supply ADC Driver +5V R1 R1 3.3V 2.5V 0.1 µF C1 VI R2 3 2 8 C2 R4 20Ÿ OPA690 4 R3 R5 20Ÿ C4 10 µF THS1040 C3 20pF C6 20pF AIN+ 10-Bit 40MSPS AIN- VREF = 1V C5 0.1 µF Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics: VS = ±5 V......................... 5 Electrical Characteristics: VS = 5 V........................... 8 Typical Characteristics ............................................ 11 Detailed Description ............................................ 17 8.1 Overview ................................................................. 17 8.2 Functional Block Diagram ....................................... 17 8.3 Feature Description................................................. 17 8.4 Device Functional Modes........................................ 24 9 Application and Implementation ........................ 26 9.1 Application Information............................................ 26 9.2 Typical Applications ................................................ 27 10 Power Supply Recommendations ..................... 31 11 Layout................................................................... 31 11.1 Layout Guidelines ................................................. 31 11.2 Layout Example .................................................... 33 12 Device and Documentation Support ................. 34 12.1 12.2 12.3 12.4 12.5 12.6 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 34 34 34 34 34 34 13 Mechanical, Packaging, and Orderable Information ........................................................... 35 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (February 2010) to Revision G Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Deleted Ordering Information table, see POA at the end of the data sheet........................................................................... 3 • Added Thermal Information table ........................................................................................................................................... 4 Changes from Revision E (November 2008) to Revision F Page • Changed data sheet format to current standards................................................................................................................... 1 • Deleted Lead Temperature specification from Absolute Maximum Ratings table.................................................................. 4 • Added Figure 25, Noninverting Overdrive Recovery plot ..................................................................................................... 14 Changes from Revision D (August 2008) to Revision E • 2 Page Deleted obsolete OPA680 from Related Products table ........................................................................................................ 3 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 5 Device Comparison Table SINGLES DUALS TRIPLES Voltage-feedback — OPA2690 OPA3690 Current-feedback OPA691 OPA2691 OPA3691 Fixed gain OPA692 — OPA3692 6 Pin Configuration and Functions D Package 8-Pin SOIC Top View DRB Package 6-Pin SOT-23 Top View NC 1 8 DIS Inverting Input 2 7 +VS Noninverting Input 3 6 Output -VS 4 5 NC Output 1 6 +VS -VS 2 5 DIS Noninverting Input 3 4 Inverting Input 4 5 6 NOTE: NC = not connected. 3 2 1 OAEI Pin Orientation/Package Marking Pin Functions PIN NAME TYPE (1) DESCRIPTION SOIC SOT-23 DIS 8 5 I Disable the op amp (low = disable, high = enable) IN– 2 4 I Inverting input IN+ 3 3 I Noninverting input NC 1, 5 — — No connection Output 6 1 O Output of amplifier –VS 4 2 P Negative power supply +VS 7 6 P Positive power supply (1) I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 3 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Power supply Internal power dissipation MAX UNIT ±6.5 VDC See Thermal Analysis Differential input voltage ±1.2 V Input voltage ±VS V 175 °C 125 °C Junction temperature, TJ Storage temperature, Tstg (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 Machine-model (MM) ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VS Total supply voltage ±2.5 ±5 ±6 UNIT V TA Operating temperature –40 85 °C 7.4 Thermal Information OPA690 THERMAL METRIC (1) D (SOIC) DRB (SOT-23) 8 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance 125 150 °C/W RθJC(top) Junction-to-case (top) thermal resistance 70 131.8 °C/W RθJB Junction-to-board thermal resistance 65.3 34.9 °C/W ψJT Junction-to-top characterization parameter 25.6 25.6 °C/W ψJB Junction-to-board characterization parameter 64.8 34.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 7.5 Electrical Characteristics: VS = ±5 V at RF = 402 Ω, RL = 100 Ω, G = 2, see Figure 36 for ac performance only (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE (SEE Figure 36) 500 (1) G = 1, VO = 0.5 VPP, RF = 25 Ω TA = 25°C G = 2, VO = 0.5 VPP Small-signal bandwidth (2) 165 TA = 0°C to 70°C (3) 160 TA = –40°C to 85°C (3) 150 TA = 25°C (2) G = 10, VO = 0.5 VPP 20 TA = 0°C to 70°C (3) TA = –40°C to 85°C Gain bandwidth product G ≥ 10 G = 2, VO < 0.5 VPP Peaking at a gain of 1 VO < 0.5 VPP Large-signal bandwidth TA = 0°C to 70°C (3) 190 (3) G = 2, 4-V step Settling time Harmonic distortion MHz 30 (1) MHz 4 (1) dB 200 1400 TA = 0°C to 70°C (3) (1) 1200 (3) V/µs 900 G = 2, VO = 0.5-V step 1.4 (1) G = 2, VO = 5-V step 2.8 (1) 0.02%, G = 2, VO = 2-V step 12 (1) 0.1%, G = 2, VO = 2-V step 8 (1) 2nd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL = 100 Ω TA = 25°C (2) 2nd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL ≥ 500 Ω TA = 25°C (2) 3rd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL = 100 Ω TA = 25°C (2) 3rd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL ≥ 500 Ω TA = 25°C (2) –68 TA = 0°C to 70°C (3) TA = –40°C to 85°C –64 dBc –70 –68 (3) dBc –66 –70 TA = 0°C to 70°C (3) TA = 0°C to 70°C ns –60 TA = 0°C to 70°C (3) TA = –40°C to 85°C ns –62 (3) –77 TA = –40°C to 85°C MHz 1800 –68 –66 (3) dBc –64 –81 (3) –78 –76 TA = –40°C to 85°C (3) dBc –75 f > 1 MHz 5.5 (1) nV/√Hz Input current noise f > 1 MHz (1) pA/√Hz Differential gain G = 2, NTSC, VO = 1.4 VP, RL = 150 Ω 0.06% (1) Differential phase G = 2, NTSC, VO = 1.4 VP, RL = 150 Ω 0.03 (1) Input voltage noise (1) (2) (3) 300 180 G = 2, VO < 0.5 VPP TA = –40°C to 85°C Rise-and-fall time 18 200 TA = 25°C (2) Slew rate MHz 30 19 (3) TA = 25°C (2) TA = –40°C to 85°C Bandwidth for 0.1-dB gain flatness 220 3.1 ° Typical value only for information. Junction temperature = ambient for 25°C specifications Junction temperature = ambient at low temperature limits; junction temperature = ambient 10°C at high temperature limit for over temperature specifications Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 5 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Electrical Characteristics: VS = ±5 V (continued) at RF = 402 Ω, RL = 100 Ω, G = 2, see Figure 36 for ac performance only (unless otherwise noted) PARAMETER DC PERFORMANCE AOL TEST CONDITIONS MIN TYP TA = 25°C (2) 58 69 TA = 0°C to 70°C (3) 56 MAX UNIT (4) Open-loop voltage gain VO = 0 V, RL = 100 Ω TA = –40°C to 85°C (3) 54 TA = 25°C (2) Input offset voltage VCM = 0 V Average offset voltage drift VCM = 0 V ±1 VCM = 0 V Average bias current drift (magnitude) ±4.5 TA = –40°C to 85°C (3) ±4.7 TA = 0°C to 70°C (3) ±10 TA = –40°C to 85°C (3) ±10 TA = 0°C to 70°C VCM = 0 V ±3 (3) ±11 ±12 TA = 0°C to 70°C (3) ±20 TA = –40°C to 85°C (3) VCM = 0 V ±40 Average offset current drift VCM = 0 V ±0.1 mV µV/°C ±10 TA = –40°C to 85°C (3) TA = 25°C (2) Input offset current ±4 TA = 0°C to 70°C (3) TA = 25°C (2) Input bias current dB µA nA/°C ±1 TA = 0°C to 70°C (3) ±1.4 TA = –40°C to 85°C (3) ±1.6 TA = 0°C to 70°C (3) ±7 TA = –40°C to 85°C (3) ±9 µA nA/°C INPUT CMIR Common-mode input voltage CMRR (5) Common-mode rejection ratio Input impedance TA = 25°C (2) ±3.4 TA = 0°C to 70°C (3) ±3.3 TA = –40°C to 85°C (3) ±3.2 VCM = ±1 V TA = 25°C (2) 60 TA = 0°C to 70°C (3) 57 TA = –40°C to 85°C (3) 56 Differential mode, VCM = 0 V Common-mode, VCM = 0 V ±3.5 V 65 dB 190 || 0.6 (1) kΩ || pF (1) MΩ || pF 3.2 || 0.9 OUTPUT TA = 25°C (2) No load TA = 0°C to 70°C Voltage output swing RL = 100 Ω Sourcing, VO = 0 V ±3.8 (3) ±3.6 TA = 25°C (2) ±3.7 (3) Sinking, VO = 0 V ±3.3 TA = 25°C (2) 160 TA = 0°C to 70°C (3) 140 (4) (5) 6 (3) ±3.9 –160 TA = 0°C to 70°C (3) –140 (3) V 190 mA 100 TA = 25°C (2) TA = –40°C to 85°C V ±3.6 TA = –40°C to 85°C (3) TA = –40°C to 85°C Current output ±3.7 TA = –40°C to 85°C (3) TA = 0°C to 70°C ±4 –190 mA –100 Short-circuit current limit VO = 0 V ±250 (1) mA Closed-loop output impedance G = 2, f = 100 kHz 0.04 (1) Ω Current is considered positive out of node. Tested < 3 dB below minimum specified CMRR at ±CMIR limits. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Electrical Characteristics: VS = ±5 V (continued) at RF = 402 Ω, RL = 100 Ω, G = 2, see Figure 36 for ac performance only (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX –100 –200 UNIT DISABLE (DISABLED LOW) TA = 25°C (2) +VS Power-down supply current TA = 0°C to 70°C (3) VDIS = 0 V TA = –40°C to 85°C –240 (3) –260 Disable time VIN = 1 VDC 200 (1) Enable time VIN = 1 VDC 25 (1) ns Off isolation G = 2, RL = 150 Ω, VIN = 0 V 70 (1) dB Output capacitance in disable G = 2, RL = 150 Ω, VIN = 0 V 4 (1) pF ±50 (1) mV ±20 (1) mV Turnon glitch Turnoff glitch TA = 25°C Enable voltage (2) 3.5 TA = 0°C to 70°C (3) 3.6 TA = –40°C to 85°C (3) 3.7 TA = 25°C (2) Disable voltage Control pin input bias current ns 3.3 V 1.8 1.7 TA = 0°C to 70°C (3) 1.6 TA = –40°C to 85°C (3) 1.5 TA = 25°C (2) VDIS µA VDIS = 0 V TA = 0°C to 70°C 75 (3) 130 150 TA = –40°C to 85°C (3) V µA 160 POWER SUPPLY ±5 (1) Specified operating voltage (2) Maximum operating voltage TA = 25°C , TA = 0°C to 70°C , and TA = –40°C to 85°C (3) ±6 TA = 25°C (2) Maximum quiescent current VS = ±5 V TA = 0°C to 70°C 5.5 (3) TA = 25°C (2) +PSRR Power-supply rejection ratio VS = ±5 V TA = 0°C to 70°C Input-referred 4.3 TA = 25°C (2) 68 TA = 0°C to 70°C TA = –40°C to 85°C (3) 5.5 4.6 TA = –40°C to 85°C (3) (3) mA 75 66 Product Folder Links: OPA690 dB 64 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated mA 6.6 5.3 (3) V 5.8 6.2 TA = –40°C to 85°C (3) Minimum quiescent current V (3) 7 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com 7.6 Electrical Characteristics: VS = 5 V RF = 402 Ω, RL = 100 Ω, and G = 2; see Figure 37 for ac performance only (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE (SEE Figure 37) 400 (1) G = 1, VO = 0.5 VPP, RF = ±25 Ω TA = 25°C G = 2, VO < 0.5 VPP Small-signal bandwidth (2) 150 TA = 0°C to 70°C (3) 145 TA = –40°C to 85°C (3) 140 TA = 25°C (2) G = 10, VO < 0.5 VPP 18 TA = 0°C to 70°C (3) TA = –40°C to 85°C Gain bandwidth product G ≥ 10 G = 2, VO < 0.5 VPP Peaking at a gain of +1 VO < 0.5 VPP Large-signal bandwidth TA = 0°C to 70°C (3) 170 (3) G = 2, 2-V step Settling time Harmonic distortion 8 MHz 20 (1) MHz 5 (1) dB 220 700 TA = 0°C to 70°C (3) (1) MHz 1000 670 (3) V/µs 550 1.6 (1) G = 2, VO = 0.5-V step ns 2 (1) G = 2, VO = 2-V step 0.02%, G = 2, VO = 2-V step 12 (1) 0.1%, G = 2, VO = 2-V step 8 (1) 2nd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL = 100 Ω to VS/2 TA = 25°C (2) 2nd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL ≥ 500 Ω to VS/2 TA = 25°C (2) 3rd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL = 100 Ω to VS/2 TA = 25°C (2) 3rd-harmonic, G = 2, f = 5 MHz, VO = 2 VPP, RL ≥ 500 Ω to VS/2 TA = 25°C (2) –65 TA = 0°C to 70°C (3) TA = –40°C to 85°C –56 TA = 0°C to 70°C (3) –66 TA = 0°C to 70°C (3) TA = 0°C to 70°C –70 –68 (3) –68 TA = –40°C to 85°C –60 –59 (3) –75 TA = –40°C to 85°C ns dBc –64 –62 (3) –60 –77 (3) –73 –71 TA = –40°C to 85°C (3) –70 f > 1 MHz 5.6 (1) nV/√Hz Input current noise f > 1 MHz (1) pA/√Hz Differential gain G = 2, NTSC, VO = 1.4 VP, RL = 150 Ω to VS/2 0.06% (1) Differential phase G = 2, NTSC, VO = 1.4 VP, RL = 150 Ω to VS/2 0.02 (1) Input voltage noise (1) (2) (3) 250 160 G = 2, VO = 2 VPP TA = –40°C to 85°C Rise-and-fall time 16 180 TA = 25°C (2) Slew rate MHz 25 17 (3) TA = 25°C (2) TA = –40°C to 85°C Bandwidth for 0.1-dB gain flatness 190 3.2 ° Typical value only for information. Junction temperature = ambient for 25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient 10°C at high temperature limit for over temperature specifications. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Electrical Characteristics: VS = 5 V (continued) RF = 402 Ω, RL = 100 Ω, and G = 2; see Figure 37 for ac performance only (unless otherwise noted) PARAMETER DC PERFORMANCE AOL TEST CONDITIONS MIN TYP 56 63 MAX UNIT (4) TA = 25°C (2) VO = 2.5 V, RL = 100 Ω TA = 0°C to 70°C (3) to VS/2 TA = –40°C to 85°C (3) Open-loop voltage gain 54 52 TA = 25°C (2) Input offset voltage VCM = 2.5 V dB ±1 ±4.3 TA = –40°C to 85°C (3) ±4.7 VCM = 2.5 V, TA = 0°C to 70°C (3) and TA = –40°C to 85°C (3) Average offset voltage drift TA = 25°C Input bias current VCM = 2.5 V Average bias current drift (magnitude) ±10 (2) TA = 0°C to 70°C VCM = 2.5 V ±3 (3) VCM = 2.5 V Average offset current drift VCM = 2.5 V mV µV/°C ±10 ±11 TA = –40°C to 85°C (3) ±12 TA = 0°C to 70°C (3) ±20 TA = –40°C to 85°C (3) ±40 TA = 25°C (2) Input offset current ±4 TA = 0°C to 70°C (3) ±0.3 µA nA/°C ±1 TA = 0°C to 70°C (3) ±1.4 TA = –40°C to 85°C (3) ±1.6 TA = 0°C to 70°C (3) ±7 TA = –40°C to 85°C (3) ±9 µA nA/°C INPUT Least positive input voltage Most positive input voltage (5) (5) TA = 25°C (2) 1.6 TA = 0°C to 70°C (3) 1.7 TA = –40°C to 85°C (3) 1.8 TA = 25°C (2) 3.4 TA = 0°C to 70°C (3) VCM = 2.5 V ±0.5 V TA = 0°C to 70°C 58 (3) V 63 56 TA = –40°C to 85°C (3) Input impedance 3.5 3.2 TA = 25°C (2) Common-mode rejection ratio V 3.3 TA = –40°C to 85°C (3) CMRR 1.5 dB 54 Differential mode, VCM = 2.5 V Common-mode, VCM = 2.5 V 92 || 1.4 (1) kΩ || pF (1) MΩ || pF 2.2 || 1.5 OUTPUT No load Most positive output voltage RL = 100 Ω to 2.5 V TA = 25°C (2) 3.8 TA = 0°C to 70°C (3) 3.6 TA = –40°C to 85°C (3) 3.5 TA = 25°C (2) 3.7 TA = 0°C to 70°C (3) TA = –40°C to 85°C No load Least positive output voltage (4) (5) V 3.9 3.5 (3) 3.4 TA = 25°C (2) 1.2 TA = 0°C to 70°C (3) 1.4 TA = –40°C to 85°C (3) 1.5 TA = 25°C (2) RL = 100 Ω to 2.5 V 4 1 1.1 1.3 TA = 0°C to 70°C (3) 1.5 TA = –40°C to 85°C (3) 1.7 V Current is considered positive out of node. Tested < 3 dB below minimum specified CMRR at ±CMIR limits. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 9 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Electrical Characteristics: VS = 5 V (continued) RF = 402 Ω, RL = 100 Ω, and G = 2; see Figure 37 for ac performance only (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN (2) MAX 160 120 TA = 0°C to 70°C (3) Sourcing TA = 25°C (2) 80 –120 TA = 0°C to 70°C (3) Sinking UNIT 100 TA = –40°C to 85°C (3) Current output –160 mA –100 TA = –40°C to 85°C (3) –80 ±250 (1) Short-circuit current Closed-loop output impedance TYP G = 2, f =100 kHz 0.04 mA (1) Ω DISABLE (DISABLED LOW) TA = 25°C (2) +VS Power-down supply current VDIS = 0 V TA = 0°C to 70°C –100 (3) –240 TA = –40°C to 85°C (3) Off isolation µA –260 65 (1) G = 2, 5 MHz Output capacitance in disable 4 dB (1) pF Turnon glitch G = 2, RL = 150 Ω, VIN = VS/2 ±50 (1) mV Turnoff glitch G = 2, RL = 150 Ω, VIN = VS/2 ±20 (1) mV Enable voltage TA = 25°C (2) 3.5 TA = 0°C to 70°C (3) 3.6 TA = –40°C to 85°C (3) 3.7 TA = 25°C (2) Disable voltage TA = 0°C to 70°C 3.3 V 1.8 (3) VDIS = 0 V V 1.5 TA = 25°C (2) Control pin input bias current 1.7 1.6 TA = –40°C to 85°C (3) VDIS –200 TA = 0°C to 70°C 75 (3) 130 150 TA = –40°C to 85°C (3) µA 160 POWER SUPPLY Specified single-supply operating voltage Maximum single-supply operating voltage 5 (1) (2) TA = 25°C , TA = 0°C to 70°C , and TA = –40°C to 85°C (3) 12 TA = 25°C (2) Maximum quiescent current VS = ±5 V 4.9 5.72 TA = –40°C to 85°C (3) 6.02 VS = ±5 V TA = 0°C to 70°C 4.48 (3) +PSRR 10 Power-supply rejection ratio Input-referred Submit Documentation Feedback mA 4.9 4 TA = –40°C to 85°C (3) V 5.44 TA = 0°C to 70°C (3) TA = 25°C (2) Minimum quiescent current V (3) mA 3.86 72 (1) dB Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 7.7 Typical Characteristics 7.7.1 Typical Characteristics: VS = ±5 V TA = 25°C, G = 2, RF = 402 Ω, and RL = 100 Ω; see Figure 36 for AC performance only (unless otherwise noted) 6 9 VO = 0.5VPP G = +1 RF = 25W 3 Normalized Gain (dB) 6 G=5 -3 -6 Gain (3dB/div) 0 G=2 G = 10 VO = 2VPP 3 VO = 1VPP 0 VO = 4VPP -9 -3 -12 VO = 7VPP -15 0.7 1 10 -6 0.5 700 100 1 10 Frequency (MHz) Frequency (MHz) Figure 1. Small−Signal Frequency Response 4 G = +2 VO = 0.5VPP 300 G = +2 VO = 5VPP 3 200 Output Voltage (V) Output Voltage (mV) 500 Figure 2. Large−Signal Frequency Response 400 100 0 -100 2 1 0 -1 -200 -2 -300 -3 -4 -400 Time (5ns/div) Time (5ns/div) Figure 3. Small-Signal Pulse Response 0.200 +5V -45 OPA690 0.150 402W -55 Optional 1.3kW Pull- Down dG 402W 0.125 dG 0.100 VDIS = 0 -50 Feedthrough (dB) 75W Figure 4. Large-Signal Pulse Response No Pull- Down With 1.3kW Pull- Down Video In 0.175 dG/dP (%/degree) 100 -5V dP 0.075 -60 -65 -70 -75 -80 -85 0.050 dP -90 0.025 Reverse -95 0 1 2 4 3 Forward -100 100k 1M 10M 100M Frequency (Hz) Number of 150W Loads Figure 5. Composite Video dG/dP Figure 6. Disable Feedthrough vs Frequency Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 11 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Typical Characteristics: VS = ±5 V (continued) TA = 25°C, G = 2, RF = 402 Ω, and RL = 100 Ω; see Figure 36 for AC performance only (unless otherwise noted) -60 -65 -70 2nd-Harmonic -75 3rd-Harmonic -80 -85 -65 2nd-Harmonic -70 3rd-Harmonic -75 -80 -90 2.0 1000 100 2.5 3.0 4.5 5.0 5.5 Figure 7. Harmonic Distortion vs Load Resistance Figure 8. 5-MHz Harmonic Distortion vs Supply Voltage -60 -50 Harmonic Distortion (dBc) VO = 2VPP RL = 100W -60 2nd-Harmonic -70 -80 3rd-Harmonic -90 6.0 RL = 100W f = 5MHz 2nd-Harmonic -65 -70 3rd-Harmonic -75 -80 0.1 1 10 0.1 20 Figure 9. Harmonic Distortion vs Frequency -40 Figure 10. Harmonic Distortion vs Output Voltage -40 Harmonic Distortion (dBc) VO = 2VPP RL = 100W f = 5MHz -50 5 1 Output Voltage Swing (VPP) Frequency (MHz) Harmonic Distortion (dBc) 4.0 Supply Voltage (±VS) -100 -60 2nd-Harmonic 3rd-Harmonic -70 -80 VO = 2VPP RL = 100W f = 5MHz RF = 1kW -50 -60 2nd-Harmonic 3rd-Harmonic -70 -80 -90 1 10 20 1 10 20 Inverting Gain (V/V) Noninverting Gain (V/V) Figure 11. Harmonic Distortion vs Noninverting Gain 12 3.5 Load Resistance (W) -40 Harmonic Distortion (dBc) VO = 2VPP RL = 100W f = 5MHz VO = 2VPP f = 5MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 Figure 12. Harmonic Distortion vs Inverting Gain Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Typical Characteristics: VS = ±5 V (continued) TA = 25°C, G = 2, RF = 402 Ω, and RL = 100 Ω; see Figure 36 for AC performance only (unless otherwise noted) -30 -35 3rd-Order Spurious Level (dBc) Voltage Noise (nV/ÖHz) Current Noise (pA/ÖHz) 100 10 Voltage Noise 5.5nV/ÖHz Current Noise 3.1pA/ÖHz 50MHz -40 -45 -50 20MHz -55 -60 -65 10MHz Load Power at Matched 50W Load, see Figure 36 -70 1 -75 100 1k 10k 100k 1M 10M -8 -6 -4 Frequency (Hz) 0 -2 2 4 Figure 13. Input Voltage and Current Noise Density 8 10 Figure 14. Two-Tone, 3rd-Order Intermodulation Spurious 9 80 G = +2 Gain-to-Capacitive Load (dB) 70 60 50 RS (W) 6 Single-Tone Load Power (dBm) 40 30 20 10 CL = 10pF 6 CL = 100pF 3 CL = 22pF 0 CL = 47pF -3 VIN RS VOUT OPA690 CL 402W -6 1kW 402W 1kW is optional. 0 -9 10 1000 100 60 80 100 120 140 160 180 200 2.0 Output Voltage 1.6 Each Channel SO-14 Package Only 1.2 0.8 G = +2 VIN = +1V 4 VDIS 2 0 Output Voltage (10mV/div) 2 6 VDIS (2V/div) 4 VDIS (2V/div) Figure 16. Frequency Response vs Capacitive Load 0 Output Voltage (0.4V/div) 40 Figure 15. Recommended RS vs Capacitive Load VDIS 0 20 Frequency (20MHz/div) 6 0.4 0 Capacitive Load (pF) 30 20 10 0 Output Voltage VI = 0V -10 -20 -30 Time (50ns/div) Time (20ns/div) Figure 17. Large-Signal Enable or Disable Response Figure 18. Enable or Disable Glitch Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 13 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Typical Characteristics: VS = ±5 V (continued) TA = 25°C, G = 2, RF = 402 Ω, and RL = 100 Ω; see Figure 36 for AC performance only (unless otherwise noted) 1 0 25W Load Line 50W Load Line -1 -2 100W Load Line -3 Input Offset Voltage (mV) 0.5 Input Offset Current (IOS) 0 0 -0.5 -10 -1.0 Input Offset Voltage (VOS) -20 -2.0 0 -100 100 200 300 -50 0 -25 IO (mA) 25 50 Ambient Temperature (°C) 8 250 Sourcing Output Current -PSRR 90 80 7 Supply Current (mA) CMRR 70 60 +PSRR 50 40 30 20 200 Sinking Output Current 6 150 5 100 Quiescent Supply Current 4 50 10 0 3 10k 100k 1M 100M 10M -50 -25 Frequency (MHz) 10 0 25 50 Open-Loop Gain (dB) OPA690 ZO -5V 402W 402W 0.1 0.01 0 100k 1M 100M 10M -30 Open-Loop Gain 50 Open-Loop Phase -60 40 -90 30 -120 20 -150 10 -180 0 -210 -10 -240 -20 10k 0 125 70 60 200W 100 Figure 22. Supply and Output Currents vs Temperature +5V 1 75 Ambient Temperature (°C) Figure 21. Common−Mode Rejection Ratio and Power−Supply Rejection Ratio vs Frequency Output Impedance ( W ) 125 100 Figure 20. Typical DC Drift Over Temperature 100 1k Frequency (Hz) 10k 100k 1M 10M 100M -270 1G Frequency (Hz) Figure 23. Closed-Loop Output Impedance vs Frequency 14 75 Output Current (mA) -200 Figure 19. Output Voltage and Current Limitations Power-Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 10 -1.5 1W Internal Power Limit Output Current Limit Input Bias Current (IB) 1.0 Open-Loop Phase (°) VO (V) 2 -5 -300 20 1.5 3 -4 2.0 Output Current Limited 1W Internal Power Limit 4 Input Bias and Offset Currents (mA) 5 Submit Documentation Feedback Figure 24. Open−Loop Gain and Phase Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Typical Characteristics: VS = ±5 V (continued) 5 10 4 8 3 6 2 4 1 Output Voltage 2 0 0 -1 -2 -2 -4 -3 -6 Input Voltage -4 Output Voltage (V) Input Voltage (V) TA = 25°C, G = 2, RF = 402 Ω, and RL = 100 Ω; see Figure 36 for AC performance only (unless otherwise noted) -8 -5 -10 Time (10ns/div) Figure 25. Noninverting Overdrive Recovery 7.7.2 Typical Characteristics: 5 V TA = 25°C, G = 2, RF = 402 Ω, and RL = 100 Ω; see Figure 37 for AC performance only (unless otherwise noted) 6 9 VO = 0.5VPP 6 VO = 3VPP G = +2 Gain (dB) Normalized Gain (dB) 3 0 G = +5 -3 3 VO = 1VPP 0 G = +10 -6 -3 -9 -6 0.7 1 10 100 700 0.5 1 10 100 500 Frequency (Hz) Frequency (MHz) Figure 26. Small−Signal Frequency Response Figure 27. Large−Signal Frequency Response 2.9 4.1 G = +2 VO = 0.5VPP 2.8 2.7 2.6 2.5 2.4 2.3 2.2 G = +2 VO = 2VPP 3.7 Output Voltage (mV) Output Voltage (mV) VO = 2VPP G = +1 RF = 25W 3.3 2.9 2.5 2.1 1.7 1.3 2.1 0.9 Time (5ns/div) Time (5ns/div) Figure 28. Small-Signal Pulse Response Figure 29. Large-Signal Pulse Response Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 15 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Typical Characteristics: 5 V (continued) TA = 25°C, G = 2, RF = 402 Ω, and RL = 100 Ω; see Figure 37 for AC performance only (unless otherwise noted) 9 50 CL = 10pF Gain-to-Capacitive Load (dB) 45 40 RS (W) 35 30 25 20 15 10 6 CL = 100pF 3 0 714W 0.1mF VIN RS 58W 714W OPA690 714W VOUT 402W -9 0 1 -60 10 100 1000 0 20 40 60 100 120 140 160 180 200 Frequency (20MHz/div) Figure 30. Recommended RS vs Capacitive Load Figure 31. Frequency Response vs Capacitive Load -40 Harmonic Distortion (dBc) VO = 2VPP f = 5MHz -65 -70 2nd-Harmonic 3rd-Harmonic -75 -50 VO = 2VPP RL = 100W to 2.5V -60 2nd-Harmonic -70 -80 3rd-Harmonic -90 -100 1000 100 0.1 1 Figure 32. Harmonic Distortion vs Load Resistance -30 RL = 100W to 2.5V f = 5MHz -65 20 Figure 33. Harmonic Distortion vs Frequency 3rd-Order Spurious Level (dBc) -60 10 Frequency (MHz) Resistance (W) Harmonic Distortion (dBc) 80 Capacitive Load (pF) -80 3rd-Harmonic -70 2nd-Harmonic -75 -80 -35 50MHz -40 -45 -50 20MHz -55 -60 -65 10MHz -70 Load Power at Matched 50W Load, see Figure 37 -75 0.1 1 3 -14 Output Voltage Swing (VPP) -12 -10 -8 -6 -4 -2 0 2 Single-Tone Load Power (dBm) Figure 34. Harmonic Distortion vs Output Voltage 16 CL = 47pF CL -6 402W +5V 5 Harmonic Distortion (dBc) CL = 22pF +5V -3 Submit Documentation Feedback Figure 35. Two-Tone, 3rd-Order Intermodulation Spurious Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 8 Detailed Description 8.1 Overview The OPA690 provides an exceptional combination of high output power capability with a wideband, unity-gain stable voltage-feedback op amp using a new high slew rate input stage. The input stage provides a very high slew rate (1800 V/µs) while consuming relatively low quiescent current (5.5 mA). This exceptional full-power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 5.5-nV/√Hz input voltage noise for the OPA690 is exceptionally low for this type of input stage. 8.2 Functional Block Diagram +5V + 0.1µF 6.8µF 0.1µF DIS RB 146Ÿ 50Ÿ Source RO 50Ÿ OPA690 50Ÿ Load RG 200Ÿ RF 402Ÿ RM 67Ÿ 0.1µF + 6.8µF -5V Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Wideband Voltage-Feedback Operation Typical differential input stages used for voltage feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA690 uses a new input stage which places the transconductance element between two input buffers, using their output currents as the forward signal. Figure 36 shows the DC-coupled, gain of 2, dual power supply circuit configuration used as the basis of the ±5 V and Typical Characteristics: VS = ±5 V. For test purposes, the input impedance is set to 50 Ω with a resistor to ground and the output impedance is set to 50 Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins, while output powers (dBm) are at the matched 50-Ω load. For the circuit of Figure 36, the total effective load is 100 Ω || 804 Ω. The disable control line is typically left open to ensure normal amplifier operation. Two optional components are included in Figure 36. An additional resistor (175 Ω) is included in series with the noninverting input. Combined with the 25-Ω DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 200-Ω source resistance seen at the inverting input (see DC Accuracy and Offset Control). In addition to the usual power-supply decoupling capacitors to ground, a 0.1-µF capacitor is included between the two powersupply pins. In practical printed-circuit board (PCB) layouts, this optional-added capacitor typically improves the 2nd-harmonic distortion performance by 3 dB to 6 dB. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 17 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Feature Description (continued) Figure 37 shows the AC-coupled, gain of 2, single-supply circuit configuration which is the basis of the 5 V and Typical Characteristics: 5 V. Though not a rail-to-rail design, the OPA690 requires minimal input and output voltage headroom compared to other very wideband voltage-feedback op amps. It delivers a 3-VPP output swing on a single 5-V supply with > 150-MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 37 establishes an input midpoint bias using a simple resistive divider from the 5-V supply (two 698-Ω resistors). The input signal is then AC-coupled into the midpoint voltage bias. The input voltage can swing to within 1.5 V of either supply pin, giving a 2-VPP input signal range centered between the supply pins. The input impedance matching resistor (59 Ω) used for testing is adjusted to give a 50-Ω input load when the parallel combination of the biasing divider network is included. +5V 0.1mF +5V +VS 6.8mF + + 0.1mF 50W Source VI 50W Source 175W 50W 6.8mF 698W DIS VO 50W VI OPA690 0.1mF 0.1mF 50W Load 59W 50W 698W DIS VO OPA690 100W VS/2 RF 402W RF 402W RG 402W RG 402W + 6.8mF 0.1mF 0.1mF -5V Figure 36. DC-Coupled, G = 2, Bipolar-Supply Specification and Test Circuit Figure 37. AC-Coupled, G = 2, Single-Supply Specification and Test Circuit Again, an additional resistor (50 Ω in this case) is included directly in series with the noninverting input. This minimum recommended value provides part of the dc source resistance matching for the noninverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies (> 500 MHz) using the input parasitic capacitance to form a bandlimiting pole. The gain resistor (RG) is ACcoupled, giving the circuit a DC gain of 1, which puts the input DC bias voltage (2.5 V) at the output as well. The output voltage can swing to within 1 V of either supply pin while delivering > 100-mA output current. A demanding 100-Ω load to a midpoint bias is used in this characterization circuit. The new output stage circuit used in the OPA690 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown in the 5-V supply, 3rd-harmonic distortion plots. 8.3.2 Bandwidth Versus Gain: Noninverting Operation Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the gain bandwidth product (GBP) shown in the Electrical Characteristics: VS = ±5 V. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) predicts the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most amplifiers exhibit a more complex response with lower phase margin. The OPA690 is compensated to give a slightly peaked response in a noninverting gain of 2 (see Figure 36). This results in a typical gain of 2 bandwidth of 220 MHz, far exceeding that predicted by dividing the 300 MHz GBP by 2. Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of 10, the 30-MHz bandwidth shown in Electrical Characteristics: VS = ±5 V agrees with that predicted using the simple formula and the typical GBP of 300 MHz. 18 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Feature Description (continued) The frequency response in a gain of 2 may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5. One way to do this, without affecting the 2 signal gain, is to add an 804-Ω resistor across the two inputs in the circuit of Figure 36. A similar technique may be used to reduce peaking in unity-gain (voltage follower) applications. For example, by using a 402-Ω feedback resistor along with a 402-Ω resistor across the two op amp inputs, the voltage follower response is similar to the gain of 2 response of Figure 37. Reducing the value of the resistor across the op amp inputs further limits the frequency response due to increased noise gain. The OPA690 exhibits minimal bandwidth reduction going to single-supply (5 V) operation as compared with ±5 V. This is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. 8.3.3 Inverting Amplifier Operation Because the OPA690 is a general-purpose, wideband voltage-feedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. Figure 38 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 36 are retained in an inverting circuit configuration. +5V + 0.1µF 6.8µF 0.1µF DIS RB 146Ÿ 50Ÿ OPA690 50Ÿ Load RG 200Ÿ Source RO 50Ÿ RF 402Ÿ RM 67Ÿ 0.1µF + 6.8µF -5V Copyright © 2016, Texas Instruments Incorporated Figure 38. Gain of –2 Example Circuit In the inverting configuration, three key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long PCB trace, or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of 2, setting RG to 50 Ω for input matching eliminates the requirement for RM but requires a 100-Ω feedback resistor. This has the interesting advantage that the noise gain becomes equal to 2 for a 50-Ω source impedance—the same as the noninverting circuits considered in the previous section. The amplifier output, however, now sees the 100-Ω feedback resistor in parallel with the external load. In general, the feedback resistor must be limited to the 200-Ω to 1.5-kΩ range. In this case, it is preferable to increase both the RF and RG values, as shown in Figure 38, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 19 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Feature Description (continued) The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 38, the RM value combines in parallel with the external 50-Ω source impedance, yielding an effective driving impedance of 50 Ω || 67 Ω = 28.6 Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 2.8 for Figure 38, as opposed to only 2 if RM could be eliminated as discussed above. Therefore, the bandwidth is slightly lower for the gain of ±2 circuit of Figure 38 than for the gain of 2 circuit of Figure 36. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input (RB). If this resistor is set equal to the total DC resistance looking out of the inverting node, the output DC error, due to the input bias currents, is reduced to (Input Offset Current) × RF. If the 50-Ω source impedance is DC-coupled in Figure 38, the total resistance to ground on the inverting input is 228 Ω. Combining this in parallel with the feedback resistor gives the RB = 146 Ω used in this example. To reduce the additional high-frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB < 350 Ω, the capacitor is not required because the total noise contribution of all other terms is less than that of the op amp input noise voltage. As a minimum, the OPA690 requires an RB value of 50 Ω to damp out parasitic-induced peaking which is a direct short to ground on the noninverting input runs the risk of a very high-frequency instability in the input stage. 8.3.4 Output Current and Voltage The OPA690 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic op amp. Under no-load conditions at 25°C, the output voltage typically swings closer than 1 V to either supply rail; the specified swing limit is within 1.2 V of either rail. Into a 15-Ω load (the minimum tested load), it delivers more than ±160 mA. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V-I product, which is more relevant to circuit operation. Refer to Figure 19, the Output Voltage and Current Limitations plot in Typical Characteristics: VS = ±5 V. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA690 output drive capabilities, noting that the graph is bounded by a safe operating area of 1-W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA690 can drive ±2.5 V into 25 Ω or ±3.5 V into 50 Ω without exceeding the output capabilities or the 1-W dissipation limit. A 100-Ω load line (the standard test circuit load) shows the full ±3.9-V output swing capability, as shown in Typical Characteristics: VS = ±5 V. The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in Electrical Characteristics: VS = ±5 V. As the output transistors deliver power, their junction temperatures increase, decreasing their VBEs (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current is always greater than that shown in the overtemperature specifications because the output stage junction temperatures is higher than the minimum specified operating ambient. To protect the output stage from accidental shorts to ground and the power supplies, output short-circuit protection is included in the OPA690. The circuit acts to limit the maximum source or sink current to approximately 250 mA. 8.3.5 Driving Capacitive Loads One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA690 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier's open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. 20 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Feature Description (continued) The typical characteristics show the recommended RS versus capacitive load (Figure 15 for ±5 V and Figure 30 for 5 V) and the resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA690. Long PCB traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA690 output pin (see Layout Guidelines). The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA690 operating in a gain of 2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain reduces the peaking as described previously. The circuit of Figure 39 demonstrates this technique, allowing lower values of RS to be used for a given capacitive load. +5V 50Ÿ 175Ÿ 50Ÿ Power-supply decoupling not shown. R RNG VO OPA690 CL 402Ÿ 402Ÿ -5V Copyright © 2016, Texas Instruments Incorporated Figure 39. Capacitive Load Driving With Noise Gain Tuning This gain of 2 circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique reduces the required RS resistor for a given capacitive load, it does increase the noise at the output. It also decreases the loop gain, slightly decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high RS value, significant dynamic range improvement can be achieved using this technique. Figure 40 shows the required RS versus CLOAD parametric on noise gain using this technique. This is the circuit of Figure 39 with RNG adjusted to increase the noise gain (increasing the phase margin) then sweeping CLOAD and finding the required RS to get a flat frequency response. This plot also gives the required RS versus CLOAD for the OPA690 operated at higher signal gains. 100 90 80 RS (W) 70 NG = 2 60 50 40 30 20 NG = 3 10 NG = 4 0 1 10 100 1000 Capacitive Load (pF) Figure 40. Required RS vs Noise Gain Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 21 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Feature Description (continued) 8.3.6 Distortion Performance The OPA690 provides good distortion performance into a 100-Ω load on ±5-V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single 5-V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the noninverting configuration (see Figure 36), this is sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply-decoupling capacitor (0.1 µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3 dB to 6 dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The new output stage used in the OPA690 actually holds the difference between fundamental power and the 2nd- and 3rdharmonic powers relatively constant with increasing output power until very large output swings are required (> 4 VPP). This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rdorder spurious levels are moderately low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics: VS = ±5 V show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20 MHz, with 10 dBm/tone into a matched 50-Ω load (that is, 2 VPP for each tone at the load, which requires 8 VPP for the overall two-tone envelope at the output pin), Figure 14 shows 47-dBc difference between the test tone powers and the 3rd-order intermodulation spurious powers. This performance improves further when operating at lower frequencies. 8.3.7 Noise Performance High slew rate, unity-gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. The 5.5-nV/√Hz input voltage noise for the OPA690 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 41 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI OPA690 RS EO IBN ERS RF 4kTRS 4kT RG RG 4kTRF IBI 4kT = 1.6E - 20J at 290°K Copyright © 2016, Texas Instruments Incorporated Figure 41. Op Amp Noise Analysis Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 41. EO = ENI2 + (IBNRS)2 + 4kTRS NG2 + (IBIRF)2 + 4kTRFNG (1) Dividing this expression by the noise gain [NG = (1 + RF/RG)] gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 2. 22 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Feature Description (continued) EN = ENI2 + (IBNRS)2 + 4kTRS + IBIRF NG 2 + 4kTRF NG (2) Evaluating these two equations for the OPA690 circuit and component values (see Figure 36) gives a total output spot noise voltage of 12.3 nV/√Hz and a total equivalent input spot noise voltage of 6.1 nV/√Hz. This is including the noise added by the bias current cancellation resistor (175 Ω) on the noninverting input. This total inputreferred spot noise voltage is only slightly higher than the 5.5-nV/√Hz specification for the op amp voltage noise alone. This is the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 300 Ω. Keeping both (RF || RG) and the noninverting input source impedance less than 300 Ω satisfies both noise and frequency response flatness considerations. Because the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 38 is not required. 8.3.8 DC Accuracy and Offset Control The balanced input stage of a wideband voltage-feedback op amp allows good output DC accuracy in a wide variety of applications. The power-supply current trim for the OPA690 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively high input bias current (typically ±8 µA at each input terminal), the close matching between them may be used to reduce the output DC error caused by this current. The total output offset voltage may be considerably reduced by matching the DC source resistances appearing at the two inputs. This reduces the output dc error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 36, and using worst-case 25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: –(NG = noninverting signal gain) ±(NG × VOS(MAX)) ± (RF × IOS(MAX)) = ±(2 × 4 mV) ± (402 Ω × 1 µA) = ±8.4 mV A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques eventually reduce to adding a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input may be considered. However, the DC offset voltage on the summing junction sets up a DC current back into the source that must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, see Figure 42 for one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This ensures that the adjustment circuit has minimal effect on the loop gain and hence, the frequency response. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 23 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Feature Description (continued) +5V Power-supply decoupling not shown. 328Ÿ 0.1 µF OPA690 VO -5V RG 500Ÿ +5V 5kŸ RF 1kŸ VI 20kŸ ±200mV Output Adjustment 10kŸ 0.1 µF 5kŸ VO VI =- RF =- 2 RG -5V Copyright © 2016, Texas Instruments Incorporated Figure 42. DC-Coupled, Inverting Gain of –2, With Offset Adjustment 8.4 Device Functional Modes 8.4.1 Disable Operation The OPA690 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA690 operates normally. To disable, the control pin must be asserted LOW. Figure 43 shows a simplified internal circuit for the disable control feature. +VS 15kW Q1 25kW VDIS 110kW IS Control -VS Figure 43. Simplified Disable Control Circuit 24 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Device Functional Modes (continued) In normal operation, base current to Q1 is provided through the 110-kΩ resistor, while the emitter current through the 15-kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1's emitter. As VDIS is pulled LOW, additional current is pulled through the 15-kΩ resistor, eventually turning on those two diodes (approximately 75 µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0 V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 43. Additional circuitry ensures that turnon time occurs faster than turnoff time (make-before-break). When disabled, the output and input nodes go to a high-impedance state. If the OPA690 is operating at a gain of 1, this shows a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than 1, the total feedback network resistance (RF + RG) appears as the impedance looking back into the output, but the circuit still shows very high forward and reverse isolation. If configured as an inverting amplifier, the input and output is connected through the feedback network resistance (RF + RG) and the isolation is very poor as a result. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 44 shows these glitches for the circuit of Figure 36 with the input signal at 0 V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. 6 4 VDIS 2 Output Voltage (10mV/div) 0 VDIS (2V/div) The transition edge rate (dV/dt) of the DIS control line influences this glitch. For the plot of Figure 44, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1-V/ns maximum slew rate may be achieved by adding a simple RC filter into the DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 1-kΩ series resistor between the logic gate and the DIS input pin provides adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring adequate logic level swing. 30 20 10 Output Voltage 0 VI = 0V -10 -20 -30 Time (20ns/div) Figure 44. Disable or Enable Glitch Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 25 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Optimizing Resistor Values Because the OPA690 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity-gain follower application, the feedback connection must be made with a 25-Ω resistor, not a direct short. This isolates the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, for G > 1 applications, the feedback resistor value must be between 200 Ω and 1.5 kΩ. Below 200 Ω, the feedback network presents additional output loading which can degrade the harmonic distortion performance of the OPA690. Above 1.5 kΩ, the typical parasitic capacitance (approximately 0.2 pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (see Figure 36) to be less than approximately 300 Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2-pF total parasitic on the inverting node, holding RF || RG < 300 Ω keeps this pole above 250 MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. 9.1.2 Thermal Analysis Due to the high output power capability of the OPA690, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature sets the maximum allowed internal power dissipation as described below. In no case must the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD × RθJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies) under the condition in Equation 3. PDL = VS2/(4 × RL) where • RL includes feedback network loading (3) NOTE It is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA690-DBV (6-pin SOT-23 package) in the circuit of Figure 36 operating at the maximum specified ambient temperature of 85°C and driving a grounded 20-Ω load. PD = 10 V × 6.2 mA + 52/(4 × (20 Ω || 804 Ω)) = 382 mW Maximum TJ = 85°C + (0.38 W × 150°C/W) = 142°C 26 Submit Documentation Feedback (4) (5) Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Application Information (continued) Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower tested junction temperatures. The highest possible internal dissipation occurs if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. Figure 19, the output V-I plot shown in Typical Characteristics: VS = ±5 V, include a boundary for 1-W maximum internal power dissipation under these conditions. 9.2 Typical Applications 9.2.1 Single-Supply ADC Interface +5V Power- supply decoupling not shown. 698Ÿ DIS 0.1µF 50Ÿ RS 30Ÿ VI 1VPP 2.5V DC ±1V AC OPA690 59Ÿ 698Ÿ 50pF ADC Input 402Ÿ 402Ÿ 0.1µF RB IB Copyright © 2016, Texas Instruments Incorporated Figure 45. SFDR vs IB Test Circuit 9.2.1.1 Design Requirements Most modern, high performance ADCs (such as the TI ADS8xx and ADS9xx series) operate on a single 5-V (or lower) power supply. It is a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5 MHz. The high slew rate, exceptional output swing, and high linearity of the OPA690 make it an ideal single-supply ADC driver. 9.2.1.2 Detailed Design Procedure The Single-Supply ADC Driver shows one possible (inverting) interface. Figure 45 shows the test circuit of Figure 37 modified for a capacitive (ADC) load and with an optional output pulldown resistor (RB). The OPA690 in the circuit of Figure 45 provides > 200-MHz bandwidth for a 2-VPP output swing. Minimal 3rdharmonic distortion or two-tone, 3rd-order intermodulation distortion is observed due to the very low crossover distortion in the OPA690 output stage. The limit of output spurious-free dynamic range (SFDR) is set by the 2ndharmonic distortion. Without RB, the circuit of Figure 45 measured at 10 MHz shows an SFDR of 57 dBc. This may be improved by pulling additional DC bias current (IB) out of the output stage through the optional RB resistor to ground (the output midpoint is at 2.5 V for Figure 45). Adjusting IB gives the improvement in SFDR shown in Figure 46. SFDR improvement is achieved for IB values up to 5 mA, with worse performance for higher values. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 27 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Typical Applications (continued) 9.2.1.3 Application Curve 70 VO = 2VPP, 10MHz 68 66 SFDR (dBc) 64 62 60 58 56 54 52 50 0 1 2 3 4 5 6 7 8 9 10 Output Pulldown Current (mA) Figure 46. SFDR vs IB 9.2.2 Single-Supply Active Filters +5V 1.87kŸ 0.1mF 137Ÿ 100pF DIS 432Ÿ VI 4VI OPA690 1.87kŸ 150pF 5MHz, 2nd-Order Butterworth Filter 1.5kŸ 500Ÿ 0.1mF Copyright © 2016, Texas Instruments Incorporated Figure 47. Single-Supply, High-Frequency Active Filter 9.2.2.1 Design Requirements The high bandwidth provided by the OPA690, while operating on a single 5-V supply, lends itself well to highfrequency active filter designs. Again, the key additional requirement is to establish the DC operating point of the signal near the supply midpoint for highest dynamic range. See Figure 47 for an example design of a 5-MHz lowpass Butterworth filter using the Sallen-Key topology. Both the input signal and the gain setting resistor are AC-coupled using 0.1-µF blocking capacitors (actually giving band-pass response with the low-frequency pole set to 32 kHz for the component values shown). As discussed for Figure 37, this allows the midpoint bias formed by the two 1.87-kΩ resistors to appear at both the input and output pins. The midband signal gain is set to 4 (12 dB) in this case. The capacitor to ground on the noninverting input is intentionally set larger to dominate input parasitic terms. At a gain of 4, the OPA690 on a single supply shows approximately 80-MHz small- and large-signal bandwidth. The resistor values have been slightly adjusted to account for this limited bandwidth in the amplifier stage. Tests of this circuit show a precise 5MHz, −3-dB point with a maximally flat pass band (above the 32-kHz AC-coupling corner), and a maximum stop band attenuation of 36 dB at the −3-dB bandwidth of 80 MHz of the amplifier. 28 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 Typical Applications (continued) 9.2.2.2 Application Curve 15 Gain (dB) 10 5 0 -5 100k 1M 10M Frequency (Hz) Figure 48. 5-MHz, 2nd-Order Butterworth Filter Response 9.2.3 High-Performance DAC Transimpedance Amplifier 50Ÿ OPA690 High-Speed DAC VO = IO RF RF CF IO CD IO Copyright © 2016, Texas Instruments Incorporated Figure 49. DAC Transimpedance Amplifier 9.2.3.1 Design Requirements High-frequency, direct digital synthesis (DDS) Digital-to-Analog Converters (DACs) require a low-distortion output amplifier to retain their SFDR performance into real-world loads. See Figure 49 for a single-ended output drive implementation. 9.2.3.2 Detailed Design Procedure In this circuit, only one side of the complementary output drive signal is used. Figure 49 shows the signal output current connected into the virtual ground summing junction of the OPA690, which is set up as a transimpedance stage or I-V converter. The unused current output of the DAC is connected to ground. If the DAC requires that its outputs terminate to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the noninverting input of the OPA690. The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance produces a zero in the noise gain for the OPA690 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in the feedback network must be set to Equation 6. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 29 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Typical Applications (continued) 1 = 2pRFCF GBP 4pRFCD (6) Equation 6 gives a closed-loop transimpedance bandwidth, f−3dB, of approximately Equation 7. f-3dB = GBP 2pRFCD where • GBP = gain bandwidth product (Hz) for the OPA690 (7) 9.2.4 High-Power Line Driver +12V 2kŸ 8VPP 50Ÿ 4VPP OPA690 0.1µF 1VPP 50Ÿ Source 2kŸ 50Ÿ 50Ÿ Load 400Ÿ 5pF Copyright © 2016, Texas Instruments Incorporated Figure 50. High-Power Coax Line Driver 9.2.4.1 Design Requirements The large output swing capability of the OPA690 and its high current capability allow it to drive a 50-Ω line with a peak-to-peak signal up to 4 VPP at the load, or 8 VPP at the output of the amplifier using a single 12-V supply. Figure 50 shows such a circuit set for a gain of 8 to the output or 4 to the load. The 5-pF capacitor in the feedback loop provides added bandwidth control for the signal path. 30 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 10 Power Supply Recommendations The OPA690 is principally intended to work in a supply range of ±2.5 V to ±6 V. Good power-supply bypassing is required. Minimize the distance (< 0.1 inch) from the power-supply pins to high frequency, 0.1-µF decoupling capacitors. Often a larger capacitor (2.2 µF is typical) is used along with a high-frequency, 0.1-µF supply decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to ground. If necessary, place the larger capacitors somewhat farther from the device and share these capacitors among several devices in the same area of the PCB. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves second harmonic distortion performance. 11 Layout 11.1 Layout Guidelines Achieving optimum performance with a high-frequency amplifier like the OPA690 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include: 1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board. 2. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-µF decoupling capacitors. At the device pins, the ground and power-plane layout must not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1-µF) across the two power supplies (for bipolar operation) improve 2ndharmonic distortion performance. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequencies, must also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. 3. Careful selection and placement of external components preserve the high-frequency performance of the OPA690. Resistors must be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PCB traces as short as possible. Never use wirewound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, must also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 1.5 kΩ, this parasitic capacitance can add a pole or zero below 500 MHz that can affect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 402-Ω feedback is a good starting point for design. A 25-Ω feedback resistor, rather than a direct short, is suggested for the unity-gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause an additional peaking in the gain of 1 frequency response. 4. Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils or 1.27 mm to 100 mils or 2.54 mm) must be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load (Figure 15 for ±5 V and Figure 30 for 5 V). Low parasitic capacitive loads (< 5 pF) may not require an RS because the OPA690 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 31 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com Layout Guidelines (continued) intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary on board, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA690 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance must be set to match the trace impedance. The high output voltage and current capability of the OPA690 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load (Figure 15 for ±5 V and Figure 30 for 5 V). This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. 5. Socketing a high-speed part like the OPA690 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA690 onto the board. 11.1.1 Input and ESD Protection The OPA690 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 51. +VCC External Pin Internal Circuitry -VCC Figure 51. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in systems with ±15-V supply parts driving into the OPA690), current-limiting series resistors must be added into the two inputs. Keep these resistor values as low as possible, because high values degrade both noise performance and frequency response. 32 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 11.2 Layout Example Ground and power plane exist on inner layers 6 Ground and power plane removed from inner layers Place bypass capacitors close to power pins 2 3 ± Place bypass capacitors close to power pins 1 + Place output resistors close to output pins to minimize parasitic capacitance 5 4 Remove GND and Power plane under pins 1 and 4 to minimize stray PCB capacitance Place input resistor close to pin 4 to minimize stray capacitance Place feedback resistor on the bottom of PCB between pins 4 and 6 Figure 52. OPA690 Layout Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 33 OPA690 SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Macromodels and Applications Support Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA690 is available through the OPA690 product folder under Simulation Models. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal ac performance. 12.1.2 Demonstration Fixtures Two printed-circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA690 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user’s guide. The summary information for these fixtures is shown in Table 1. Table 1. Demonstration Fixtures by Package PRODUCT PACKAGE ORDERING NUMBER LITERATURE NUMBER OPA690ID 8-pin SOIC DEM-OPA-SO-1A SBOU009 OPA690IDBV 6-pin SOT-23 DEM-OPA-SOT-1A SBOU010 The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA690 product folder. 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 34 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 OPA690 www.ti.com SBOS223G – DECEMBER 2001 – REVISED AUGUST 2016 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: OPA690 35 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA690ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 Samples OPA690IDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OAEI Samples OPA690IDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OAEI Samples OPA690IDBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OAEI Samples OPA690IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 Samples OPA690IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 Samples OPA690IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of