OPA725, OPA2725
OPA726, OPA2726
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
Very Low Noise, High-Speed, 12V CMOS
Operational Amplifier
FEATURES
D
D
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D
D
D
D
D
DESCRIPTION
BANDWIDTH: 20MHz
SLEW RATE: 30V/µs
FAST 16-BIT SETTLING TIME
LOW NOISE: 6nV/√Hz (typ) at 100kHz
EXCELLENT CMRR, PSRR, and AOL
RAIL-TO-RAIL OUTPUT
CM RANGE INCLUDES GND
THD+N: 0.0003% (typ) at 1kHz
QUIESCENT CURRENT: 5.5mA/ch (max)
SUPPLY VOLTAGE: 4V to 12V
SHUTDOWN MODE (OPAx726): 6µA/ch
The OPA725 and OPA726 series op amps use a
state-of-the-art 12V analog CMOS process, and combine
outstanding ac performance with low bias current and
excellent CMRR, PSRR, and AOL. The 20MHz
Gain-Bandwidth (GBW) Product is achieved by using a
proprietary and patent-pending output stage design.
These characteristics allow excellent 16-bit settling times
for driving 16-bit Analog-to-Digital converters (ADCs).
Excellent ac characteristics, such as 20MHz GBW, 30V/µs
slew rate and 0.0003% THD+N make the OPA725 and
OPA726 well-suited for communication, high-end audio,
and active filter applications. With a bias current of less
than 200pA, they are well-suited for use as
transimpedance (I/V-conversion) amplifiers for monitoring
optical power in ONET applications.
APPLICATIONS
D
D
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OPTICAL NETWORKING
TRANSIMPEDANCE AMPLIFIERS
INTEGRATORS
ACTIVE FILTERS
A/D CONVERTER BUFFERS
I/V CONVERTER FOR DACs
PORTABLE AUDIO
PROCESS CONTROL
TEST EQUIPMENT
The OPA725 and OPA726 op amps can be used in
single-supply applications from 4V up to 12V, or
dual-supply from ±2V to ±6V. The output swings to within
150mV of the rails, maximizing dynamic range. The
shutdown versions (OPAx726) reduce the quiescent
current to less than 6µA and feature a reference pin for
easy shutdown operation with standard CMOS logic in
dual-supply applications.
OPA725 RELATED PRODUCTS
FEATURES
PRODUCT
10MHz, 16V, 16V/µs, 8.5nV/√Hz at 1kHz
8MHz, 36V, FET Input, 20V/µs, 8.5nV/√Hz at 1kHz
100MHz, 5.5V, Precision Transimpedance Amplifier
500MHz, ±5V, FET Input, 290V/µs, 7nV/√Hz at 100kHz
7MHz, 12V, RRIO, 10V/µs, 30nV/√Hz at 10kHz
16-Bit, 250kSPS, 4-Channel, Parallel Output ADC
TLC080
OPA132
OPA380
OPA656
OPA743
ADS8342
The OPA725 (single) is available in SOT23-5 and SO-8
packages, and the OPA2725 (dual) is available in MSOP-8
and SO-8 packages. The OPA726 (single with shutdown)
is available in MSOP-8 and SO-8. The OPA2726 (dual with
shutdown) is available in MSOP-10. All versions are
specified for operation from −40°C to +125°C.
+5V
+5V
+12V
75Ω
O PA726
λ
VOUT
VIN
±2.5V
OPA725
ADS8342
330pF
−5V
Enable
AIN
16−Bit ADC
Common
−5V
−VB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright 2003−2004, Texas Instruments Incorporated
! !
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
ORDERING INFORMATION
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA725
″
OPA725
″
SOT23-5
″
SO-8
″
DBV
″
D
″
−40°C to +125°C
″
−40°C to +125°C
″
OALI
″
OPA725A
″
OPA725AIDBVT
OPA725AIDBVR
OPA725AID
OPA725AIDR
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
OPA2725
″
OPA2725
″
SO-8
″
MSOP-8
″
D
″
DGK
″
−40°C to +125°C
″
−40°C to +125°C
″
OPA2725A
″
BGM
″
OPA2725AID
OPA2725AIDR
OPA2725AIDGKT
OPA2725AIDGKR
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
OPA726
″
OPA726
″
SO-8
″
MSOP-8
″
D
″
DGK
″
−40°C to +125°C
″
−40°C to +125°C
″
OPA726A
″
BHC
″
OPA726AID
OPA726AIDR
OPA726AIDGKT
OPA726AIDGKR
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
OPA2726
″
MSOP-10
″
DGS
″
−40°C to +125°C
″
BHB
″
OPA2726AIDGST
OPA2726AIDGSR
Tape and Reel, 250
Tape and Reel, 2500
PRODUCT
Non-Shutdown
Shutdown
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
2
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.2V
Signal Input Terminals, Voltage(2) . . . . . . . . . −0.5V to (V+) + 0.5V
Current(2) . . . . . . . . . . . . . . . . . . . ±10mA
Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C
Storage Termperature . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 1000 V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
PIN CONFIGURATIONS
OPA725
OPA726
OPA725
Out
1
V−
2
+IN
3
5
4
NC(1)
1
8
NC(1)
−IN
2
7
+IN
3
V−
4
DGND(2)
1
8
Enable
V+
−IN
2
7
V+
6
OUT
+IN
3
6
OUT
5
NC(1)
V−
4
5
NC(1)
V+
−IN
SOT23−5
SO−8
SO−8, MSOP−8
OPA2725
OUT A
1
−IN A 2
+IN A
3
V−
4
OPA2726
8
A
7
B
V+
OUT A
1
−IN A 2
OUT B
10 V+
A
B
9
OUT B
8
−IN B
6
−IN B
+IN A
3
5
+IN B
V−
4
7
+IN B
DGND(2)
5
6
Enable
SO−8, MSOP−8
MSOP−10
(1) NC denotes no internal connection.
(2) DGND = reference voltage for Enable Reference pin. Voltage on this pin
will be the voltage to which the Enable Reference pin is referenced.
3
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V
Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA725, OPA726, OPA2725, OPA2726
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
OPA725, OPA726
OPA2725, OPA2726
Drift
vs Power Supply
Over Temperature
Channel Separation, DC
INPUT BIAS CURRENT
Input Bias Current
Over Temperature
Input Offset Current
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Voltage Noise Density, f = 10kHz
Input Voltage Noise Density, f = 100kHz
Input Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Over Temperature
CONDITIONS
MIN
VS = ±6V, VCM = 0V
VS = ±6V, VCM = 0V
dVOS/dT
PSRR
VS = ±2V to ±6V, VCM = V−
VS = ±2V to ±6V, VCM = V−
4
UNIT
1.2
1.5
4
30
3
5
mV
mV
µV/°C
µV/V
mV/V
µV/V
100
150
1
IB
30
200
See Typical Characteristics
10
50
IOS
en
en
en
in
VCM
CMRR
VS = ±6V,
VS = ±6V,
VS = ±6V,
VS = ±6V,
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
(V−) ≤ VCM ≤ (V+) − 2V
(V−) ≤ VCM ≤ (V+) − 2V
(V−) ≤ VCM ≤ (V+) − 3V
(V−) ≤ VCM ≤ (V+) − 3V
(V−)
88
84
94
84
(V+) − 2
94
100
pA
pA
µVPP
nV/√Hz
nV/√Hz
fA/√Hz
10
10
6
2.5
INPUT IMPEDANCE
Differential
Common-Mode
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time, 0.1%
0.01%
Overload Recovery Time
Total Harmonic Distortion + Noise
MAX
VOS
Over Temperature
OPEN-LOOP GAIN
Open-Loop Voltage Gain
OPA725, OPA726
Over Temperature
OPA2725, OPA2726
Over Temperature
OPA725, OPA726
Over Temperature
OPA2725, OPA2726
Over Temperature
TYP
V
dB
dB
dB
dB
1011 5
1011 4
Ω pF
Ω pF
120
dB
dB
dB
dB
dB
dB
dB
dB
AOL
RL = 100kΩ, 0.15V < VO < (V+) − 0.15V
RL = 100kΩ, 0.15V < VO < (V+) − 0.15V
RL = 100kΩ, 0.175V < VO < (V+) − 0.175V
RL = 100kΩ, 0.175V < VO < (V+) − 0.175V
RL = 1kΩ, 0.25V < VO < (V+) − 0.25V
RL = 1kΩ, 0.25V < VO < (V+) − 0.25V
RL = 2kΩ, 0.25V < VO < (V+) − 0.25V
RL = 2kΩ, 0.25V < VO < (V+) − 0.25V
110
100
110
100
106
96
106
96
120
116
116
CL = 20pF
GBW
SR
tS
THD+N
G = +1
VS = ±6V, 5V Step, G = +1
VS = ±6V, 5V Step, G = +1
VIN • Gain > VS
VS = ±6V, VOUT = 2VRMS, RL = 600Ω,
G = +1, f = 1kHz
20
30
350
450
50
0.0003
MHz
V/µs
ns
ns
ns
%
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V (continued)
Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA725, OPA726, OPA2725, OPA2726
PARAMETER
OUTPUT
Voltage Output Swing from Rail
OPA725, OPA726
Over Temperature
OPA2725, OPA2726
Over Temperature
OPA725, OPA726
Over Temperature
OPA2725, OPA2726
Over Temperature
Output Current
Short-Circuit Current
Capacitive Load Drive
Open-Loop Output Impedance
ENABLE/SHUTDOWN (OPAx726)
tOFF
tON
Enable Reference (DGND) Voltage Range
VL (shutdown)
VH (amplifier is active)
Input Disable Current
IQSD (per amplifier)
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
Quiescent Current (per amplifier)
Over Temperature
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance
SOT23-5
MSOP-8, MSOP-10, SO-8
CONDITIONS
IOUT
ISC
MIN
RL = 100kΩ, AOL > 110dB
RL = 100kΩ, AOL > 100dB
RL = 100kΩ, AOL > 110dB
RL = 100kΩ, AOL > 100dB
RL = 1kΩ, AOL > 106dB
RL = 1kΩ, AOL > 96dB
RL = 2kΩ, AOL > 106dB
RL = 2kΩ, AOL > 96dB
VS − VOUT < 1V
TYP
MAX
UNIT
100
150
150
175
175
250
250
250
250
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
125
200
200
40
±55
See Typical Characteristics
40
CLOAD
f = 1MHz, IO = 0
5
30
VDGND
V−
(V+) − 2
< VDGND +0.8V
> VDGND +2V
Ref Pin = Enable Pin = V−
VS
VS
IQ
5
6
4
12
3.5 to 13.2
4.3
IO = 0
15
−40
−55
−55
Ω
µs
µs
V
V
V
µA
µA
5.5
6
V
V
mA
mA
125
125
150
°C
°C
°C
qJA
200
150
°C/W
°C/W
5
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
COMMON−MODE REJECTION RATIO vs FREQUENCY
GAIN AND PHASE vs FREQUENCY
180
180
160
160
140
140
100
80
80
60
60
Gain
40
40
20
20
0
0
−20
100
1k
10k
100k
1M
10M
CMRR (dB)
120
Phase
100
10
100
Phase (_)
Gain (dB)
120
120
80
60
40
20
(V−) ≤ VCM ≤ (V+) − 2V
−20
100M
0
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
Frequency (Hz)
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
7
100
VS = ±6V
90
6
80
5
Amplitude (V)
PSRR (dB)
70
60
50
40
30
4
3
Indicates maximum output
for no visible distortion.
2
20
1
10
0
0
100
1k
10k
100k
1M
10M
100M
10M
1M
Frequency (Hz)
CHANNEL SEPARATION vs FREQUENCY
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
140
1000
120
Voltage Noise (nV/√Hz)
Channel Separation (dB)
100k
10k
Frequency (Hz)
100
80
60
40
100
10
20
1k
10k
100k
1M
Frequency (Hz)
6
10M
100M
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
INPUT BIAS CURRENT vs COMMON −MODE VOLTAGE
OFFSET CURRENT vs TEMPERATURE
100k
10k
+125_C
10k
1k
+85_C
100
100
IOS (pA)
+25_ C
10
IB < ±10pA
−10
+25_C
−100
−1k
+85_ C
−10k
0.1
−50
6.5
4.5
3.5
0.01
2.5
1.5
−0.5
−1.5
−2.5
−3.5
−4.5
−5.5
0.5
+125_ C
−100k
−6.5
10
1
5.5
Input Bias Current (pA)
1k
−25
0
25
50
75
100
125
150
Temperature (_ C)
Common−Mode Voltage (V)
OPEN−LOOP GAIN vs TEMPERATURE
POWER−SUPPLY REJECTION RATIO vs TEMPERATURE
140
120
130
RL = 100kΩ
PSRR (dB)
AOL (dB)
120
110
RL = 1kΩ
100
100
80
90
80
−50
−25
60
0
25
50
75
100
125
150
−50
−25
0
100
4
90
3
IQ (mA)
CMRR (dB)
5
80
2
70
1
0
50
75
Temperature (_ C)
50
75
100
125
150
QUIESCENT CURRENT vs TEMPERATURE
COMMON−MODE REJECTION RATIO vs TEMPERATURE
110
(V−) ≤ VCM ≤ (V+) − 2V
60
−50
−25
0
25
25
Temperature (_C)
Temperature (_ C)
100
125
150
−50
−25
0
25
50
75
100
125
150
Temperature (_C)
7
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
SHORT−CIRCUIT CURRENT vs TEMPERATURE
90
4.8
80
4.6
70
Short−Circuit (mA)
I Q per Amplifier (mA)
QUIESCENT CURRENT vs SUPPLY VOLTAGE
5.0
4.4
4.2
4.0
3.8
3.6
Sourcing
60
50
Sinking
40
30
20
3.4
10
3.2
0
3.0
3
4
5
6
7
8
9
10
11
12
13
14
−50
−25
0
SHORT−CIRCUIT CURRENT vs SUPPLY VOLTAGE
75
100
125
6
Sourcing
80
150
−40_ C
4
70
Output Voltage (V)
Short−Circuit Current (mA)
50
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
90
60
Sinking
50
40
30
2
25_C
125_C
0
−2
20
−4
10
−40_C
−6
13.5
12.5
11.5
10.5
9.5
8.5
7.5
6.5
5.5
4.5
3.5
0
0
10
20
30
40
50
60
70
80
Output Current (mA)
Supply Voltage (V)
SETTLING TIME vs GAIN
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
5000
0.01
RL = 600Ω
VOUT = 2Vrms
BW = 80kHz
4500
4000
Settling Time (ns)
THD + Noise (%)
25
Temperature (_ C)
Supply Voltage (V)
0.001
3500
3000
2500
2000
1500
0.01%
1000
0.1%
500
0
0.0001
10
100
1k
Frequency (Hz)
8
10k
100k
1
10
Noninverting Gain (V/V)
100
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
SMALL−SIGNAL OVERSHOOT vs CAPACITIVE LOAD
90
80
Population
60
G = +1
50
40
G = −1
CF = 3pF
30
20
0
10
100
1000
−3.3
−3.0
−2.7
−2.4
−2.1
−1.8
−1.5
−1.2
−0.9
−0.6
−0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
G = +5
CF = 1pF
10
Capacitive Load (pF)
Offset Voltage (mV)
VOLTAGE OFFSET DRIFT PRODUCTION DISTRIBUTION
SMALL−SIGNAL STEP RESPONSE
Typical production distribution
of packaged units.
G = +1
RL = 10kΩ
CL = 20pF
10mV/div
Population
0
2
4
6
8
10
12
14
16
100ns/div
Voltage Offset Drift (µV/_C)
LARGE−SIGNAL STEP RESPONSE
SMALL−SIGNAL STEP RESPONSE
G = +1
RL = 10kΩ
CL = 20pF
CF = 2pF
CF = 3pF
10mV/div
CF = 4pF
1V/div
Overshoot (%)
70
CF
G = −1
RF
10kΩ
10kΩ
O P A 7 25
CL
20pF
400ns/div
200ns/div
9
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
LARGE−SIGNAL STEP RESPONSE
1V/div
CF
4pF
G = −1
RF
10kΩ
10kΩ
OPA725
CL
20pF
400ns/div
10
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
APPLICATIONS INFORMATION
a) Single−Supply Configuration
OPA725 and OPA726 series 20MHz CMOS op amps have
a fast slew rate, low noise, and excellent PSRR, CMRR,
and AOL. These op amps can operate on typically 4.3mA
quiescent current from a single (or split) supply in the range
of 4V to 12V (±2V to ±6V), making them highly versatile
and easy to use. They are stable in a unity-gain
configuration.
Enable
+12V
Digital
Logic
OPA726
VOUT
DGND
Power-supply pins should be bypassed with 1nF ceramic
capacitors in parallel with 1µF tantalum capacitors.
OPERATING VOLTAGE
b) Dual−Supply Configuration
OPA725 series op amps are specified from 4V to 12V
supplies over a temperature range of −40°C to +125°C.
They will operate well in ±5V or +5V to +12V power-supply
systems. Parameters that vary significantly with operating
voltage or temperature are shown in the Typical
Characteristics.
Enable
+5V
Digital
Logic
OPA726
DGND
VOUT
−5V
ENABLE/SHUTDOWN
OPA725 series op amps require approximately 4.3mA
quiescent current. The enable/shutdown feature of the
OPA726 allows the op amp to be shut off to reduce this
current to approximately 6µA.
The enable/shutdown input is referenced to the Enable
Reference Pin, DGND (see Pin Configurations). This pin
can be connected to logic ground in dual-supply op amp
configurations to avoid level-shifting the enable logic
signal, as shown in Figure 1.
The Enable Reference Pin voltage, VDGND, must not
exceed (V+) − 2V. It may be set as low as V−. The amplifier
is enabled when the Enable Pin voltage is greater than
VDGND + 2V. The amplifier is disabled (shutdown) if the
Enable Pin voltage is less than VDGND + 0.8V. The Enable
Pin is connected to internal pull-up circuitry and will enable
the device if left unconnected.
Figure 1. Enable Reference Pin Connection for
Single- and Dual-Supply Configurations
INPUT OVER-VOLTAGE PROTECTION
Device inputs are protected by ESD diodes that will
conduct if the input voltages exceed the power supplies by
more than approximately 300mV. Momentary voltages
greater than 300mV beyond the power supply can be
tolerated if the current is limited to 10mA. This is easily
accomplished with an input resistor in series with the op
amp, as shown in Figure 2. The OPA725 series features
no phase inversion when the inputs extend beyond
supplies, if the input is current limited.
COMMON-MODE VOLTAGE RANGE
V+
IOVERLOAD
The input common-mode voltage range of the OPA725
and OPA726 series extends from V− to (V+) − 2V.
Common-mode rejection is excellent throughout the input
voltage range from V− to (V+) − 3V. CMRR decreases
somewhat as the common-mode voltage extends to
(V+) − 2V, but remains very good and is tested throughout
this range. See the Electrical Characteristics table for
details.
10mA max
R
VOUT
OPA725
VIN
V−
Figure 2. Input Current Protection for Voltages
Exceeding the Supply Voltage
11
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
RAIL-TO-RAIL OUTPUT
A class AB output stage with common-source transistors
is used to achieve rail-to-rail output. This output stage is
capable of driving heavy loads connected to any point
between V+ and V−. For light resistive loads ( > 100kΩ ),
the output voltage can swing to 150mV (175mV for dual)
from the supply rail, while still maintaining excellent
linearity (AOL > 110dB). With 1kΩ (2kΩ for dual) resistive
loads, the output is specified to swing to within 250mV from
the supply rails with excellent linearity (see the Typical
Characteristics curve Output Voltage Swing vs Output
Current).
CAPACITIVE LOAD AND STABILITY
+5V
75Ω
VIN
±2.5V
OPA725
AIN
330pF
−5V
ADS8342
16−Bit ADC
Common
−5V
Figure 4. OPA725 Driving an ADC
TRANSIMPEDANCE AMPLIFIER
Capacitive load drive is dependent upon gain and the
overshoot requirements of the application. Increasing the
gain enhances the ability of the amplifier to drive greater
capacitive loads (see the Typical Characteristics curve
Small-Signal Overshoot vs Capacitive Load).
One method of improving capacitive load drive in the
unity-gain configuration is to insert a 10Ω to 20Ω resistor
inside the feedback loop, as shown in Figure 3. This
reduces ringing with large capacitive loads while
maintaining DC accuracy.
V+
RS
20Ω
VOUT
OPA725
+5V
Wide bandwidth, low input bias current, and low input
voltage and current noise make the OPA725 an ideal
wideband photodiode transimpedance amplifier. Lowvoltage noise is important because photodiode capacitance causes the effective noise gain of the circuit to
increase at high frequency.
The key elements to a transimpedance design, as shown
in Figure 5, are the expected diode capacitance (CD),
which should include the parasitic input common-mode
and differential-mode input capacitance (4pF + 5pF for the
OPA725); the desired transimpedance gain (RF); and the
GBW for the OPA725 (20MHz). With these three variables
set, the feedback capacitor value (CF) can be set to control
the frequency response. CF includes the stray capacitance
of RF, which is 0.2pF for a typical surface-mount resistor.
VIN
CL
RL
CF(1)
< 1pF
Figure 3. Series Resistor in Unity-Gain Buffer
Configuration Improves Capacitive Load Drive
RF
10MΩ
DRIVING FAST 16-BIT ADCs
The OPA725 series is optimized for driving fast 16-bit
ADCs such as the ADS8342. The OPA725 op amps buffer
the converter input capacitance and resulting charge
injection, while providing signal gain. Figure 4 shows the
OPA725 in a single-ended method of interfacing to the
ADS8342 16-bit, 250kSPS, 4-channel ADC with an input
range of ±2.5V. The OPA725 has demonstrated excellent
settling time to the 16-bit level within the 600ns acquisition
time of the ADS8342. The RC filter, shown in Figure 4, has
been carefully tuned for best noise and settling
performance. It may need to be adjusted for different op
amp configurations. Please refer to the ADS8342 data
sheet (available for download at www.ti.com) for additional
information on this product.
12
+5V
λ
CD
OPA725
VOUT
−5V
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
Figure 5. Dual-Supply Transimpedance Amplifier
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To achieve a maximally-flat, 2nd-order Butterworth
frequency response, the feedback pole should be set to:
1
+
2pR FCF
GBW
Ǹ4pR
C
F
(1)
D
Bandwidth is calculated by:
f *3dB +
GBW Hz
Ǹ2pR
C
F
(2)
D
For even higher transimpedance bandwidth, the
high-speed CMOS OPA354 (100MHz GBW), OPA300
(180 MHz GBW), OPA355 (200MHz GBW), or OPA656,
OPA657 (400MHz GBW) may be used.
For single-supply applications, the +IN input can be biased
with a positive dc voltage to allow the output to reach true
zero when the photodiode is not exposed to any light, and
respond without the added delay that results from coming
out of the negative rail. (Refer to Figure 6.) This bias
voltage also appears across the photodiode, providing a
reverse bias for faster operation.
For additional information, refer to Application Bulletin
SBOA055, Compensate Transimpedance Amplifiers
Intuitively, available for download at www.ti.com.
OPTIMIZING THE TRANSIMPEDANCE
CIRCUIT
To achieve the best performance, components should be
selected according to the following guidelines:
1.
For lowest noise, select RF to create the total required
gain. Using a lower value for RF and adding gain after
the transimpedance amplifier generally produces
poorer noise performance. The noise produced by RF
increases with the square-root of RF, whereas the
signal increases linearly. Therefore, signal-to-noise
ratio is improved when all the required gain is placed
in the transimpedance stage.
2.
Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting input).
This capacitance causes the voltage noise of the op
amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to
reverse-bias a photodiode can significantly reduce its
capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a small
photodiode.
3.
Noise increases with increased bandwidth. Limit the
circuit bandwidth to only that required. Use a capacitor
across the RF to limit bandwidth, even if not required
for stability.
4.
Circuit board leakage can degrade the performance of
an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that
encircles the summing junction and is driven at the
same voltage can help control leakage.
CF(1)
< 1pF
RF
10MΩ
V+
λ
OPA725
VOUT
+VBias
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
For additional information, refer to the Application Bulletins
Noise Analysis of FET Transimpedance Amplifiers
(SBOA060), and Noise Analysis for High-Speed Op Amps
(SBOA066), available for download at the TI web site.
Figure 6. Single-Supply Transimpedance
Amplifier
13
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
C3
2.2nF
C1
1nF
R1
1.93kΩ
R2
15.9kΩ
1/2
OPA2725
C2
330pF
R3
2.07kΩ
R4
22.3kΩ
1/2
OPA2725
VOUT
C4
100pF
DC Gain = 1
Cutoff Frequency = 50kHz
NOTE: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The program can be used
to determine component values for other cutoff frequencies or filter types.
Figure 7. Four-Pole Butterworth Sallen-Key Low-Pass Filter
14
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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