OPA728

OPA727, OPA2727 OPA4727, OPA728 SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 e-trim 20MHz, High Precision CMOS Operational Amplifier FEATURES D D D D D D D D D D D D D D D D D D D OFFSET: 15µV (typ), 150µV (max) DRIFT: 0.3µV/°C (typ), 1.5µV/°C (max) BANDWIDTH: 20MHz SLEW RATE: 30V/µs BIAS CURRENT: 100pA (max) LOW NOISE: 6nV/√Hz at 100kHz THD+N: 0.0003% at 1kHz QUIESCENT CURRENT: 4.3mA/ch SUPPLY VOLTAGE: 4V to 12V SHUTDOWN MODE (OPA728): 6µA OPTICAL NETWORKING TRANSIMPEDANCE AMPLIFIERS INTEGRATORS ACTIVE FILTERS A/D CONVERTER DRIVERS I/V CONVERTER FOR DACs HIGH PERFORMANCE AUDIO PROCESS CONTROL TEST EQUIPMENT DESCRIPTION The OPA727 and OPA728 series op amps use a state-of-the-art 12V analog CMOS process and e-trim, a package-level trim, offering outstanding dc precision and ac performance. The extremely low offset (150µV max) and drift (1.5µV/°C) are achieved by trimming the IC digitally after packaging to avoid the shift in parameters as a result of stresses during package assembly. To correct for offset drift, the OPA727/OPA728 family is trimmed over temperature. The devices feature very high CMRR and open loop gain to minimize errors. Excellent ac characteristics, such as 20MHz GBW, 30V/µs slew rate and 0.0003% THD+N make the OPA727 and OPA728 well-suited for communication, high-end audio, and active filter applications. With a bias current of less than 100pA, they are ideal for use as transimpedance (I/V-conversion) amplifiers for monitoring optical power in ONET applications. Optimized for single-supply operation up to 12V, the input common-mode range extends to GND for true single-supply functionality. The output swings to within 150mV of the rails, maximizing dynamic range. The low quiescent current of 4.3mA makes it well-suited for use in battery-operated equipment. The OPA728 shutdown version reduces the quiescent current to typically 6µA and features a reference pin for easy shutdown operation with standard CMOS logic in dual-supply applications. For ease of use, the OPA727 and OPA728 op amp families are fully specified and tested over the supply range of 4V to 12V. The OPA727 (single) and OPA728 (single with shutdown) are available in MSOP-8 and DFN-8; the OPA2727 (dual) is available in DFN-8 and SO-8, and the quad version OPA4727 will be available Q1’05 in TSSOP-14. All versions are specified for operation from −40°C to +125°C. APPLICATIONS OPAx727 AND OPAx728 RELATED PRODUCTS FEATURES 20MHz, 3mV, 4µV/°C (non-etrim version of OPA727) 20MHz, 3mV, 4µV/°C, Shutdown (non-etrim version of OPA728) PRODUCT OPA725 OPA726 +12V λ OPA727 VOUT − VB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. e-trim is a trademark of Texas Instruments, Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2004, Texas Instruments Incorporated www.ti.com OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 PACKAGE/ORDERING INFORMATION(1) PRODUCT Non-Shutdown OPA727 OPA2727 OPA2727 OPA4727(2) Shutdown OPA728 MSOP-8 DFN-8 DGK DRB AUF NSG MSOP-8 DFN-8 DFN-8(2) SO-8 TSSOP-14 DGK DRB DRB D PW AUE NSF NSD OPA2727A OPA4727A PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet. (2) Available Q1’05. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.2V Signal Input Terminals, Voltage(2) . . . . . . . . . −0.5V to (V+) + 0.5V Current(2) . . . . . . . . . . . . . . . . . . . ±10mA Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 2000V (Charged Device Model) . . . . . . . . . . . . . . . . . 1000V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. (3) Short-circuit to ground, one amplifier per package. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 2 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 PIN CONFIGURATIONS OPA727 NC(1) − IN +IN V− 1 2 3 4 MSOP−8 8 7 6 5 NC(1) V+ OUT NC(1) NC (1 ) − IN +IN V− OPA727 1 2 3 4 8 NC (1 ) 7 V+ 6 OUT 5 NC (1 ) Exposed Thermal Die Pad on Underside(2 ) DFN−8 OPA728 REF(3) − IN +IN V− 1 2 3 4 MSOP−8 8 7 6 5 Enable V+ OUT NC(1) REF (3) − IN +IN V− OPA728 1 2 3 4 8 Enable 7 V+ 6 OUT 5 NC (1) Exposed Thermal Die Pad on Underside(2) DFN−8 OPA2727 OUT A − IN A +IN A V− 1 2 3 4 SO−8 A B 8 7 6 5 V+ OUT B − IN B +IN B OUT A − IN A +IN A V− OPA2727(4) 1 2 3 4 8 V+ 7 OUT B 6 − IN B 5 +IN B Exposed Thermal Die Pad on Underside(2) DFN−8 OPA4727(4) OUT A 1 A B 14 OUT D 13 − IN D 12 +IN D 11 V+ 10 +IN C A B 9 8 TSSOP−14 − IN C OUT C − IN A 2 +IN A V− +IN B 3 4 5 (1) NC denotes no internal connection. (2) Connect thermal die pad to V−. (3) REF is the reference voltage for ENABLE pin. (4) Available Q1’05. − IN B 6 OUT B 7 3 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V Boldface limits apply over the specified temperature range, TA = −40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. OPA727, OPA728, OPA2727 PARAMETER OFFSET VOLTAGE Input Offset Voltage Drift vs Power Supply Over Temperature Channel Separation, dc INPUT BIAS CURRENT Input Bias Current, OPA727, OPA728 Input Bias Current, OPA2727 Over Temperature Input Offset Current NOISE Input Voltage Noise, f = 0.1Hz to 10Hz Input Voltage Noise Density, f = 10kHz Input Voltage Noise Density, f = 100kHz Input Current Noise Density, f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio Over Temperature Over Temperature INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain OPA727, OPA728 Over Temperature OPA2727 Over Temperature OPA727, OPA728 Over Temperature OPA2727 Over Temperature FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time, 0.1% 0.01% Overload Recovery Time Total Harmonic Distortion + Noise AOL RL = 100kΩ, 0.15V < VO < (V+) − 0.15V RL = 100kΩ, 0.15V < VO < (V+) − 0.15V RL = 100kΩ, 0.175V < VO < (V+) − 0.175V CONDITIONS VOS dVOS/dT PSRR VS = ±5V, VCM = 0V 0°C to +85°C −40°C to +125°C VS = ±2V to ±6V, VCM = V− VS = ±2V to ±6V, VCM = V− MIN TYP 15 0.3 0.6 30 1 MAX 150 1.5 3.0 150 150 UNIT µV µV/°C µV/°C µV/V µV/V µV/V pA pA pA µVPP nV/√Hz nV/√Hz fA/√Hz IB IOS en en en in VCM CMRR VS = ±6V, VS = ±6V, VS = ±6V, VS = ±6V, VCM = 0V VCM = 0V VCM = 0V VCM = 0V ±10 ±100 ±60 ±500 See Typical Characteristics ±10 ±100 10 10 6 2.5 (V−) 86 84 94 84 (V+) − 2.5 94 100 (V−) ≤ VCM ≤ (V+) − 2.5V (V−) ≤ VCM ≤ (V+) − 2.5V (V−) ≤ VCM ≤ (V+) − 3V (V−) ≤ VCM ≤ (V+) − 3V V dB dB dB dB Ω pF Ω pF 1011 5 1011 4 RL = 100kΩ, 0.175V < VO < (V+) − 0.175V RL = 1kΩ, 0.25V < VO < (V+) − 0.25V RL = 1kΩ, 0.25V < VO < (V+) − 0.25V RL = 2kΩ, 0.25V < VO < (V+) − 0.25V RL = 2kΩ, 0.5V < VO < (V+) − 0.5V CL = 20pF GBW SR tS G = +1 VS = ±6V, 5V Step, G = +1 VS = ±6V, 5V Step, G = +1 VIN • Gain > VS VS = ±6V, VOUT = 2VRMS, RL = 600Ω, G = +1, f = 1kHz 110 100 110 100 106 96 106 96 120 120 116 116 dB dB dB dB dB dB dB dB MHz V/µs ns ns ns % THD+N 20 30 350 450 50 0.0003 4 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V (continued) Boldface limits apply over the specified temperature range, TA = −40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. OPA727, OPA728, OPA2727 PARAMETER OUTPUT Voltage Output Swing from Rail OPA727, OPA728 Over Temperature OPA2727 Over Temperature OPA727, OPA728 Over Temperature OPA2727 Over Temperature Output Current Short-Circuit Current Capacitive Load Drive Open-Loop Output Impedance CONDITIONS MIN TYP MAX UNIT IOUT ISC CLOAD RL = 100kΩ, AOL > 110dB RL = 100kΩ, AOL > 100dB RL = 100kΩ, AOL > 110dB RL = 100kΩ, AOL > 100dB RL = 1kΩ, AOL > 106dB RL = 1kΩ, AOL > 96dB RL = 2kΩ, AOL = 106dB RL = 2kΩ, AOL = 96dB  VS − VOUT < 1V 100 125 200 200 150 150 175 175 250 250 250 500 f = 1MHz, IO = 0 40 ±55 See Typical Characteristics 40 5 80 V− > VDGND +2V (V+) − 2 < VDGND+0.8V 5 6 4 mV mV mV mV mV mV mV mV mA mA Ω µs µs V V V pA µA V V mA mA °C °C °C °C/W °C/W °C/W ENABLE/SHUTDOWN (OPA728) tOFF tON Enable Reference (Ref Pin) Voltage Range VL (amplifier is disabled) VH (amplifier is enabled) Input Bias Current of Enable Pin IQSD POWER SUPPLY Specified Voltage Range Operating Voltage Range Quiescent Current (per amplifier) Over Temperature TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance MSOP-8, SO-8 TSSOP-14 DFN-8 VS VS IQ Amplifier Disabled 15 12 IO = 0 3.5 to 13.2 4.3 6.5 6.5 +125 +125 +150 −40 −55 −55 qJA 150 100 46 5 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. GAIN AND PHASE vs FREQUENCY 180 160 140 120 Gain (dB) 100 80 60 40 20 0 − 20 10 100 1k 10k 100k 1M 10M Frequency (Hz) Gain Phase 180 160 140 120 100 80 60 40 20 0 − 20 100M CMRR (dB) Phase (_ ) COMMON−MODE REJECTION RATIO vs FREQUENCY 120 100 80 60 40 20 (V− ) ≤ VCM ≤ (V+) − 2V 0 10 100 1k 10k 100k 1M 10M Frequency (Hz) POWER−SUPPLY REJECTION RATIO vs FREQUENCY 100 90 80 Amplitude (V) 70 PSRR (dB) 60 50 40 30 20 10 0 100 1k 10k 100k Frequency (Hz) 1M 10M 100M 0 10k 5 4 3 2 1 7 MAXIMUM OUTPUT VOLTAGE vs FREQUENCY VS = ± 6V 6 Indicates maximum output for no visible distortion. 100k Frequency (Hz) 1M 10M CHANNEL SEPARATION vs FREQUENCY 140 120 100 80 60 40 20 1k 10k 100k 1M 10M 100M 1 10 Voltage Noise (nV/√ Hz) 1000 INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY Channel Separation (dB) 100 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) 6 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. INPUT BIAS CURRENT vs COMMON−MODE VOLTAGE 100k 10k Input Bias Current (pA) 1k 100 10 − 10 − 100 − 1k − 10k −100k −6 +25_ C +85_ C +125_ C −4 −2 0 2 4 6 IB < ± 10pA +25_ C IOS (pA) +125_ C +85_ C OFFSET CURRENT vs TEMPERATURE 10k 1k 100 10 1 0.1 0.01 − 50 − 25 0 25 50 75 100 125 150 Temperature (_ C) Common−Mode Voltage (V) OPEN−LOOP GAIN vs TEMPERATURE 140 130 120 AOL (dB) 110 100 90 80 − 50 60 0 25 50 75 100 125 150 Temperature (_ C) RL = 1kΩ 120 POWER−SUPPLY REJECTION RATIO vs TEMPERATURE RL = 100kΩ PSRR (dB) 100 80 − 25 − 50 − 25 0 25 50 75 100 125 150 Temperature (_ C) COMMON−MODE REJECTION RATIO vs TEMPERATURE 110 QUIESCENT CURRENT vs TEMPERATURE 5 100 CMRR (dB) 4 90 IQ (mA) 3 80 2 70 (V− ) ≤ VCM ≤ (V+) − 2V 60 − 50 − 25 0 25 1 0 50 75 100 125 150 − 50 − 25 0 25 50 75 100 125 150 Temperature (_ C) Temperature (_ C) 7 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. QUIESCENT CURRENT vs SUPPLY VOLTAGE 5.0 4.8 4.6 I Q per Amplifier (mA) 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 3 4 5 6 7 8 9 10 11 12 13 14 Supply Voltage (V) Short− Circuit (mA) SHORT−CIRCUIT CURRENT vs TEMPERATURE 90 80 70 60 50 Sinking 40 30 20 10 0 − 50 − 25 0 25 50 75 100 125 150 Sourcing Temperature (_ C) SHORT−CIRCUIT CURRENT vs SUPPLY VOLTAGE 90 80 Short− Circuit Current (mA) 70 60 50 40 30 20 10 0 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 −4 −6 0 Sinking Output Voltage (V) Sourcing 6 4 2 OUTPUT VOLTAGE SWING vs OUTPUT CURRENT − 40_ C 125_ C 0 −2 25_ C − 40_ C 10 20 30 40 50 60 70 80 Supply Voltage (V) Output Current (mA) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.01 RL = 600Ω VOUT = 2Vrms BW = 80kHz Settling Time (ns) SETTLING TIME vs GAIN 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0.1% 0.01% THD + Noise (%) 0.001 0.0001 10 100 1k Frequency (Hz) 10k 100k 0 1 10 Noninverting Gain (V/V) 100 8 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. SMALL− SIGNAL OVERSHOOT vs CAPACITIVE LOAD 90 80 70 Overshoot (%) G = +1 Population 60 50 40 30 20 10 0 10 100 Capacitive Load (pF) 1000 G = −1 CF = 3pF G = +5 CF = 1pF OFFSET VOLTAGE PRODUCTION DISTRIBUTION VS = ± 5V OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION (0_ C to +85_ C) VS = ± 5V Population 0 0 .1 0.2 0.3 0 .4 0.5 0 .6 0 .7 0 .8 0.9 1.0 1.1 1 .2 1 .3 1.4 1.5 Population Offset Voltage Drift (µ V/_ C) OFFSET VOLTAGE vs TEMPERATURE 300 200 Offset Voltage (µ V) 100 0 − 100 − 200 5 Representative Units Shown − 300 − 50 − 25 0 25 50 75 100 125 4σ 10mV/div VS = ± 5V 4σ Temperature (_ C) −150 −140 −130 −120 −110 −100 − 90 − 80 − 70 − 60 − 50 − 40 − 30 − 20 − 10 0 10 20 30 40 50 60 70 80 90 10 0 11 0 12 0 13 0 14 0 15 0 Offset Voltage (µV) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION (− 40_ C to +125_ C) VS = ± 5V 0 0.2 0.4 0.6 0.8 1.0 1.2 1 .4 1.6 1.8 2.0 2 .2 2.4 2 .6 2.8 3.0 Offset Voltage Drift (µ V/ _ C) SMALL− SIGNAL STEP RESPONSE G = +1 RL = 10kΩ CL = 20pF 100ns/div 9 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. LARGE−SIGNAL STEP RESPONSE G = +1 RL = 10kΩ CL = 20pF 10mV/div CF = 2pF SMALL− SIGNAL STEP RESPONSE CF = 3pF CF = 4pF 1V/div CF RF 10kΩ 10kΩ O P A 7 27 G = −1 CL 20pF 400ns/div 200ns/div LARGE−SIGNAL STEP RESPONSE 1V/div CF 4pF RF Ω 10 kΩ 10kΩ OPA727 G = −1 CL 20pF 400ns/div 10 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 APPLICATIONS INFORMATION The OPA727 and OPA728 family of op amps use e-trim, an adjustment to offset voltage and temperature drift made during the final steps of manufacturing after the plastic molding is completed. This compensates for performance shifts that can occur during the molding process. Through e-trim, the OPA727 and OPA728 deliver excellent offset voltage (150µV max) and extremely low offset voltage drift (1.5µV/°C). Additionally, these 20MHz CMOS op amps have a fast slew rate, low noise, and excellent PSRR, CMRR, and AOL. They can operate on typically 4.3mA quiescent current from a single (or split) supply in the range of 4V to 12V (±2V to ±6V), making them highly versatile and easy to use. They are stable in a unity-gain configuration. Power-supply pins should be bypassed with 1nF ceramic capacitors in parallel with 1µF tantalum capacitors. a) Single− Supply Configuration Enable +12V Digital Logic OPA728 VO Ref DGND b) Dual− Supply Configuration Enable Digital Logic OPA728 +5V OPERATING VOLTAGE OPA727 series op amps are specified from 4V to 12V supplies over a temperature range of −40°C to +125°C. They will operate well in ±5V or +5V to +12V power-supply systems. Parameters that vary significantly with operating voltage or temperature are shown in the Typical Characteristics. DGND VO Ref − 5V ENABLE/SHUTDOWN OPA727 series op amps require approximately 4.3mA quiescent current. The enable/shutdown feature of the OPA728 allows the op amp to be shut off to reduce this current to approximately 6µA. The enable/shutdown input is referenced to the Enable Reference Pin, DGND (see Pin Configurations). This pin can be connected to logic ground in dual-supply op amp configurations to avoid level-shifting the enable logic signal, as shown in Figure 1. The Enable Reference Pin voltage, VDGND, must not exceed (V+) − 2V. It may be set as low as V−. The amplifier is enabled when the Enable Pin voltage is greater than VDGND + 2V. The amplifier is disabled (shutdown) if the Enable Pin voltage is less than VDGND + 0.8V. The Enable Pin is connected to internal pull-up circuitry and will enable the device if left unconnected. Figure 1. Enable Reference Pin Connection for Single- and Dual-Supply Configurations INPUT OVER-VOLTAGE PROTECTION Device inputs are protected by ESD diodes that will conduct if the input voltages exceed the power supplies by more than approximately 300mV. Momentary voltages greater than 300mV beyond the power supply can be tolerated if the current is limited to 10mA. This is easily accomplished with an input resistor in series with the op amp, as shown in Figure 2. The OPA727 series features no phase inversion when the inputs extend beyond supplies, if the input is current limited. V+ COMMON-MODE VOLTAGE RANGE The input common-mode voltage range of the OPA727 and OPA728 series extends from V− to (V+) − 2.5V. Common-mode rejection is excellent throughout the input voltage range from V− to (V+) − 3V. CMRR decreases somewhat as the common-mode voltage extends to (V+) − 2.5V, but remains very good and is tested throughout this range. See the Electrical Characteristics table for details. VIN I OVERLOAD 10mA max R OPA727 VOUT V− Figure 2. Input Current Protection for Voltages Exceeding the Supply Voltage 11 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 RAIL-TO-RAIL OUTPUT A class AB output stage with common-source transistors is used to achieve rail-to-rail output. This output stage is capable of driving heavy loads connected to any point between V+ and V−. For light resistive loads ( > 100kΩ ), the output voltage can swing to 150mV from the supply rail, while still maintaining excellent linearity (AOL > 110dB). With 1kΩ resistive loads, the output is specified to swing to within 250mV from the supply rails with excellent linearity (see the Typical Characteristics curve, Output Voltage Swing vs Output Current). +5V 75Ω VIN ±2.5V OPA727 AIN ADS8342 16− ADC Bit Common +5V 330pF −5V −5V Figure 4. OPA727 Driving an ADC CAPACITIVE LOAD AND STABILITY Capacitive load drive is dependent upon gain and the overshoot requirements of the application. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads (see the Typical Characteristics curve, Small-Signal Overshoot vs Capacitive Load). One method of improving capacitive load drive in the unity-gain configuration is to insert a 10Ω to 20Ω resistor inside the feedback loop, as shown in Figure 3. This reduces ringing with large capacitive loads while maintaining DC accuracy. TRANSIMPEDANCE AMPLIFIER Wide bandwidth, low input bias current, and low input voltage and current noise make the OPA727 an ideal wideband photodiode transimpedance amplifier. Lowvoltage noise is important because photodiode capacitance causes the effective noise gain of the circuit to increase at high frequency. The key elements to a transimpedance design, as shown in Figure 5, are the expected diode capacitance (CD), which should include the parasitic input common-mode and differential-mode input capacitance (4pF + 5pF for the OPA727); the desired transimpedance gain (RF); and the GBW for the OPA727 (20MHz). With these three variables set, the feedback capacitor value (CF) can be set to control the frequency response. CF includes the stray capacitance of RF, which is 0.2pF for a typical surface-mount resistor. V+ RS 20Ω OPA727 VOUT CL RL VIN CF(1) < 1pF Figure 3. Series Resistor in Unity-Gain Buffer Configuration Improves Capacitive Load Drive DRIVING FAST 16-BIT ADCs The OPA727 series is optimized for driving fast 16-bit ADCs such as the ADS8342. The OPA727 op amps buffer the converter input capacitance and resulting charge injection, while providing signal gain. Figure 4 shows the OPA727 in a single-ended method of interfacing to the ADS8342 16-bit, 250kSPS, 4-channel ADC with an input range of ±2.5V. The OPA727 has demonstrated excellent settling time to the 16-bit level within the 600ns acquisition time of the ADS8342. The RC filter, shown in Figure 4, has been carefully tuned for best noise and settling performance. It may need to be adjusted for different op amp configurations. Please refer to the ADS8342 data sheet (available for download at www.ti.com) for additional information on this product. RF 10MΩ +5V λ CD OPA727 VOUT − 5V NOTE: (1) CF is optional to prevent gain peaking. It includes the stray capacitance of RF. Figure 5. Dual-Supply Transimpedance Amplifier 12 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 To achieve a maximally-flat, 2nd-order Butterworth frequency response, the feedback pole should be set to: 1 + 2pR FCF Bandwidth is calculated by: GBW 4pR FC D For additional information, refer to Application Bulletin SBOA055, Compensate Transimpedance Amplifiers Intuitively, available for download at www.ti.com. (1) OPTIMIZING THE TRANSIMPEDANCE CIRCUIT To achieve the best performance, components should be selected according to the following guidelines: 1. For lowest noise, select RF to create the total required gain. Using a lower value for RF and adding gain after the transimpedance amplifier generally produces poorer noise performance. The noise produced by RF increases with the square-root of RF, whereas the signal increases linearly. Therefore, signal-to-noise ratio is improved when all the required gain is placed in the transimpedance stage. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high frequency). Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce its capacitance. Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small photodiode. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor across the RF to limit bandwidth, even if not required for stability. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same voltage can help control leakage. f *3dB + GBW Hz 2pRFC D (2) For even higher transimpedance high-speed CMOS OPA380 (90MHz (100MHz GBW), OPA300 (180 MHz (200MHz GBW), or OPA656, OPA657 may be used. bandwidth, the GBW), OPA354 GBW), OPA355 (400MHz GBW) For single-supply applications, the +IN input can be biased with a positive dc voltage to allow the output to reach true zero when the photodiode is not exposed to any light, and respond without the added delay that results from coming out of the negative rail. (Refer to Figure 6.) This bias voltage also appears across the photodiode, providing a reverse bias for faster operation. CF(1) < 1pF 2. RF 10MΩ 3. V+ λ OPA727 4. VOUT +VBias NOTE: (1) CF is optional to prevent gain peaking. It includes the stray capacitance of RF. For additional information, refer to the Application Bulletins Noise Analysis of FET Transimpedance Amplifiers (SBOA060), and Noise Analysis for High-Speed Op Amps (SBOA066), available for download at the TI web site. Figure 6. Single-Supply Transimpedance Amplifier 13 OPA727, OPA2727 OPA4727, OPA728 www.ti.com SBOS314B − SEPTEMBER 2004 − REVISED DECEMBER 2004 C1 1nF R3 2.07kΩ C3 2.2nF R1 1.93kΩ R2 15.9kΩ 1/2 OPA2727 R4 22.3kΩ C4 100pF 1/2 OPA2727 VO C2 330pF DC Gain = 1 Cutoff Frequency = 50kHz NOTE: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The program can be used to determine component values for other cutoff frequencies or filter types. Figure 7. Four-Pole Butterworth Sallen-Key Low-Pass Filter DFN PACKAGE The OPA727 series uses the 8-lead DFN (also known as SON), which is a QFN package with lead contacts on only two sides of the bottom of the package. This leadless, near-chip-scale package maximizes board space and enhances thermal and electrical characteristics through an exposed pad. DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external leads eliminates bent-lead issues. The DFN package can be easily mounted using standard printed circuit board (PCB) assembly techniques. See Application Note, QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages (SCBA017), both available for download at www.ti.com. The exposed leadframe die pad on the bottom of the package should be connected to V−. LAYOUT GUIDELINES The leadframe die pad should be soldered to a thermal pad on the PCB. A mechanical data sheet showing an example layout is attached at the end of this data sheet. Refinements to this layout may be required based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability. 14 PACKAGE OPTION ADDENDUM www.ti.com 22-Feb-2005 PACKAGING INFORMATION Orderable Device OPA727AIDGKR OPA727AIDGKT OPA727AIDRBR OPA727AIDRBT OPA728AIDGKR OPA728AIDGKT OPA728AIDRBR OPA728AIDRBT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type MSOP MSOP SON SON MSOP MSOP SON SON Package Drawing DGK DGK DRB DRB DGK DGK DRB DRB Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 2500 250 3000 250 2500 250 3000 250 None None None None None None None None Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-3-240C-168 HR Level-3-240C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-240C-168 HR Level-3-240C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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