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OPA828
SBOS671B – SEPTEMBER 2018 – REVISED DECEMBER 2018
OPA828 Low-Offset, Low-Drift, Low-Noise, 45-MHz, 36-V JFET-Input, RRO
Operational Amplifier
1 Features
3 Description
•
The OPA828 JFET is the next generation OPA627
and OPA827 operational amplifier (op amp),
combining high speed with high DC precision and AC
performance. This op amp supplies low-offset voltage
(50 μV), low-drift over temperature (0.45 μV/°C
typical), low bias current (1 pA typical), and low noise
(4 nV/√Hz typical) with only 60-nVRMS 0.1- to 10-Hz
noise. The OPA828 operates over a wide supplyvoltage range, ±4 V to ±18 V on a supply current (5.5
mA/channel typical).
1
•
•
•
•
•
•
•
•
•
•
•
Low Input Voltage Noise Density:
4 nV/√Hz at 1 kHz
Input Voltage Noise:
0.1 Hz to 10 Hz: 60 nVRMS
Low Input Bias Current: 1 pA
Input Offset Voltage: 50 μV
Input Offset Drift: 0.45 μV/°C
MUX-Friendly Inputs
Gain Bandwidth: 45 MHz
Slew Rate: 150 V/μs
14-bit Settling Time: 120 ns
Overload Power Limiter
Wide Supply Voltage Range: ±4 V to ±18 V
Package: 8-pin SOIC
AC characteristics, including a 45-MHz gain
bandwidth product (GBW), a slew rate of 150 V/μs,
and precision dc characteristics, make the OPA828
an excellent choice for a variety of systems. These
include high-speed and high-resolution dataacquisition systems, such as 16-bit to 18-bit mixed
signal systems, transimpedance (I/V-conversion)
amplifiers, filters, precision ±10-V front ends, and
high-impedance sensor-interface applications.
2 Applications
•
•
•
•
•
The OPA828 is available in the industry-standard 8pin SOIC surface-mount package and is specified
from –40°C to +125°C.
Data Acquisition (DAQ)
Optical Module
Seismic Test Equipment
Mixed Module
Ultrasound Scanners
Device Information(1)
PART NUMBER
OPA828
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
x
x
x
x
Open-Loop Gain and Phase vs Frequency
120
120
25%
100
80
80
40
60
0
40
-40
20
-80
0
-120
-20
-160
-40
100m
1
10
100
1k
10k 100k
Frequency (Hz)
1M
-200
10M 100M
Total Amplifiers (%)
200
Open Loop Gain
160
Phase
30%
140
Phase (q)
Open Loop Gain (db)
160
Offset Voltage Drift
20%
15%
10%
5%
0
-1.5
-1
-0.5
0
0.5
Offset Voltage Drift (PV/qC)
1
1.5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA828
SBOS671B – SEPTEMBER 2018 – REVISED DECEMBER 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics.............................................
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram ......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
26
8
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 34
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2018) to Revision B
•
2
Page
First release of production-data data sheet............................................................................................................................ 1
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SBOS671B – SEPTEMBER 2018 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
NC: no internal connection
Pin Functions
NAME
–IN
NO.
I/O
2
I
Negative (inverting) input
DESCRIPTION
Positive (non-inverting) input
+IN
3
I
NC
1, 5, 8
—
No internal connection (can be left floating or grounded)
OUT
6
O
Output
V+
7
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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SBOS671B – SEPTEMBER 2018 – REVISED DECEMBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS = (V+) – (V–)
±20
Common-mode (2)
Voltage
Current
(V–) – 0.5
Differential (3)
(V+) – (V–)
±10
(4)
mA
Continuous
Temperature
(3)
V
(V+) + 0.5
(2)
Output short current (4)
(2)
UNIT
40
Dual-supply
Signal input pins
(1)
MAX
Single-supply
Junction, TJ
-55
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Ratings. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Current-limit input signals that can swing more than 0.5 V beyond the
supply rails to 10 mA or less.
Input terminals are not clamped to each other with anti-parallel diodes. The JFET input stage allows large differential voltage values up
to the supply voltage of the device.
Short circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Single supply
Supply voltage, (V+) – (V–)
Dual supply
Ambient temperature
NOM
MAX
8
36
±4
±18
–40
125
UNIT
V
°C
6.4 Thermal Information
OPA828
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
121.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
64.3
°C/W
RθJB
Junction-to-board thermal resistance
65
°C/W
ψJT
Junction-to-top characterization parameter
18
°C/W
ψJB
Junction-to-board characterization parameter
64.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS671B – SEPTEMBER 2018 – REVISED DECEMBER 2018
6.5 Electrical Characteristics
At TA = 25°C, (V+) = 15 V, (V–) = –15 V, VCM = VO = midsupply, CL = 20 pF, RL = 2 kΩ connected to midsupply, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±50
±300
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
PSRR
Power-supply rejection
ratio
TA = 0°C to 85°C
±350
TA = –40°C to 125°C
±400
TA = 0°C to 85°C
TA = –40°C to 125°C
8 V ≤ VS ≤ 36 V
±0.3
±1.3
±0.45
±1.5
1.4
±5.6
TA = –0°C to 85°C
µV
µV/°C
±7
TA = –40°C to 125°C
µV/V
±10
INPUT BIAS CURRENT
±1
IB
Input bias current
TA = 0°C to 85°C
±3
±1
Input offset current
pA
±400
TA = –40°C to 125°C
IOS
±8
nA
±8
TA = 0°C to 85°C
±500
TA = –40°C to 125°C
±1.5
pA
nA
NOISE
EN
Input voltage noise
eN
Input voltage noise
density
iN
Input current noise
density
f = 0.1 Hz to 10 Hz, peak-to-peak
0.34
µVPP
f = 0.1 Hz to 10 Hz, RMS
0.06
µVRMS
f = 10 Hz
7.5
f = 100 Hz
4.8
f = 1 kHz
4
f = 1 kHz
1.2
nV/√Hz
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) +
2.5
CMRR
Common-mode rejection (V–) + 2.5 V < VCM < (V+) –
ratio
3.5 V
(V+) –
3.5
108
TA = 0°C to 85°C
105
TA = –40°C to 125°C
103
V
115
dB
INPUT IMPEDANCE
ZID
ZICM
1012 || 6
Differential
12
Common-mode
10
|| 9
Ω || pF
Ω || pF
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Electrical Characteristics (continued)
At TA = 25°C, (V+) = 15 V, (V–) = –15 V, VCM = VO = midsupply, CL = 20 pF, RL = 2 kΩ connected to midsupply, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
(V–) + 1.6 V< VO < (V+) – 1.6 V, RL = 600 Ω
120
130
(V–) + 1.5 V < VO < (V+) – 1.5 V, RL = 10 kΩ
120
130
MAX
UNIT
OPEN-LOOP GAIN
TA = –0°C to 85°C
AOL
Open-loop voltage gain
TA = –40°C to 125°C
(V–) + 1.6 V< VO
< (V+) – 1.6 V, RL = 600
Ω
117
(V–) + 1.5 V < VO
< (V+) – 1.5 V, RL = 10
kΩ
118
(V–) + 1.6 V< VO
< (V+) – 1.6 V, RL = 600
Ω
114
(V–) + 1.5 V < VO
< (V+) – 1.5 V, RL = 10
kΩ
114
dB
FREQUENCY RESPONSE
Unity gain frequency
VO = 10 mVPP, CL = 30 pF
45
MHz
Phase margin
VO = 10 mVPP, CL = 30 pF
57
Degrees
GBW
Gain-bandwidth product
VO = 10 mVPP, CL = 30 pF
45
MHz
SR
Slew rate
VO = 10-V step
tS
Settling time (input to
output)
VO = 10-V step, CL = 30 pF,
G = -1
Overshoot
VO = 100-mV step, G = +1,
CL = 30 pF
Overload recovery time
G = –10
G = +1
150
G = –1
150
To ±0.0244% (12-bit
accuracy)
110
To ±0.0061% (14-bit
accuracy)
120
VO = 100-mV step, G =
+1, CL = 30 pF
8%
ns
55
RL = 10 kΩ
0.000028
%
RL = 600 Ω
0.000028
%
–130
Total harmonic distortion VO = 3.5 VRMS, G = +1, f = 1
+ noise (THD+N)
kHz
–130
HD2
Second-order harmonic
distortion
VO = 5 VPP, G = +1
HD3
Third-order harmonic
distortion
VO = 5 VPP, G = +1
IMD
6
V/µs
f = 100 kHz
119
f = 500 kHz
90
f = 100 kHz
125
f = 500 kHz
105
ns
dB
dB
dBc
dBc
SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz), G = 1,
Second-order
VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement
intermodulation distortion
bandwidth
132
dB
Third-order
CCIF twin-tone (19 kHz and 20 kHz), G = 1, VO = 3
intermodulation distortion VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth
137
dB
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SBOS671B – SEPTEMBER 2018 – REVISED DECEMBER 2018
Electrical Characteristics (continued)
At TA = 25°C, (V+) = 15 V, (V–) = –15 V, VCM = VO = midsupply, CL = 20 pF, RL = 2 kΩ connected to midsupply, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 10 kΩ
0.9
1.2
RL = 600 Ω
1.2
For linear operation, AOL ≥ 120 dB
±30
mA
±50
mA
OUTPUT
Output voltage swing
IO
Output current
ISC
Short-circuit current
CL
Capactive load drive
ZO
Open-loop output
impedance
See Typical Curves
f = 1 MHz, IO = 0 mA
13.5
V
pF
Ω
POWER SUPPLY
VS
Specified voltage
±4
±18
V
6.2
mA
TA = 0°C to 85°C
7.1
mA
TA = –40°C to 125°C
7.9
mA
125
°C
IO = 0 A
IQ
Quiescent current (per
amplifier)
IO = 0 A
5.5
TEMPERATURE RANGE
TA
Operating ambient
temperature
–40
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6.6
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Typical Characteristics
Table 1. Table of Graphs
8
DESCRIPTION
FIGURE
Input Voltage Noise Density vs Frequency
Figure 1
. Integrated Input Voltage Noise vs Bandwidth
Figure 2
Total Harmonic Distortion + Noise Ratio vs Frequency
Figure 3
Total Harmonic Distortion + Noise Ratio vs Output Amplitude
Figure 4
. 0.1-Hz To 10-Hz Noise
Figure 5
Offset Voltage Production Distribution
Figure 6
Offset Voltage Drift Production Distribution
Figure 7
Offset Voltage vs Common-Mode Voltage
Figure 8
Offset Voltage vs Power Supply Voltage
Figure 9
Offset Voltage vs Output Voltage
Figure 10
. Offset Voltage vs Temperature
Figure 11
Input Bias and Input Offset Current vs Common-Mode Voltage
Figure 12
Input Bias and Input Offset Current vs Temperature
Figure 13
Quiescent Current vs Output Voltage
Figure 14
Quiescent Current vs Temperature
Figure 15
Output Voltage Swing vs Output Sourcing Current
Figure 16
Output Voltage Swing vs Output Sinking Current
Figure 17
Power-Supply Rejection Ratio vs Frequency
Figure 18
Common-Mode Rejection Ratio vs Frequency
Figure 19
Power-Supply Rejection Ratio vs Temperature
Figure 20
Common-Mode Rejection Ratio vs Temperature
Figure 21
Open-Loop Gain and Phase vs Frequency
Figure 22
Closed-Loop Gain vs Frequency
Figure 23
Open-Loop Gain vs Temperature
Figure 24
Open-Loop Output Impedance vs Frequency
Figure 25
Small-Signal Overshoot vs Capacitive Load, Gain = +1
Figure 26
Small-Signal Overshoot vs Capacitive Load, Gain = -1
Figure 27
No Phase Reversal
Figure 28
Positive Overload Recovery
Figure 29
Negative Overload Recovery
Figure 30
. Small-Signal Step Response
Figure 31
Large-Signal Step Response
Figure 32
12-bit, 14-bit Settling Time
Figure 33
Short-Circuit Current vs Temperature
Figure 35
Slew Rate vs Temperature
Figure 36
Slew Rate vs Output Step Size
Figure 37
Maximum Output Voltage vs Frequency
Figure 38
Intermodulation Distortion
Figure 39
Electromagnetic Interference Rejection
Figure 40
Harmonic Distortion vs Frequency
Figure 41
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SBOS671B – SEPTEMBER 2018 – REVISED DECEMBER 2018
At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, Vs = ±18V, unless otherwise noted.
100
50
Integrated Voltage Noise (uV)
10
1
100m
20
10
5
2
1
0.5
0.2
0.1
0.05
Noise Bandwidth: 0.1Hz
to indicated frequency
0.02
0.01
1
10
100
1k
Frequency (Hz)
10k
100k
1
Figure 1. Input Voltage Noise Density vs Frequency
1, RLoad = 10K:
1, RLoad = 2K:
1, RLoad = 10K:
1, RLoad = 2K:
0.001
-100
-120
0.0001
100
1k
Frequency (Hz)
1k
10k
Bandwidth(Hz)
G
G
G
G
0.01
100k
1M
10M
-60
1, RLoad = 10K:
1, RLoad = 2K:
1, RLoad = 10K:
1, RLoad = 2K: -80
0.001
-100
0.0001
-120
-140
1E-5
100
0.1
Total Harmonic Distortion Noise (dB)
Total Harmonic Distortion Noise (%)
Noise ( )
G
G
G
G
10
Figure 2. Integrated Input Voltage Noise vs Bandwidth
-80
0.01
Total Harmonic Distortion
VRMS
VPP
-140
1E-5
10m
10k
Figure 3. Total Harmonic Distortion + Noise Ratio vs
Frequency
Total Harmonic Distortion + Noise (dB)
Voltage Noise Density (nV/—Hz)
100
100m
1
Output Amplitude (VRMS)
10
Figure 4. Total Harmonic Distortion + Noise Ratio vs Output
Amplitude
15%
125 nV/div
Total Amplifiers (%)
12.5%
10%
7.5%
5%
2.5%
Time (1 s/div)
0
0
-300 -240 -180 -120 -60
60 120 180
Input Reference Offset Voltage (PV)
240
300
Vs = ±15 V
Figure 5. 0.1-Hz To 10-Hz Noise
Figure 6. Offset Voltage Production Distribution
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At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, Vs = ±18V, unless otherwise noted.
170
30%
Input Offset Voltage (PV)
Total Amplifiers (%)
5 Typical Units
130
25%
20%
15%
10%
5%
-12.5V
90
11.5V
50
10
-30
-70
-110
0
-1.5
-1
-0.5
0
0.5
Offset Voltage Drift (PV/qC)
1
-150
-15
1.5
-10
-5
0
5
Common-Mode Voltage (V)
TA = –40°C to 125°C
15
Vs = ±15V
Figure 7. Offset Voltage Drift Production Distribution
Figure 8. Offset Voltage vs Common-Mode Voltage
150
125
5 Typical Units
100
100
75
Offset Voltage (PV)
Input Offset Voltage (PV)
10
50
0
-50
50
25
0
-25
-50
-75
-100
-100
5 Typical Units
-150
4
6
8
10
12
14
16
Power-Supply Voltage (V)
18
-125
-15
20
-10
-5
0
Vo(V)
5
10
15
Vs = ±15V
Figure 9. Offset Voltage vs Power Supply Voltage
Figure 10. Offset Voltage vs Output Voltage
30
300
20
200
Input-Bias Current (pA)
Input-referred Offset Voltage (PV)
400
100
0
-100
-200
-50
-25
0
25
50
75 100
Temperature (qC)
125
150
Figure 11. Offset Voltage vs Temperature
10
0
-10
IBIB+
Ios
-20
-300
-400
-75
10
175
-30
-18 -15 -12
-9
-6 -3
0
3
6
9
Common-mode Voltage (V)
12
15
18
Figure 12. Input Bias and Input Offset Current vs CommonMode Voltage
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At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, Vs = ±18V, unless otherwise noted.
0
0.8
8
0.6
0
-0.2
IBn
IBp
-0.6
-0.8
Quiescent Current (mA)
Input Current (nA)
0.2
-0.4
Vs = 8 V
7
Ios
0.4
-1
6
5
4
3
2
1
-1.2
-75
-50
-25
0
25
50
75
Temperature (qC)
100
125
0
150
4
Figure 13. Input Bias and Input Offset Current vs
Temperature
8
12
16
20
24
Supply Voltage (V)
28
32
36
Figure 14. Quiescent Current vs Output Voltage
14
8
13
7.5
Output Voltage (V)
Quiescent Current (mA)
12
7
6.5
6
5.5
11
10
9
8
7
5
-40qC
25qC
85qC
125qC
6
4.5
Vs = r4V
Vs = r18V
4
-75
5
4
-50
-25
0
25
50
75 100
Temperature (qC)
125
150
0
175
5
10
15
20 25 30 35
Output Current (mA)
40
45
50
55
Vs = ±15V
Figure 15. Quiescent Current vs Temperature
Figure 16. Output Voltage Swing vs Output Sourcing
Current
140
-4
-40qC
25qC
85qC
125qC
-5
Rejection Ratio (dB)
Output Voltage (V)
-6
PSRR
PSRR
120
-7
-8
-9
-10
-11
100
80
60
40
-12
20
-13
0
-14
0
5
10
15
20 25 30 35
Output Current (mA)
40
45
50
55
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Vs = ±15V
Figure 17. Output Voltage Swing vs Output Sinking Current
Figure 18. Power-Supply Rejection Ratio vs Frequency
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At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, Vs = ±18V, unless otherwise noted.
7
Power Supply Rejection Ratio (PV/V)
Common-Mode Rejection Ratio (db)
140
120
100
80
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
6
5
4
3
2
1
0
-1
-2
-75
10M
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Differential amp configuration, 10-kΩ resistors
Figure 20. Power-Supply Rejection Ratio vs Temperature
160
Open Loop Gain (db)
Common Mode Rejection Ratio (PV/V)
1
0
-1
-2
140
200
Open Loop Gain
160
Phase
120
120
100
80
80
40
60
0
40
-40
20
-80
0
-120
-20
-160
-3
-4
-75
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
-40
100m
50
1k
10k 100k
Frequency (Hz)
1M
-200
10M 100M
20
10
0
-10
0.3
Open Loop Gain (uV/V)
G= 1
G= 1
G = 10
G = +100
30
Gain (dB)
100
0.4
40
0.2
0.1
0
-0.1
-0.2
-0.3
1k
10k
100k
1M
Frequency (Hz)
10M
100M
-0.4
-60
Figure 23. Closed-Loop Gain vs Frequency
12
10
Figure 22. Open-Loop Gain and Phase vs Frequency
Figure 21. Common-Mode Rejection Ratio vs Temperature
-20
100
1
Phase (q)
Figure 19. Common-Mode Rejection Ratio vs Frequency
2
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-40
-20
0
20
40
60
Temperature(oC)
80
100
120
140
Figure 24. Open-Loop Gain vs Temperature
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At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, Vs = ±18V, unless otherwise noted.
65
40
RISO = 0 :
RISO = 25 :
RISO = 50 :
60
Open Loop Impedance (:)
55
50
30
Overshoot (%)
45
20
40
35
30
25
20
10
15
10
0
0.1
5
1
10
100
1K
10K 100K
freq (Hz)
1M
0
10M
Figure 25. Open-Loop Output Impedance vs Frequency
100
800
900 1000
Input
Output
RISO = 0 :
RISO = 25 :
RISO = 50 :
24
300 400 500 600 700
Capacitive Load (pF)
Figure 26. Small-Signal Overshoot vs Capacitive Load,
Gain = +1
30
27
200
Voltage (5 V/div)
Overshoot (%)
21
18
15
12
9
6
3
0
-3
0
100
200
300 400 500 600 700
Capacitive Load (pF)
800
900 1000
Time (200 Ps/div)
Gain = +1
Figure 28. No Phase Reversal
Figure 27. Small-Signal Overshoot vs Capacitive Load,
Gain = –1
Input
Output
Voltage (5 V/div)
Voltage (5 V/div)
Intput
Output
Time (100 ns/div)
Time (100 ns/div)
Figure 29. Positive Overload Recovery
Figure 30. Negative Overload Recovery
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At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, Vs = ±18V, unless otherwise noted.
100
Input
Output
80
60
Output (2 V/Div)
Voltagte (mV)
40
20
0
-20
-40
-60
G = -1
G = +1
-80
-100
0
0.5
1
time (Ps)
1.5
2
Time (100 ns/Div)
Figure 32. Large-Signal Step Response
Figure 31. Small-Signal Step Response
Falling
Rising
Output Delta to Final Value (0.3 mV/div)
Output Delta to Final Value (1 mV/div)
Falling
Rising
Time (100 ns/div)
Time (100 ns/div)
Figure 34. 14-bit Settling Time
200
175
150
Slew Rate (V/PV)
Short Circuit Current (mA)
Figure 33. 12-bit Settling Time
51
50.8
50.6
50.4
50.2
50
49.8
49.6
49.4
49.2
49
48.8
48.6
48.4
48.2
48
-50
125
100
75
50
25
Sinking
Sourcing
-25
0
25
50
Temperature (qC)
75
100
125
0
-40
Figure 35. Short-Circuit Current vs Temperature
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-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 36. Slew Rate vs Temperature
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At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, Vs = ±18V, unless otherwise noted.
40
200
VS = r18V
VS = r4V
Maximum Output Voltage (V)
175
Slew Rate (V/Ps)
150
125
100
75
50
32
24
16
8
25
0
1k
0
0
1
2
3
4
5
6
Step Size (V)
7
8
9
10
10k
100k
1M
Frequency (Hz)
10M
Buffer Configuration
Figure 37. Slew Rate vs Output Step Size
Figure 38. Maximum Output Voltage vs Frequency
-60
0.01
-80
0.001
-100
0.0001
-120
100
EMIRR IN+ (dB)
Intermodulation Distortion (%)
CCIF
SMPTE
120
Intermodulation Distortion (dB)
0.1
80
60
40
1E-5
0.01
0.1
-140
10
1
Voltage (VRMS)
20
10M
100M
1G
Frequency (Hz)
10G
Figure 39. Intermodulation Distortion
Figure 40. Electromagnetic Interference Rejection
Harmonic Distortion ( )
0.0001
HD2
HD3
HD4
HD5
-120
1E-5
-140
1E-6
-160
Harmonic Distortion (dB)
-100
0.001
-180
1E-7
100
1k
10k
Frequency (Hz)
100k
Figure 41. Harmonic Distortion vs Frequency
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7 Detailed Description
7.1 Overview
The OPA828 is a low-noise, high-speed JFET input amplifier providing the highest levels of precision and
accuracy. Each device is laser trimmed in production to ensure the lowest input referred offset voltage. Likewise,
input referred offset voltage drift is trimmed and guaranteed over the specified junction temperature range from
–40°C to +125°C. Additionally each device has its quiescent current laser trimmed to minimize part-to-part
variations for dynamic parameters such as input referred noise voltage, gain-bandwidth product, slew rate, and
settling time. The combination of low-noise, DC precision, and dynamic performance of the OPA828 is
unsurpassed in the industry with the OPA828 taking full advantage of the latest and most advanced high-voltage,
SiGe-complementary, JFET/bipolar process technology.
7.2 Functional Block Diagram
V+
+IN
+
_
gm
Buffer
OUT
+
JFET
_
-IN
GND
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7.3 Feature Description
7.3.1 Operating Characteristics
The OPA828 operational amplifier is specified for operation from 8 V to 36 V (±4 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in Typical Characteristics.
7.3.2 Phase-Reversal Protection
Many operational amplifiers exhibit a phase reversal when the input drives beyond their specified input commonmode range. This condition is most often encountered in non-inverting circuits when the input drives beyond the
specified common-mode voltage range, which can cause the output to reverse into the opposite rail. The
OPA828 has an internal phase-reversal protection circuitry. The input architecture of the OPA828 prevents phase
reversal with input common-mode voltages that exceed the specified maximum and minimum values. The
OPA828 output limits to the appropriate rail. This performance is shown in Figure 42. When input voltages can
exceed the minimum or maximum specified limits, care must be taken to limit the maximum input current through
internal ESD protection diodes.
Voltage (5 V/div)
Input
Output
Time (200 Ps/div)
Figure 42. No Phase Reversal
7.3.3 Electrical Overstress
The OPA828 is internally protected against ESD events which can occur during manufacturing, handling, or
printed-circuit-board assembly. The internal ESD protection diodes are not intended to protect the OPA828
during normal operation when the device is operating under power. The ESD protection circuitry involves several
current-steering diodes connected from the input and output pins and routed back to the internal power-supply
lines, where the diodes meet at the power-supply ESD cell, an absorption device, internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. In cases where
the inputs or output can be driven above the positive power supply or below the negative power supply care must
be taken to limit the current through the internal diodes to 10 mA or less. In harsh electrical environments
external protection circuitry may be required and is dependant upon the application requirements and
environmental conditions.
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Feature Description (continued)
V+
+IN
+
-IN
±
OUT
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Figure 43. Equivalent Internal ESD Circuitry
One example of protecting the OPA828 inputs against an input over-voltage condition is illustrated in Figure 44.
In this example the non-inverting input to the OPA828 is protected with the addition of an external resistor. If the
input voltage, VIN, exceeds either power supply voltage, the input ESD diodes become forward biased at
approximately 0.5 V. It is recommended to limit the current through the forward-biased internal ESD diodes under
such conditions; see Absolute Maximum Ratings. In this specific example illustrated in Figure 44, the addition of
the input resistor provides the necessary current limiting and allows for input voltages at VIN up to ±25.5 V.
Assuming a symmetrical, dual power supply configuration, the maximum input voltage for this circuit
configuration can be determined from Equation 1:
r VIN
VS
0.5V 10mA u RIN
(1)
+VS = +15 V
DP
±
RIN = 1 NŸ
+
VIN = ± 25.5 V
OUT
+
±
DN
GND
-VS = -15 V
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Figure 44. Limiting the Input Current
Adding the series input protection resistor as described above will add an additional source of noise to the circuit.
Resistance values below 250 Ω contribute less than 10% of additional noise. A resistance value of 1 kΩ
increases the noise by approximately by 40%. The OPA828 has an equivalent input noise resistance of
approximately 1 kΩ.
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Feature Description (continued)
7.3.4 MUX Friendly Inputs
Multiplexing is a frequently-used technique to perform data acquisition in multi-channel systems with minimal
signal-chain requirements. In this context, the role of the multiplexer (MUX) in an acquisition system is to switch
between channels and send each signal as fast as possible to a single data converter — maximizing system
throughput and minimizing delay. To ensure accurate processing, a precision amplifier is placed downstream
from the multiplexer to precisely drive the analog-to-digital converter (ADC). This concept is illustrated in
Figure 45.
Input 1
Input 2
MUX
Input 3
Input 4
+
OPA
±
ADC
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Figure 45. Typical Multiplexed System Block Diagram
In a typical multiplexed application it is common that large transient voltages can be presented to the input of the
op amp driving the ADC. Large input differential voltages are commonly seen during slewing or open-loop
operation, which is especially common when switching from one MUX input to another. Traditional precision
amplifiers often consist of a differential transistor pair that is protected from large differential transient input
voltages with anti-parallel diodes between the inputs of the amplifier. These anti-parallel diodes are effective at
limiting the voltage differential between the inputs to one or two forward diode voltage drops, which protects the
precision input devices from damage. However, the anti-parallel diodes do have considerable drawbacks such as
large inrush currents when they are turned on. lf passive filtering or high source impedance is present, large
inrush current can disturb settling time, limiting the throughput of the system and degrading signal-chain
precision. The OPA828 does not need anti-parallel diodes to protect the input JFET transistors and is free from
large inrush currents even with differential input voltages as large as ±18 V. These concepts are illustrated in
Figure 46:
+
s
MUX
10 V
+
RSOURCE
Traditional
opamp
s
+
RMUX
-10 V
+
+
s
±
ADC
RSOURCE
s
MUX
OPA828
10 V
RSOURCE
+
RMUX
-10 V
+
ADC
RSOURCE
±
s
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Figure 46. Typical Multiplexed System Block Diagram
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Feature Description (continued)
7.3.5 Overload Power Limiter
In many applications, tight limits on opamp power consumption exist and it is therefore highly desirable that the
amplifier’s power consumption remains constant even during fault conditions, such as a large voltage across the
inputs or the output hitting the rail. In particular, high slew-rate amplifiers, such as the OPA828 temporarily
increase the supply current when the amplifier is slewing. In slew-boosted amplifiers, the presence of a large
input signal can present a specific problem, since it applies a large voltage across the amplifier’s inputs. This will
activate the slew-boost and can lead to a significant increase in current consumption. In addition, at high supply
voltages the large current consumption can lead to significant amplifier self-heating.
OPA828 offers a high slew rate of 150 V/us in combination with a comparably low supply current of 5.5 mA. Like
many other amplifiers, this is achieved by a so called slew-boosting method, which temporarily increases the
amplifier’s current consumption when the amplifier is slewing. Such a slewing condition is detected by measuring
the voltage across the input pins. In quiescent condition, this voltage is very small (equal to the amplifier’s offset).
If, on the other hand, an input voltage is changed rapidly, a large voltage will be applied across the inputs and
the amplifier output needs to slew. On OPA828, the supply current increase is gradual and proportional to the
applied input voltage, ensuring a well-behaved large step response and excellent THD. Because the high slew
rate ensures the output re-settles in less than about 300ns, the increased power consumption is absorbed by the
decoupling capacitors, and therefore does not additionally load the power supplies.
In OPA828, such an increase in current consumption is avoided by an additional protection circuit, which
continuously monitors both the amplifier’s inputs and output. If a large input voltage is detected, the protection
circuit checks for the presence of a rapid change in voltage at the output. If the output voltage is not changing,
for instance because the output is at a supply rails, the protection circuit will disable the slew-boost circuit after a
delay of about 300ns. After the overload condition is removed, the amplifier rapidly recovers to a normal
operating condition. This is indicated in Figure 47, where the amplifiers supply current is measured with its
decoupling capacitors removed. It can be observed that after 300 ns, the power consumption of the amplifier
goes back to quiescent levels. At the same time, the amplifier still has an excellent overload recovery time of less
than 55 ns.
6
36
2
30
Competition
OPA828
0
24
18
-2
12
Input
-4
6
-6
0
-8
Output Railed
-10
-6
Input/Output Voltage (V)
Supply Current Delta (mA)
4
-12
-12
-18
Time
Figure 47. Supply Current Change with Overloaded Output
7.3.6 Capacitive Load and Stability
Figure 48 shows the total circuit noise for varying source impedances with the operational amplifier in a unitygain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPA828 and OPA211 are shown with total circuit noise calculated. The op amp itself contributes both a voltage
noise component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise
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Feature Description (continued)
op amp for a given application depends on the source impedance. For low source impedance, current noise is
negligible, and voltage noise generally dominates. The OPA828 device has both low voltage noise and extremely
low current noise because of the FET input of the op amp. As a result, the current noise contribution of the
OPA828 is negligible for any practical source impedance, which makes it the better choice for applications with
high source impedance.
Voltage Noise Spectral Density, EO (V/—HZ)
The equation in shows the calculation of the total circuit noise, with these parameters:
• en = voltage noise
• In = current noise
• RS = source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
• T = temperature in degrees Kelvin (K)
10P
Resistor Noise
OPA828
OPA211
1P
100n
10n
1n
0.1n
1
10
100
1k
10k
100k
Source resistance, RS (:)
1M
Figure 48. Noise Performance of the OPA828 and OPA211 in Unity-Gain Buffer Configuration
7.3.7 Capacitive Load and Stability
The dynamic characteristics of the OPA828 are optimized for common operating conditions. The combination of
low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain
peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way
to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. The
Figure 49 graph show small-signal overshoot versus capacitive load. See Feedback Plots Define Op Amp AC
Performance for details of analysis techniques and application circuits.
80
70
G=+1
G = -1
60
Overshoot (%)
50
40
30
20
10
0
-10
-20
30
40 50 6070
100
200
300 400500 700 1000
Capacitive Load (pF)
Figure 49. Small-Signal Overshoot vs Capacitive Load
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Feature Description (continued)
7.3.8 Settling Time
Settling time is a measure of an amplifiers output to settle to within some percentage (error band) of the input
amplitude and is used to describe an amplifiers response to a step input. An amplifiers settling time is comprised
of both a large signal response and small signal response. The large signal response is characterized by the rise
and fall times while the small signal response is characterized by overshoot and ringing. Figure 50 illustrates the
concepts and terminology associated with an amplifiers settling time. Specifically the settling time is defined as
the time it takes the output to settle to within a specified error band from the time the input signal was applied.
Settling Time
Overshoot
Error Band
1+0
1-0
1
0.9
Output
Voltage
0.1
0
ûVOUT
ût
Time
Figure 50. Settling Time
The OPA828 minimizes settling time for high-resolution systems by incorporating an internal slew boost circuit
which minimizes rise and fall times and having wide bandwidth with excellent phase margin with low ringing,
enabling small signal settling in minimal time. The OPA828 is trimmed in laser production that will minimize partto-part variation in the device slew rate, bandwidth and phase margin thus mainlining excellent unit-to-unit
variations across all manufacturing lots.
7.3.9 Slew Rate
The parameter of an amplifier that best describes the large signal dynamic behavior is the slew rate. Slew rate is
a measure the maximum rate of change of the output voltage with respect to time and is generally expressed in
units of volts-per-microsecond, (V/µs). Typically the slew rate is measured as the time it takes for the output to
swing from 10% of its final value to 90% of its final value. The slew rate for the signal illustrated in Figure 50 is
given by Equation 2.
Slew Rate
'VOUT
't
VOUT90 VOUT10
t90 t10
(2)
The slew rate of an amplifier is limited by the internal architecture of the amplifier, the amplifiers quiescent power
and internal capacitances. The OPA828 maximizes slew rate by incorporating a slew-boost circuit. The
proprietary slew boost circuit used in the OPA828 results in a very high slew rate while maintaining low quiescent
power levels. The internal slew boost circuit measures the input differential voltage present between +IN and –IN
input pins. If this input differential voltage is sufficiently large enough, the internal slew boost circuit increases the
internal biasing currents of the amplifier thereby increasing the ability of the output to slew faster. TI recommends
placing power supply bypass capacitors close to the OPA828 to make sure of optimum dynamic performance.
Should the inputs of the amplifier have a large static or DC differential voltage present, the OPA828 recognizes
that condition, not as an indicator of the need to slew faster, but rather as an overload condition. In this case the
OPA828 internal biasing currents do not increase, and the quiescent current remains unchanged from normal
operation.
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Feature Description (continued)
7.3.10 Full Power Bandwidth
The full power bandwidth of an amplifier describes the frequency at which the largest sinusoidal signal the
amplifier can provide at its output before slew rate induced distortion becomes a dominant source of error. This
concept is illustrated in Figure 51.
Figure 51. Slew Rate Induced Distortion
If the inputs of the amplifier are driven too far apart, such as when a multiplexer connected to the inverting input
changes channels, a slew boost circuit is enabled to help settling time but can distort the signal. If low distortion
is needed, avoid driving the inputs too far apart from each other. The OPA828 has a full power bandwidth of 1.2
MHz with 10-VPEAK output voltage. The maximum output voltage as a function of frequency is illustrated in
Figure 52.
40
Maximum Output Voltage (V)
VS = r18V
VS = r4V
32
24
16
8
0
1k
10k
100k
1M
Frequency (Hz)
10M
Figure 52. Maximum Output Voltage vs Frequency
7.3.11 Small Signal Response
The parameters of an amplifier the best describes the small signal dynamic behaviour are the gain-bandwidth
product (GBP), unity gain frequency (UGF) and phase margin (PM) of an amplifier. The GBP is a useful
parameter to determine the bandwidth of an application in closed loop configurations. Equation 3 can be used to
approximate the closed loop bandwidth for the OPA828. Typically the GBP is a specified parameter with the
amplifier configured in a non-inverting gain of 100 (40 dB). The GBP of an amplifier is generally assumed to be
constant over frequency but in some higher speed amplifiers this is not always the case. The OPA828 has a
constant GBP all the way to its UGF, as such the OPA828 open-loop gain has a constant –20 dB/decade slope
(–6 dB/octave). The UGF is defined as the frequency at which the gain of the amplifier crosses 1V/V (0 dB).
Figure 53 Illustrates the concept of GBP and UGF. The OPA828 has both a GBP and UGF of 45 MHz.
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Feature Description (continued)
Bandwidth
GBP
ACL
45MHz
ACL
(3)
Gain-Bandwidth Product
Slope = -20 dB/dec
Unity Gain
Frequency
Gain
Bandwidth
Figure 53. Gain-Bandwidth Product and Unity Gain Frequency
7.3.12 Thermal Considerations
Through normal operation the OPA828 experiences self-heating, a natural increase in the die junction
temperature which occurs in every amplifier. This is a result of several factors including the quiescent power
consumption, the package’s thermal resistance, PCB layout and the device operating conditions.
To fully ensure the amplifier will operate without entering thermal shutdown it is important to calculate the
approximate junction (die) temperature which can be done using Equation 4.
TJ
PD 4JA TA
(4)
Equation 5 shows the approximate junction temperature for the OPA828 while unloaded with an ambient
temperature of 25°C.
TJ
(36V 5.5mA) 121.5qC / W
TJ
49qC
25qC
(5)
For high voltage, high precision amplifiers such as the OPA828 the junction temperature can easily be 10s of
degrees higher than the ambient temperature in a quiescent (unloaded) condition. If the device then begins to
drive a heavy load the junction temperature may rise and trip the thermal shutdown circuit. The Figure 54 shows
the maximum output voltage of the OPA828 without entering thermal shutdown vs ambient temperature in both a
loaded and unloaded condition.
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Feature Description (continued)
20
18
Max Output Voltage (V)
16
14
12
10
8
6
4
2
0
25
Unloaded
Loaded (600:)
50
75
100
125
Ambient Temperature (qC)
150
175
Figure 54. OPA828 Thermal Safe Operating Area
7.3.13 Thermal Shutdown
The OPA828 is protected from thermal overloads due to an internal thermal shutdown feature. The shutdown
design assures thermal protection when operated in demanding, high-temperature industrial environments. The
device accurately measures the die junction temperature at the hottest spot on the die. As the junction
temperature reaches the thermal shutdown temperature the device is disabled by placing the output into a high
impedance state — this prevents further power dissipation by the OPA828 and allows the OPA828 to begin
cooling. Once the junction temperature reduces by the thermal hysteresis amount, the OPA828 resumes normal
operation. If the output condition that caused the OPA828 to heat up is still present the device may enter thermal
shutdown again. The OPA828 quiescent current during shutdown reduces to approximately 20 µA. Identify the
cause of any thermal shutdown, and correct for normal device operation. Thermal shutdown occurs when the
OPA828 junction temperature exceeds approximately 165°C. Once in thermal shutdown, the OPA828 returns to
normal operation when the junction temperature cools to approximately 145°C.
7.3.14 Low Noise
The OPA828 is fabricated on a state-of-the-art SiGe Precision, High-Speed, High-Voltage, BiFET wafer process.
Patented wafer processing techniques are used to reduce the noise associated with the JFET gate regions. The
OPA828 noise spectral density is shown in Figure 55.
Voltage Noise Density (nV/—Hz)
100
10
1
100m
1
10
100
1k
Frequency (Hz)
10k
100k
Figure 55. Noise Spectral Density vs Frequency
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Feature Description (continued)
7.3.15 Low Offset Voltage Drift
Each OPA828 is laser trimmed in production. Input offset voltage is trimmed at two temperatures assuring low
input offset voltage drift across the full temperature range.
Input-referred Offset Voltage (PV)
400
300
200
100
0
-100
-200
-300
-400
-75
-50
-25
0
25
50
75 100
Temperature (qC)
125
150
175
Figure 56. Input Offset Voltage vs Temperature
7.3.16 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from the saturated state to
the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds
the rated operating voltage resulting from the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices must have time to return back to the normal state.
After the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate.
As a result, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the OPA828 is approximately 55 ns.
7.4 Device Functional Modes
7.4.1 Functional Modes
The OPA828 is operational when the applied power supply voltage is between ±4 V and ±18 V. When operating
the OPA828 device self-heating occurs. Device self-heating is a function of the power-supply voltage and power
delivered to the load. Under heavy loading conditions and elevated ambient temperatures the OPA828 may enter
thermal shutdown. Thermal shutdown occurs when the OPA828 junction temperature exceeds approximately
165°C. Once in thermal shutdown, the OPA828 returns to normal operation when the junction temperature cools
to approximately 145°C.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA828 combines low offset and offset drift with low noise across a wide bandwidth, making it well suited
for a variety of test equipment and data acquisition systems.
8.2 Typical Applications
8.2.1 Typical Application: SAR ADC Driver
The high DC precision and AC performance of the OPA828 along with the 45-MHz bandwidth enable it to quickly
and accurately drive a 16-bit successive approximate register (SAR) analog-to-digital converter (ADC).
C3 820pF
R1 1kŸ
Vee 15V
C2 100nF
R2 4.02kŸ
-
VIN
-10V
++
OPA828
R5 13.7Ÿ
AINP
C1 100nF
Cfilt 1nF
Vbias
R4 1.1kŸ
R3
7.15kŸ
R7 13.7Ÿ
ADS8860
AINM
Vcc 15V
Figure 57. OPA828 Configured as a SAR Driver
8.2.1.1 Design Requirements
The design requirements for this example include:
• Power the OPA828 from ±15-V power supplies
• Amplifier output must settle to 16-bit accuracy in less than 290 ns
• Gain = –1/4
• Amplifier output is biased to 2V
• Amplifier input = ±10 V, Output = 0 V to 5 V
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
The OPA828 is configured as shown in to enable a wide input voltage range of ±10 V to be attenuated to 0 V to
5 V. The output range of the amplifier is selected based on the full scale input range of the ADS8860, a 16-bit, 1
MSPS SAR ADC. Supply rails of ±15 V are used so the amplifier can achieve linear swing across the full input
range. This design allows the amplifier output to settle to 16-bits within the 290-ns acquisition time of the
selected ADC.
The Analog Engineer's Calculator is used to select the resistors and capacitors used to set the signal attenuation
as well as the charge bucket between the amplifier and ADC. The input and feedback resistors are chosen to
provide a gain of –1/4 (for example, a 4× attenuation in an inverting configuration). VBIAS is fixed at 2 V to enable
the output to swing from 0 V to 5 V. shows the simulated settling time of this circuit. To function properly the
output of the amplifier must settle to within ± ½LSB before the end of the ADC's acquisition cycle. In this example
using the OPA8860, the output of the amplifier must settle to within ±38.15 µV. Verror is the difference between
the expected output and the actual output of the amplifier.
An 820 pF capacitor is added to the feedback to create a lowpass filter with a cutoff frequency of 194 kHz. This
filter reduces the noise seen by the ADC and improves the accuracy of the system. The DC transfer function of
this circuit is shown in Figure 59 and the AC response in shown in Figure 60.
See TI Precision Labs for more details and training on configuring an amplifier for ADC drive, selecting the
resistors and capacitor for the charge bucket and other signal chain topics.
8.2.1.3 Application Curves
5
15
Verror
-0.5 LSB
+0.5 LSB
5
Verror (PV)
4.5
4
Amplifier Output (V)
10
0
-5
-10
3.5
3
2.5
2
1.5
1
0.5
-15
0
100
200
300
Time (µs)
400
500
600
0
-10
-8
Figure 58. OPA828 Output Settling Time
-6
-4
-2
0
2
Input Voltage (V)
4
6
8
10
Figure 59. OPA828 DC Transfer Function
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-5
200
-10
180
-15
160
-20
140
-25
120
Phase (degrees)
Gain (dB)
Typical Applications (continued)
Gain
Phase
-30
0.01
0.1
1
10
Frequency (kHz)
100
1000
100
Figure 60. OPA828 AC Response
8.2.2 Typical Application: Low-Pass Filter
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
±
Output
+
C2
39 nF
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Figure 61. Typical OPA828 Application Schematic
8.2.2.1 Design Requirements
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 61. Use Equation 6
to calculate the voltage transfer function.
-1/ R1R3C2C5
Output
(s) = 2
Input
s + (s / C2 )(1/ R1 + 1/ R3 + 1/ R 4 ) + 1/ R3R 4C2C5
(6)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 7:
R
Gain = 4
R1
fc =
1
(1/ R3R 4C2C5 )
2p
(7)
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Typical Applications (continued)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets designers create optimized
filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows to
design, optimize, and simulate complete multi-stage active filter solutions within minutes.
8.2.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 62. Low-Pass Filter Transfer Function
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9 Power Supply Recommendations
The OPA828 is specified to operate from 8 V to 36 V (±4 V to ±18 V); many specifications apply from –40°C to
+125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the typical curves.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including
the following guidelines:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to
in parallel with the noisy trace.
• Place the external components as close as possible to the device.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• TI recommends cleaning the PCB following board assembly for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
RF
C1
V+
RG
±
INPUT
OUTPUT
+
C2
V-
V+
INPUT
RG
RF
1
1
2
OUTPUT
2
1
8
2
7
3
6
4
5
2
1
2
C2
1
C1
Ground
plane
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Figure 63. OPA828 PCB Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support see the following:
WEBENCH® Filter Designer
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Compensate Transimpedance Amplifiers Intuitively
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA828ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA828
OPA828IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA828
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
