OPA832DBVR

OPA832 SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 Low-Power, Single-Supply, Fixed-Gain Video Buffer Amplifier FEATURES D HIGH BANDWIDTH: 80MHz (G = +2) D LOW SUPPLY CURRENT: 3.9mA D FLEXIBLE SUPPLY RANGE: D D D D D +2.8V to +11V Single Supply ±1.4V to ±5.5V Dual Supply INPUT RANGE INCLUDES GROUND ON SINGLE SUPPLY 4.9VPP OUTPUT SWING ON +5V SUPPLY HIGH SLEW RATE: 350V/µsec LOW INPUT VOLTAGE NOISE: 9.3nV/√Hz AVAILABLE IN AN SOT23 PACKAGE DESCRIPTION The OPA832 is a low-power, high-speed, fixed-gain amplifier designed to operate on a single +3.3V or +5V supply. Operation on ±5V or +10V supplies is also supported. The input range extends below ground and to within 1V of the positive supply. Using complementary common-emitter outputs provides an output swing to within 30mV of ground and 130mV of the positive supply. The high output drive current and low differential gain and phase errors also make it ideal for single-supply consumer video products. Low distortion operation is ensured by the high gain bandwidth product (200MHz) and slew rate (850V/µs), making the OPA832 an ideal input buffer stage to 3V and 5V CMOS converters. Unlike other low-power, single-supply amplifiers, distortion performance improves as the signal swing is decreased. A low 9.3nV/√Hz input voltage noise supports wide dynamic range operation. The OPA832 is available in an industry-standard SO-8 package. The OPA832 is also available in an ultra-small SOT23-5 package. For gains other than +1, −1, or +2, consider using the OPA830. APPLICATIONS D D D D SINGLE-SUPPLY VIDEO LINE DRIVERS CCD IMAGING CHANNELS LOW-POWER ULTRASOUND PORTABLE CONSUMER ELECTRONICS RELATED PRODUCTS DESCRIPTION Medium Speed Medium Speed, Fixed Gain SINGLES OPA830 — DUALS OPA2830 OPA2832 TRIPLES — OPA3832 QUADS OPA4830 — +3.3V Video DAC VI 976 Ω 75Ω LARGE−SIGNAL BANDWIDTH (1VPP AT MATCHED LOAD) 0 80.6Ω II OPA832 75 Ω Load 400 Ω VO 400 Ω VI VO −3 Gain (dB) −6 = 1V/V −9 Single-Supply, Low-Cost Video Line Driver 1 10 Frequency (MHz) 100 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003−2004, Texas Instruments Incorporated www.ti.com OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS(1) Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12VDC Internal Power Dissipation . . . . . . . . . See Thermal Characteristics Differential Input Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Input Voltage Range . . . . . . . . . . . . . . . . . . . . . −0.5V to +VS + 0.3V Storage Temperature Range: D, DBV . . . . . . . . . −40°C to +125°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 2000V Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . 1500V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Noninverting input to internal inverting node. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT OPA832 ″ OPA832 PACKAGE-LEAD SO-8 Surface-Mount ″ SOT23-5 PACKAGE DESIGNATOR D ″ DBV SPECIFIED TEMPERATURE RANGE −40°C to +85°C ″ −40°C to +85°C PACKAGE MARKING OPA832 ″ A74 ORDERING NUMBER OPA832ID OPA832IDR OPA832IDBVT TRANSPORT MEDIA, QUANTITY Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 ″ ″ ″ ″ ″ OPA832IDBVR Tape and Reel, 3000 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. PIN CONFIGURATIONS Output 1 5 +VS − VS NC Inverting Input Noninverting Input − VS 1 400Ω 2 3 4 SO−8 NC = No Connection 7 6 5 +VS 400Ω 8 NC Noninverting Input 2 400Ω 400Ω 4 3 SOT23−5 Inverting Input Output 5 NC 4 2 3 A74 Pin Orientation/Package Marking 1 2 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At TA = 25°C, G = +2, and RL = 150Ω to GND, unless otherwise noted (see Figure 3). OPA832ID, IDBV TYP PARAMETER AC PERFORMANCE (see Figure 3) Small-Signal Bandwidth Peaking at a Gain of +1 Slew Rate Rise Time Fall Time Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise NTSC Differential Gain NTSC Differential Phase DC PERFORMANCE(4) Gain Error Internal RF and RG Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Negative Input Voltage Range Positive Input Voltage Range Input Impedance Differential Mode Common-Mode OUTPUT Output Voltage Swing Current Output, Sinking Current Output, Sourcing Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: ID, IDBV Thermal Resistance D SO-8 DBV SOT23-5 RL = 1kΩ to GND RL = 150Ω to GND CONDITIONS G = +2, VO ≤ 0.5VPP G = −1, VO ≤ 0.5VPP VO ≤ 0.5VPP G = +2, 2V Step 0.5V Step 0.5V Step G = +2, 1V Step VO = 2VPP, 5MHz RL = 150Ω RL = 500Ω RL = 150Ω RL = 500Ω f > 1MHz f > 1MHz RL = 150Ω RL = 150Ω G = +2 G = −1 +25°C 80 99 4.2 350 4.6 4.9 45 −64 −66 −57 −73 9.2 2.2 0.10 0.16 ±0.3 ±0.2 400 400 ±1.4 — +5.5 ±0.1 — −5.4 3.2 10  2.1 400  1.2 ±4.9 ±4.6 85 85 120 0.2 ±1.4 — 4.25 4.25 68 −40 to +85 125 150 ±4.8 ±4.5 65 65 ±4.75 ±4.45 60 60 ±4.75 ±4.4 55 55 MIN/MAX OVER TEMPERATURE +25°C(1) 55 57 230 0°C to 70°C(2) 54 56 230 −40°C to +85°C(2) 54 56 220 UNITS MHz MHz dB V/µs ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz % ° % % Ω Ω %/°C mV µV/°C µA nA/°C µA nA/°C V V kΩ  pF kΩ  pF V V mA mA mA Ω V V mA mA dB °C °C/W °C/W MIN/ MAX min min typ min max max max max max max max max max typ typ min max max max max max max max max max max max min typ typ max max min min typ typ min max max min min typ typ typ TEST LEVEL(3) B B C B B B B B B B B B B C C A B A A B A B A B A B B A C C A A A A C C B A A A A C C C −60 −63 −50 −64 −60 −63 −49 −61 −60 −63 −48 −57 ±1.5 ±1.5 455 345 ±7 +10 ±1.5 ±1.6 ±1.6 460 340 ±0.1 ±8 ±20 +12 ±12 ±2 ±10 −5.0 3.0 ±1.7 ±1.7 462 338 ±0.1 ±8.5 ±20 +13 ±12 ±2.5 ±10 −4.9 2.9 −5.2 3.1 Output Shorted to Either Supply G = +2, f ≤ 100kHz VS = ±5V VS = ±5V Input-Referred ±5.5 4.7 4.0 63 ±5.5 5.3 3.6 62 ±5.5 5.9 3.3 61 (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. 3 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1). OPA832ID, IDBV TYP PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth Peaking at a Gain of +1 Slew Rate Rise Time Fall Time Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise NTSC Differential Gain NTSC Differential Phase DC PERFORMANCE(4) Gain Error Internal RF and RG, Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Input Impedance Differential-Mode Common-Mode OUTPUT Least Positive Output Voltage Most Positive Output Voltage Current Output, Sourcing Current Output, Sinking Short-Circuit Output Current Closed-Loop Output Impedance POWER SUPPLY Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: ID, IDBV Thermal Resistance D SO-8 DBV SOT23-5 (1) (2) MIN/MAX OVER TEMPERATURE +25°C(1) 56 60 230 0°C to 70°C(2) 55 58 223 −40°C to +85°C(2) 55 58 223 UNITS MHz MHz dB V/µs ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz % ° % % Ω Ω %/°C mV µV/°C µA nA/°C µA nA/°C V V kΩ  pF kΩ  pF 0.16 0.3 4.8 4.6 60 60 0.18 0.35 4.6 4.5 55 55 0.20 0.40 4.4 4.4 52 52 V V V V mA mA mA Ω V V mA mA dB °C °C/W °C/W MIN/ MAX min min typ min max max max max max max max max max typ typ min max max max max max max max max max max max min typ typ max max min min min min typ typ typ max max min min typ typ typ TEST LEVEL(3) B B C B B B B B B B B B B C C A B A A B A B A B A B B B C C A A A A A A C C C A A A A C C C CONDITIONS G = +2, VO ≤ 0.5VPP G = −1, VO ≤ 0.5VPP VO ≤ 0.5VPP G = +2, 2V Step 0.5V Step 0.5V Step G = +2, 1V Step VO = 2VPP, 5MHz RL = 150Ω RL = 500Ω RL = 150Ω RL = 500Ω f > 1MHz f > 1MHz RL = 150Ω RL = 150Ω G = +2 G = −1 +25°C 92 103 4.2 348 4.3 4.6 4.6 −59 −62 −56 −72 9.3 2.3 0.11 0.14 ±0.3 ±0.2 400 400 ±0.5 — 5.5 ±0.1 — −0.5 3.3 10  2.1 400  1.2 −56 −59 −50 −65 −56 −59 −49 −62 −55 −59 −47 −58 ±1.5 ±1.5 455 345 ±5 +10 ±1.5 VCM = 2.0V VCM = 2.0V ±1.6 ±1.6 460 340 0.1 ±6 ±20 +12 ±12 ±2 ±10 0 3.1 ±1.7 ±1.7 462 338 0.1 ±6.5 ±20 +13 ±12 ±2.5 ±10 +0.1 3.0 −0.2 3.2 RL = 1kΩ to 2.0V RL = 150Ω to 2.0V RL = 1kΩ to 2.0V RL = 150Ω to 2.0V Output Shorted to Either Supply G = +2, f ≤ 100kHz 0.03 0.18 4.94 4.86 80 80 100 0.2 +2.8 — 3.9 3.9 66 −40 to +85 125 150 VS = +5V VS = +5V Input-Referred +11 4.1 3.7 61 +11 4.8 3.5 60 +11 5.5 3.2 59 Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. 4 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +3.3V Boldface limits are tested at +25°C. At TA = 25°C, G = +2, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 2). OPA832ID, IDBV TYP PARAMETER AC PERFORMANCE (see Figure 2) Small-Signal Bandwidth Peaking at a Gain of +1 Slew Rate Rise Time Fall Time Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise DC PERFORMANCE(4) Gain Error Internal RF and RG Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Input Impedance, Differential-Mode Common-Mode OUTPUT Least Positive Output Voltage Most Positive Output Voltage Current Output, Sourcing Current Output, Sinking Short-Circuit Output Current Closed-Loop Output Impedance POWER SUPPLY Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (PSRR) THERMAL CHARACTERISTICS Specification: ID, IDBV Thermal Resistance D SO-8 DBV SOT23-5 RL = 1kΩ to 0.75V RL = 150Ω to 0.75V RL = 1kΩ to 0.75V RL = 150Ω to 0.75V CONDITIONS G = +2, VO ≤ 0.5VPP G = −1, VO ≤ 0.5VPP VO ≤ 0.5VPP 1V Step 0.5V Step 0.5V Step 1V Step 5MHz RL = 150Ω RL = 500Ω RL = 150Ω RL = 500Ω f > 1MHz f > 1MHz G = +2 G = −1 +25°C 95 103 4.2 170 4 4.2 48 −71 −74 −66 −69 9.4 2.4 ±0.3 ±0.2 400 400 ±1 MIN/MAX OVER TEMPERATURE +25°C(1) 59 63 115 0°C to 70°C(2) 57 61 115 UNITS MHz MHz dB V/µs ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz % % Ω Ω %/°C mV µV/°C µA nA/°C µA nA/°C V V kΩ  pF kΩ  pF V V V V mA mA mA Ω V V mA mA dB °C °C/W °C/W MIN/ MAX min min typ min max max max max max max max max max min max max max max max max max max max max max min typ typ max max min min min min typ typ typ max max min typ typ typ typ TEST LEVEL(3) B B C B B B B B B B B B B A B A A B A B A B A B B B C C B B B B A A C C C A A A C C C C −64 −70 −60 −66 −62 −66 −55 −62 ±1.5 ±1.5 455 345 ±7 +10 ±1.5 ±1.6 ±1.6 460 340 0.1 ±8 ±20 +12 ±12 ±2 ±10 −0.2 1.3 VCM = 0.75V VCM = 0.75V — 5.5 ±0.1 — −0.5 1.5 10  2.1 400  1.2 0.03 0.1 3 3 35 35 80 0.2 +2.8 — 3.8 3.8 60 −40 to +85 125 150 −0.3 1.4 0.16 0.3 2.8 2.8 25 25 0.18 0.35 2.6 2.6 20 20 Output Shorted to Either Supply See Figure 2, f < 100kHz VS = +3.3V VS = +3.3V Input-Referred +11 4.0 3.4 +11 4.7 3.2 (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. 5 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V At TA = 25°C, G = +2, and RL = 150Ω to GND, unless otherwise noted (see Figure 3). SMALL−SIGNAL FREQUENCY RESPONSE 3 0 Normalized Gain (dB) −3 −6 −9 G = +2 − 12 − 15 1 10 Frequency (MHz) 100 500 VO = 0.2VPP RL = 150Ω Normalized Gain (dB) 3 0 −3 −6 −9 LARGE−SIGNAL FREQUENCY RESPONSE RL = 150Ω G = +2V/V VO = 1VPP G = −1 VO = 0.5VPP VO = 4VPP − 12 − 15 1 10 Frequency (MHz) VO = 2VPP 100 400 SMALL−SIGNAL PULSE RESPONSE 150 Output Voltage (500mV/div) 100 50 0 − 50 − 100 − 150 Time (10ns/div) G = +2V/V RL = 150Ω VO = 0.2VPP 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 LARGE−SIGNAL PULSE RESPONSE G = +2V/V RL = 150Ω VO = 2VPP Output Voltage (50mV/div) Time (10ns/div) REQUIRED RS vs CAPACITIVE LOAD 1dB Peaking Targeted Normalized Gain to Capacitive Load (dB) 40 35 30 25 RS (Ω ) 20 15 10 5 0 10 100 Capacitive Load (pF) 1k 3 FREQUENCY RESPONSE vs CAPACITIVE LOAD CL = 10pF 0 −3 CL = 1000pF −6 C L = 100pF −9 VI OPA832 RS CL 1k Ω (1) − 12 − 15 1 NOTE: (1) 1kΩ is optional. 10 Frequency (MHz) 100 400 6 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = 25°C, G = +2, and RL = 150Ω to GND, unless otherwise noted (see Figure 3). HARMONIC DISTORTION vs LOAD RESISTANCE − 40 − 50 − 60 2nd−Harmonic − 70 3rd−Harmonic − 80 − 90 100 Load Resistance (Ω) 1k G = +2V/V VO = 2VPP f = 5MHz − 50 − 60 − 70 HARMONIC DISTORTION vs OUTPUT VOLTAGE G = +2V/V RL = 500Ω f = 5MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) 3rd−Harmonic − 80 2nd−Harmonic − 90 −100 0 1 2 3 4 5 6 7 8 9 10 Output Swing (VPP) HARMONIC DISTORTION vs FREQUENCY − 40 − 50 Harmonic Distortion (dBc) − 60 − 70 − 80 3rd−Harmonic − 90 − 100 − 110 0.1 1 Frequency (MHz) 10 20 G = +2V/V RL = 500Ω VO = 2VPP − 40 3rd−Order Spurious Level (dBc) − 45 − 50 − 55 − 60 − 65 − 70 − 75 − 80 − 85 − 90 − 26 − 22 PI TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS 50Ω OPA832 500Ω 400Ω 400Ω PO 2nd−Harmonic 20MHz 10MHz 5MHz − 18 − 14 − 10 −6 −2 2 6 Single−Tone Load Power (2dBm/div) OUTPUT VOLTAGE AND CURRENT LIMITATIONS 6 5 4 3 VO (V) 2 1 0 −1 −2 −3 −4 −5 −6 − 160 Output Current Limit 1W Internal P ower Limit 1W In ternal Power Limit OUTPUT SWING vs LOAD RESISTANCE 5 Maximum Output Voltage (V) 4 3 2 1 0 −1 −2 −3 −4 −5 10 100 RL (Ω ) 1k G = +2V/V VS = ± 5V Output Current Lim it RL = 500Ω RL = 50Ω RL = 100Ω − 120 − 80 − 40 0 I O (mA) 40 80 120 160 7 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = +5V At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1). SMALL−SIGNAL FREQUENCY RESPONSE 3 0 Normalized Gain (dB) −3 −6 −9 − 12 − 15 1 10 Frequency (MHz) 100 400 G = +2 VO = 0.2VPP RL = 150Ω Normalized Gain (dB) 3 0 −3 −6 −9 − 12 − 15 1 LARGE−SIGNAL FREQUENCY RESPONSE R L = 150Ω G = +2VPP VO = 2VPP VO = 1VPP G = −1 VO = 0.5VPP 10 Frequency (MHz) 100 400 SMALL−SIGNAL PULSE RESPONSE 0.15 Output Voltage (500mV/div) 0.10 0.05 0 − 0.05 − 0.10 − 0.15 Time (10ns/div) G = +2V/V RL = 150Ω VO = 0.2VPP 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 LARGE−SIGNAL PULSE RESPONSE G = +2V/V RL = 150Ω VO = 2VPP Output Voltage (50mV/div) Time (10ns/div) REQUIRED RS vs CAPACITIVE LOAD 1dB Peaking Targeted Normalized Gain to Capacitive Load (dB) 40 35 30 RS ( Ω ) 25 20 15 10 5 0 10 100 Capacitive Load (pF) 1k 3 FREQUENCY RESPONSE vs CAPACITIVE LOAD CL = 10pF 0 −3 −6 −9 − 12 − 15 − 18 1 NOTE: (1) 1kΩ is optional. VI CL = 1000pF CL = 100pF RS 1k Ω (1) CL 10 Frequency (MHz) 100 300 8 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = +5V (continued) At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1). HARMONIC DISTORTION vs LOAD RESISTANCE − 40 − 50 − 60 2nd−Harmonic − 70 − 80 − 90 100 Load Resistance (Ω ) 1k 3rd−Harmonic G = +2V/V VO = 2VPP f = 5MHz − 40 − 50 Harmonic Distortion (dBc) − 60 − 70 − 80 − 90 G = +2, HARMONIC DISTORTION vs FREQUENCY G = +2V/V RL = 500Ω VO = 2VPP 2nd−Harmonic Harmonic Distortion (dBc) 3rd−Harmonic − 100 − 110 0.1 1 Frequency (MHz) 10 20 HARMONIC DISTORTION vs OUTPUT VOLTAGE − 40 − 50 − 60 − 70 − 80 − 90 − 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Output Voltage Swing (VPP) 3rd−Harmonic 2nd−Harmonic G = +2V/V RL = 500Ω f = 5MHz Harmonic Distortion (dBc) − 30 − 40 − 50 − 60 − 70 G = − 1, HARMONIC DISTORTION vs FREQUENCY G = − 1V/V RL = 500Ω f = 5MHz Harmonic Distortion (dBc) 3rd−Harmonic − 80 − 90 − 100 − 110 0.1 1 Frequency (MHz) 10 20 2nd−Harmonic − 40 3rd−Order Spurious Level (dBc) − 45 − 50 − 55 − 60 − 65 − 70 − 75 − 80 − 85 − 90 PI 50Ω TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS 100 OPA832 500Ω INPUT VOLTAGE AND CURRENT NOISE Input Voltage Noise (nV/√ Hz) Input Current Noise (pA/ √ Hz) PO 10 Voltage Noise (9.3nV/√ Hz) 20MHz 10MHz 5MHz Current Noise (2.3nV/√ Hz) 1 100 1k 10k 100k 1M 10M − 24 − 22 − 20 − 18 − 16 − 14 − 12 − 10 − 8 Single−Tone Load Power (dBm) −6 −4 −2 Frequency (Hz) 9 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = +5V (continued) At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1). COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY 80 70 CMRR PSRR and CMRR (dB) 60 +PSRR dG/dP 50 40 30 20 10 COMPOSITE VIDEO dG/dP 1.2 +5V 1.0 0.8 VI OPA832 Video Loads dP 0.6 0.4 dG 0.2 0 0 100 1k 10k 100k Frequency (Hz) 1M 10M 100M 1 2 3 4 Number of 150Ω Loads OUTPUT SWING vs LOAD RESISTANCE 5.0 4.5 Maximum Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10 100 RL (Ω) 1k 0.1 100 G = +2V/V VS = +5V Output Impedance (Ω) CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY 400Ω +5V 400Ω 10 OPA832 ZO 1 200Ω 1k 10k 100k 1M 10M 100M Frequency (Hz) VOLTAGE RANGES vs TEMPERATURE 5.0 4.5 4.0 Voltage Ranges (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 50 0 50 90 Ambient Temperature (10_ C/div) Least Positive Output Voltage Least Positive Input Voltage Input Offset Voltage (mV) Most Positive Output Voltage Most Positive Input Voltage RL = 150Ω 1.0 0.8 0.6 0.4 0.2 0 − 0.2 − 0.4 − 0.6 − 0.8 − 1.0 − 40 TYPICAL DC DRIFT OVER TEMPERATURE 10 Bias Current (IB) 8 6 4 10 × Input Offset (IOS) 2 0 −2 Input Offset Voltage (VOS) −4 −6 −8 − 20 0 20 40 60 80 100 120 − 10 130 Input Bias and Offset Voltage (µA) Ambient Temperature (10_ C/div) 10 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = +5V (continued) At TA = 25°C, G = +2, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 1). SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 100 90 80 Output Current (mA) 70 60 50 40 30 20 10 0 − 40 − 20 130 0 20 40 60 80 100 120 Quiescent Current Output Current, Sinking Output Current, Sourcing 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 Ambient Temperature (_ C/div) Supply Current (mA) 11 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = +3.3V At TA = 25°C, G = +2, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 2). SMALL−SIGNAL FREQUENCY RESPONSE 3 0 Normalized Gain (dB) −3 G = +2 −6 −9 − 12 − 15 1 10 Frequency (MHz) 100 300 VO = 0.2VPP RL = 150Ω Normalized Gain (dB) G = −1 3 0 −3 LARGE−SIGNAL FREQUENCY RESPONSE RL = 150Ω G = +2V/V VO = 1VPP VO = 0.5VPP −6 −9 − 12 − 15 1 10 Frequency (MHz) 100 300 VO = 2VPP SMALL−SIGNAL PULSE RESPONSE 1.65 1.60 Output Voltage (V) 1.55 1.50 1.45 1.40 1.35 Time (10ns/div) G = +2V/V RL = 150Ω VO = 200mVPP Output Voltage (V) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 LARGE−SIGNAL PULSE RESPONSE G = +2V/V RL = 150Ω VO = 1VPP Time (10ns/div) REQUIRED RS vs CAPACITIVE LOAD 1dB Peaking Targeted Normalized Gain to Capacitive Load (dB) 60 50 40 RS ( Ω ) 30 20 10 0 1 10 100 1k Capacitive Load (pF) 3 FREQUENCY RESPONSE vs CAPACITIVE LOAD CL = 10pF 0 −3 −6 CL = 100pF −9 − 12 − 15 1 10 Frequency (MHz) 100 300 C L = 1000pF 12 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS: VS = +3.3V (continued) At TA = 25°C, G = +2, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 2). HARMONIC DISTORTION vs LOAD RESISTANCE − 50 − 55 − 60 3rd−Harmonic − 65 − 70 − 75 − 80 100 Load Resistance (Ω) 1k 2nd−Harmonic G = +2V/V VO = 1VPP f = 5MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE − 40 − 50 − 60 − 70 2nd−Harmonic − 80 − 90 − 100 0.50 0.75 1.00 1.25 1.50 Output Voltage Swing (V) G = +2V/V RL = 500Ω f = 5MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) 3rd−Harmonic HARMONIC DISTORTION vs FREQUENCY − 40 − 50 Harmonic Distortion (dBc) − 60 − 70 − 80 2nd−Harmonic − 90 − 100 − 110 0.1 1 Frequency (MHz) 10 20 3rd−Harmonic G = +2V/V RL = 500Ω VO = 1VPP − 40 3rd−Order Spurious Level (dBc) − 45 − 50 − 55 − 60 − 65 − 70 − 75 − 80 − 85 − 90 − 26 − 24 PI TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS 50Ω OPA832 500Ω PO 20MHz 10MHz 5MHz − 22 − 20 − 18 − 16 − 14 − 12 − 10 −8 Single−Tone Load Power (dBm) OUTPUT SWING vs LOAD RESISTANCE 3.3 3.0 Maximum Output Voltage (V) 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 10 100 RL (Ω ) 1k Least Positive Output Voltage G = +2V/V VS = +3.3V Most Positive Output Voltage 13 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 APPLICATIONS INFORMATION WIDEBAND VOLTAGE-FEEDBACK OPERATION The OPA832 is a fixed-gain, high-speed, voltagefeedback op amp designed for single-supply operation (+3V to +10V). It features internal RF and RG resistors which make it easy to select a gain of +2, +1, and −1 without external resistors.The input stage supports input voltages below ground and to within 1.7V of the positive supply. The complementary common-emitter output stage provides an output swing to within 25mV of either supply pin. The OPA832 is compensated to provide stable operation with a wide range of resistive loads. Figure 1 shows the AC-coupled, gain of +2 configuration used for the +5V Specifications and Typical Characteristic Curves. The input impedance matching resistor (66.5Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins. For the circuit of Figure 1, the total effective load on the output at high frequencies is 150Ω || 800Ω. The 332Ω and 499Ω resistors at the noninverting input provide the common-mode bias voltage. Their parallel combination equals the DC resistance at the inverting input (RF RG), reducing the DC output offset due to input bias current. Electrical Characteristics are taken directly at the input and output pins. For the circuit of Figure 2, the total effective load on the output at high frequencies is 150Ω || 800Ω. The 887Ω and 258Ω resistors at the noninverting input provide the common-mode bias voltage. Their parallel combination equals the DC resistance at the inverting input (RF RG), reducing the DC output offset due to input bias current. VS = +3.3V 6.8µF + 887Ω 0.1µF 0.1µF VIN 66.5Ω VCM = 0.75V 258Ω OPA832 VOUT RL 150Ω RG 400Ω RF 400Ω VCM = 0.75V VCM = 0.75V Figure 2. AC-Coupled, G = +2, +3.3V Single-Supply Specification and Test Circuit VS = +5V 6.8µF + 499Ω 0.1µF VIN 66.5Ω 0.1µF VCM = 2V 332Ω OPA832 RL 150Ω VOUT RG 400Ω VCM = 2V RF 400Ω VCM = 2V Figure 1. AC-Coupled, G = +2, +5V Single-Supply Specification and Test Circuit Figure 2 shows the AC-coupled, gain of +2 configuration used for the +3.3V Specifications and Typical Characteristic Curves. The input impedance matching resistor (66.5Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. Voltage swings reported in the 14 Figure 3 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5V Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins. For the circuit of Figure 3, the total effective load will be 150Ω || 800Ω. Two optional components are included in Figure 3. An additional resistor (175Ω) is included in series with the noninverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 200Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power-supply decoupling capacitors to ground, a 0.01µF capacitor is included between the two power-supply pins. In practical PC board layouts, this optionally-added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 +5V 0.1µ F 6.8µ F + transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC performance. 50Ω Source VIN 0.01µF 175Ω GAIN OF +2V/V VIDEO LINE DRIVER OPA832 150Ω RF 400Ω RG 400Ω + − 5V 6.8µ F 0.1µ F Video In +5V VOUT 50Ω One of the most suitable applicarions for the OPA832 is a simple gain of 2 video line driver. Figure 4 shows how simple this circuit is to implement, shown as a ±5V implementation. Single +5V operation is similar with blocking caps and DC common-mode biasing provided. OPA832 Video Loads Optional 1.3kΩ Pull−Down Figure 3. DC-Coupled, G = +2, Bipolar Supply Specification and Test Circuit − 5V DESIGN-IN TOOLS DEMONSTRATION BOARDS Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA832 in its two package styles. All of these are available, free, as unpopulated PC boards delivered with descriptive documentation. The summary information for these boards is shown in Table 1. Figure 4. Gain of 2 Video Line Driver One optional element is shown in Figure 4. A 1.3kΩ pull-down to the negative supply will improve the differential phase significantly and the differential gain slightly. Figure 5 shows measured dG/dP with and without that pull-down resistor from 1 to 4 video loads. Table 1. Demo Board Availability PRODUCT OPA832ID OPA832IDBV PACKAGE SO-8 SOT23-5 DEMO BOARD NUMBER DEM-OPA68xU DEM-OPA6xxN ORDERING NUMBER SBOU009 dG/dP 1.2 +5V 1.0 0.8 0.6 Video In OPA832 V ide o L oa ds O ptio nal 1.3k Ω Pull−Down − 5V SBOU010 dP 0.4 dP Go to the TI web site (www.ti.com) to request evaluation boards through the OPA832 product folder. dG 0.2 dG 0 No Pull−Down With 1.3kΩ Pull−Down 3 4 MACROMODEL AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA832 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA832 is available through the TI web page (www.ti.com). The applications department is also available for design assistance. These models predict typical small signal AC, 1 2 Number of 150Ω Loads Figure 5. dG/dP vs Video Loads 15 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 SINGLE-SUPPLY ADC INTERFACE The circuit shown in Figure 6 uses the OPA832 as a differential driver followed by an RC filter. In this circuit, the single-ended to differential conversion is realized by a 1:1 transformer driving the noninverting inputs of the two OPA832s. The common-mode level (CML) of the ADS5203 is reduced to the appropriate input level of 0.885V by the network divider composed of R1 and the CML output impedance, and connected to the transformer center tap, biasing the OPA832s. This input bias voltage is then amplified to provide the correct common-mode voltage to the input of the ADC. Using only 25.1mW power (3.8mA × 2 amplifiers × 3.3V), this configuration (amplifier + ADC) provides greater than 59dB SNR and 70dB SFDR to 2MHz, with all the components running on a low +3.3V supply. +3.3V RT 20Ω OPA832 RS 50Ω +3.3V IN VIN 50Ω Source 1:1 RM 50Ω RG 400Ω RF 400Ω C 15pF 1/2 ADS5203 10−Bit 40MSPS +3.3V RT 20Ω OPA832 RS 50Ω IN CML 2.3kΩ Output Impedance VCM = 0.885V RI 1.91kΩ C1 0.1µ F RG 400Ω RF 400Ω Figure 6. Low-Power, Single-Supply ADC Driver 16 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 This circuit removes the peaking by bootstrapping out any parasitic effects on RG. The input impedance is still set by RM as the apparent impedance looking into RG is very high. RM may be increased to show a higher input impedance, but larger values will start to impact DC output offset voltage. This circuit creates an additional input offset voltage as the difference in the two input bias current times the impedance to ground at VIN. Figure 8 shows a comparison of small-signal frequency response for the unity-gain buffer of Figure 2 (with VCM removed from RG) compared to the improved approach shown in Figure 7. OPERATING SUGGESTIONS GAIN SETTING Setting the gain for the OPA832 is very easy. For a gain of +2, ground the −IN pin and drive the +IN pin with the signal. For a gain of +1, either leave the −IN pin open and drive the +IN pin or drive both the +IN and −IN pins as shown in Figure 7. For a gain of −1, ground the +IN pin and drive the −IN pin with the input signal. An external resistor may be used in series with the −IN pin to reduce the gain. However, since the internal resistors (RF and RG) have a tolerance and temperature drift different than the external resistor, the absolute gain accuracy and gain drift over temperature will be relatively poor compared to the previously described standard gain connections using no external resistor. +5V RO 75Ω OPA832 VOUT OUTPUT CURRENT AND VOLTAGES The OPA832 provides outstanding output voltage capability. Under no-load conditions at +25°C, the output voltage typically swings closer than 90mV to either supply rail. The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the min/max tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBEs (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally be a problem, since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power-supply pin (8-pin packages) will possibly destroy the amplifier. If additional short-circuit protection is required, consider a small series resistor in the power-supply leads. This will reduce the available output voltage swing under heavy output loads. RG 400Ω VIN RM 50Ω RF 400Ω Figure 7. Improved Unity-Gain Buffer UNITY-GAIN BUFFER This buffer can simply be realized by not connecting RG to ground. This type of realization shows a peaking in the frequency response. A similar circuit that holds a flat frequency response giving improved pulse fidelity is shown in Figure 7. 6 3 0 Gain (dB) −3 −6 −9 − 12 1 10 Frequency (MHz) 100 400 G = +1 Buffer RG Floating G = +1 Buffer Figure 5 DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA832 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the primary considerations are frequency response flatness, pulse response fidelity, 17 Figure 8. Buffer Frequency Response Comparison OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. The Typical Characteristic curves show the recommended RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA832. Long PC board traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the output pin (see the Board Layout Guidelines section). The criterion for setting this RS resistor is a 1dB peaked frequency response at the load. Increasing the noise gain will also reduce the peaking (see Figure 7). NOISE PERFORMANCE Unity-gain stable, rail-to-rail (RR) output, voltage-feedback op amps usually show a higher input noise voltage. The 9.2nV/√Hz input voltage noise for the OPA832 however, is much lower than comparable amplifiers. The input-referred voltage noise and the two input-referred current noise terms (2.8pA/√Hz) combine to give low output noise under a wide variety of operating conditions. Figure 10 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI DISTORTION PERFORMANCE The OPA832 provides good distortion performance into a 150Ω load. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +3.3V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the noninverting configuration (see Figure 3) this is sum of RF + RG, while in the inverting configuration, only RF needs to be included in parallel with the actual load. Figure 9 shows the 2nd- and 3rd-harmonic distortion versus supply voltage. In order to maintain the input signal within acceptable operating range, the input common-mode voltage is adjusted for each supply voltage. For example, the common-mode voltage is +2V for a single +5V supply, and the distortion is −66.5dBc for the 2nd-harmonic and −74.6dBc for the 3rd-harmonic. RS OPA832 IBN EO ERS √ 4kTRS RF √ 4kTRF 4kT = 1.6E − 20J at 290_ K 4kT RG RG I BI Figure 10. Noise Analysis Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 10: EO + E NI ) I BNRS 2 2 ) 4kTRS NG 2 ) I BIR F 2 ) 4kTRFNG −66 −67 Harmonic Distortion (dBc) −68 −69 −70 −71 −72 −73 −74 −75 −76 5 2nd−Harmonic Left Scale 4.5 4.0 3.5 3.0 2.5 G = +2V/V RL = 500Ω VO = 2VPP f = 5MHz 8 9 10 11 2.0 1.5 1.0 0.5 6 7 Supply Voltage (V) Common−Mode Voltage (V) Common−Mode Voltage Right Scale 5.5 5.0 (1) Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 2: EN + ENI ) IBNR S ) 4kTRS ) 2 2 IBIRF NG 2 ) 4kTRF NG 3rd−Harmonic Left Scale (2) Figure 9. 5MHz Harmonic Distortion vs Supply Voltage Evaluating these two equations for the circuit and component values shown in Figure 1 will give a total output spot noise voltage of 19.3nV/√Hz and a total equivalent input spot noise voltage of 9.65nV/√Hz. This is including the noise added by the resistors. This total input-referred spot noise voltage is not much higher than the 9.2nV/√Hz specification for the op amp voltage noise alone. 18 OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage-feedback op amp allows good output DC accuracy in a wide variety of applications. The power-supply current trim for the OPA832 gives even tighter control than comparable products. Although the high-speed input stage does require relatively high input bias current (typically 5µA out of each input terminal), the close matching between them may be used to reduce the output DC error caused by this current. This is done by matching the DC source resistances appearing at the two inputs. Evaluating the configuration of Figure 3 (which has matched DC input resistances), using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: Note that it is the power in the output stage, and not into the load, that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA832 (SOT23-5 package) in the circuit of Figure 3 operating at the maximum specified ambient temperature of +85°C and driving a 150Ω load at mid-supply. PD = 10V × 3.9mA + 52/(16 × (150Ω || 400Ω)) = 53.3mW Maximum TJ = +85°C + (0.053W × 150°C/W) = 93°C. (NG = noninverting signal gain at DC) ±(NG × VOS(MAX)) ± (RF × IOS(MAX)) = ±(2 × 10mV) ± (400Ω × 1.5µA) = ±10.6mV A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques are based on adding a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input may be considered. Bring the DC offsetting current into the inverting input node through resistor values that are much larger than the signal path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower ensured junction temperatures. The highest possible internal dissipation will occur if the load requires current to be forced into the output at high output voltages or sourced from the output at low output voltages. This puts a high current through a large internal voltage drop in the output transistors. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA832 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance ( < 0.25”) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Each powersupply connection should always be decoupled with one of these capacitors. An optional supply decoupling capacitor (0.1µF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good highfrequency performance. Again, keep their leads and PC 19 THERMAL ANALYSIS Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + P D × q JA. The total internal power dissipation (P D) is the sum of quiescent power (P DQ ) and additional power dissipated in the output stage (P DL ) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load; though, for resistive loads connected to mid-supply (V S/2), PDL is at a maximum when the output is fixed at a voltage equal to VS/4 or 3V S/4. Under this condition, PDL = V S2 /(16 × R L ), where RL includes feedback network loading. OPA832 www.ti.com SBOS266B − JUNE 2003 − REVISED SEPTEMBER 2004 board traces as short as possible. Never use wire-wound type resistors in a high-frequency application. Since the output pin is the most sensitive to parasitic capacitance, always position the series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the typical characteristic curve Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA832 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA832 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the typical characteristic curve Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA832 onto the board. INPUT AND ESD PROTECTION The OPA832 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 11. +VCC External Pin Internal Circuitry − VCC Figure 11. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (that is, in systems with ±15V supply parts driving into the OPA832), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and frequency response. 20 PACKAGE OPTION ADDENDUM www.ti.com 15−Sep−2004 PACKAGING INFORMATION ORDERABLE DEVICE OPA832ID OPA832IDR OPA832DBVT OPA832DBVR STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE SO− 8 SO− 8 SOT23 SOT23 PACKAGE DRAWING D D DBV DBV PINS 8 8 5 5 PACKAGE QTY 100 2500 250 3000 ECO−STATUS(2) N/A N/A Pb− Free, Green Pb− Free, Green (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime− period is in effect. buy NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco− Status information  Additional details including specific material content can be accessed at www.ti.com/leadfree GREEN: Ti defines Green to mean Lead (Pb)− Free and in addition, uses less package materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)− Free; for estimated conversion dates, go to www.ti.com/leadfree. Pb− FREE: Ti defines Lead (Pb)− Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead− free soldering processes. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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