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OPA838
SBOS867B – AUGUST 2017 – REVISED OCTOBER 2018
OPA838 1-mA, 300-MHz Gain Bandwidth, Voltage-Feedback Op Amp
1 Features
3 Description
•
•
•
•
•
•
•
•
The OPA838 decompensated voltage feedback
operational amplifier provides a high 300-MHz gain
bandwidth product with 1.8-nV/√Hz input noise
voltage, requiring only a trimmed 0.95-mA supply
current. These features combine to provide an
extremely power-efficient solution for photodiode
transimpedance designs and high-voltage gain
stages, which require the lowest input voltage noise
in signal receiver applications.
1
•
•
•
Gain Bandwidth Product: 300 MHz
Very-Low (Trimmed) Supply Current: 950 µA
Bandwidth: 90 MHz (AV = 6 V/V)
High Full-Power Bandwidth: 45 MHz, 4 VPP
Negative Rail Input, Rail-to-Rail Output
Single-Supply Operating Range: 2.7 V to 5.4 V
25°C Input Offset: ±125 µV (Maximum)
Input Offset Voltage Drift: < ±1.6 µV/°C
(Maximum)
Input Voltage Noise: 1.8 nV/√Hz (> 200 Hz)
Input Current Noise: 1 pA/√Hz (> 2000 Hz)
< 1-µA Shutdown Current for Power Savings
Operating
at
the
minimum
recommended
noninverting gain of 6 V/V results in a 90-MHz, –3-dB
bandwidth. Extremely low input noise and offset
voltage make the OPA838 particularly suitable for
high gains. Even at a DC-coupled gain of 1000 V/V, a
300-kHz signal bandwidth is available with a
maximum output offset voltage of ±125 mV.
2 Applications
•
•
•
•
•
The single-channel OPA838 is available in 6-pin
SOT-23 and SC70 packages with a power shutdown
feature and a 5-pin SC70 package.
Low-Power Transimpedance Amplifiers
Low-Noise High-Gain Stages
12-Bit to 16-Bit Low-Power SAR ADC Drivers
High-Gain Active Filter Designs
Ultrasonic Flow Meters
Device Information(1)
PART NUMBER
OPA838
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SC70 (6)
2.00 mm × 1.25 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SPACE
SPACE
Single 3-V Supply, < 3-mW Photodiode Amplifier With
< 1.1-pA/√Hz Total Input-Referred Current Noise and 100-kΩ Gain With Overall 1-MHz SSBW
1 pF
Large Area Photodetector
With 100-pF Capacitance
100 k
VCC = 3 V
73.2
VOUT
+
2.2 nF
100 k
Diode
Current
Direction
100 nF
100 pF
±
1-MHz
Post Filter
-VBIAS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA838
SBOS867B – AUGUST 2017 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: VS = 5 V........................... 6
Electrical Characteristics: VS = 3 V........................... 8
Typical Characteristics: VS = 5 V ............................ 10
Typical Characteristics: VS = 3 V ............................ 13
Typical Characteristics: Over Supply Range .......... 16
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2
8.3
8.4
8.5
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Power Shutdown Operation ....................................
20
20
24
27
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 Device and Documentation Support ................. 38
12.1
12.2
12.3
12.4
12.5
Device Support ....................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
39
39
39
13 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2018) to Revision B
Page
•
Changed < 5-µA Shutdown Current to < 1-µA Shutdown Current in Features section ......................................................... 1
•
Changed value of common-mode and differential-mode input impedance in Electrical Characterictics: VS = 5 V
and Electrical Characterictics: VS = 3 V tables....................................................................................................................... 7
•
Changed value of power-down quiescent current in Electrical Characteristics: VS = 5 V and Electrical
Characteristics: VS = 3 V tables.............................................................................................................................................. 7
•
Changed 5 µA to 1 µA in Overview section ........................................................................................................................ 20
•
Changed standby current from 5 µA to 1 µA in Power-Down Operation section................................................................. 21
•
Changed common-mode input capacitance from 1.3 pF to 1 pF in Trade-Offs in Selecting The Feedback Resistor
Value section ........................................................................................................................................................................ 22
•
Changed 1 + 6.3 / 1.2 = 6.25 V/V, adding the 1.3-pF device common-mode capacitance to 1 + 6 / 1.2 = 6 V/V,
adding the 1-pF device common-mode capacitance in Trade-Offs in Selecting The Feedback Resistor Value section..... 22
•
Changed 2 µA to 0.1 µA and 5 µA to 1 µA in last sentence of Power Shutdown Operation section .................................. 27
•
Changed Power Supply Recommendations and Thermal Notes title to Power Supply Recommendations ....................... 36
Changes from Original (August 2017) to Revision A
Page
•
Added OPA837 to the Device Comparison table ................................................................................................................... 4
•
Changed Device Comparison table note................................................................................................................................ 4
•
Changed format of pin names in pinout drawings in Pin Configuration and Functions section ............................................ 4
•
Added DCK to pinout description in 6-pin SOT-23 and SC70 pinout drawing ....................................................................... 4
•
Changed I/O column header to "TYPE" in Pin Configuration and Functions section ........................................................... 4
•
Added table note to table to define pin types in Pin Configuration and Functions section ................................................... 4
•
Added table note to Absolute Maximum Ratings table ......................................................................................................... 5
•
Changed bandwidth for 0.1-dB flatness test condition from VOUT = 2 VPP and G = 10 to VOUT = 200 mVPP and G = 6
in the Electrical Characteristics: VS = 5 V table...................................................................................................................... 6
•
Added values for VOH and VOL parameters at TA = -40 to +125°C in Electrical Characteristics: VS = 5 V table.................... 7
2
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SBOS867B – AUGUST 2017 – REVISED OCTOBER 2018
•
Changed typical bandwidth for 0.1-dB flatness from 5 MHz to 9 MHz in Electrical Characteristics: VS = 3 V table ............. 8
•
Changed bandwidth for 0.1-dB flatness test conditions from VOUT = 2 VPP and G = 10 to VOUT = 200 mVPP and G = 6
in Electrical Characteristics: VS = 3 V table .......................................................................................................................... 8
•
Added values for VOH and VOL parameters at TA = -40 to +125°C in Electrical Characteristics: VS = 3 V table ................... 9
•
Changed VO test condition from 20 mV to 200 mV in Figure 5............................................................................................ 10
•
Changed VO test condition from 20 mV to 200 mV in Figure 6............................................................................................ 10
•
Changed test conditions from VOUT = 2 VPP, RF = 0 Ω, G = 1 V/V to RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V in
Typical Characteristics: VS = 3 V section ............................................................................................................................. 13
•
Changed VO test condition from 20 mV to 200 mV in Figure 23.......................................................................................... 13
•
Changed VO test condition from 20 mV to 200 mV in Figure 24.......................................................................................... 13
•
Added condition statement to Typical Characteristics: Over Supply Range ....................................................................... 16
•
Changed Y-axis label from "Disable and Vo (Bipolar supplies)" to "Disable and VOUT (Bipolar Supplies, Volts)" in
Figure 51............................................................................................................................................................................... 17
•
Changed Y-axis label from "PD and Output Voltages" to " Disable and VOUT (Bipolar Supplies, Volts)" in Figure 52 ........ 17
•
Deleted 5-V supply and changed the Y-axis label of Figure 57 .......................................................................................... 18
•
Changed specification load value from 1-kΩ to 2-kΩ in Output Voltage Range section...................................................... 21
•
Changed first paragraph to correct power down logic in Power-Down Operation section................................................... 21
•
Changed image references in Power-Down Operation section ........................................................................................... 21
•
Changed V1 value from 2.5 Ω to 2.5 V in Figure 64 ............................................................................................................ 22
•
Changed V2 value from 2.5 Ω to –2.5 V in Figure 64 .......................................................................................................... 22
•
Changed V1 value from 2.5 Ω to 2.5 V, changed V2 value from 2.5 Ω to –2.5 V, and changed ROUT to RLOAD in
Figure 66 ............................................................................................................................................................................. 23
•
Changed VOUT input signal from ±.035 VOUT to ±0.35 VIN in Figure 68 ................................................................................ 24
•
Changed V1 value from 4.5 Ω to 4.5 V in Figure 70 ............................................................................................................ 25
•
Changed VEE to ground in Figure 70 ................................................................................................................................... 25
•
Changed V1 value from 3 Ω to 3 V in Figure 72 .................................................................................................................. 26
•
Updated Single-Supply Op Amp Design Techniques application report link in Device Functional Modes section ............. 27
•
Changed "Cs" and "Cf" to "CS" and "CF" in Application Information section ........................................................................ 34
•
Updated Transimpedance Considerations for High-Speed Amplifiers application report link in Detailed Design
Procedure section................................................................................................................................................................. 35
•
Changed EVM guide link in Layout Guidelines section........................................................................................................ 37
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SBOS867B – AUGUST 2017 – REVISED OCTOBER 2018
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Device Comparison Table (1)
5
5-V IQ
(mA, MAXIMUM
25°C)
INPUT NOISE
VOLTAGE
(nV/√Hz)
2-VPP THD
(dBc, 100 kHz)
RAIL-TO-RAIL
INPUT/OUTPUT
300
0.99
1.9
–110
Negative in/out
None
50
0.625
4.7
–120
Negative in/out
OPA2837
OPA835
30
0.35
9.3
–100
Negative in/out
OPA2835
OPA836
110
1
4.8
–115
Negative in/out
OPA2836
LMP7717
88
1.4
5.8
—
Negative in/out
LMP7718
OPA830
100
4.7
9.5
–105
Negative in/out
OPA2830
THS4281
38
0.93
12.5
12.5
In/out
None
PART NUMBER
GBP (MHz)
OPA838
OPA837
(1)
DUALS
For a complete selection of TI high-speed amplifiers, visit www.ti.com
6 Pin Configuration and Functions
DBV and DCK Package
6-Pin SOT-23 and SC70
Top View
DCK Package
5-Pin SC70
Top View
VOUT
1
6
VS+
VS-
2
5
PD
VIN+
3
4
VIN-
VOUT
1
VS-
2
VIN+
3
5
VS+
4
VIN-
Pin Functions
PIN
TYPE (1)
DESCRIPTION
SOT-23 and
SC70
SC70
PD
5
—
I/O
Amplifier power down.
Low = disabled, high = normal operation (pin must be driven).
VIN–
4
4
I/O
Inverting input pin
VIN+
3
3
I/O
Noninverting input pin
VOUT
1
1
I/O
Output pin
VS–
2
2
P
Negative power-supply pin
VS+
6
5
P
Positive power-supply input
NAME
(1)
4
I = input, O = output, and P = power.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS– to VS+
MAX
Supply voltage
Supply turnon, off maximum dV/dT
VI
Input voltage
VID
UNIT
5.5
(2)
V
1
VS– – 0.5
V/µs
VS+ + 0.5
V
Differential input voltage
±1
V
II
Continuous input current
±10
mA
IO
Continuous output current (3)
±20
mA
Continuous power dissipation
See Thermal Information
TJ
Maximum junction temperature
150
°C
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Staying below this ± supply turn-on edge rate prevents the edge-triggered ESD absorption device across the supply pins from turning
on.
Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VS+
Single-supply voltage
2.7
5
5.4
V
TA
Ambient temperature
–40
25
125
°C
7.4 Thermal Information
OPA838
THERMAL METRIC
(1)
DBV
(SOT-23)
DCK
(SC70)
DCKS
(SC70)
UNIT
6 PINS
5 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
194
203
189
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
129
152
150
°C/W
RθJB
Junction-to-board thermal resistance
39
76
79
°C/W
ψJT
Junction-to-top characterization parameter
26
58
61
°C/W
ψJB
Junction-to-board characterization parameter
39
76
79
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: VS = 5 V
at VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
75
90
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
VOUT = 20 mVPP, G = 6, (peaking < 4 dB)
SSBW
Small-signal bandwidth
VOUT = 20 mVPP, G = 10, RF = 1.6 kΩ
VOUT = 20 mVPP, G = 100, RF = 16.9 kΩ
GBP
Gain-bandwidth product
VOUT = 20 mVPP, G = 100
LSBW
Large-signal bandwidth
C
50
MHz
3
C
300
MHz
C
VOUT = 2 VPP, G = 6
45
MHz
C
Bandwidth for 0.1-dB flatness
VOUT = 200 mVPP, G = 6
10
MHz
C
Slew rate
From LSBW (2)
350
V/µs
C
Overshoot, undershoot
VOUT = 2-V step, G = 6, input tR = 12 ns
Rise, fall time
VOUT = 2-V step, G = 6, RL = 2 kΩ,
input tR = 12 ns
Settling time to 0.1%
VOUT = 2-V step, G = 6, input tR = 12 ns
Settling time to 0.01%
VOUT = 2-V step, G = 6, input tR = 12 ns
HD2
Second-order harmonic distortion
f = 100 kHz, VO = 4 VPP, G = 6 (see Figure 74)
HD3
Third-order harmonic distortion
f = 100 kHz, VO = 4 VPP, G = 6 (see Figure 74)
Input voltage noise
f > 1 kHz
SR
tR, tF
240
C
250
Voltage noise 1/f corner frequency
Input current noise
f > 100 kHz
Current noise 1/f corner frequency
1%
2%
12.5
13
C
ns
C
30
ns
C
40
ns
C
–110
dBc
C
–120
dBc
C
1.8
nV/√Hz
C
100
Hz
C
1
pA/√Hz
C
7
kHz
C
Overdrive recovery time
G = 6, 2x output overdrive, DC-coupled
50
ns
C
Closed-loop output impedance
f = 1 MHz, G = 6
0.3
Ω
C
dB
A
DC PERFORMANCE
AOL
Open-loop voltage gain
Input-referred offset voltage
Input offset voltage drift (3)
VO = ±2 V, RL = 2 kΩ
120
125
TA ≈ 25°C
–125
±15
125
TA = 0°C to 70°C
–165
±15
200
TA = –40°C to 85°C
–230
±15
220
TA = –40°C to 125°C
–230
±15
285
TA = –40°C to 125°C (4)
–1.6
±0.4
1.6
0.7
1.5
2.8
TA = 0°C to 70°C
.2
1.5
3.5
TA = –40°C to 85°C
.2
1.5
3.7
TA = –40°C to 125°C
.2
1.5
4.4
TA = –40°C to 125°C
4.5
7.8
17
TA ≈ 25°C
–70
±20
70
TA = 0°C to 70°C
–83
±20
93
TA = –40°C to 85°C
–105
±20
100
TA = –40°C to 125°C
–105
±20
120
TA = –40°C to 125°C
–500
±40
500
TA ≈ 25°C
Input bias current (5)
Input bias current drift (3)
Input offset current
Input offset current drift (3)
(1)
(2)
(3)
(4)
(5)
6
A
µV
B
B
B
µV/°C
B
A
µA
B
B
B
nA/°C
B
A
nA
B
B
B
pA/°C
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB
where this f–3dB is the typical measured 4-VPP bandwidth at gains of 6 V/V.
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
Input offset voltage drift, input bias current drift, and input offset current drift typical specifications are mean ± 1σ characterized by the full
temperature range end-point data. Maximum drift specifications are set by the min, max packaged test range on the wafer-level
screened drift. Drift is not specified by the final automated test equipment (ATE) or by QA sample testing.
Current is considered positive out of the pin.
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Electrical Characteristics: VS = 5 V (continued)
at VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VS– – 0.2
VS– – 0
UNIT
TEST
LEVEL (1)
INPUT
Common-mode input range, low
Common-mode input range, high
CMRR
TA ≈ 25°C, CMRR > 92 dB
TA = –40°C to 125°C, CMRR > 92 dB
TA ≈ 25°C, CMRR > 92 dB
VS– – 0
VS+ – 1.3
TA = –40°C to 125°C, CMRR > 92 dB
Common-mode rejection ratio
VS+ – 1.2
V
VS+ – 1.3
95
Input impedance common-mode
Input impedance differential mode
V
105
A
B
A
B
dB
A
35 || 1
MΩ || pF
C
30 || 1.3
kΩ || pF
C
OUTPUT
VOL
Output voltage, low
VOH
Output voltage, high
Maximum current into a resistive
load
TA ≈ 25°C, G = 6
VS– + 0.05
VS– + 0.1
TA = –40°C to 125°C, G = 6
VS– + 0.05
VS– + 0.1
TA ≈ 25°C, G = 6
VS+ – 0.1
VS+ – 0.05
TA = –40°C to 125°C, G = 6
VS+ – 0.2
VS+ – 0.1
TA ≈ 25°C, ±1.53 V into 41.3 Ω, VIO < 2 mV
±35
±40
TA ≈ 25°C, ±1.81 V into 70.6 Ω, AOL > 80 dB
±25
±28
Linear current into a resistive load
TA = –40°C to 125°C, ±1.58 V into 70.6 Ω, AOL
> 80 dB
DC output impedance
G=6
±22
V
V
mA
A
B
A
B
A
A
mA
±25
0.02
B
Ω
C
V
B
POWER SUPPLY
Specified operating voltage
Quiescent operating current
2.7
5
5.4
913
960
993
TA = –40°C to 125°C
700
960
1330
TA = –40°C to 125°C
2.6
3
3.4
TA ≈ 25°C
(6)
dIq/dT
Quiescent current temperature
coefficient
+PSRR
Positive power-supply rejection
ratio
98
–PSRR
Negative power-supply rejection
ratio
93
µA
A
B
µA/°C
B
110
dB
A
105
dB
A
POWER DOWN (Pin Must be Driven, SOT23-6 and SC70-6)
(6)
Enable voltage threshold
Specified on above VS–+ 1.5 V
Disable voltage threshold
Specified off below VS–+ 0.55 V
Disable pin bias current
PD = VS– to VS+
Power-down quiescent current
1.5
V
A
0.55
V
A
20
50
nA
A
PD = 0.55 V
0.1
1
µA
A
Turnon time delay
Time from PD = high to VOUT = 90% of final
value
1.7
usec
C
Turnoff time delay
Time from PD = low to VOUT = 10% of original
value
100
ns
C
–50
The typical specification is at 25°C TJ. The minimum and maximum limits are expanded for the ATE to account for an ambient range
from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.
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7.6 Electrical Characteristics: VS = 3 V
at VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
70
86
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
VOUT = 20 mVPP, G = 6 (peaking < 4 dB)
SSBW
Small-signal bandwidth
VOUT = 20 mVPP, G = 10, RF = 1.6 kΩ
C
50
VOUT = 20 mVPP, G = 100, RF = 16.9 kΩ
MHz
3
C
GBP
Gain-bandwidth product
VOUT = 20 mVPP, G = 100
LSBW
Large-signal bandwidth
VOUT = 2 VPP, G = 6
Bandwidth for 0.1-dB flatness
VOUT = 200 mVPP, G = 6
Slew rate
From LSBW (2)
Overshoot, undershoot
VOUT = 1-V step, G = 6, input tR = 6 ns
2%
4%
Rise, fall time
VOUT = 1-V step, G = 6, input tR = 6 ns
6.3
7
Settling time to 0.1%
VOUT = 1-V step, G = 6, input tR = 6 ns
Settling time to 0.01%
VOUT = 1-V step, G = 6, input tR = 6 ns
HD2
Second-order harmonic distortion
f = 100 kHz, VO = 2 VPP, G = 6 (see Figure 74)
HD3
Third-order harmonic distortion
f = 100 kHz, VO = 2 VPP, G = 6 (see Figure 74)
Input voltage noise
f > 1 kHz
SR
tR, tF
240
250
Input current noise
300
MHz
C
45
MHz
C
9
MHz
C
350
V/µs
C
f > 100 kHz
Current noise 1/f corner frequency
C
ns
C
30
ns
C
40
ns
C
–108
dBc
C
–125
dBc
C
nV/√Hz
C
100
Hz
C
1.0
pA/√Hz
C
7
kHz
C
1.8
Voltage noise 1/f corner frequency
C
Overdrive recovery time
G = 6, 2x output overdrive, DC-coupled
50
ns
C
Closed-loop output impedance
f = 1 MHz, G = 6
0.3
Ω
C
dB
A
DC PERFORMANCE
AOL
Open-loop voltage gain
Input-referred offset voltage
Input offset voltage drift (3)
Input bias current (5)
Input bias current drift (3)
Input offset current
Input offset current drift (3)
(1)
(2)
(3)
(4)
(5)
8
VO = ±1 V, RL = 2 kΩ
110
125
TA ≈ 25°C
–125
±15
125
TA = 0°C to 70°C
–165
±15
200
TA = –40°C to 85°C
–230
±15
220
TA = –40°C to 125°C
–230
±15
285
–1.6
±0.4
1.6
TA ≈ 25°C
.7
1.5
2.8
TA = 0°C to 70°C
.2
1.5
3.5
TA = –40°C to 85°C
.2
1.5
3.7
TA = –40°C to 125°C
.2
1.5
4.4
TA = –40°C to 125°C
4.5
7.8
17
TA ≈ 25°C
–70
±20
70
TA = 0°C to 70°C
–83
±20
93
TA = –40°C to 85°C
–105
±20
100
TA = –40°C to 125°C
–105
±13
120
TA = –40°C to 125°C
–500
±20
500
TA = –40°C to 125°C
(4)
A
µV
B
B
B
µV/°C
B
A
µA
B
B
B
nA/°C
B
A
nA
B
B
B
pA/°C
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB
where this f–3dB is the typical measured 2-VPP bandwidth at gains of 6 V/V.
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
Input offset voltage drift, input bias current drift, and input offset current drift typical specifications are mean ± 1σ characterized by the full
temperature range end-point data. Maximum drift specifications are set by the min, max packaged test range on the wafer-level
screened drift. Drift is not specified by the final automated test equipment (ATE) or by QA sample testing.
Current is considered positive out of the pin.
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Electrical Characteristics: VS = 3 V (continued)
at VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VS– – 0.2
VS– – 0
UNIT
TEST
LEVEL (1)
INPUT
Common-mode input range, low
Common-mode input range, high
CMRR
TA ≈ 25°C, CMRR > 92 dB
TA = –40°C to 125°C, CMRR > 92 dB
TA ≈ 25°C, CMRR > 92 dB
VS– – 0
VS+ – 1.3
TA = –40°C to 125°C, CMRR > 92 dB
Common-mode rejection ratio
VS+ – 1.2
V
VS+ – 1.3
95
V
105
A
B
A
B
dB
A
Input impedance common-mode
55 || 1.1
MΩ || pF
C
Input impedance differential mode
30 || 1.3
kΩ || pF
C
OUTPUT
VOL
Output voltage, low
VOH
Output voltage, high
Maximum current into a resistive
load
TA ≈ 25°C, G = 6
TA = –40°C to 125°C, G = 6
VS– + 0.05
VS– + 0.1
VS– + 0.1
VS– + 0.2
TA ≈ 25°C, G = 6
VS+ – 0.1
VS+ – 0.05
TA = –40°C to 125°C, G = 6
VS+ – 0.2
VS+ – 0.1
TA ≈ 25°C, ±0.77 V into 26.7 Ω, VIO < 2 mV
±28
±30
TA ≈ 25°C, ±0.88 V into 37 Ω, AOL > 70 dB
±23
±25
Linear current into a resistive load
TA = –40°C to 125°C, ±0.76 V into 37 Ω,
AOL > 70 dB
DC output impedance
G=6
±20
V
V
mA
A
B
A
B
A
A
mA
±23
0.02
B
Ω
C
V
B
POWER SUPPLY
Specified operating voltage
Quiescent operating current
2.7
5
5.4
TA ≈ 25°C (6)
890
930
970
TA = –40°C to 125°C
680
930
1290
TA = –40°C to 125°C
2.2
2.7
3.2
dIq/dT
Quiescent current temperature
coefficient
+PSRR
Positive power-supply rejection
ratio
95
–PSRR
Negative power-supply rejection
ratio
90
µA
A
B
µA/°C
B
110
dB
A
105
dB
A
POWER DOWN (Pin Must be Driven, SOT23-6 and SC70-6)
(6)
Enable voltage threshold
Specified on above VS– + 1.5 V
Disable voltage threshold
Specified off below VS– + 0.55 V
Disable pin bias current
PD = VS– to VS+
Power-down quiescent current
1.5
V
A
0.55
V
A
20
50
nA
A
PD = 0.55 V
0.1
1
µA
A
Turnon time delay
Time from PD = high to VOUT = 90% of final
value
3.5
usec
C
Turnoff time delay
Time from PD = low to VOUT = 10% of original
value
100
ns
C
–50
The typical specification is at 25°C TJ. The minimum and maximum limits are expanded for the ATE to account for an ambient range
from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.
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7.7 Typical Characteristics: VS = 5 V
3
6
0
3
Normalized Gain (dB)
Normalized Gain (dB)
VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, TA ≈ 25°C
(unless otherwise noted)
-3
-6
-9
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 50 V/V
-12
-15
100m
1
-3
-6
-9
10
Frequency (MHz)
-15
100m
100
15
12
12
Gain (dB)
15
9
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
3
10
Frequency (MHz)
0
100m
100
Gain = 6 V/V, R LOAD = 2 kΩ
Figure 3. Noninverting Large-Signal Bandwidth vs VOPP
1
Normalized Gain (dB)
Normalized Gain (dB)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
-1.2
100m
1
10
Frequency (MHz)
100
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
100m
100
Figure 5. Noninverting Response Flatness vs Gain
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
1
10
100
Frequency (MHz)
D005
See Figure 74 and Table 1 (VO = 200 mVPP, R LOAD = 2 kΩ)
10
10
Frequency (MHz)
Figure 4. Inverting Large-Signal Bandwidth vs VOPP
0.8
-1
1
Gain = –6 V/V, R LOAD = 2 kΩ
1.2
-0.8
100
9
6
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
1
10
Frequency (MHz)
Figure 2. Inverting Small-Signal Frequency Response vs
Gain
18
0
100m
1
See Figure 75 and Table 2 (VO = 20 mVPP, R LOAD= 2 kΩ)
18
3
6 V/V
10 V/V
20 V/V
50 V/V
D001
Figure 1. Noninverting Small-Signal Frequency Response
vs Gain
6
Gain =
Gain =
Gain =
Gain =
-12
See Figure 74 and Table 1 (VO = 20 mVPP, R LOAD = 2 kΩ)
Gain (dB)
0
See Figure 75 and Table 2 (VO = 200 mVPP; R LOAD = 2 kΩ)
Figure 6. Inverting Response Flatness vs Gain
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Typical Characteristics: VS = 5 V (continued)
VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, TA ≈ 25°C
(unless otherwise noted)
2.25
2.25
VO = r0.25 V
VO = r0.5 V
VO = r1 V
VO = r2 V
1.25
0.75
0.25
-0.25
-0.75
1.25
0.75
0.25
-0.25
-0.75
-1.25
-1.25
-1.75
-1.75
-2.25
20
70
120
170
Time (nsec)
VO = r0.25 V
VO = r0.50 V
VO = r1 V
VO = r2 V
1.75
Output Voltage (Volts)
Output Voltage (Volts)
1.75
220
-2.25
20
260
70
See Figure 74 (gain of 6 V/V)
% Error to final value
% Error to final value
10
20
30
40
50
60
70
Time from Input Step (nsec)
80
90
0.02
0.018
0.016
0.014
0.012
0.01
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
100
AV =
AV =
AV =
AV =
0
20
See Figure 74 and Table 1
40
60
Time from Input Step (nsec)
80
100
Figure 10. Simulated Inverting Settling Time
5
5
VIN u 10 gain
VOUT (AV = 10)
VIN u 6 gain
VOUT (AV = 6)
4
3
4
3
2
I/O Voltages (V)
I/O Voltages (V)
6, 500-mV Step, TR = 3 ns
6 , 2-V Step, TR = 12 ns
10 , 500-mV Step, TR = 3 ns
10 , 2-V Step, TR = 12 ns
See Figure 75 and Table 2
Figure 9. Simulated Noninverting Settling Time
1
0
-1
-2
2
1
0
-1
-2
-3
-3
-4
-4
-5
50
260
Figure 8. Inverting Step Response vs VOPP
AV = 6, 500-mV Step, TR = 3 ns
AV = 6, 2-V Step, TR = 12 ns
AV = 10, 500-mV Step, TR = 3 ns
AV = 10, 2-V Step, TR = 12 ns
0
220
See Figure 75 (gain of –6 V/V)
Figure 7. Noninverting Step Response vs VOPP
0.02
0.018
0.016
0.014
0.012
0.01
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.01
-0.012
120
170
Time (nsec)
250
450
650
850
Time (nsec)
1050
1250
1450
-5
50
D011
See Figure 74 and Table 1
VIN u 10 gain
VOUT (AV = 10)
VIN u 6 gain
VOUT (AV = 6)
250
450
650
850
Time (nsec)
1050
1250
1450
D012
See Figure 75 and Table 2
Figure 11. Noninverting Overdrive Recovery
Figure 12. Inverting Overdrive Recovery
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Typical Characteristics: VS = 5 V (continued)
VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, TA ≈ 25°C
(unless otherwise noted)
-80
-85
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
-90
-90
-95
Distortion (dBc)
Distortion (dBc)
-100
-110
-120
-130
HD2, G = 6 V/V
HD3, G = 6 V/V
HD2, G = 6 V/V
HD3, G = 6 V/V
-140
-150
10k
100k
Frequency (Hz)
-100
-105
-110
-115
-120
-125
-130
100
1M
1k
RLOAD (:)
See Figure 74, Figure 75, Table 1, and Table 2
(VO = 2 VPP, F = 100 kHz)
See Figure 74, Figure 75, Table 1, and Table 2
Figure 14. Harmonic Distortion vs RLOAD
Figure 13. Harmonic Distortion vs Frequency
-95
-100
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
-100
-105
Distortion (dBc)
Distortion (dBc)
-105
-110
-115
-120
-110
HD2, 100 kHz, +Gain
HD3, 100 kHz, +Gain
HD2, 100 kHz, Gain
HD3, 100 kHz, Gain
-115
-120
-125
-125
-130
-135
0.5
-130
1
1.5
2
2.5
VOPP (V)
3
3.5
4
6
See Figure 74, Figure 75, Table 1, and Table 2
(F = 100 kHz, RLOAD = 2 kΩ)
7
-105
-110
-110
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 10 V/V
HD3, 100 kHz, G = 10 V/V
-125
-130
1.5
-115
HD2, 100 kHz, G =
HD3, 100 kHz, G =
HD2, 100 kHz, G =
HD3, 100 kHz, G =
-120
6 V/V
6 V/V
10 V/V
10 V/V
-125
2
2.5
VOCM (V)
3
3.5
-130
1.5
2
D017
See Figure 74 and Table 1
(VO = 2 VPP, F = 100 kHz, RLOAD = 2 kΩ)
2.5
VOCM (V)
3
3.5
See Figure 75 and Table 2
(VO = 2 VPP, F = 100 kHz, RLOAD = 2 kΩ)
Figure 17. Noninverting Distortion vs
Output Common-Mode Voltage
12
10 11 12 13 14 15 16 17 18 19 20
Gain Magnitude (V/V)
Figure 16. Harmonic Distortion vs Gain
Distortion (dBc)
Distortion (dBc)
Figure 15. Harmonic Distortion vs Output Swing
-120
9
See Figure 74, Figure 75, Table 1, and Table 2
(VO = 2 VPP, RLOAD = 2 kΩ, F = 100 kHz)
-105
-115
8
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Figure 18. Inverting Distortion vs
Output Common-Mode Voltage
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7.8 Typical Characteristics: VS = 3 V
6
6
3
3
Normalized Gain (dB)
Normalized Gain (dB)
VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply. TA = 25°C
(unless otherwise noted)
0
-3
-6
-9
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 50 V/V
-12
-15
0.1
1
0
-3
-6
-9
Gain =
Gain =
Gain =
Gain =
-12
10
Frequency (MHz)
-15
0.1
100
15
15
12
12
Gain (dB)
Gain (dB)
18
9
6
9
6
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
1
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
3
10
Frequency (MHz)
0
0.1
100
See Figure 74 (AV = 6 V/V)
1
10
Frequency (MHz)
100
See Figure 75 (AV = –6 V/V)
Figure 21. Noninverting Large-Signal Bandwidth vs VOPP
Figure 22. Inverting Large-Signal Bandwidth vs VOPP
1.8
1.4
1
Normalized Gain (dB)
Normalized Gain (dB)
100
Figure 20. Inverting Small-Signal Response vs Gain
18
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
0.1
10
Frequency (MHz)
See Figure 75 and Table 2
Figure 19. Noninverting Small-Signal Response vs Gain
0
0.1
1
D019
See Figure 74 and Table 1
3
6 V/V
10 V/V
20 V/V
50 V/V
0.6
0.2
-0.2
-0.6
-1
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
-1.4
1
10
Frequency (MHz)
100
-1.8
0.1
See Figure 74 and Table 1 (VO = 200 mVPP, R LOAD = 2 kΩ)
Figure 23. Noninverting Response Flatness vs Gain
1
10
100
Frequency (MHz)
D023
See Figure 75 and Table 2 (VO = 200 mVPP, R LOAD = 2 kΩ)
Figure 24. Inverting Response Flatness vs Gain
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Typical Characteristics: VS = 3 V (continued)
VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply. TA = 25°C
(unless otherwise noted)
1.5
1.5
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
1
Output Voltage (V)
Output Voltage (V)
1
0.5
0
-0.5
-1
0.5
0
-0.5
-1
-1.5
20
70
120
170
Time (nsec)
220
-1.5
20
260
70
See Figure 74 and Table 1
Figure 25. Noninverting Step Response vs V
Figure 26. Inverting Step Response vs VOPP
OPP
AV = 6, 500-mV Step, TR = 3 ns
AV = 6, 1-V Step, TR = 6 ns
AV = 10, 500-mV Step, TR = 3 ns
AV = 10, 1-V Step, TR = 6 ns
0.004
0.002
0
-0.002
-0.004
AV =
AV =
AV =
AV =
0.018
0.016
% Error to final value
% Error to final value
0.006
0.014
6, 500-mV Step, TR = 3 ns
6, 1-V Step, TR = 6 ns
10, 500-mV Step, TR = 3 ns
10, 1-V Step, TR = 6 ns
0.012
0.01
0.008
0.006
0.004
0.002
-0.006
0
-0.008
-0.002
-0.01
-0.004
0
10
20
30
40
50
60
70
Time from Input Step (nsec)
80
90
100
0
10
See Figure 74 and Table 1
20
30
40
50
60
70
Time from Input Step (nsec)
80
90
100
See Figure 75 and Table 2
Figure 27. Noninverting Settling Time
Figure 28. Inverting Settling Time
3
3
VIN u 10 gain
VOUT (AV = 10)
VIN u 6 gain
VOUT (AV = 6)
2
Input and Output Voltage (V)
Input and Output Voltage (V)
260
0.02
0.008
1
0
-1
-2
250
450
650
850
Time (nsec)
1050
1250
1450
VIN u 10 gain
VOUT (AV = 10)
VIN u 6 gain
VOUT (AV = 6)
2
1
0
-1
-2
-3
50
D029
See Figure 74 and Table 1
250
450
650
850
Time (nsec)
1050
1250
1450
D030
See Figure 75 and Table 2
Figure 29. Noninverting Overdrive Recovery
14
220
See Figure 75 and Table 2
0.01
-3
50
120
170
Time (nsec)
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Figure 30. Inverting Overdrive Recovery
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Typical Characteristics: VS = 3 V (continued)
VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply. TA = 25°C
(unless otherwise noted)
-80
-85
HD2, G = 6 V/V
HD3, G = 6 V/V
HD2, G = 6 V/V
HD3, G = 6 V/V
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
-90
-95
-100
Distortion (dBc)
Distortion (dBc)
-90
-110
-120
-100
-105
-110
-115
-120
-130
-125
-140
10k
100k
Frequency (Hz)
-130
100
1M
1k
RLOAD (:)
See Figure 74, Figure 75, Table 1, and Table 2
See Figure 74, Figure 75, Table 1, and Table 2
Figure 32. Harmonic Distortion vs Load
-105
-110
-110
-115
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
-120
Distortion (dBc)
Distortion (dBc)
Figure 31. Harmonic Distortion vs Frequency
-105
-125
HD2, 100 kHz, +Gain
HD3, 100 kHz, +Gain
HD2, 100 kHz, Gain
HD3, 100 kHz, Gain
-115
-120
-125
-130
0.5
-130
0.7
0.9
1.1
1.3
VOPP (V)
1.5
1.7
1.9 2
See Figure 74, Figure 75, Table 1, and Table 2
6
8
9
10 11 12 13 14 15 16 17 18 19 20
Gain Magnitude (V/V)
See Figure 74, Figure 75, Table 1, and Table 2 (2-kΩ load, 2 VPP)
Figure 33. Harmonic Distortion vs Output Swing
Figure 34. Harmonic Distortion vs Gain
-90
-105
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 10 V/V
HD3, 100 kHz, G = 10 V/V
-95
-100
-105
-110
Distortion (dBc)
Distortion (dBc)
7
-110
-115
-120
-125
-115
HD2, 100 kHz, G =
HD3, 100 kHz, G =
HD2, 100 kHz, G =
HD3, 100 kHz, G =
-120
6 V/V
6 V/V
10 V/V
10 V/V
-125
-130
-135
0.5
0.7
0.9
1.1
1.3
1.5
VOCM (V)
1.7
1.9
2.1
-130
0.8
See Figure 74 and Table 1 (VO = 1 VPP)
Figure 35. Noninverting Harmonic Distortion vs Output
Common-Mode Voltage
0.9
1
1.1
1.2
1.3 1.4
VOCM (V)
1.5
1.6
1.7
1.8
1.9
See Figure 75 and Table 2 (VO = 1 VPP)
Figure 36. Inverting Harmonic Distortion vs Output
Common-Mode Voltage
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7.9 Typical Characteristics: Over Supply Range
100
1k
10k
100k
1M
Frequency (Hz)
20
5-V Gain
0
5-V Phase -20
3-V Gain
-40
3-V Phase
-60
-80
-100
-120
-140
-160
-180
-200
-220
-240
-260
-280
10M 100M 1G
100
50
Output Impedance (:)
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
Open Loop Phase (deg)
Open Loop Gain (dB)
PD = VS+ and TA = 25°C (unless otherwise noted)
AV = 6, 5-V supply
AV = 10, 5-V supply
AV = 20, 5-V supply
AV = 6, 3-V supply
AV = 10, 3-V supply
AV = 20, 3-V supply
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.01
No load, simulation
10
D038
See Figure 74 and Table 1 (simulation)
Figure 37. Open-Loop Gain and Phase
Figure 38. Closed-Loop Output Impedance
100
5 V En
3 V En
5 V In
3 V In
5-V supply
3-V supply
80
60
Input noise (nV)
Input Voltage (nV/vHz) Current (pA/vHz) Noise
0.1
1
Frequency (MHz)
10
40
20
0
-20
-40
-60
-80
1
10
100
1k
10k
100k
Frequency (Hz)
1M
0
10M
1
2
3
4
5
6
Time (sec)
7
8
9
10
Input referred
Figure 40. Low-Frequency Voltage Noise
120
-65
110
-70
-75
100
Feedthrough (dB)
Rejection Ratio (dB)
Figure 39. Input Spot Noise Density
90
80
70
5-V PSRR
5-V PSRR
5-V CMRR
3-V PSRR
3-V PSRR
3-V CMRR
60
50
10
100
-85
-90
-95
-105
1k
10k
Frequency (Hz)
100k
1M
10M
-110
0.1
Simulated results
Figure 41. PSRR and CMRR
16
5 V, 200 mVPP
5 V, 1 VPP
3 V, 200 mVPP
3 V, 1 VPP
-100
40
1
-80
1
Frequency (MHz)
10
D042
Measured, AV = 6 V/V, 100-Ω load
Figure 42. Disabled Isolation Noninverting Input to Output
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Typical Characteristics: Over Supply Range (continued)
PD = VS+ and TA = 25°C (unless otherwise noted)
300
240
5-V Supply
3-V Supply
275
250
200
180
# of units in 10nA bins
# of units in 25µV bins
225
200
175
150
125
100
75
5-V Supply
3-V Supply
220
160
140
120
100
80
60
50
40
25
20
0
0
-125 -100 -75
-50 -25 0
25 50
Input offset Voltage (µV)
75
100 125
-70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70
Input Offset Current (nA)
600 units at each supply voltage
600 units at each supply voltage
Figure 43. Input Offset Voltage Distribution
Figure 44. Input Offset Current Distribution
80
20
Input offset current shift (nA)
25
Input offset shift from 25°C (uV)
100
60
40
20
0
-20
-40
-60
15
10
5
0
-5
-10
-15
-20
-80
-100
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
-25
-40
-25
D045
51 units at 5-V and 3-V supply
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D046
51 units at 5-V and 3-V supply
Figure 45. Input Offset Voltage vs Temperature
Figure 46. Input Offset Current vs Temperature
27
16
5-V drift
3-V drift
14
10
8
6
4
5-V supply
3-V supply
24
# of occurences in bin
12
21
18
15
12
9
6
e
1.
5
or
M
5
1
Input offset voltage drift (uV/°C)
1.
2
0.
0
0
25
0.
5
0.
75
0
-1
-0
.7
5
-0
.5
-0
.2
5
3
-1
.5
-1
.2
5
2
-5
0
-4 0
5
-4 0
0
-3 0
5
-3 0
0
-2 0
5
-2 0
0
-1 0
5
-1 0
00
-5
0
0
50
10
0
15
0
20
0
25
0
30
0
35
0
40
0
45
0
50
0
# of units
-10
Input offset current drift (pA/°C)
51 units at each supply
51 units at each supply
Figure 47. Input Offset Voltage Drift Distribution
Figure 48. Input Offset Current Drift Distribution
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Typical Characteristics: Over Supply Range (continued)
PD = VS+ and TA = 25°C (unless otherwise noted)
220
33
30
27
24
21
18
15
12
9
6
3
0
-3
-6
10k
AV = 6 V/V
AV = 10 V/V
AV = 20 V/V
180
160
Gain (dB)
ROUT (:)
140
120
100
80
60
40
20
0
1
10
100
CLOAD (pF)
1k
10k
AV = 6, CLOAD = 100 pF
AV = 10, CLOAD = 100 pF
AV = 20, CLOAD = 100 pF
AV = 6, CLOAD = 1 nF
AV = 10, CLOAD = 1 nF
AV = 20, CLOAD = 1 nF
100k
D049
See Figure 66 and Table 1
(small signal, targeting 30° phase margin)
Disable and VOUT (Bipolar Supplies, Volts)
Disable and VOUT (Bipolar supplies, Volts)
2
1.5
1
0.5
0
-0.5
PD Voltage (5 V)
Output Voltage (5 V)
PD Voltage (3 V)
Output Voltage (3 V)
-2
-2.5
4.5
5
5.5
6
6.5
7
7.5
Time (Ps)
8
8.5
9
9.5
PD Voltage (5 V)
Output Voltage (5 V)
PD Voltage (3 V)
Output Voltage (3 V)
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
1.8
1.84 1.88 1.92 1.96 2 2.04 2.08 2.12 2.16
Time (Ps)
Figure 51. Turnon Time to Sinusoidal Input
4
6
0.006
5.5
0.005
5
0.004
4.5
0.003
3.5
0.002
3
0.001
2.5
0
2
-0.001
%Err to final value
Disable and VOUT (V)
4.5
D052
0.007
5 V Disable V
5 V VOUT
5 V %Err
3 V Disable V
3 V VOUT
3 V %Err
4
0.006
0.005
0.004
0.003
3.5
0.002
3
0.001
2.5
0
2
-0.001
1.5
-0.002
1.5
-0.002
1
-0.003
1
-0.003
0.5
-0.004
0.5
-0.004
0
-0.005
0
0
0.5
1
1.5
2
2.5
Time from turn on (Ps)
3
3.5
4
Single-supply, DC input to produce midscale output (simulation)
Figure 53. Gain of 6-V/V Turnon Time to Final DC Value at
Midscale
18
2.2
Figure 52. Turnoff Time to Sinusoidal Input
0.007
Disable and VOUT (V)
5 V Disable V
5 V VOUT
5 V %Err
3 V Disable V
3 V VOUT
3 V %Err
5
D050
2.5
D051
6
5.5
100M
Figure 50. Small-Signal Response Shapes vs CLOAD With
Recommended ROUT
2.5
-1.5
10M
See Figure 66 and Table 1
(2-kΩ parallel load to C LOAD)
Figure 49. Output Resistor vs CLOAD
-1
1M
Frequency (Hz)
%Err to final value
200
-0.005
0
0.5
1
1.5
2
2.5
Time from turn on (Ps)
3
3.5
4
Single-supply, DC input to produce midscale output (simulation)
Figure 54. Gain of 10-V/V Turnon Time to Final DC Value at
Midscale
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Typical Characteristics: Over Supply Range (continued)
PD = VS+ and TA = 25°C (unless otherwise noted)
2.5
2
2
1.5
1.5
1
0.5
Output Voltage (V)
+VCC 2.5 V
+VCC 1.5 V
-V CC -2.5 V
-V CC -1.5 V
0
-0.5
-1
-1.5
1
0.5
+VCC 2.5 V
+VCC 1.5 V
-V CC -2.5 V
-V CC -1.5 V
0
-0.5
-1
-1.5
-2
-2
-2.5
100
-2.5
0.1
1k
1
IOUT (mA)
RLOAD to Ground (Ω)
Figure 56. Output Saturation Voltage vs Load Current
1300
1200
1200
1000
Supply Current (µA)
3 V & 5 V ICC (PA)
Figure 55. Output Voltage Swing vs Load Resistor
1100
1000
900
800
700
-40
800
IQ 5 V
IQ 3 V
600
400
200
0
-20
0
20
40
60
80
Ambient Temperature (qC)
100
-200
0.5
120
0.75
1
1.25
PD Voltage Above -VS Supply (V)
D058
100
80
Input Bias Current (nA)
60
40
20
0
-20
-40
-60
-80
-100
-2.7 -2.3 -1.9 -1.5 -1.1 -0.7 -0.3 0.1 0.5 0.9 1.3
Input Common-Mode Voltage (Split Supplies, Volts)
1.5
Figure 58. Supply Current vs Power-Down Voltage:
Turnon Higher Than Turnoff
Figure 57. Quiescent Current vs Temperature
Input Offset Voltage (PV)
10
1.7
1700
1650
1600
1550
1500
1450
1400
1350
1300
1250
1200
1150
1100
1050
1000
-0.4
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
5 V IB5 V IB+
5 V IOS
3 V IB3 V IB+
3 V IOS
0
5 units, 3-V and 5-V supplies
0.4
0.8 1.2 1.6
2
2.4 2.8 3.2
Input Common-Mode Voltage (V)
3.6
Input Offset Current (nA)
Output Voltage (V)
2.5
4
Measured single device
Figure 59. Input Offset Voltage vs Input Common-Mode
Voltage
Figure 60. Input Bias and Offset Current vs VICM
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8 Detailed Description
8.1 Overview
The OPA838 is a power efficient, decompensated, voltage feedback amplifier (VFA). Combining a negative rail
input stage and a rail-to-rail output (RRO) stage, the device provides a flexible solution where higher gain or
transimpedance designs are required. This 300-MHz gain bandwidth product (GBP) amplifier requires less than
1 mA of supply current over a 2.7 to 5.4-V total supply operating range. A shutdown feature on the 6-pin package
versions provides power savings where the system requires less than 1 µA when shut down. A decompensated
amplifier operating at low gains (less than 6 V/V) may experience a low phase margin that may risk oscillation.
The TINA model for the OPA838 predicts those conditions.
8.2 Functional Block Diagram
The OPA838 is a standard voltage feedback op amp with two high-impedance inputs and a low-impedance
output. Standard applications circuits are supported; see Figure 61 and Figure 62. These application circuits are
shown with a DC VREF on the inputs that set the DC operating points for single-supply designs. The VREF is often
ground, especially for split-supply applications.
VSIG
VS+
VREF
VIN
VOUT
OPA838
RG
GVSIG
VREF
VREF
VSRF
Figure 61. Noninverting Amplifier
VS+
VREF
VSIG
VREF
RG
OPA838
VOUT
GVSIG
V IN
VREF
VSRF
Figure 62. Inverting Amplifier
8.3 Feature Description
8.3.1 Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier with high CMRR, the input pins must stay within the input
operating range (VICR.) These are referenced off of each supply as an input headroom requirement. Ensured
operation at 25°C is maintained to the negative supply voltage and to within 1.3 V of the positive supply voltage.
The common-mode input range specifications in the table data use CMRR to set the limit. The limits are selected
to ensure CMRR does not degrade more than 3 dB below the minimum CMRR value if the input voltage is within
the specified range.
20
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Feature Description (continued)
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (0 V) and the
input common-mode voltage is analyzed at either input pin, assuming the other input pin is at the same potential.
The voltage at VIN+ is simple to evaluate. In noninverting configuration (see Figure 61), the input signal (VIN) must
not violate the VICR. In inverting configuration (see Figure 62), the reference voltage (VREF), must be within the
VICR.
The input voltage limits have fixed headroom to the power rails and track the power supply voltages. For a single
5-V supply, the linear 25°C minimum input voltage ranges from 0 V to 3.7 V, and 0 V to 1.4 V for a single 2.7-V
supply. The delta headroom from each power supply rail is the same in each case (0 V and 1.3 V).
8.3.2 Output Voltage Range
The OPA838 device is a rail-to-rail output op amp. Rail-to-rail output typically means that the output voltage
swings to within 100 mV of the supply rails. There are different ways to specify this: one is with the output still in
linear operation and another is with the output saturated. Saturated output voltages are closer to the power
supply rails than linear outputs, but the signal is not a linear representation of the input. Saturation and linear
operation limits are affected by the output current, where higher currents lead to more voltage loss in the output
transistors; see Figure 56.
The specification tables show saturated output voltage specifications with a 2-kΩ load. Figure 11 and Figure 43
illustrate saturated voltage-swing limits versus output load resistance, and Figure 12 and Figure 44 illustrate the
output saturation voltage versus load current. With a light load, the output voltage limits have constant headroom
to the power rails and track the power supply voltages. For example, with a 1-kΩ load and a single 5-V supply,
the linear output voltage ranges from 0.12 V to 4.88 V and ranges from 0.12 V to 2.58 V for a 2.7-V supply. The
delta from each power supply rail is the same in each case: 0.12 V.
With devices like the OPA838 where the input range is lower than the output range, the input limits the available
signal swing at low gains. Because the OPA838 is intended for higher gains, the smaller input swing range does
not limit operation and full rail-to-rail output is available. Inverting voltage gain and transimpedance configurations
are typically limited by the output voltage limits of the op amp if the noninverting input pin is biased in range.
8.3.3 Power-Down Operation
The OPA838 includes a power-down feature. Under logic control, the amplifier can switch from normal operation
to a standby current of less than 1 µA. When the PD pin is connected high (greater than or equal to 1.5 V above
the negative supply), the amplifier is active. Connecting the PD pin low (less than or equal to 0.55 V above the
negative supply) disables the amplifier. To protect the input stage of the amplifier, the device uses internal, backto-back diodes (two in series each way) between the inverting and noninverting input pins. If the differential
voltage in shutdown exceeds 1.2 V, those diodes turn on.
The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used,
PD may be tied to the positive supply rail.
When the op amp is powered from a single-supply and ground, with PD driven from logic devices with similar
VDD voltages to the op amp, no special considerations are required. When the op amp is powered from a splitsupply with VS– below ground, an open-collector type of interface with a pullup resistor is more appropriate.
Pullup resistor values must be lower than 100 kΩ. Recovery from power down is illustrated in Figure 53 and
Figure 54 for several gains. In single-supply mode with the gain resistor at ground, the output approaches the
positive supply on initial power up until the internal nodes charge then recover to the target output voltage; see
Figure 51 and Figure 52.
8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
The OPA838 is specified using a 1-kΩ feedback resistor with a 200-Ω gain resistor to ground in a noninverting
gain of 6 V/V configuration. These values give a good compromise, keeping the noise contribution of the
resistors well below that of the amplifier noise terms and minimal power in the feedback network as the output
voltage swing creates load current back into the feedback network. Decreasing these values improves the noise
at the cost of more power dissipated in the feedback network. Low values increase the harmonic distortion as the
feedback load decreases. Increasing the RF value at a particular gain increases the output noise contribution of
those resistors possibly becoming dominant. As the feedback resistor values continue to increase (and the RG at
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Feature Description (continued)
a fixed target gain), there is a loss of phase margin as the impedance that drives the inverting input capacitance
brings in an added loop pole at lower frequencies. Figure 63 shows this at a gain of 6 V/V with increasing RF
values. This noninverting test shows more peaking as the RF values increase due to the 1-pF
common-mode input capacitance at the inverting input. The TINA simulation model gives excellent prediction of
these effects.
27
RF = 1 k
RF = 2 k
RF = 5 k
RF = 10 k
RF = 20 k
24
Gain (dB)
21
18
15
12
9
10k
100k
1M
10M
Frequency (Hz)
100M
D063
Figure 63. Frequency Response With Various Feedback Resistor Values
Operating the OPA838 in inverting mode with higher RF values increases response peaking due to the loss of
phase margin effect. In the inverting case, a pair of capacitors can flatten the response at the cost of lower
closed-loop bandwidth. Figure 64 shows an example with a 20-kΩ RF value at an inverting gain of –5 V/V (noise
gain = 6 V/V) with optional capacitors (CF and CG). Figure 64 shows optional bias current cancellation elements
on the noninverting input. The total resistance value matches the parallel combination of RG || RF, which reduces
the DC output error term due to bias current to IOS × RF. The 10-nF capacitor is added across the larger part of
this bias current canceling resistance to filter noise and the 20 Ω is split out to isolate the capacitor self
resonance from the noninverting input. Figure 65 illustrates the small-signal response shape with and without
these capacitors. The feedback capacitor (CF), is selected to set a desired closed-loop bandwidth with RF. CG is
added to ground to shape the noise gain up over frequency to be greater than or equal to 6 V/V at higher
frequencies. In this example, that higher frequency noise gain is 1 + 6 / 1.2 = 6 V/V, adding the 1-pF device
common-mode capacitance to the external 5 pF. Using the capacitors to set the feedback ratio removes the pole
produced in the feedback driving from purely resistive source to the inverting parasitic capacitance.
CF 1.2 pF
RG 4.02 NŸ
CG 5 pF
VEE
±
Inverting with
High Rf values RG 4.02 Ÿ
+
+
C1 10n
R1 2 NŸ
Input
RF 20 NŸ
PD
RM 3.24 NŸ
+
V
VOUT
VCC
Bias current
cancellation with
resistor noise
filtering
VCC
VEE
+
+
V1 2.5 V
V2 ±2.5 V
Figure 64. G = –5 V/V With Optional Compensation
22
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Feature Description (continued)
18
15
12
9
Gain (dB)
6
3
0
-3
-6
-9
No caps
With caps
-12
-15
10k
100k
1M
Frequency (Hz)
10M
100M
D070
Figure 65. Inverting Response With and Without Compensation
8.3.5 Driving Capacitive Loads
The OPA838 can drive small capacitive loads directly without oscillation (less than 6 pF). When driving capacitive
loads greater than 6 pF, Figure 49 illustrates the recommended ROUT vs capacitor load parametric on gains. At
higher gains, the amplifier starts with greater phase margin into a resistive load and can operate with lower ROUT
for a given capacitive load. Without ROUT, output capacitance interacts with the output impedance of the
amplifier, which causes phase shift in the loop gain of the amplifier that reduces the phase margin. This causes
peaking in the frequency response with overshoot and ringing in the pulse response. Figure 49 targets a 30°
phase margin for the OPA838. A 30° phase margin produces a 5.7-dB peaking in the frequency response at the
amplifier output pin that is rolled off by the output RC pole; see Figure 67. This peaking can cause clipping for
large signals driving a capacitive load. Increasing the ROUT value can reduce the peaking at the cost of a more
band-limited overall response.
RG 200 Ÿ
RF 1 NŸ
VEE
±
PD
RLOAD 2 NŸ
+
+ VG1
CLOAD 1n
+
ROUT 68.1 Ÿ
VCC
VCC
VEE
+
+
V1 2.5 V
+
V
VOUT
V2 ±2.5 V
Figure 66. ROUT versus CL Test Circuit
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Feature Description (continued)
25
Small Signal Response (dB)
22
At capacitive load
At output pin
19
16
13
10
7
4
1
-2
-5
10k
100k
1M
Frequency (Hz)
10M
100M
CapL
Figure 67. Frequency Response to Output Pin and Capacitive Load
8.4 Device Functional Modes
8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
To facilitate testing with common lab equipment, the OPA838 EVM (see EVM board link) is built to allow splitsupply operation. This configuration eases lab testing because the midpoint between the power rails is ground,
and most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and other lab equipment
have inputs and outputs with a ground reference. This simplifies characterization by removing the requirement for
blocking capacitors.
Figure 68 shows a simple noninverting configuration analogous to Figure 61 with a ±2.5-V supply and VREF equal
to ground. The input and output swing symmetrically around ground. For ease of use, split-supplies are preferred
in systems where signals swing around ground. Using bipolar (or split) supplies shifts the thresholds for the
shutdown control. The disable control is referenced from the negative supply. Typically, this is ground in a singlesupply application, but using a negative supply requires that the pin is set to within 0.55 V above the negative
supply to disable. If disable is not required, connecting that pin to the positive supply ensures correct operation,
even for split-supply applications. This disable pin cannot be floated but must be asserted to a voltage.
RG 200 Ÿ
RF 1 NŸ
VEE
R2 165 Ÿ
+
±0.35 VIN
20 nsec edge
2 MHz input
Input
Signal
+
R1 2 NŸ
U1 OPA838
±
±2.1 VOUT
Ground
Centered
PD
+
V
VM1
VCC
VCC
+
V1 2.5 V
VEE
+
V2 ±2.5 V
Figure 68. Split-Supply Operation
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Device Functional Modes (continued)
2.5
Input
Output
Input/Output Voltage (V)
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
200
300
400
500
Time (nsec)
600
700
800
D068
Figure 69. Bipolar-Supply Step Response
8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
Most newer systems use a single power supply to improve efficiency and to simplify power supply design. The
OPA838 can be used with single-supply power (ground for the negative supply) with no change in performance
from split supply, as long as the input and output pins are biased within the linear operating region of the device.
The outputs nominally swing rail-to-rail with approximately a 100-mV headroom required for linear operation. The
inputs can swing below the negative rail (typically ground) and to within 1.3 V of the positive supply. For DCcoupled single-supply operation, the higher gain operating applications typical of a decompensated op amp keep
the input swings below the input swing limit to the positive supply. Typically, the 1.3-V input headroom required
to the positive supply does not limit operation.
Figure 70 shows an example design taking a 0 V to 0.5 V input range, level shifting the output up to 0.15 V for a
0-V input using the 4.5-V reference voltage common for 5-V SAR ADCs, and sets the gain to produce a 4.1-V
output swing for the 0.5-V input swing. This example is assuming a 0-Ω source that is required to sink the 39 µA
required to bias the positive input pin to produce the 0.15-V output for 0-V input. The RF and RG values are
scaled down slightly to provide bias current cancellation by matching the parallel combination of the two bias setup resistors on the noninverting input. Figure 71 illustrates an example step response for this circuit that
produces an output from 0.15 V for a 0-V input to 4.35 V for a 0.5-V input.
RG 56.2 Ÿ
VREF
RF 1 NŸ
+
V1 4.5 V
±
RB2 49.9 Ÿ
VG1
0 V to 0.5 V
Input Swing
RB1 11.8 NŸ
+
+
VOUT
+
PD
VCC
VREF VCC
+
VCC 5 V
Figure 70. DC-Coupled, Single-Supply, Noninverting Interface With Output Level Shift
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Device Functional Modes (continued)
4.5
Input and Output Voltage (V)
4
3.5
3
2.5
Input
Output
2
1.5
1
0.5
0
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Time (µsec)
0.2
D065
Figure 71. Unipolar Input to Level Shifted Output Step Response
If AC-coupling is acceptable, a simple way to operate single-supply is to run inverting. Figure 72 shows a lowpower, high-gain example. In this example, a gain of –20 V/V is implemented (inverting usually does not matter
for AC-coupled channels) where the V+ input is biased midscale. This example is showing an optional bias
current cancellation setup, which may not be necessary unless the output DC level requires good accuracy. The
parallel combination of the divider resistors plus the 80.7-Ω isolating resistor match the feedback resistor value.
With the blocking capacitor at the inverting input, the feedback resistor impedance must be matched to achieve
bias current cancellation. In this 3-V supply example, the two inputs and the output are biased at 1.5 V. This
places the input pins in range and centers the output for maximum V PP available. Figure 73 illustrates the smallsignal response for this example showing a F-3dB range from a low-end cutoff of 887 Hz set by the input capacitor
value to a 17.5-MHz high-frequency cutoff.
C2 1µF RG 178 Ÿ
VG1
887 Hz to
17.5 Mhz gain
of -20 V/V
Riso 80.6
RB2 6.98 NŸ
+
C1 1 µF
U1 OPA838
±
+
PD
1.5 V
DC Out
VCC
RB1 6.98 NŸ
VCC
RLOAD 2 NŸ
+
RF 3.57 NŸ
+
V
VM1
+
V1 3 V
Figure 72. Single-Supply Inverting Gain Stage With AC-Coupled Input
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Device Functional Modes (continued)
Small Signal Response (dB)
27
24
21
18
15
Output
12
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
D069
Figure 73. Inverting Single-Supply Response With AC-Coupled Input
These are only two of the many ways a single-supply design may be implemented. Many others exist where
using a DC reference voltage or AC-coupling are common. A good compilation of options can be found in SingleSupply Op Amp Design Techniques.
8.5 Power Shutdown Operation
As noted, the 6-pin packages that offer a power shutdown feature must have that pin asserted. To retain the
lowest possible shutdown power, no internal pullup resistors are present in the OPA838. The control threshold is
referenced off the negative supply with a nominal internal threshold near 1 V above the negative supply. Worstcase tolerances dictate the required low-level voltage to ensure shutdown of 0.55 V or less above the negative
supply and 1.5 V or greater above the negative supply to ensure enabled operation. The required control pin
current is less than ±50 nA. For SOT-23-6 applications that do not require a shutdown functionality, connect the
disable control pin to the positive supply. For SC70 package applications that do not require a shutdown, use the
5-pin package where the control pad is internally connected to the positive supply. When disabled, the output
nominally goes to a high impedance. However, the feedback network provides a path for discharge for off state
voltage condition. Figure 51 illustrates the turnon time with a sinusoidal input that is relatively slow, while
Figure 52 illustrates the turnoff time is fast. Figure 53 and Figure 54 illustrate the single-supply operation with a
DC input to produce a midsupply output at gains of 6 V/V and 10 V/V. In all cases, the output voltage transitions
to a point close to the positive supply voltage and then moves to the desired output voltage 0.5 µs to 1.5 µs after
the disable control line goes high. The supply current in shutdown is a low 0.1 µA nominally with a maximum
1 µA.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Noninverting Amplifier
The OPA838 can be used as noninverting amplifier with signal input to the noninverting input (VIN+). Figure 61
illustrates a basic block diagram of the circuit. VREF is often ground when split supplies are used.
If VIN = VREF + VSIG, and the gain setting resistor (RG) is DC referenced to VREF, use Equation 1 to calculate the
output of the amplifier.
æ
RF ö
V
= VSIG ç 1 +
÷ + VREF
OUT
RG ø
è
(1)
RF
RG
G= 1 +
The noninverting signal gain (also called the noise gain) of the circuit is set by:
VREF provides a reference around which the input and output signals swing. Output signals are in-phase with the
input signals within the flat portion of the frequency response. For a high-speed, low-noise device like the
OPA838, the values selected for RF (and the RG for the desired gain) can strongly influence the operation of the
circuit. For the characteristic curves, the noninverting circuit of Figure 74 shows the test configuration. Table 1
lists the recommended resistor values over gain.
RG 200 Ÿ
RF 1 NŸ
Å 50 Ÿ VRXUFH
VEE
50 Ÿ
Cable
±
RS 50 Ÿ
+
R3 1.96 NŸ
+
50 Ÿ
Cable
Network
Analyzer
Æ 2 NŸ ORDG
PD
+
R6 51.1 Ÿ
+
RT 50 Ÿ
Network
Analyzer
RLOAD 50 Ÿ
VM1
VCC
VCC
V
VEE
+
+
V1 2.5 V
V2 -2.5 V
Figure 74. Noninverting Characterization Circuit
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Application Information (continued)
Table 1 lists the recommended resistor values from target gains of 6 V/V to 20 V/V. This table controls the RF
and RG values to set the resistor noise contribution at approximately 40% of the total output noise power. This
increases the spot noise at the output over what the op amp voltage noise produces by 20%. Lower values
reduce the output noise of any design at the cost of more power in the feedback circuit. Using the TINA model
and simulation tool shows the impact of different resistor value choices on response shape and noise.
Table 1. Noninverting Recommended Resistor Values
TARGET
AVERAGE
RF (OHMS)
RG (OHMS)
6
1000
7
1180
8
9
ACTUAL GAIN (V/V)
GAIN (dB)
200
6
15.56
196
7.02
16.93
1370
196
7.99
18.05
1540
191
9.06
19.15
10
1690
187
10.04
20.03
11
1870
187
11
20.83
12
2050
187
11.96
21.56
13
2210
182
13.14
22.37
14
2370
182
14.02
22.94
15
2550
182
15.01
23.53
16
2740
182
16.05
24.11
17
2870
178
17.12
24.67
18
3090
182
17.98
25.09
19
3240
178
19.20
25.67
20
3400
178
20.1
26.06
21
3570
178
21.06
26.47
9.1.2 Inverting Amplifier
The OPA838 can be used as an inverting amplifier with signal input to the inverting input (VIN–) through the gainsetting resistor (RG.) Figure 62 illustrates a basic block diagram of the circuit.
If VIN = VREF + VSIG, and the noninverting input is DC biased to VREF, the output of the amplifier may be
calculated according to Equation 2.
æ -R
VOUT = VSIG ç F
è RG
ö
÷ + VREF
ø
(2)
-RF
G=
RG and V
The signal gain of the circuit
REF provides a reference point around which the input and output
signals swing. For bipolar-supply operation, VREF is often GND. The output signal is 180˚ out-of-phase with the
input signal in the passband of the application. Figure 75 illustrates the 50-Ω input matched configuration used
for the inverting characterization plots. In this case, an added termination resistor is placed in parallel with the
input RG resistor to provide an impedance match to 50-Ω test equipment. Table 2 lists the suggested values for
RF, RG, and RT for inverting gains from –6 V/V to –20 V/V.
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50 Ÿ input
matching
RG 187 Ÿ
RT 68.1 Ÿ
+
RF 1.87 NŸ
VSOURCE
±
RB 191 Ÿ
+
VCC
Gain of -10 V/V
VEE
VOUT
+
RLOAD 2 NŸ
RG 50 Ÿ
PD
VCC
VEE
+
+
V3 2.5 V
V4 -2.5 V
Figure 75. Inverting With Input Impedance Matching
Table 2. Inverting Recommended Resistor Values
AVERAGE
RF (OHMS)
RG
(OHMS)
EXACT RT
STANDARD RT
INPUT ZI
ACTUAL (V/V)
GAIN (dB)
–6
1180
196
67.1
66.5
49.7
–6.02
15.59
–7
1370
196
67.1
66.5
49.7
–6.99
16.89
–8
1540
191
67.7
68.1
50.2
–8.06
18.13
–9
1690
187
68.2
68.1
49.9
–9.04
19.12
–10
1870
187
68.2
68.1
49.9
–10
20
–11
2050
187
68.2
68.1
49.9
–10.96
20.80
–12
2210
182
68.9
68.1
49.6
–12.14
21.69
–13
2370
182
68.9
68.1
49.6
–13.02
22.29
–14
2550
182
68.9
68.1
49.6
–14.01
22.93
–15
2740
182
68.9
68.1
49.6
–15.05
23.55
–16
2870
178
69.5
69.8
50.1
–16.12
24.15
–17
3090
182
68.9
69.8
50.5
–16.98
24.6
–18
3240
178
69.5
69.8
50.1
–18.20
25.2
–19
3400
178
69.5
69.8
50.1
–19.10
25.62
–20
3570
178
69.5
69.8
50.1
–20.06
26.04
9.1.3 Output DC Error Calculations
The OPA838 can provide excellent DC signal accuracy due to high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full
advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise
input stage for the OPA838 has a relatively high input bias current (1.6 µA typical out the pins) but with a close
match between the two input currents. This is a negative rail input device using PNP input devices where the
base current flows out of the device pins. A large resistor to ground on the V+ input shifts positively because of
the input bias current. The mismatch between the two input bias currents is very low, typically only ±20 nA of
input offset current. Match the DC source impedances out of the two inputs to reduce the total output offset
voltage. For example, one way to add bias current cancellation to the circuit in Figure 68 is to insert a 165-Ω
series resistor into the noninverting input to match the parallel combination of RF and RG for this basic gain of
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6 V/V noninverting gain circuit. These same calculations apply to the output offset drift. Analyzing the simple
circuit of Figure 68, the noise gain for the input offset voltage drift is 1 + 1k / 200 = 6 V/V. This results in an
output drift term of ±1.6 µV/°C × 6 = ±9.6 µV/°C. Because the two impedances out of the inputs are matched, the
residual error due to the maximum ±500 pA/°C offset current drift is exactly that number times the 1-kΩ feedback
resistor value, or ±50 µV/°C. The total output DC error drift band is ±59 µV/°C.
9.1.4 Output Noise Calculations
The decompensated voltage feedback of the OPA838 op amp offers among the lowest input voltage and current
noise terms for any device with a supply current less than 1 mA. Figure 76 shows the op amp noise analysis
model that includes all noise terms. In this model, all the noise terms are shown as noise voltage or current
density terms in nV/√Hz or pA/√Hz.
ENI
+
OPA838
RS
EO
IBN
ERS
RF
4kTRS
RG
4kTRF
IBI
4kT
RG
4kT = 1.6E ± 20J
at 290° K
Figure 76. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation is adding all the contributing noise powers at the output by superposition,
then taking the square root to return to a spot noise voltage. Equation 3 shows the general form for this output
noise voltage using the terms presented in Figure 76.
EO
2
ªENI
¬
IBNRS
4kTRS º NG2
¼
IBIRF
2
4kTRFNG
(3)
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Dividing this expression by the noise gain (NG = 1 + RF / RG) gives the equivalent input referred spot noise
voltage at the noninverting input, as shown in Equation 4.
EN
2
ENI
IBNRS
2
4kTRS
§ IBIRF ·
¨ NG ¸
©
¹
2
4kTRF
NG
(4)
Using the resistor values shown in Table 1 with RS = 0 Ω results in a constant input referred voltage noise of
2.86nV / √Hz. Reducing the resistor values brings this number closer to the intrinsic 1.9 nV / √Hz of the OPA838.
Adding RS for bias current cancellation in noninverting mode adds the noise from RS to the total output noise, as
shown in Equation 3. In inverting mode, the RS bias current cancellation resistor must be bypassed with a
capacitor for the best noise performance.
9.1.5 High-Gain Differential I/O Designs
A high-gain differential-to-differential I/O circuit can be used to drive a second-stage FDA or a differential-tosingle-ended stage. This circuit is frequently used in applications where high input impedance is required (for
example, if the source cannot be loaded). Figure 76 illustrates an example design where the differential gain is
41 V/V. An added element between the two RG resistors increases the noise gain for the common-mode
feedback. It is important to provision for the added element because a decompensated VFA (like the OPA838)
often oscillates without it in this circuit. With only the RG elements in the differential I/O design, the commonmode feedback is unity-gain and often causes high-frequency, common-mode oscillations. To resolve this issue,
split the RG elements in half and add a low-impedance path such as a capacitor or a DC reference between the
two RG values.
VCC
+
PD
OPA838
±
VEE
RG1 88.7 Ÿ
CCM
RF 3.57 NŸ
R1 500 Ÿ
Vindiff
Vodiff
VCM
10nF
RG1 88.7 Ÿ
RF 3.57 NŸ
R2 500 Ÿ
VCC
±
PD
OPA838
+
High Gain
Differential
I/O
VEE
Figure 77. High-Gain Differential I/O Stage
Integrated results are available, but the OPA838 device provides a low-power, high-frequency result. For best
CMRR performance, resistors must be matched. A good rule is CMRR ≈ the resistor tolerance; so 0.1%
tolerance provides approximately 60-dB CMRR.
9.1.5.1 Differential I/O Design Requirements
As an example design, start with the circuit in Figure 77.
• Set the target gain and split the RG element in half. For this example, target a gain of 41 V/V.
• Assess the DC common-mode biasing on the noninverting inputs. The DC biasing must be in range and have
a gain of 1 to the output. This is not illustrated in Figure 76.
• If a DC reference is used as the mid-R G bias, setting the reference equal to the noninverting input bias
voltage sets the output common-mode to that voltage. Using a capacitor as illustrated in Figure 76
accomplishes the same results.
9.1.5.2 Detailed Design Procedure
• Set the total R G value near the high gain values using Table 1. This 178-Ω total must be split for a center tap
to increase the common-mode noise gain, as shown by the 88.7-Ω value in Figure 77.
• Set RF using a standard value near the calculated from solving Equation 1 using half of the total RG value.
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Simulate the common-mode noise with different elements on the RG center tap, as shown in Figure 78.
Decide which is most appropriate to the application.
The common-mode loop instability without the RG center tap is not often apparent in the closed-loop differential
simulations. It can often be detected in a common-mode output noise simulation as Figure 78 shows. Grounding
the inputs Figure 77 and running a output noise simulation for the common-mode tap point in Figure 76 shows a
peaking in the noise at high frequency. This peaking indicates low-phase margin for the common-mode loop.
Figure 78 shows this peaking in the lowest noise curve, with two options for improving phase margin. The first
option used in Figure 77 is a capacitor to ground set to increase the common-mode noise gain only at higher
frequencies. This can be seen by the peaking in the common-mode noise of Figure 78. Another alternative is to
provide a DC voltage reference on the RG center tap. This raises the common-mode noise gain from DC on up in
frequency. Neither of these latter two show any evidence of low phase margin peaking. They do increase the
output common-mode noise significantly at lower frequencies. Typically, an increase in output common-mode
noise is more acceptable than low-phase margin as the next stage (FDA, ADC, differential to single stage)
rejects common-mode noise.
180
No center tap
10 nF
Ground
Output Noise (nV/vHz)
160
140
120
100
80
60
40
20
0
10k
100k
1M
Frequency (Hz)
10M
100M
Diff
Figure 78. Common-Mode Output Noise for Differential I/O Design
Using the 10-nF center tap capacitor, Figure 79 shows the differential I/O small-signal response showing the
expected 300 MHz / 41 ≈ 7.3 MHz closed-loop bandwidth. The capacitor to ground between the RG elements
does not impact the differential frequency response.
33
30
Gain (dB)
27
24
21
18
15
12
1
10
Frequency (MHz)
100
D074
Figure 79. Differential Small-Signal Frequency Response
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9.1.6 Transimpedance Amplifiers
A common application for a high gain bandwidth voltage feedback op amp is to amplify a small photo-diode
current from a capacitive detector. Figure 80 shows the front page transimpedance circuit with more detail. Here,
a fixed –0.23 negative voltage generator (LM7705) is used on the negative supply to ensure the output has
adequate headroom when it is at 0 V. The transimpedance stage is designed here for a 2.4Mhz flat (Butterworth)
response while a simple RC post-filter band-limits the broadband noise and sets the overall bandwidth to 1MHz.
The requirements for a high dynamic range transimpedance (or charge) amplifier include the very low input
voltage noise intrinsic to a decompensated device like the OPA838. The noise gain over frequency for this type
of circuit starts out at unity gain then begins to peak with a single zero response due to the pole formed in the
feedback by the feedback resistor and the total capacitance on the inverting input. That noise gain response is
flattened out at higher frequencies by the feedback capacitor value to be the 1 + CS/CF capacitor ratio. This is
normally a very high noise gain allowing the decompensated OPA838 to be applied to this application. Since the
noise gain is intentionally peaked to a high value in this application, the very low input voltage noise (1.8 nV/√Hz)
of the OPA838 improves dynamic range.
CF1.0 pF
RF100 k
CS 100 pF
IDIODE
2.4-Mhz
Butterworth
1-MHz
Low Pass
VEE
R1 20
C1 1 uF
RM 100 k
+
Bias Current
Cancellation
and R-noise
filtering
+
R2 73.2
C3 2.2 nF
U1 OPA838
±
PD
VCC
VCC
+
VOUT
VM1
VEE
+
V1 3 V
LM7805 ± 230 mV
Figure 80. 100-kΩ Wide Bandwidth Transimpedance Design
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9.1.7 Design Requirements
To implement a controlled frequency response transimpedance design, set the transimpedance stage amplifier
bandwidth higher than a controlled post RC filter. This allows variation in the source capacitance and amplifier
gain bandwidth product with less overall bandwidth variation to the final output. In this example design:
• Assume a nominal source capacitance value of 100 pF. This normally comes from the capacitance versus
reverse bias plot for the photodiode. No reverse bias is illustrated in Figure 81, but the current source is
typically a back biased diode with a negative supply on the anode and the cathode connected to the op amp
inverting input. In this polarity, the signal current sinks into the diode and raises the op amp output voltage
above ground.
• For the best DC precision, add a matching resistor on the noninverting input to reduce the input bias current
error to IOS × RF . This resistor adds to the input voltage noise; TI recommends bypassing that resistor with as
large as a capacitor as required to roll off resistor noise. This capacitor has a relatively low frequency self
resonance that interacts with the input stage and might impair stability. Add a small series 20-Ω resistor from
the capacitor into the noninverting input to de-Q the resonant source impedance without adding too much
noise.
• Set the feedback capacitor to achieve the desired frequency response shape.
• Add a post RC filter to control the overall bandwidth to 1 MHz. In this example, a 2.2-nF capacitor allows a
low 73.2-Ω series resistor. When driving a sampling ADC (like a SAR), this combination helps reduce the
sampling glitch and speed settling time.
9.1.7.1 Detailed Design Procedure
The primary design requirement is to set the achievable transimpedance gain and compensate the operational
amplifier with CF for the desired response shape. A detailed transimpedance design methodology is available in
Transimpedance Considerations for High-Speed Amplifiers. With a source capacitance set and the amplifier
selected to provide a particular gain bandwidth product, the achievable transimpedance gain and resulting
Butterworth bandwidth are tightly coupled as Equation 5 illustrates. Use Equation 6 to solve for a maximum RF
value. When the RF is selected, the feedback pole is set by Equation 7 to be at .707 of the characteristic
frequency. At that compensation point, the closed-loop bandwidth is that characteristic frequency with a
Butterworth response.
• With the 100-pF source capacitance, 300-MHz gain bandwidth product, and the 2.2-MHz closed-loop
bandwidth target in the transimpedance stage, solve Equation 6 for a maximum gain of 100 kΩ.
• Set the feedback pole at 0.707 times that 2.2-MHz Butterworth bandwidth. This sets the target 1 / (2π × R F ×
CF) = 1.55 MHz. Solving for CF sets the target to 1 pF
• If DC precision is desired, add a 100-kΩ resistor to ground on the noninverting input. If DC precision is not
required, ground the noninverting input
• Add a resistor noise filtering capacitor in parallel with the 100-kΩ resistor.
• Add a small series resistor isolating this capacitor from the noninverting input.
• Select a final filter capacitor for the load. (In this example, a value of 2.2 nF is used as a typical SAR input
capacitor.)
• Add a series resistor to the final filter capacitor to form a 1-MHz pole. In this example, that is 73.2 Ω.
• Confirm this resistor is greater than the minimum recommended value illustrated in Figure 49.
F
3dB
|
R ¦ PD[ |
1
2SR¦C¦
GBP
2SR ¦CS
(5)
GBP
F23dB 2SCS
0.707 u
(6)
GBP
2SR ¦CS
(7)
Implementing this design and simulating the performance using the TINA model for the response to the output
pin and to the final capacitive load shows the expected results of Figure 81. Here the exact 2.2-MHz flat
Butterworth response to the output pin is shown with the final single pole rolloff at 1 MHz at the final 2.2-nF
capacitor.
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103
100
97
Gain (dBohm)
94
91
88
85
82
79
76
73
0.001
Gain output pin
Gain Load (dB)
0.01
0.1
Frequency (MHz)
1
10
D075
Figure 81. Small-Signal Response for 100-kΩ Transimpedance Gain
10 Power Supply Recommendations
The OPA838 device is intended to work in a supply range of 2.7 V to 5.4 V. Good power-supply bypassing is
required. Minimize the distance (less than 0.1 inch) from the power-supply pins to high-frequency, 0.1-μF
decoupling capacitors. A larger capacitor (2.2 µF is typical) is used with a high-frequency, 0.1-µF supplydecoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these
capacitors. When a split-supply is used, use these capacitors for each supply to ground. If necessary, place the
larger capacitors further from the device and share these capacitors among several devices in the same area of
the PCB. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. An optional 0.1-µF supply decoupling capacitor across the two power supplies (for bipolar operation)
reduces second harmonic distortion.
The OPA838 has a positive supply current temperature coefficient; see Figure 57. This helps improve the input
offset voltage drift. Supply current requirements in system design must account for this effect using the maximum
intended ambient and Figure 57 to size the supply required. The very low power dissipation for the OPA838
typically does not require any special thermal design considerations. For the extreme case of 125°C operating
ambient, use the approximate maximum 200°C/W for the three packages, and a maximum internal power of
5.4-V supply × 1.25-mA 125°C supply current from Figure 57 gives a maximum internal power of 6.75 mW. This
only gives a 1.35°C rise from ambient to junction temperature which is well below the maximum 150°C junction
temperature. Load power adds to this, but also increases the junction temperature only slightly over ambient
temperature.
36
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11 Layout
11.1 Layout Guidelines
The OPA838 EVM can be used as a reference when designing the circuit board. TI recommends following the
EVM layout of the external components near to the amplifier, ground plane construction, and power routing as
closely as possible. General guidelines are listed below:
1. Signal routing must be direct and as short as possible into and out of the op amp.
2. The feedback path must be short and direct avoiding vias if possible.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. TI recommends placing a series output resistor as close to the output pin as possible when driving capacitive
or matched loads.
5. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be
shared with other op amps. For split-supply operation, a capacitor is required for both supplies.
6. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible,
preferably within 0.1 inch. For split-supply operation, a capacitor is required for both supplies.
7. The PD pin uses logic levels referenced off the negative supply. If the pin is not used, the pin must tie to the
positive supply to enable the amplifier. If the pin is used, the pin must be actively driven. A bypass capacitor
is not necessary, but is used for EMI rejection in noisy environments.
11.2 Layout Example
Ground and power plane exist on
inner layers
Ground and power plane removed
from inner layers
Place output resistors close
to output pins to minimize
parasitic capacitance
1
6
Place bypass capacitors
close to power pins
Non-inverting input
terminated in 50 Ÿ
+
2
3
±
Place bypass capacitors
close to power pins
5
Power control (disable) pin
Must be driven
4
Place input resistor close to pin 4
to minimize stray capacitance
Place feedback resistor on the bottom
of PCB between pins 4 and 6
Remove GND and Power plane
under pins 1 and 4 to minimize
stray PCB capacitance
Figure 82. EVM Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Support
12.1.1.1 TINA-TI™ Simulation Model Features
The device model is available on the product folder www.ti.com in a typical application circuit file. The model
includes numerous features intended to speed designer progress over a wide range of application requirements.
The following list shows the performance parameters included in the model:
• For the small-signal response shape with any external circuit:
– Differential Open-Loop Gain and Phase
– Parasitic Input Capacitance
– Open-Loop Differential Output Impedance
• For noise simulations:
– Input Differential Spot Voltage Noise and a 100-Hz 1/f Corner
– Input Current Noise on Each Input With a 6-kHz 1/f Corner
• For time-domain, step-response simulations:
– Differential Slew Rate
– I/O Headroom Models to Predict Clipping
– Input Stage Diodes to Predict Overdrive Limiting
• Fine-scale, DC precision terms
– PSRR
– CMRR
– Nominal Input Offset Voltage
– Nominal Input Offset Current
– Nominal Input Bias Current
The Typical Characteristics table provides more detail than the macromodels can provide. Some of the
unmodeled features include:
• Harmonic Distortion
• Temperature Drift in DC Error (VIO and IOS)
• Overdrive Recovery Time
• Turnon and Turnoff Times Using the Power-Down Feature
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, OPA835DBV, OPA836DBV EVM user's guide
12.2.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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Documentation Support (continued)
12.2.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA838IDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1C3F
OPA838IDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1C3F
OPA838IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
17Q
OPA838IDCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
17Q
OPA838SIDCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19C
OPA838SIDCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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