OPA858-Q1
OPA858-Q1
SBOSA58 – FEBRUARY
2021
SBOSA58 – FEBRUARY 2021
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OPA858-Q1 5.5-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, FET Input
Amplifier
1 Features
3 Description
•
The OPA858-Q1 is a wideband, low-noise operational
amplifier with CMOS inputs for wideband
transimpedance and voltage amplifier applications.
When the device is configured as a transimpedance
amplifier (TIA), the 5.5-GHz gain bandwidth product
(GBWP) enables high closed-loop bandwidths at
transimpedance gains in the range of tens to
hundreds of kΩs.
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
•
•
•
Automotive LIDAR
Time of flight (ToF) Camera
Optical Time Domain Reflectometry (OTDR)
3D Scanner
Laser Distance Measurement
Solid-State Scanning LIDAR
Optical ToF Position Sensor
Drone Vision
Silicon Photomultiplier (SiPM) Buffer Amplifier
Photomultiplier Tube Post Amplifier
The graph below shows the bandwidth and noise
performance of the OPA858-Q1 as a function of the
photodiode capacitance when the amplifier is
configured as a TIA. The total noise is calculated
along a bandwidth range extending from DC to the
calculated frequency (f) on the left scale. The
OPA858-Q1 package has a feedback pin (FB) that
simplifies the feedback network connection between
the input and the output.
The OPA858-Q1 is optimized to operate in optical
time-of-flight (ToF) systems where the OPA858-Q1 is
used with time-to-digital converters, such as the
TDC7201. Use the OPA858-Q1 to drive a high-speed
analog-to-digital converter (ADC) in high-resolution
LIDAR systems with a differential output amplifier,
such as the THS4541-Q1.
Device Information
PART NUMBER(1)
OPA858-Q1
(1)
RF
5V
TLV3501
±
+
3.5 V
OPA858
+
Stop 2
VREF
±
Start 2
Object
CF
TDC7201
(Time-toDigital
Converter)
RF
VBIAS
5V
TLV3501
±
+
3.5 V
+
OPA858
VREF
Stop 1
±
Start 1
110
f-3dB , R F = 10 k:
f-3dB , R F = 20 k:
IRN , R F = 10 k:
IRN , R F = 20 k:
400
350
Pulsed Laser
Diode
MSP430
Controller
100
90
300
80
250
70
200
60
150
50
100
40
50
30
0
0
Tx
Lens
2.00 mm × 2.00 mm
450
Closed-loop Bandwidth, f -3dB (MHz)
Rx
Lens
WSON (8)
BODY SIZE (NOM)
For all available packages, see the package option
addendum at the end of the data sheet.
CF
VBIAS
PACKAGE
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
20
20
Integrated Input Referred Noise, I RN (nA RMS )
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications:
– Temperature grade 1: –40°C to +125°C, TA
High Gain Bandwidth Product: 5.5 GHz
Decompensated, Gain ≥ 7 V/V (Stable)
Ultra-Low Bias Current MOSFET Inputs: 10 pA
Low Input Voltage Noise: 2.5 nV/√Hz
Slew rate: 2000 V/µs
Low Input Capacitance:
– Common-Mode: 0.6 pF
– Differential: 0.2 pF
Wide Input Common-Mode Range:
– 1.4 V from Positive Supply
– Includes Negative Supply
2.5 VPP Output Swing in TIA Configuration
Supply Voltage Range: 3.3 V to 5.25 V
Quiescent Current: 20.5 mA
Package: 8-Pin WSON
Temperature Range: –40°C to +125°C
D209
Photodiode Capacitance vs Bandwidth and Noise
High-Speed Time-of-Flight Receiver
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SBOSA58 – FEBRUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................ 8
7 Parameter Measurement Information.......................... 15
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................20
9 Application and Implementation.................................. 21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................25
11 Layout........................................................................... 26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................28
12.1 Device Support....................................................... 28
12.2 Documentation Support.......................................... 28
12.3 Receiving Notification of Documentation Updates..28
12.4 Support Resources................................................. 28
12.5 Trademarks............................................................. 28
12.6 Electrostatic Discharge Caution..............................28
12.7 Glossary..................................................................28
13 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February 2021
*
Initial Release
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Device Comparison Table
DEVICE
INPUT TYPE
MINIMUM
STABLE GAIN
VOLTAGE
NOISE (nV/√ Hz)
INPUT
CAPACITANCE (pF)
GAIN
BANDWIDTH (GHz)
OPA855-Q1
Bipolar
7 V/V
0.98
0.8
8
OPA858-Q1
CMOS
7 V/V
2.5
0.8
5.5
OPA859-Q1
CMOS
1 V/V
3.3
0.8
0.9
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5 Pin Configuration and Functions
FB
1
NC
2
8
PD
7
VS+
Thermal pad
IN±
3
6
OUT
IN+
4
5
VS±
Not to scale
Figure 5-1. DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
FB
1
I
Feedback connection to output of amplifier
IN–
3
I
Inverting input
IN+
4
I
Noninverting input
NC
2
—
Do not connect
OUT
6
O
Amplifier output
PD
8
I
Power down connection. PD = logic low = power off mode; PD = logic high = normal operation.
VS–
5
—
Negative voltage supply
VS+
7
—
Positive voltage supply
—
Connect the thermal pad to VS–
Thermal pad
4
NO.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VS
Total supply voltage (VS+ – VS– )
VIN+, VIN–
Input voltage
VID
Differential input voltage
VOUT
Output voltage
MIN
MAX
UNIT
5.5
V
(VS–) – 0.5
(VS+) + 0.5
V
1
V
(VS–) – 0.5
(VS+) + 0.5
V
IIN
Continuous input current
IOUT
Continuous output current(2)
TJ
Junction temperature
150
°C
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
±10
mA
±100
mA
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Long-term continuous output current for electromigration limits.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
± 1500
Charged-device model (CDM), per AEC
Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
5
5.25
V
125
°C
VS
Total supply voltage (VS+ – VS– )
3.3
TA
Operating free-air temperature
–40
UNIT
6.4 Thermal Information
OPA858-Q1
THERMAL METRIC(1)
DSG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
80.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
100
°C/W
RθJB
Junction-to-board thermal resistance
45
°C/W
ΨJT
Junction-to-top characterization parameter
6.8
°C/W
ΨJB
Junction-to-board characterization parameter
45.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
22.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
Small-signal bandwidth
VOUT = 100 mVPP
1.2
GHz
LSBW
Large-signal bandwidth
VOUT = 2 VPP
600
MHz
GBWP
Gain-bandwidth product
5.5
GHz
Bandwidth for 0.1-dB flatness
130
MHz
2000
V/µs
SR
Slew rate (10% - 90%)
VOUT = 2-V step
tr
Rise time
VOUT = 100-mV step
0.3
ns
tf
Fall time
VOUT = 100-mV step
0.3
ns
Settling time to 0.1%
VOUT = 2-V step
8
ns
Settling time to 0.001%
VOUT = 2-V step
3000
ns
Overshoot or undershoot
VOUT = 2-V step
7%
Overdrive recovery
2x output overdrive (0.1% recovery)
200
HD2
Second-order harmonic distortion
HD3
Third-order harmonic distortion
f = 10 MHz, VOUT = 2 VPP
88
f = 100 MHz, VOUT = 2 VPP
64
f = 10 MHz, VOUT = 2 VPP
86
f = 100 MHz, VOUT = 2 VPP
68
ns
dBc
dBc
en
Input-referred voltage noise
f = 1 MHz
2.5
nV/√Hz
ZOUT
Closed-loop output impedance
f = 1 MHz
0.15
Ω
72
75
dB
–5
±0.8
DC PERFORMANCE
AOL
Open-loop voltage gain
VOS
Input offset voltage
TA = 25°C
ΔVOS/ΔT
Input offset voltage drift
TA = –40°C to +125°C
5
IBN, IBI
Input bias current
TA = 25°C
±0.4
5
pA
IBOS
Input offset current
TA = 25°C
±0.01
5
pA
CMRR
Common-mode rejection ratio
VCM = ±0.5 V, referenced to midsupply
±2
70
mV
µV/°C
90
dB
INPUT
Common-mode input resistance
CCM
Common-mode input capacitance
Differential input resistance
CDIFF
Differential input capacitance
VIH
Common-mode input range (high)
CMRR > 66 dB, VS+ = 3.3 V
VIL
Common-mode input range (low)
CMRR > 66 dB, VS+ = 3.3 V
VIH
Common-mode input range (high)
VIL
Common-mode input range (low)
CMRR > 66 dB
1.7
1
GΩ
0.62
pF
1
GΩ
0.2
pF
1.9
0
3.4
TA = –40°C to +125°C, CMRR > 66 dB
V
0.4
3.6
V
3.3
CMRR > 66 dB
0
TA = –40°C to +125°C, CMRR > 66 dB
V
0.4
0.35
V
OUTPUT
VOH
Output voltage (high)
VOH
Output voltage (high)
VOL
Output voltage (low)
VOL
6
Output voltage (low)
TA = 25°C, VS+ = 3.3 V
TA = 25°C
TA = –40°C to +125°C
2.3
2.4
3.95
4.1
V
V
3.9
TA = 25°C, VS+ = 3.3 V
1.05
1.15
TA = 25°C
1.05
1.15
TA = –40°C to +125°C
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1.2
V
V
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6.5 Electrical Characteristics (continued)
VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RL = 10 Ω, AOL > 60 dB
Linear output drive (sink and source)
ISC
MIN
TYP
65
80
TA = –40°C to +125°C, RL = 10 Ω,
AOL > 60 dB
Output short-circuit current
MAX
mA
64
85
UNIT
105
mA
POWER SUPPLY
VS
Operating voltage
3.3
5.25
IQ
Quiescent current
VS+ = 5 V
IQ
Quiescent current
VS+ = 3.3 V
IQ
Quiescent current
VS+ = 5.25 V
IQ
Quiescent current
TA = 125°C
IQ
Quiescent current
TA = –40°C
PSRR+
Positive power-supply rejection ratio
74
84
PSRR–
Negative power-supply rejection ratio
70
80
V
18
20.5
24
mA
17.5
20
23.5
mA
21
24
mA
18
24.5
mA
18.5
mA
dB
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Enable voltage threshold
Amplifier ON above this voltage
0.65
1
V
1.5
1.8
V
Power-down quiescent current
70
140
µA
PD bias current
70
200
µA
Turnon time delay
Time to VOUT = 90% of final value
Turnoff time delay
13
ns
120
ns
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6.6 Typical Characteristics
at VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
3
4
0
0
Normalized Gain (dB)
Normalized Gain (dB)
2
-2
-4
-6
-8
-10
-12
1M
Gain = +7 V/V
Gain = +10 V/V
Gain = +20 V/V
Gain = 7 V/V
10M
-3
-6
-9
VS = 5 V
VS = 3.3 V
100M
Frequency (Hz)
1G
-12
1M
5G
10M
100M
Frequency (Hz)
D100
VOUT = 100 mVPP; see Figure 7-1 and Figure 7-2 for circuit
configuration
Figure 6-1. Small-Signal Frequency Response vs Gain
1G
5G
D102
VOUT = 100 mVPP
Figure 6-2. Small-Signal Frequency Response vs Supply
Voltage
3
2
1
0
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
-6
-9
-12
1M
-2
-3
-4
-5
TA = 40qC
TA = 0qC
TA = 25qC
TA = 85qC
TA = 125qC
-6
RL = 200 :
RL = 400 :
RL = 100 :
10M
-1
-7
100M
Frequency (Hz)
1G
-8
1M
5G
VOUT = 100 mVPP
2
2
0
Normalized Gain (dB)
Normalized Gain (dB)
4
-2
-4
-6
-12
1M
RS = 24 :, C L = 10 pF
RS = 10 :, C L = 47 pF
RS = 5.6 :, C L = 100 pF
RS = 1.8 :, C L = 1 nF
10M
100M
Frequency (Hz)
D104
0
-2
-4
-6
-8
-10
-12
1M
1G
D105
VOUT = 100 mVPP; see Figure 7-3 for circuit configuration
Figure 6-5. Small-Signal Frequency Response vs Capacitive
Load
8
1G
Figure 6-4. Small-Signal Frequency Response vs Ambient
Temperature
4
-10
100M
Frequency (Hz)
VOUT = 100 mVPP
Figure 6-3. Small-Signal Frequency Response vs Output Load
-8
10M
D103
Gain = 7 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 7 V/V
10M
100M
Frequency (Hz)
1G
D106
VOUT = 2 VPP
Figure 6-6. Large-Signal Frequency Response vs Gain
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6.6 Typical Characteristics (continued)
at VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
0.4
4
0.3
2
Normalized Gain (dB)
Normalized Gain (dB)
0.2
0.1
0
-0.1
-0.2
-0.3
0
-2
-4
-6
-8
-0.4
-10
-0.5
10M
100M
Frequency (Hz)
-12
1M
1G
VOUT = 2 VPP
VS = 3.3 V
Figure 6-7. Large-Signal Response for 0.1-dB Gain Flatness
Open-Loop Magnitude (dB)
0.1
1M
10M
Frequency (Hz)
-45
45
-90
30
-135
15
-180
0
-225
100k
10M
100M
Frequency (Hz)
-270
10G
1G
D500
Small-Signal Response
Figure 6-9. Closed-Loop Output Impedance vs Frequency
Figure 6-10. Open-Loop Magnitude and Phase vs Frequency
3.2
Input Referred Voltage Noise (nV/ —Hz)
100
Input Referred Voltage Noise (nV/ —Hz)
1M
D109
Small-Signal Response
10
1
1k
D108
60
-15
10k
100M
5G
45
AOL magnitude (dB)
AOL phase (q)
0
75
1
1G
VOUT = 1 VPP
90
Gain = 7 V/V
Gain = 20 V/V
10
100M
Frequency (Hz)
Figure 6-8. Large-Signal Frequency Response
100
Closed-Loop Output Impedance (:)
10M
D107
Open-Loop Phase (q)
-0.6
1M
10k
100k
1M
Frequency (Hz)
10M
100M
3
2.8
2.6
2.4
2.2
2
1.8
-40
D111
-20
0
20
40
60
80
Ambient Temperature (qC)
100
120
140
D112
Frequency = 10 MHz
Figure 6-11. Voltage Noise Density vs Frequency
Figure 6-12. Voltage Noise Density vs Ambient Temperature
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6.6 Typical Characteristics (continued)
at VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
-40
-40
-60
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
HD2, VOUT = 0.5 VPP
HD2, VOUT = 1 VPP
HD2, VOUT = 2 VPP
HD2, VOUT = 2.5 VPP
-70
-80
-90
-100
10M
Frequency (Hz)
-100
-50
-70
-80
-90
-100
-110
10M
Frequency (Hz)
-70
-80
-90
-100
-120
1M
100M
D115
10M
Frequency (Hz)
100M
D116
VOUT = 2 VPP
Figure 6-16. Harmonic Distortion (HD3) vs Output Load
-40
-40
HD2, G = 7 V/V
HD2, G = 7 V/V
HD2, G = 20 V/V
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
HD3, RL = 100 :
HD3, RL = 200 :
HD3, RL = 400 :
-110
Figure 6-15. Harmonic Distortion (HD2) vs Output Load
-60
-70
-80
-90
-100
-110
HD3, G = 7 V/V
HD3, G = 7 V/V
HD3, G = 20 V/V
-60
-70
-80
-90
-100
-110
10M
Frequency (Hz)
100M
-120
1M
D117
VOUT = 2 VPP
10M
Frequency (Hz)
100M
D118
VOUT = 2 VPP
Figure 6-17. Harmonic Distortion (HD2) vs Gain
10
D114
-60
VOUT = 2 VPP
-120
1M
100M
-40
HD2, RL = 100 :
HD2, RL = 200 :
HD2, RL = 400 :
-60
-50
10M
Frequency (Hz)
Figure 6-14. Harmonic Distortion (HD3) vs Output Swing
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-90
D113
-40
-120
1M
-80
-120
1M
100M
Figure 6-13. Harmonic Distortion (HD2) vs Output Swing
-50
-70
-110
-110
-120
1M
-60
HD3, VOUT = 0.5 VPP
HD3, VOUT = 1 VPP
HD3, VOUT = 2 VPP
HD3, VOUT = 2.5 VPP
Figure 6-18. Harmonic Distortion (HD3) vs Gain
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6.6 Typical Characteristics (continued)
at VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
80
60
1.25
Input
Output
Input
Output
1
0.5
Voltage Swing (V)
Voltage Swing (mV)
0.75
40
20
0
-20
0.25
0
-0.25
-0.5
-40
-0.75
-60
-1
-80
-1.25
Time (5 ns/div)
Time (5 ns/div)
D119
Figure 6-19. Small-Signal Transient Response
Figure 6-20. Large-Signal Transient Response
80
3
60
Measured Output
Ideal Output
2
40
Voltage Swing (V)
Voltage Swing (mV)
D120
Average Rise and Fall Time (10% - 90%) = 750 ps
Average Rise and Fall Time (10% - 90%) = 450 ps
20
0
-20
-40
-60
RS = 24 :, CL = 10 pF
RS = 10 :, CL = 47 pF
RS = 5.6 :, CL = 100 pF
RS = 1.8 :, CL = 1 nF
1
0
-1
-2
-80
-3
0
Time (5 ns/div)
10
D121
20
30
40
50
60
Time (ns)
70
80
90
100
D122
2x Output Overdrive
Figure 6-22. Output Overload Response
5
5
4.5
4.5
4
4
3.5
3.5
Voltage Swing (V)
Voltage Swing (V)
Figure 6-21. Small-Signal Transient Response vs Capacitive
Load
3
2.5
2
1.5
1
Power Down (PD)
Output
3
2.5
2
1.5
1
Power Down (PD)
Output
0.5
0.5
0
0
Time (5 ns/div)
Time (5 ns/div)
D123
D124
VS+ = 5 V, VS– = Ground
VS+ = 5 V, VS– = Ground
Figure 6-23. Turnon Transient Response
Figure 6-24. Turnoff Transient Response
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6.6 Typical Characteristics (continued)
at VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
100
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
100
80
60
40
20
0
-20
10k
100k
1M
10M
Frequency (Hz)
100M
PSRR
PSRR+
80
60
40
20
0
-20
-40
10k
1G
100k
D125
Small-Signal Response
22.5
25
Quiescent Current (mA)
Quiescent Current (mA)
26
22
21.5
21
20.5
20
19.5
19
3.75
4
4.25 4.5
Total Supply Voltage (V)
D126
4.75
5
24
23
22
21
20
Unit 1 (VS = 3.3 V)
Unit 1 (VS = 5 V)
Unit 2 (VS = 3.3 V)
Unit 2 (VS = 5 V)
19
Unit1
Unit2
3.5
1G
Figure 6-26. Power Supply Rejection Ratio vs Frequency
23
3.25
100M
Small-Signal Response
Figure 6-25. Common-Mode Rejection Ratio vs Frequency
3
1M
10M
Frequency (Hz)
18
-40
5.25
-20
0
D160
2 Typical Units
20
40
60
80
Ambient Temperature (qC)
100
120
D161
2 Typical Units
Figure 6-27. Quiescent Current vs Supply Voltage
Figure 6-28. Quiescent Current vs Ambient Temperature
85
1.5
1.2
Offset Voltage (mV)
Quiescent Current (PA)
0.9
80
75
70
Unit 1
Unit 2
Unit 3
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
65
-40
-1.5
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
3
3.5
3.75
4
4.25 4.5
Total Supply Voltage (V)
4.75
5
5.25
D163
3 Typical Units
30 Units Tested
Figure 6-29. Quiescent Current (Amplifier Disabled) vs Ambient
Temperature
12
3.25
D162
Figure 6-30. Offset Voltage vs Supply Voltage
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6.6 Typical Characteristics (continued)
at VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
4
0.8
Unit 1
Unit 2
Unit 3
3.5
0.6
3
Offset Voltage (mV)
Offset Voltage (mV)
0.4
0.2
0
-0.2
-0.4
2.5
2
1.5
1
0.5
0
-0.5
-0.6
-1
-0.8
-40
-20
0
20
40
60
80
Ambient Temperature (qC)
µ = 1 µV/°C
σ = 2.2 µV/°C
100
120
-1.5
140
0
D164
28 Units Tested
Figure 6-31. Offset Voltage vs Ambient Temperature
VS = 3.3 V
D165
3 Typical Units
2
Unit 1
Unit 2
Unit 3
2.5
1.2
Offset Voltage (mV)
2
1.6
1.5
1
0.5
0
-0.5
0.8
0.4
0
-0.4
-0.8
-1
-1.2
-1.5
-1.6
-2
TA = 40qC
TA = 25qC
TA = 125qC
-2
0
0.5
VS = 5 V
1
1.5
2
2.5
3
3.5
Common-Mode Voltage (V)
4
4.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Common-Mode Voltage (V)
D166
3.2
3.6
4
D167
3 Typical Units
Figure 6-33. Offset Voltage vs Input Common-Mode Voltage
Figure 6-34. Offset Voltage vs Input Common-Mode Voltage vs
Ambient Temperature
2.5
4
2
3
1.5
2
Offset Voltage (mV)
Offset Voltage (mV)
2.25 2.5 2.75
Figure 6-32. Offset Voltage vs Input Common-Mode Voltage
3
Offset Voltage (mV)
0.25 0.5 0.75 1 1.25 1.5 1.75 2
Common-Mode Voltage (V)
1
0
-1
Unit 1
Unit 2
Unit 3
1
0.5
0
-0.5
-1
-2
-1.5
Unit 1
Unit 2
Unit 3
-3
-2
-4
1
VS = 3.3 V
1.2
1.4
1.6
1.8
2
Output Voltage (V)
2.2
2.4
2.6
-2.5
0.8
D168
3 Typical Units
VS = 5 V
Figure 6-35. Offset Voltage vs Output Swing
1.2
1.6
2
2.4
2.8
Output Voltage (V)
3.2
3.6
4
D169
3 Typical Units
Figure 6-36. Offset Voltage vs Output Swing
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6.6 Typical Characteristics (continued)
at VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
1.5
1000
100
Input Bias Current (pA)
Offset Voltage (mV)
1
0.5
0
-0.5
-1.5
0.8
1.2
1.6
2
2.4
2.8
Output Voltage (V)
3.2
3.6
1
0.1
TA = 40qC
TA = 25qC
TA = 125qC
-1
10
Unit 1
Unit 2
Unit 3
0.01
-40
4
-20
0
D170
20
40
60
80
Ambient Temperature (qC)
100
120
140
D171
3 Typical Units
Figure 6-38. Input Bias Current vs Ambient Temperature
5
4000
0
3500
3000
2000
1.5
2
2.5
3
Common-Mode Voltage (V)
3.5
4
σ = 0.2 mA
24
23
22
4555 units tested
Figure 6-40. Quiescent Current Distribution
Figure 6-39. Input Bias Current vs Input Common-Mode Voltage
1750
1200
1500
750
Offset Voltage (mV)
µ = –0.28 mV
σ = 0.8 mV
D141
4555 units tested
Figure 6-41. Offset Voltage Distribution
Input Bias Current (pA)
µ = –0.1 pA
σ = 0.39 pA
1.5
1
1.25
0.5
0.75
0
0.25
0
0
250
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
200
-0.25
500
-0.75
400
1000
-1
600
1250
-1.25
800
-1.5
Amplifiers (Count)
1000
Amplifiers (Count)
D140
Quiescent Current (mA)
D172
µ = 20.35 mA
14
23.5
1
22.5
0.5
-0.5
0
21
0
-30
21.5
500
20.5
-25
20
1000
19.5
1500
-20
19
-15
2500
18.5
-10
18
-5
Amplifiers (Count)
Input Bias Current (pA)
Figure 6-37. Offset Voltage vs Output Swing vs Ambient
Temperature
D142
4555 units tested
Figure 6-42. Input Bias Current Distribution
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7 Parameter Measurement Information
The various test setup configurations for the OPA858-Q1 are shown in Figure 7-1, Figure 7-2, and Figure 7-3.
When configuring the OPA858-Q1 in a gain of +39.2 V/V, feedback resistor RF was set to 953 Ω.
Figure 6-1 shows 5-dB of peaking with the amplifier in an inverting configuration of –7 V/V with the amplifier
configured as shown in Figure 7-2. The 50-Ω matched termination of this circuit configuration results in the
amplifier being configured in a noise gain of 5.3 V/V, which is lower than the recommended +7 V/V.
GND
50
2.5 V
50
50Source
169
+
±
í2.5 V
RG
50
71.5
453
50Measurement
System
GND
GND
GND
RG values depend on gain configuration
Figure 7-1. Noninverting Configuration
2.5 V
169
+
GND
50Source
50Measurement
System
±
í2.5 V
50
64
50
71.5
GND
453
GND
220
GND
Figure 7-2. Inverting Configuration (Gain = –7 V/V)
GND
50
50Source
2.5 V
50
+
RS
1k
±
í2.5 V
75
GND
453
CL
53.6
GND
GND
50
50Measurement
System
GND
Figure 7-3. Capacitive Load Driver Configuration
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8 Detailed Description
8.1 Overview
The ultra-wide, 5.5-GHz gain bandwidth product (GBWP) of the OPA858-Q1, combined with the broadband
voltage noise of 2.5 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed
data acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front
ends. The OPA858-Q1 combines multiple features to optimize dynamic performance. In addition to the wide,
small-signal bandwidth, the OPA858-Q1 has 600 MHz of large-signal bandwidth (VOUT = 2 VPP), and a slew rate
of 2000 V/µs.
The OPA858-Q1 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a
simple feedback network connection between the amplifiers output and inverting input. Excess capacitance on
an amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of
very wideband amplifiers like the OPA858-Q1. To reduce the effects of stray capacitance on the input node, the
OPA858-Q1 pinout features an isolation pin (NC) between the feedback and inverting input pins that increases
the physical spacing between them thereby reducing parasitic coupling at high frequencies. The OPA858-Q1
also features a very low capacitance input stage with only 0.8-pF of total input capacitance.
8.2 Functional Block Diagram
The OPA858-Q1 is a classic voltage feedback operational amplifier (op amp) with two high-impedance inputs
and a low-impedance output. Standard application circuits are supported, like the two basic options shown in
Figure 8-1 and Figure 8-2. The DC operating point for each configuration is level-shifted by the reference voltage
(VREF), which is typically set to midsupply in single-supply operation. VREF is typically connected to ground in
split-supply applications.
VSIG
VS+
VREF
VIN
(1 + RF / RG) × VSIG
+
VOUT
VREF
±
RG
VS±
VREF
RF
Figure 8-1. Noninverting Amplifier
VS+
VREF
VSIG
VREF
±(RF / RG) × VSIG
+
VOUT
VIN
RG
VREF
±
VS±
RF
Figure 8-2. Inverting Amplifier
16
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8.3 Feature Description
8.3.1 Input and ESD Protection
The OPA858-Q1 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as Figure 8-3 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
±
VINí
FB
VSí
Figure 8-3. Internal ESD Structure
8.3.2 Feedback Pin
The OPA858-Q1 pin layout is optimized to minimize parasitic inductance and capacitance, which is a critical care
about in high-speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The
FB pin is separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin
must be left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see
Figure 8-4) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by
increasing the physical separation between the pins.
RF
FB 1
8
PD
NC 2
7
VS+
6
OUT
5
VS±
±
IN± 3
+
IN+ 4
Figure 8-4. RF Connection Between FB and IN– Pins
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8.3.3 Wide Gain-Bandwidth Product
Figure 6-10 shows the open-loop magnitude and phase response of the OPA858-Q1. Calculate the gain
bandwidth product of any op amp by determining the frequency at which the AOL is 60 dB and multiplying that
frequency by a factor of 1000. The second pole in the AOL response occurs before the magnitude crosses 0 dB,
and the resultant phase margin is less than 0°. This indicates instability at a gain of 0 dB (1 V/V). Amplifiers that
are not unity-gain stable are known as decompensated amplifiers. Decompensated amplifiers typically have
higher gain-bandwidth product, higher slew rate, and lower voltage noise, compared to a unity-gain stable
amplifier with the same amount of quiescent power consumption.
Figure 8-5 shows the open-loop magnitude (AOL) of the OPA858-Q1 as a function of temperature. The results
show minimal variation over temperature. The phase margin of the OPA858-Q1 configured in a noise gain of 7
V/V (16.9 dB) is close to 55° across temperature. Similarly Figure 8-6 shows the AOL magnitude of the OPA858Q1 as a function of process variation. The results show the AOL curve for the nominal process corner and the
variation one standard deviation from the nominal. The simulated results suggest less than 1° of phase margin
difference within a standard deviation of process variation when the amplifier is configured in a gain of 7 V/V.
One of the primary applications for the OPA858-Q1 is as a high-speed transimpedance amplifier (TIA), as Figure
9-4 shows. The low-frequency noise gain of a TIA is 0 dB (1 V/V). At high frequencies the ratio of the total input
capacitance and the feedback capacitance set the noise gain. To maximize the TIA closed-loop bandwidth, the
feedback capacitance is typically smaller than the input capacitance, which implies that the high-frequency noise
gain is greater than 0 dB. As a result, op amps configured as TIAs are not required to be unity-gain stable, which
makes a decompensated amplifier a viable option for a TIA. What You Need To Know About Transimpedance
Amplifiers – Part 1 and What You Need To Know About Transimpedance Amplifiers – Part 2 describe
transimpedance amplifier compensation in greater detail.
90
90
AOL at 40qC
AOL at 25qC
AOL at +125qC
60
45
30
15
1M
10M
100M
Frequency (Hz)
1G
10G
45
30
15
-15
100k
D204
Figure 8-5. Open-Loop Gain vs Temperature
18
60
0
0
-15
100k
AOL ( V)
AOL (Typ.)
AOL ( V)
75
Open-Loop Gain (dB)
Open-Loop Gain (dB)
75
1M
10M
100M
Frequency (Hz)
1G
10G
D205
Figure 8-6. Open-Loop Gain vs Process Variation
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8.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA858-Q1 features a high slew rate of 2000 V/µs. The slew rate is a critical
parameter in high-speed pulse applications with narrow sub-10-ns pulses, such as optical time-domain
reflectometry (OTDR) and LIDAR. The high slew rate of the OPA858-Q1 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge, as seen in Figure 6-20. The wide bandwidth and slew rate of the OPA858Q1 make it an excellent amplifier for high-speed signal-chain front ends.
Figure 8-7 shows the open-loop output impedance of the OPA858-Q1 as a function of frequency. To achieve
high slew rates and low output impedance across frequency, the output swing of the OPA858-Q1 is limited to
approximately 3 V. The OPA858-Q1 is typically used in conjunction with high-speed pipeline ADCs and flash
ADCs that have limited input ranges. Therefore, the OPA858-Q1 output swing range coupled with the classleading voltage noise specification for a CMOS amplifier maximizes the overall dynamic range of the signal
chain.
Open-Loop Output Impedance (ohms)
20
18
16
14
12
10
8
6
4
2
0
10k
100k
1M
10M
100M
Frequency (Hz)
1G
10G
D601
Figure 8-7. Open-Loop Output Impedance (ZOL) vs Frequency
8.3.5 Current Noise
The input impedance of CMOS and JFET input amplifiers at low frequencies exceed several GΩs. However, at
higher frequencies, the transistors parasitic capacitance to the drain, source, and substrate reduces the
impedance. The high impedance at low frequencies eliminates any bias current and the associated shot noise.
At higher frequencies, the input current noise increases (see Figure 8-8) as a result of capacitive coupling
between the CMOS gate oxide and the underlying transistor channel. This phenomenon is a natural artifact of
the construction of the transistor and is unavoidable.
100p
Current Noise (A/—Hz)
10p
1p
100f
10f
1f
1k
10k
100k
1M
10M
Frequency (Hz)
100M
1G
D607
Figure 8-8. Input Current Noise (IBN and IBI) vs Frequency
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8.4 Device Functional Modes
8.4.1 Split-Supply and Single-Supply Operation
The OPA858-Q1 can be configured with single-sided supplies or split-supplies as shown in Figure 10-1. Splitsupply operation using balanced supplies with the input common-mode set to ground eases lab testing because
most signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference
inputs and outputs to ground. In split-supply operation, the thermal pad must be connected to the negative
supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply.
The OPA858-Q1 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. In
single-supply operation, level shift the DC input and output reference voltages by half the difference between the
power supply rails. This configuration maintains the input common-mode and output load reference at midsupply.
To eliminate gain errors, the source driving the reference input common-mode voltage must have low output
impedance across the frequency range of interest. In this case, the thermal pad must be connected to ground.
8.4.2 Power-Down Mode
The OPA858-Q1 features a power-down mode to reduce the quiescent current to conserve power. Figure 6-23
and Figure 6-24 show the transient response of the OPA858-Q1 as the PD pin toggles between the disabled and
enabled states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65 V supplies, then
the threshold voltages are at –1 V and 0.15 V. If the amplifier is configured with ±2.5 V supplies, then the
threshold voltages are at –1.85 V and –0.7 V.
25
25
20
20
Quiescent Current (mA)
Quiescent Current (mA)
Figure 8-9 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled
state to the disabled state. Similarly, Figure 8-10 shows the switching behavior of a typical amplifier as the PD
pin is swept up from the disabled state to the enabled state. The small difference in the switching thresholds
between the down sweep and the up sweep is caused by the hysteresis designed into the amplifier to increase
immunity to noise on the PD pin.
15
10
5
15
10
5
TA = -40qC
TA = 25qC
TA = 125qC
0
TA = -40qC
TA = 25qC
TA = 125qC
0
-2
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
2
-2
D200
Figure 8-9. Switching Threshold ( PD Pin Swept
from High to Low)
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
2
D201
Figure 8-10. Switching Threshold ( PD Pin Swept
from Low to High)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the
amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a
parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA858-Q1 uses
internal, back-to-back protection diodes between the inverting and noninverting input pins as Figure 8-3 shows.
In the power-down state, if the differential voltage between the input pins of the amplifier exceeds a diode
voltage drop, an additional low-impedance path is created between the noninverting input pin and the output pin.
20
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Using the OPA858-Q1 as a Transimpedance Amplifier
The OPA858-Q1 design has been optimized to meet the industry's growing demand for wideband, low-noise
photodiode amplifiers. The closed-loop bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance. This includes the photodiode capacitance, input capacitance of the amplifier
(common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP), and,
3. The transimpedance gain RF.
5V
+
100 V
3.4 V
+
OPA858
±
±
GND
GND
RF
CF
Figure 9-1. Transimpedance Amplifier Circuit
Figure 9-1 shows the OPA858-Q1 configured as a TIA with the avalanche photodiode (APD) reverse biased
such that the APD cathode is tied to a large positive bias voltage. In this configuration the APD sources current
into the op amp feedback loop so that the output swings in a negative direction relative to the input commonmode voltage. To maximize the output swing in the negative direction, the OPA858-Q1 common-mode is set
close to the positive limit, 1.6 V from the positive supply rail.
The feedback resistance RF and the input capacitance form a zero in the noise gain that results in instability if
left unchecked. To counteract the effect of the zero, a pole is inserted by adding the feedback capacitor (CF.) into
the noise gain transfer function. The Transimpedance Considerations for High-Speed Amplifiers application
report discusses theories and equations that show how to compensate a transimpedance amplifier for a
particular gain and input capacitance. The bandwidth and compensation equations from the application report
are available in a Microsoft Excel ® calculator. What You Need To Know About Transimpedance Amplifiers – Part
1 provides a link to the calculator.
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350
100
90
300
80
250
70
200
60
150
50
100
40
50
30
0
0
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
20
20
18
350
Closed-loop Bandwidth, f -3dB (MHz)
110
f-3dB , R F = 10 k:
f-3dB , R F = 20 k:
IRN , R F = 10 k:
IRN , R F = 20 k:
400
Integrated Input Referred Noise, I RN (nA RMS )
Closed-loop Bandwidth, f -3dB (MHz)
450
120
f-3dB , C F = 1 pF
f-3dB , C F = 2 pF
IRN , C F = 1 pF
IRN , C F = 2 pF
300
250
80
200
60
150
40
100
20
50
0
100
10
Feedback Resistance (k:)
D209
Figure 9-2. Bandwidth and Noise Performance vs
Photodiode Capacitance
100
Integrated Input Referred Noise, I RN (nA RMS )
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SBOSA58 – FEBRUARY 2021
D210
Figure 9-3. Bandwidth and Noise Performance vs
Feedback Resistance
The equations and calculators in the application report and blog posts referenced above are used to model the
bandwidth (f-3dB) and noise (IRN) performance of the OPA858-Q1 configured as a TIA. The resultant performance
is shown in Figure 9-2 and Figure 9-3. The left side Y-axis shows the closed-loop bandwidth performance, while
the right side of the graph shows the integrated input referred noise. The noise bandwidth to calculate IRN, for a
fixed RF and CPD is set equal to the f–3dB frequency.
Figure 9-2 shows the amplifier performance as a function of photodiode capacitance (CPD) for RF = 10 kΩ and
20 kΩ. Increasing CPD decreases the closed-loop bandwidth. It is vital to reduce any stray parasitic capacitance
from the PCB to maximize bandwidth. The OPA858-Q1 is designed with 0.8 pF of total input capacitance to
minimize the effect on system performance.
Figure 9-3 shows the amplifier performance as a function of RF for CPD = 1 pF and 2 pF. Increasing RF results in
lower bandwidth. To maximize the signal-to-noise ratio (SNR) in an optical front-end system, maximize the gain
in the TIA stage. Increasing RF by a factor of X increases the signal level by X, but only increases the resistor
noise contribution by √ X, thereby improving SNR.
9.2 Typical Application
The high GBWP, low input voltage noise and high slew rate of the OPA858-Q1 makes the device a viable
wideband, high input impedance voltage amplifier.
2.5 V
+
GND
50Source
±
í2.5 V
50
226
62
169
71.5
453
50
50Measurement
System
GND
GND
Supply decoupling not shown
GND
GND
Figure 9-4. OPA858-Q1 in a Gain of –2V/V (No Noise Gain Shaping)
22
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Product Folder Links: OPA858-Q1
OPA858-Q1
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SBOSA58 – FEBRUARY 2021
2.5 V
169
+
GND
50Source
±
í2.5 V
50
226
62
71.5
453
50Measurement
System
GND
GND
2.7 pF
Supply decoupling not shown
0.5 pF
GND
GND
50
GND
Figure 9-5. OPA858-Q1 in a Gain of –2V/V (With Noise Gain Shaping)
9.2.1 Design Requirements
Design a high-bandwidth, high-gain, voltage amplifier with the design requirements listed in Table 9-1. An
inverting amplifier configuration is chosen here; however, the theory is applicable to a noninverting configuration
as well. In an inverting configuration the signal gain and noise gain transfer functions are not equal, unlike the
noninverting configuration.
Table 9-1. Design Requirements
TARGET BANDWIDTH
(MHz)
SIGNAL GAIN (V/V)
FEEDBACK RESISTANCE
(Ω)
FREQUENCY
PEAKING (dB)
> 750
–2
453
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