OPA875IDRG4

Burr Brown Products from Texas Instruments TIV 675 OPA875 SBOS340 – DECEMBER 2006 Single 2:1 High-Speed Video Multiplexer FEATURES • • • • • • • • • • • • • 700MHz SMALL-SIGNAL BANDWIDTH (AV = +2) 425MHz, 4VPP BANDWIDTH 0.1dB GAIN FLATNESS to 200MHz 4ns CHANNEL SWITCHING TIME LOW SWITCHING GLITCH: 40mVPP 3100V/µs SLEW RATE 0.025%/0.025° DIFFERENTIAL GAIN, PHASE HIGH GAIN ACCURACY: 2.0V/V ±0.4% DESCRIPTION The OPA875 offers a very wideband, single-channel 2:1 multiplexer in an SO-8 or a small MSOP-8 package. Using only 11mA, the OPA875 provides a gain of +2 video amplifier channel with > 425MHz large-signal bandwidth (4VPP). Gain accuracy and switching glitch are improved over earlier solutions using a new input stage switching approach. This technique uses current steering as the input switch while maintaining an overall closed-loop design. With > 700MHz small-signal bandwidth at a gain of 2, the OPA875 gives a typical 0.1dB gain flatness to > 200MHz. System power may be reduced using the chip enable feature for the OPA875. Taking the chip enable line high powers down the OPA875 to < 300µA total supply current. Muxing multiple OPA875 outputs together, then using the chip enable to select which channels are active, increases the number of possible inputs. Where three channels are required, consider using the OPA3875 for the same level of performance. Out SEL Channel Select APPLICATIONS RGB SWITCHING LCD PROJECTOR INPUT SELECT WORKSTATION GRAPHICS ADC INPUT MUX DROP-IN UPGRADE TO LT1675-1 EN Ch 0 75W OPA875 (Patented) 75W OPA875 RELATED PRODUCTS DESCRIPTION OPA3875 OPA692 OPA693 Triple-Channel OPA875 225MHz Video Buffer 700MHz Video Buffer Ch 1 75W 2:1 Video Multiplexer Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated OPA875 www.ti.com SBOS340 – DECEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PACKAGELEAD SO-8 MSOP-8 PACKAGE DESIGNATOR D DGK SPECIFIED TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C PACKAGE MARKING OPA875 BPL ORDERING NUMBER OPA875ID OPA875IDR OPA875IDGKT OPA875IDGKR TRANSPORT MEDIA, QUANTITY Rails, 75 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 PRODUCT OPA875 OPA875 ABSOLUTE MAXIMUM RATINGS Over operating temperature range, unless otherwise noted. OPA875 Power Supply Internal Power Dissipation Input Voltage Range Storage Temperature Range Lead Temperature (soldering, 10s) Operating Junction Temperature Continuous Operating Junction Temperature ESD Rating: Human Body Model (HBM) Charge Device Model (CDM) Machine Model 2000 1500 200 V V V ±VS –40 to +125 +260 +150 +140 ±6.5 See Thermal Analysis V °C °C °C °C UNIT V Table 1. TRUTH TABLE OPA875 SELECT 1 0 X ENABLE 0 0 1 VOUT R0 R1 Off Channel 0 (V0) GND Channel 1 (V1) -VS 1 2 3 4 Top View PIN CONFIGURATION MSOP SO , OPA875 8 7 6 402W 402W 5 +VS Chip Enable (EN) Output (VOUT) Channel Select (SEL) 2 Submit Documentation Feedback OPA875 www.ti.com SBOS340 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS: VS = ±5V At G = +2, RL = 150Ω, unless otherwise noted. OPA875 TYP PARAMETER AC PERFORMANCE Small-Signal Bandwidth Large-Signal Bandwidth Bandwidth for 0.1dB Gain Flatness Maximum Small-Signal Gain Minimum Small-Signal Gain SFDR Input Voltage Noise Input Current Noise NTSC Differential Gain NTSC Differential Phase Slew Rate Rise Time and Fall Time CONDITIONS See Figure 1 VO = 200mVPP, RL = 150Ω VO = 4VPP, RL = 150Ω VO = 200mVPP VO = 200mVPP, RL = 150Ω, f = 5MHz VO = 200mVPP, RL = 150Ω, f = 5MHz 10MHz, VO = 2VPP, RL = 150Ω f > 100kHz f > 100kHz RL = 150Ω RL = 150Ω VO = ±2V VO = 0.5V Step VO = 1.4V Step CHANNEL-TO-CHANNEL PERFORMANCE Gain Match Output Offset Voltage Mismatch Crosstalk CHANNEL AND CHIP-SELECT PERFORMANCE SEL (Channel Select) Switching Time EN (Chip Select) Switching Time RL = 150Ω Turn On Turn Off SEL (Channel Select) Switching Glitch EN (Chip-Select) Switching Glitch Off Isolation Maximum Logic 0 Minimum Logic 1 EN Logic Input Current SEL Logic Input Current DC PERFORMANCE Output Offset Voltage Average Output Offset Voltage Drift Input Bias Current Average Input Bias Current Drift Gain Error (from 2V/V) INPUT Input Voltage Range Input Resistance Input Capacitance Channel Selected Channel Deselected Chip Disabled ±2.8 1.75 0.9 0.9 0.9 V MΩ pF pF pF min typ typ typ typ C C C C C VO = ±2V 0.4 1.4 ±5 ±18 RIN = 0Ω, G = +2V/V ±2.5 ±14 ±15.8 ±50 ±19.5 ±40 1.5 ±17 ±50 ±20.5 ±40 1.6 mV µV/°C µA nA/°C % max max max max max A B A B A Both Inputs to Ground, At Matched Load Both Inputs to Ground, At Matched Load 50MHz, Chip Disabled (EN = High) EN, A0, A1 EN, A0, A1 0V to 4.5V 0V to 4.5V 25 55 4 9 60 40 30 –70 0.8 2.0 35 70 0.8 2.0 45 85 0.8 2.0 50 100 ns ns ns mVPP mVPP dB V V µA µA typ typ typ typ typ typ max min max max C C C C C C A A A A f < 50MHz, RL = 150Ω RL = 150Ω ±0.05 ±3 –65 ±0.25 ±9 ±0.3 ±10 ±0.35 ±12 % mV dB max max typ A A C 700 425 200 2.0 2.0 –66 6.7 3.8 0.025 0.025 3100 460 600 2800 2700 2600 2.02 1.98 –64 7.0 4.2 2.03 1.97 –63 7.2 4.6 2.05 1.95 –62 7.4 4.9 525 390 515 380 505 370 MHz MHz MHz V/V V/V dBc nV/√Hz pA/√Hz % ° V/µs ps ps min min typ max min max max max typ typ min typ typ B B C B B B B B C C B C C +25°C +25°C (2) MIN/MAX OVER TEMPERATURE 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) (1) (2) (3) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +14°C at high temperature limit for over temperature specifications. Submit Documentation Feedback 3 OPA875 www.ti.com SBOS340 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2, RL = 150Ω, unless otherwise noted. OPA875 TYP PARAMETER OUTPUT Output Voltage Range Output Current Output Resistance VO = 0V, Linear Operation Chip enabled Chip Disabled, Maximum Chip Disabled, Minimum Output Capacitance POWER SUPPLY Specified Operating Voltage Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Maximum Quiescent Current Power-Supply Rejection Ratio (+PSRR) (–PSRR) THERMAL CHARACTERISTICS Specified Operating Range D Package Thermal Resistance θJA D DGK SO-8 MSOP-8 Junction-to-Ambient +100 +140 °C/W °C/W typ typ C C –40 to +85 °C typ C Chip Selected, VS = ±5V Chip Selected, VS = ±5V Chip Deselected Input-Referred Input-Referred 11 11 300 56 55 ±5 ±3.0 ±6.0 11.5 10 500 50 51 ±3.0 ±6.0 11.7 9.5 550 48 49 ±3.0 ±6.0 12 9 600 47 48 V V V mA mA µA dB dB typ min max max min max min min C B A A A A A A Chip Disabled ±3.5 ±70 0.3 800 800 2 912 688 915 685 918 682 ±3.4 ±50 ±3.35 ±45 ±3.3 ±40 V mA Ω Ω Ω pF min min typ max min typ A A C A A C CONDITIONS +25°C +25°C (2) MIN/MAX OVER TEMPERATURE 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) 4 Submit Documentation Feedback OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V At G = +2 and RL = 150Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 7 6 5 0.3 1 LARGE-SIGNAL FREQUENCY RESPONSE Normalized Gain Flatness (dB) 0.2 0.1 0 -0.1 -0.2 VO = 500mVPP RL = 150W G = +2V/V 1M 10M 100M Frequency (Hz) 1G -0.3 -0.4 0 Normalized Gain (dB) -1 -2 -3 -4 2VPP -5 -6 0 200M 400M 600M 800M 1G Frequency (Hz) 5VPP Gain (dB) 4 3 2 1 0 4VPP 500mVPP 1VPP Figure 1. NONINVERTING PULSE RESPONSE 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 Time (1ns/div) 100MHz Square-Wave Input Small-Signal 0.4VPP RL = 150W G = +2V/V 2.5 Large-Signal 4VPP Figure 2. DISABLE FEEDTHROUGH vs FREQUENCY 0 Large-Signal Offset Voltage (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Small-Signal Offset Voltage (V) -10 -20 Input-Referred BW = +5V Isolation (dB) -30 -40 -50 -60 -70 -80 -90 -100 1M 10M 100M Frequency (Hz) 1G Figure 3. RECOMMENDED RS vs CAPACITIVE LOAD 80 8 7 0.1dB Peaking Targeted 70 60 50 Figure 4. FREQUENCY RESPONSE vs CAPACITIVE LOAD Gain to Capacitive Load (dB) 6 5 4 3 2 1 0 -1 -2 -3 75W NOTE: (1) 1kW is optional. 75W x2 CL = 10pF RS (W) 40 30 20 10 0 1 10 100 1000 Capacitive Load (pF) CL = 47pF RS CL 1kW (1) CL = 100pF CL = 22pF 1M 10M Frequency (Hz) 100M 400M Figure 5. Figure 6. Submit Documentation Feedback 5 OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE -60 -65 2nd-Harmonic -70 -75 -80 3rd-Harmonic -85 dBc = dB Below Carrier -90 100 Resistance (W) 1k VO = 2VPP f = 10MHz -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 dBc = dB Below Carrier -95 ±2.5 ±3.0 ±3.5 ±4.0 3rd-Harmonic 2nd-Harmonic HARMONIC DISTORTION vs SUPPLY VOLTAGE VO = 2VPP RL = 150W f = 10MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) ±4.5 ±5.0 ±5.5 ±6.0 Supply Voltage (±VS) Figure 7. HARMONIC DISTORTION vs FREQUENCY -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 1M 10M Frequency (Hz) 3rd-Harmonic dBc = dB Below Carrier 100M VO = 2VPP RL = 150W -55 -60 Figure 8. HARMONIC DISTORTION vs OUTPUT VOLTAGE RL = 150W f = 10MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) -65 -70 -75 -80 -85 -90 -95 -100 -105 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.0 Output Voltage Swing (VPP) dBc = dB Below Carrier 3rd-Harmonic 2nd-Harmonic 2nd-Harmonic Figure 9. TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -50 5 RL = 100W Load Power at Matched 50W Load dBc = dB Below Carrier 4 3 2 1W Internal Power Limit Figure 10. OUTPUT VOLTAGE AND CURRENT LIMITATIONS Third-Order Spurious Level (dBc) -60 VOUT (V) -70 50MHz -80 20MHz -90 10MHz 1 0 -1 -2 -3 -4 100W Load Line 25W Load Line 50W Load Line 1W Internal Power Limit -100 -6 -4 -2 0 2 4 6 8 10 Single-Tone Load Power (dBm) -5 -200 -150 -100 -50 0 IO (mA) 50 100 150 200 Figure 11. Figure 12. 6 Submit Documentation Feedback OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. CHANNEL SWITCHING 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 CHANNEL-TO-CHANNEL SWITCHING TIME Output Voltage (V) Output Voltage (V) Output Voltage Output Voltage 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 VSEL RL = 150W VIN_RI = 400MHz, 1VPP VIN_RO = 0VDC Time (5ns/div) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 Channel Select (V) VSEL VIN_Ch0 = +0.5VDC VIN_Ch1 = -0.5VDC Time (5ns/div) Figure 13. CHANNEL SWITCHING GLITCH Output (mV) 20 10 0 -10 -20 7.5 VSEL 5.0 2.5 0 -2.5 Time (10ns/div) At Matched Load Figure 14. DISABLE/ENABLE TIME 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 Output Voltage (V) 30 Output Voltage Channel Select (V) VEN VIN_Ch1 = 0V VIN_Ch0 = 200MHz, 1VPP Time (20ns/div) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 Figure 15. DISABLE/ENABLE SWITCHING GLITCH 15 10 At Matched Load Figure 16. CHANNEL-TO-CHANNEL CROSSTALK 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 1M 10M 100M Frequency (Hz) 1G Ch 1 Selected Ch 0 Driven Ch 0 Selected Ch 1 Driven Input-Referred Output (mV) 5 0 -10 -15 VEN 5.0 2.5 0 -2.5 Time (100ns/div) Figure 17. Enable Voltage (V) Output (V) -5 Figure 18. Submit Documentation Feedback Enable Voltage (V) Channel Select (V) 7 OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10k Disabled 10M INPUT IMPEDANCE vs FREQUENCY Output Impedance (W) 1k 1M 100 Input Impedance (W) Enabled 1M 10M Frequency (Hz) 100M 1G 100k 10 10k 1 1k 0.1 100k 100 100k 1M 10M Frequency (Hz) 100M 1G Figure 19. PSRR vs FREQUENCY 60 18 -PSRR 50 40 30 20 10 0 100 16 Figure 20. SUPPLY CURRENT vs TEMPERATURE Power-Supply Rejection Ratio (dB) Supply Current (mA) 1M 10M 100M 1G +PSRR 14 12 10 8 6 4 2 1k 10k 100k -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) Figure 21. TYPICAL DC DRIFT OVER TEMPERATURE 3.0 8 VOS 2.5 IB 2.0 4 6 100 Figure 22. INPUT VOLTAGE AND CURRENT NOISE Output Offset Voltage (mV) Input Bias Current (mA) Voltage Noise (nV/ÖHz) Current noise (pA/ÖHz) 10 Voltage Noise (6.7nV/ÖHz) 1.5 2 Input Current Noise (3.8pA/ÖHz) 1.0 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) 0 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 23. Figure 24. 8 Submit Documentation Feedback OPA875 www.ti.com SBOS340 – DECEMBER 2006 APPLICATIONS INFORMATION 1-BIT HIGH-SPEED PGA The OPA875 can be used as a 1-bit, high-speed programmable gain amplifier (PGA) when used in conjunction with another amplifier. Figure 25 shows the OPA695 used twice with one amplifier configured in a unity-gain structure, and the other amplifier configured in a gain of +8V/V. When channel 0 is selected, the overall gain to the matched load of the OPA875 is 0dB. When channel 1 is selected, this circuit delivers an 18dB gain to the matched load. TRANSMIT/RECEIVE SWITCH The OPA875 can be used as a transmit/receive switch in which the receive channel is disconnected, when the OPA875 is switched from channel 0 to channel 1, to prevent the transmit pulse from going through the receive signal chain. This architecture is shown in Figure 26. HIGH ISOLATION RGB VIDEO MUX Three OPA875s can be used as a triple, 2:1 video MUX (see Figure 27). This configuration has the advantage of having higher R to G to B isolation than a comparable and more integrated solution does, such as the OPA3875, especially at higher frequencies. This comparison is shown in Figure 28. +5V +5V OPA695 50W IN 50W Source 50W +5V 50W -5V 523W OPA875 Channel 0 x1 50W x2 Channel 1 x1 50W Load OPA695 -5V -5V 402W 57.6W Figure 25. 1-Bit, High-Speed PGA OPA875 Receive Channel Channel 0 x1 x2 Channel 1 x1 Figure 26. Transmit/Receive Switch Submit Documentation Feedback 9 OPA875 www.ti.com SBOS340 – DECEMBER 2006 4-INPUT RGB ROUTER OPA875_A Ch 0 x1 x2 Ch 1 x1 R1 x1 x2 R2 x1 EN ROUT Two OPA875s can be used together to form a four-input RGB router. The router for the red component is shown in Figure 29. OPA875 RO 69W OPA875_B Ch 0 x1 x2 Ch 1 x1 GOUT R3 x1 x2 OPA875_C Ch 0 x1 R4 x1 RO 69W 75W EN Red Out x2 Ch 1 x1 BOUT Chip Select Figure 29. 4-Input RGB Router Figure 27. High Isolation RGB Video MUX 0 Input-Referred -10 -20 OPA3875 OPA3875 All Hostile Adjacent Channel Crosstalk Crosstalk When connecting OPA875 outputs together, maintain a gain of +1 at the load. The OPA875 operates at a gain of +6dB; thus, matching resistance must be selected to achieve –6dB attenuation. The set of equations to solve are shown in Equation 1 and Equation 2. Here, the impedance of interest is ZO = 75Ω. RO = ZO || (R + RF + RG) 1+ RF RG =2 Crosstalk (dB) -30 -40 -50 -60 -70 -80 -90 1 OPA875_C Ch. 0 Driven Adjacent Channel Crosstalk OPA875 OPA875_A All Hostile Ch. 1 Driven, Adjacent Crosstalk Channel Crosstalk 10 100 1G (1) RF + RG = 804W RF = RG (2) Frequency (MHz) Solving for RO with n devices connected together, we get Equation 3: RO = 75 ´ (n - 1) + 804 2 ´ 1+ 241200 [75 ´ (n - 1) + 804] 2 Figure 28. All-Hostile and Adjacent Channel Crosstalk The configuration of the three OPA875 devices used is shown in Figure 27. Note that for the test, the OPA875_B was measured when both the OPA875_A and OPA875_C were driven for all hostile crosstalk and only the OPA875_A or OPA875_C was driven for the adjacent channel crosstalk. -1 (3) 10 Submit Documentation Feedback OPA875 www.ti.com SBOS340 – DECEMBER 2006 Results for n varying from 2 to 6 are given in Table 2. Table 2. Series Resistance versus Number of Parallel Outputs NUMBER OF OPA875s 2 3 4 5 6 RO (Ω) 69 63.94 59.49 55.59 52.15 OPERATING SUGGESTIONS DRIVING CAPACITIVE LOADS One of the most demanding, yet very common load conditions is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed device such as the OPA875 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the device open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This isolation resistor does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS versus capacitive load and the resulting frequency response at the load; see Figure 5. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA875. Long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA875 output pin (see the Board Layout Guidelines section). The two major limitations of this circuit are the device requirements for each OPA875 and the acceptable return loss because of the mismatch between the load (75Ω) and the matching resistor. DESIGN-IN TOOLS DEMONSTRATION FIXTURES A printed circuit board (PCB) is available to assist in the initial evaluation of circuit performance using the OPA875. The fixture is offered free of charge as an unpopulated PCB, delivered with a user's guide. The summary information for this fixture is shown in Table 3. Table 3. OPA875 Demonstration Fixture PRODUCT OPA875IDGK OPA875ID PACKAGE MSOP-8 SO-8 ORDERING NUMBER DEM-TIV-MSOP-1A DEM-TIV-SO-1A LITERATURE NUMBER SBOU044 SBOU045 The demonstration fixture can be requested at the Texas Instruments web site at (www.ti.com) through the OPA875 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA875 is available through the Texas Instruments web site at www.ti.com. These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. DC ACCURACY The OPA875 offers excellent DC signal accuracy. Parameters that influence the output DC offset voltage are: • Output offset voltage • Input bias current • Gain error • Power-supply rejection ratio • Temperature Submit Documentation Feedback 11 OPA875 www.ti.com SBOS340 – DECEMBER 2006 Leaving both temperature and gain error parameters aside, the output offset voltage envelope can be described as shown in Equation 4: VOSO_envelope = VOSO + (RS·Ib) x G ± |5 - (VS+)| x 10 ± |-5 - (VS-)| x 10 - PSRR20 - PSRR+ 20 (4) With: VOSO: Output offset voltage RS: Input resistance seen by R0, R1, G0, G1, B0, or B1. Ib: Input bias current G: Gain VS+: Positive supply voltage VS–: Negative supply voltage PSRR+: Positive supply PSRR PSRR–: Negative supply PSRR Evaluating the front-page schematic, using a worst-case, +25°C offset voltage, bias current and PSRR specifications and operating at ±6V, gives a worst-case output equal to Equation 5: ±14mV + 75W x ±18mA x 2 ± |5 - 6| x 10 ± |-5 - (-6)| x 10 = ±22.7mV - 51 20 - 50 20 are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 4dBm/tone into a matched 50Ω load (that is, 1VPP for each tone at the load, which requires 4VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show a 82dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. NOISE PERFORMANCE The OPA875 offers an excellent balance between voltage and current noise terms to achieve low output noise. As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The device input voltage noise and the input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 30 shows this device noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. +5V (5) DISTORTION PERFORMANCE The OPA875 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2X rate while the 3rd-harmonic increases at a little less than the expected 3X rate. Where the test power doubles, the 2nd-harmonic increases only by less than the expected 6dB, whereas the 3rd-harmonic increases by less than the expected 12dB. This also shows up in the two-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels 12 en +1 RS ib +1 +2 eO OPA875 e RS -5V Channel Select EN Figure 30. Noise Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 6 shows the general form for the output noise voltage using the terms shown in Figure 30. eo = 2 en + (ibRS) + 4kTRS 2 2 (6) Submit Documentation Feedback OPA875 www.ti.com SBOS340 – DECEMBER 2006 Dividing this expression by the device gain (2V/V) gives the equivalent input-referred spot noise voltage at the noninverting input as shown in Equation 7. en = en + (ibRS) + 4kTRS 2 2 BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier such as the OPA875 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pin can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 9, 11, 13, and 15) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA875. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and printed circuit board (PCB) trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Other network components, such as noninverting input termination resistors, should also be placed close to the package. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. (7) Evaluating these two equations for the OPA875 circuit and component values shown in Figure 30 gives a total output spot noise voltage of 13.6nV/√Hz and a total equivalent input spot noise voltage of 6.8nV/√Hz. This total input-referred spot noise voltage is higher than the 6.7nV/√Hz specification for the mux voltage noise alone. This number reflects the noise added to the output by the bias current noise times the source resistor. THERMAL ANALYSIS Heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as discussed in this document. In no case should the maximum junction temperature be allowed to exceed +150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 × RL), where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA875IDGK in the circuit of Figure 30 operating at the maximum specified ambient temperature of +85°C with its outputs driving a grounded 100Ω load to +2.5V: PD = 10V x 11mA + (5 [4 x (100W || 804W) ] ) = 180mW Maximum TJ = +85°C + (0.18mW x 140°C/W) = 110°C 2 This worst-case condition does not exceed the maximum junction temperature. Normally, this extreme case is not encountered. Careful attention to internal power dissipation is required. Submit Documentation Feedback 13 OPA875 www.ti.com SBOS340 – DECEMBER 2006 Estimate the total capacitive load and set RS from the plot of Figure 5. Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA875 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the Distortion versus Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA875 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA875 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in Figure 5. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA875 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA875 onto the board. INPUT AND ESD PROTECTION The OPA875 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 31. +VCC External Pin Internal Circuitry -VCC Figure 31. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA875), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible because high values degrade both noise performance and frequency response. 14 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device OPA875ID OPA875IDG4 OPA875IDGKR OPA875IDGKRG4 OPA875IDGKT OPA875IDGKTG4 OPA875IDR OPA875IDRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC MSOP MSOP MSOP MSOP SOIC SOIC Package Drawing D D DGK DGK DGK DGK D D Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Device Package Pins Site Reel Diameter (mm) 330 Reel Width (mm) 12 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8 W Pin1 (mm) Quadrant 12 PKGORN T1TR-MS P PKGORN T1TR-MS P PKGORN T1TR-MS P OPA875IDGKR DGK 8 MLA 5.3 3.4 1.4 OPA875IDGKT DGK 8 MLA 180 12 5.3 3.4 1.4 8 12 OPA875IDR D 8 MLA 330 12 6.4 5.2 2.1 8 12 TAPE AND REEL BOX INFORMATION Device OPA875IDGKR OPA875IDGKT OPA875IDR Package DGK DGK D Pins 8 8 8 Site MLA MLA MLA Length (mm) 342.9 190.0 342.9 Width (mm) 336.6 212.7 336.6 Height (mm) 31.75 31.75 28.58 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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