OPA990IDCKR

厂商：
BURR-BROWN(德州仪器)
封装：
TSSOP5,SC70-5,SOT353
描述：
通用放大器 1 电路满摆幅 SC-70-5

数据手册：

下载OPA990IDCKR.pdf

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数据手册
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OPA990IDCKR 数据手册

OPA990, OPA2990, OPA4990 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp 1 Features 3 Description • • • • • • • The OPAx990 family (OPA990, OPA2990, and OPA4990) is a family of high voltage (40 V) general purpose operational amplifiers. These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset (±300 µV, typ), and low offset drift (±0.6 µV/°C, typ). • • • • • • Low offset voltage: ±300 µV Low offset voltage drift: ±0.6 µV/°C Low noise: 30 nV/√Hz at 1 kHz High common-mode rejection: 115 dB Low bias current: ±10 pA Rail-to-rail input and output MUX-friendly/comparator inputs – Amplifier operates with differential inputs up to supply rail – Amplifier can be used in open-loop or as comparator Wide bandwidth: 1.1-MHz GBW High slew rate: 4.5 V/µs Low quiescent current: 120 µA per amplifier Wide supply: ±1.35 V to ±20 V, 2.7 V to 40 V Robust EMIRR performance: 78 dB at 1.8 GHz Differential and common-mode input voltage range to supply rail Unique features such as differential and commonmode input voltage range to the supply rail, high short-circuit current (±80 mA), high slew rate (4.5 V/ µs), and shutdown make the OPAx990 an extremely flexible, robust, and high-performance op amp for high-voltage industrial applications. The OPAx990 family of op amps is available in micro-size packages (such as X2QFN, WSON, and SOT-553), as well as standard packages (such as SOT-23, SOIC, and TSSOP), and is specified from –40°C to 125°C. Device Information 2 Applications • • • • • Multiplexed data-acquisition systems Test and measurement equipment Motor drive: power stage and control modules Power delivery: UPS, server, and merchant network power ADC driver and reference buffer amplifier Programmable logic controllers Analog input and output modules High-side and low-side current sensing High precision comparator OPA990 OPA2990 OPA4990 (1) PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm SOT-23 (6) 2.90 mm × 1.60 mm SC70 (5) 2.00 mm × 1.25 mm SOT-553 (5)(2) 1.60 mm × 1.20 mm SOIC (8) 4.90 mm × 3.90 mm SOT-23 (8) 2.90 mm × 1.60 mm TSSOP (8) 3.00 mm × 4.40 mm VSSOP (8) 3.00 mm × 3.00 mm VSSOP (10) 3.00 mm × 3.00 mm WSON (8) 2.00 mm × 2.00 mm X2QFN (10) 2.00 mm × 1.50 mm SOIC (14) 8.65 mm × 3.90 mm TSSOP (14) 5.00 mm × 4.40 mm WQFN (16) 3.00 mm × 3.00 mm X2QFN (14) 2.00 mm × 2.00 mm For all available packages, see the orderable addendum at the end of the data sheet. This package is preview only. (2) Analog Inputs REF3140 Bridge Sensor OPA990 Gain Network Gain Network RC Filter OPA375 RC Filter Reference Driver + MUX509 Thermocouple + OPA990 Current Sensing LED Photo Detector Optical Sensor High-Voltage Multiplexed Input REF OPA990 + Gain Network Gain Network • • • • PART NUMBER(1) High-Voltage Level Translation VINP Antialiasing Filter ADS8860 VINM VCM OPAx990 in a High-Voltage, Multiplexed, Data-Acquisition System An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................4 6 Specifications................................................................ 10 6.1 Absolute Maximum Ratings ..................................... 10 6.2 ESD Ratings ............................................................ 10 6.3 Recommended Operating Conditions ......................10 6.4 Thermal Information for Single Channel .................. 11 6.5 Thermal Information for Dual Channel ..................... 11 6.6 Thermal Information for Quad Channel ................... 12 6.7 Electrical Characteristics ..........................................13 6.8 Typical Characteristics.............................................. 16 7 Detailed Description......................................................24 7.1 Overview................................................................... 24 7.2 Functional Block Diagram......................................... 24 7.3 Feature Description...................................................25 7.4 Device Functional Modes..........................................33 8 Application and Implementation.................................. 34 8.1 Application Information............................................. 34 8.2 Typical Applications.................................................. 34 9 Power Supply Recommendations................................36 10 Layout...........................................................................36 10.1 Layout Guidelines................................................... 36 10.2 Layout Example...................................................... 36 11 Device and Documentation Support..........................39 11.1 Device Support........................................................39 11.2 Documentation Support.......................................... 39 11.3 Receiving Notification of Documentation Updates.. 39 11.4 Support Resources................................................. 39 11.5 Trademarks............................................................. 39 11.6 Electrostatic Discharge Caution.............................. 39 11.7 Glossary.................................................................. 39 12 Mechanical, Packaging, and Orderable Information.................................................................... 40 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (May 2021) to Revision I (August 2021) Page • Removed preview notation from OPA2990 VSSOP-8 package (DGK) from Device Information table.............. 1 • Removed preview notation from OPA2990 VSSOP-8 package (DGK) in the Pin Configuration and Functions section................................................................................................................................................................ 4 • Added note explaining difference between DDF and TDDF packages in the Pin Configuration and Functions section................................................................................................................................................................ 4 • Corrected typo describing shutdown region in Recommended Operating Conditions to match rest of data sheet................................................................................................................................................................. 10 • Changed Junction-to-ambient thermal resistance value for SOT-23-6 (DBV-6) from 1174.5ºC/W to 174.5ºC/W in the Thermal Information for Single Channel section..................................................................................... 11 • Added clarifying statement regarding logic low signal for SHDN pin in the Shutdown section.........................32 • Corrected statement on shutdown enable and disable times in the Shutdown section from 30 µs and 3 µs to 11 µs and 2.5 µs, respectively, to match the Electrical Characteristics section................................................ 32 Changes from Revision G (December 2020) to Revision H (May 2021) Page • Removed preview notation from OPA4990 WQFN (16) package from Device Information table.......................1 • Removed preview notation from OPA4990 X2QFN (14) package from Device Information table......................1 • Removed preview notation from OPA4990 and OPA4990S RTE package (WQFN) in the Pin Configuration and Functions section.........................................................................................................................................4 • Removed Table of Graphs from Specifications section.................................................................................... 10 • Clarified threshold and maximum voltage levels of the shutdown pin in the Shutdown section....................... 32 • Removed Related Links from Device and Documentation section...................................................................39 Changes from Revision F (May 2020) to Revision G (December 2020) Page • Updated the numbering format for tables, figures and cross-references throughout the document ..................1 • Removed preview notation from OPA2990 SOT-23 (8) package from Device Information table....................... 1 • Added OPA2990 VSSOP (10) package to Device Information table..................................................................1 • Clarified SHDN notation on OPA990S Pin Functions ........................................................................................ 4 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 www.ti.com • • • • OPA990, OPA2990, OPA4990 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 Removed preview notation from OPA2990 DDF package (SOT-23) in the Pin Configuration and Functions section................................................................................................................................................................ 4 Removed preview notation from OPA2990S DGS package (VSSOP) in the Pin Configuration and Functions section ............................................................................................................................................................... 4 Clarified SHDN notation for OPA2990S in the Pin Functions section ................................................................4 Clarified SHDN notation for OPA4990S in the Pin Functions section ................................................................4 Changes from Revision E (December 2019) to Revision F (May 2020) Page • Removed preview notation from OPA2990 X2QFN (10) package from Device Information table .....................1 • Removed preview notation from OPA2990S RUG package (X2QFN) in the Pin Configuration and Functions section ............................................................................................................................................................... 4 • Changed RUG (X2QFN) in Thermal Information for Dual Channel section....................................................... 4 Changes from Revision D (July 2019) to Revision E (December 2019) Page • Changed the OPA990 and OPA4990 device statuses from Advance Information to Production Data ..............1 • Removed preview notation from OPA990 SOT-23 (5) package from Device Information table......................... 1 • Removed preview notation from OPA990S SOT-23 (6) package from Device Information table....................... 1 • Removed preview notation from OPA990 SC70 (5) package from Device Information table.............................1 • Removed preview notation from OPA4990 SOIC (14) package from Device Information table......................... 1 • Removed preview notation from OPA4990 TSSOP (14) package from Device Information table..................... 1 • Removed preview notation from OPA990 DBV package (SOT-23) in the Pin Configuration and Functions section................................................................................................................................................................ 4 • Removed preview notation from OPA990 DCK package (SC70) in the Pin Configuration and Functions section................................................................................................................................................................ 4 • Removed preview notation from OPA4990 D (SOIC) and TSSOP (PW) packages in the Pin Configuration and Functions section................................................................................................................................................4 • Removed preview notation from OPA990S DBV package (SOT-23) in the Pin Configuration and Functions section................................................................................................................................................................ 4 Changes from Revision C (May 2019) to Revision D (July 2019) Page • Removed preview notation from OPA2990 WSON (8) package from Device Information table........................ 1 • Removed preview notation from OPA2990 DSG package (WSON) in the Pin Configuration and Functions section................................................................................................................................................................ 4 • Added SHUTDOWN to Electrical Characteristics table.................................................................................... 13 • Added Shutdown section to the Detailed Description section.......................................................................... 32 Changes from Revision B (April 2019) to Revision C (May 2019) Page • Removed preview notation from OPA2990 TSSOP (8) package from Device Information table....................... 1 • Removed preview notation from OPA2990 PW package (TSSOP) in the Pin Configuration and Functions section................................................................................................................................................................ 4 Changes from Revision A (March 2019) to Revision B (April 2019) Page • Removed preview notation from OPA2990 SOIC (8) package from Device Information table........................... 1 • Removed preview notation from OPA2990 D package (SOIC) in the Pin Configuration and Functions section.. 4 Changes from Revision * (February 2019) to Revision A (March 2019) Page • Changed the OPA2990 device status from Advance Information to Production Data .......................................1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 3 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 5 Pin Configuration and Functions OUT 1 V± 2 IN+ 3 5 V+ 4 IN± IN+ 1 V± 2 IN± 3 Not to scale A. 5 V+ 4 OUT Not to scale Figure 5-2. OPA990 DCK Package 5-Pin SC70 Top View DRL package is preview only. Figure 5-1. OPA990 DBV and DRL Package(A) 5-Pin SOT-23 and SOT-553 Top View Table 5-1. Pin Functions: OPA990 PIN NAME I/O DESCRIPTION DBV and DRL DCK IN+ 3 1 I Noninverting input IN– 4 3 I Inverting input OUT 1 4 O Output V+ 5 5 — Positive (highest) power supply V– 2 2 — Negative (lowest) power supply OUT 1 6 V+ V– 2 5 SHDN +IN 3 4 –IN Not to scale A. DRL package is preview only. Figure 5-3. OPA990S DBV and DRL Package(A) 6-Pin SOT-23 and SOT-563 Top View Table 5-2. Pin Functions: OPA990S PIN NAME 4 NO. IN+ 3 IN– OUT I/O DESCRIPTION I Noninverting input 4 I Inverting input 1 O Output SHDN 5 I Shutdown: low = amplifier enabled, high = amplifier disabled. See Shutdown section for more information. V+ 6 — Positive (highest) power supply V– 2 — Negative (lowest) power supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 OUT1 1 8 V+ IN1± 2 7 OUT2 IN1+ 3 6 IN2± V± 4 5 IN2+ OUT1 1 IN1± 2 IN1+ 3 V± 4 Thermal Pad 8 V+ 7 OUT2 6 IN2± 5 IN2+ Not to scale A. DDF and TDDF differ in pin 1 orientation within tape and reel. See Mechanical, Packaging, and Orderable Information section A. for more information. Figure 5-4. OPA2990 D, DDF, DGK, PW, and TDDF Package(A) 8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP Top View Not to scale Connect thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information. Figure 5-5. OPA2990 DSG Package(A) 8-Pin WSON With Exposed Thermal Pad Top View Table 5-3. Pin Functions: OPA2990 PIN NAME NO. I/O DESCRIPTION IN1+ 3 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2+ 5 I Noninverting input, channel 2 IN2– 6 I Inverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 5 OPA990, OPA2990, OPA4990 www.ti.com IN1+ SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 1 10 V+ IN1– 2 9 OUT2 IN1+ 3 8 IN2– V– 4 7 IN2+ SHDN1 5 6 SHDN2 V– 1 9 IN1– SHDN1 2 8 OUT1 SHDN2 3 7 V+ IN2+ 4 6 OUT2 5 10 OUT1 Not to scale Figure 5-6. OPA2990S DGS Package 10-Pin VSSOP Top View IN2– Not to scale Figure 5-7. OPA2990S RUG Package 10-Pin X2QFN Top View Table 5-4. Pin Functions: OPA2990S PIN NAME 6 VSSOP X2QFN I/O DESCRIPTION IN1+ 3 10 I Noninverting input, channel 1 IN1– 2 9 I Inverting input, channel 1 IN2+ 7 4 I Noninverting input, channel 2 IN2– 8 5 I Inverting input, channel 2 OUT1 1 8 O Output, channel 1 OUT2 9 6 O Output, channel 2 SHDN1 5 2 I Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Shutdown section for more information. SHDN2 6 3 I Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Shutdown section for more information. V+ 10 7 — Positive (highest) power supply V– 4 1 — Negative (lowest) power supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com IN4± IN1+ 3 12 IN4+ V+ 4 11 V± IN2+ 5 10 IN3+ IN1+ 1 V+ 2 IN4± 13 13 2 OUT4 IN1± 14 OUT4 OUT1 14 15 1 IN1± OUT1 16 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 12 IN4+ 11 V± 10 IN3+ 9 IN3± Thermal 8 OUT3 IN2± 4 8 7 OUT3 OUT2 Pad 7 3 NC IN2+ 6 IN3± NC 9 5 6 OUT2 IN2± Not to scale Figure 5-8. OPA4990 D and PW Package 14-Pin SOIC and TSSOP Top View A. Not to scale Connect thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information. IN4± 2 11 IN4+ V+ 3 10 V± IN2+ 4 9 IN3+ IN2± 5 8 IN3± OUT3 OUT2 7 IN1+ 13 12 14 1 6 IN1± OUT4 OUT1 Figure 5-9. OPA4990 RTE Package(A) 16-Pin WQFN With Exposed Thermal Pad Top View Not to scale Figure 5-10. OPA4990 RUC Package 14-Pin X2QFN With Exposed Thermal Pad Top View Table 5-5. Pin Functions: OPA4990 PIN NAME SOIC and TSSOP WQFN X2QFN I/O DESCRIPTION IN1+ 3 1 2 I Noninverting input, channel 1 IN1– 2 16 1 I Inverting input, channel 1 IN2+ 5 3 4 I Noninverting input, channel 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 7 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 Table 5-5. Pin Functions: OPA4990 (continued) PIN 8 I/O DESCRIPTION SOIC and TSSOP WQFN X2QFN IN2– 6 4 5 I Inverting input, channel 2 IN3+ 10 10 9 I Noninverting input, channel 3 IN3– 9 9 8 I Inverting input, channel 3 IN4+ 12 12 11 I Noninverting input, channel 4 IN4– 13 13 12 I Inverting input, channel 4 NC — 6, 7 — — Do not connect OUT1 1 15 14 O Output, channel 1 OUT2 7 5 6 O Output, channel 2 OUT3 8 8 7 O Output, channel 3 OUT4 14 14 13 O Output, channel 4 V+ 4 2 3 — Positive (highest) power supply V– 11 11 10 — Negative (lowest) power supply NAME Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com IN1+ 1 V+ 2 IN1– OUT1 OUT4 IN4– 16 15 14 13 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 12 IN4+ 11 V– 10 IN3+ 9 IN3– Thermal A. 6 7 8 SHDN34 OUT3 4 SHDN12 IN2– Pad 5 3 OUT2 IN2+ Not to scale Connect thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information. Figure 5-11. OPA4990S RTE Package(A) 16-Pin WQFN With Exposed Thermal Pad Top View Table 5-6. Pin Functions: OPA4990S PIN NAME NO. I/O DESCRIPTION IN1+ 1 I Noninverting input, channel 1 IN1– 16 I Inverting input, channel 1 IN2+ 3 I Noninverting input, channel 2 IN2– 4 I Inverting input, channel 2 IN3+ 10 I Noninverting input, channel 3 IN3– 9 I Inverting input, channel 3 IN4+ 12 I Noninverting input, channel 4 IN4– 13 I Inverting input, channel 4 OUT1 15 O Output, channel 1 OUT2 5 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 SHDN12 6 I Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers disabled. See Shutdown section for more information. SHDN34 7 I Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers disabled. See Shutdown section for more information. VCC+ 2 — Positive (highest) power supply VCC– 11 — Negative (lowest) power supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 9 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted)(1) MIN MAX 0 42 V (V–) – 0.5 (V+) + 0.5 V Supply voltage, VS = (V+) – (V–) Common-mode voltage(3) Differential voltage(3) Signal input pins VS + 0.2 Current(3) Shutdown pin voltage(4) Output short-circuit(2) 10 V– (V–) + 20 V 150 °C 150 °C 150 °C –55 Junction temperature, TJ Storage temperature, Tstg (2) (3) (4) V –10 mA Continuous Operating ambient temperature, TA (1) UNIT –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual destruction. See the Thermal Protection section for more information. Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. Cannot exceed V+. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101(2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN MAX 2.7 40 V Input voltage range (V–) – 0.2 (V+) + 0.2 V VIH High level input voltage at shutdown pin (amplifier disabled) (V–) + 1.1 (V–) + 20 V(1) V VIL Low level input voltage at shutdown pin (amplifier enabled) (V–) (V–) + 0.2 V TA Specified temperature –40 125 °C VS Supply voltage, (V+) – (V–) VI (1) 10 UNIT Cannot exceed V+. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.4 Thermal Information for Single Channel OPA990, OPA990S DBV (SOT-23) THERMAL METRIC(1) DRL(2) (SOT-553) DCK (SC70) UNIT 5 PINS 6 PINS 5 PINS 5 PINS 6 PINS RθJA Junction-to-ambient thermal resistance 192.1 174.5 204.6 TBD TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 113.6 113.4 116.5 TBD TBD °C/W RθJB Junction-to-board thermal resistance 60.5 55.8 51.8 TBD TBD °C/W ψJT Junction-to-top characterization parameter 37.2 39.6 24.9 TBD TBD °C/W ψJB Junction-to-board characterization parameter 60.3 55.6 51.5 TBD TBD °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A TBD TBD °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. This package option is preview for OPA990. 6.5 Thermal Information for Dual Channel OPA2990, OPA2990S THERMAL METRIC(1) D (SOIC) DDF (SOT-23-8) DGK (VSSOP) DGS (VSSOP) DSG (WSON) PW (TSSOP) RUG (X2QFN) UNIT 8 PINS 8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 138.7 150.4 189.3 152.2 81.6 188.4 149.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.7 85.6 75.8 67.3 101.6 77.1 58.3 °C/W RθJB Junction-to-board thermal resistance 82.2 70.0 111.0 95.5 48.3 119.1 77.7 °C/W ψJT Junction-to-top characterization parameter 27.8 8.1 15.4 67.9 6.0 14.2 1.3 °C/W ψJB Junction-to-board characterization parameter 81.4 69.6 109.3 94.3 48.3 117.4 77.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 22.8 N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 11 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.6 Thermal Information for Quad Channel OPA4990, OPA4990S THERMAL METRIC(1) D (SOIC) PW (TSSOP) RTE(2) (WQFN) RUC (WQFN) 14 PINS 14 PINS 16 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 105.2 134.7 53.5 143.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 61.2 55.0 58.3 46.4 °C/W RθJB Junction-to-board thermal resistance 61.1 79.0 28.6 81.8 °C/W ψJT Junction-to-top characterization parameter 21.4 9.2 2.1 1.0 °C/W ψJB Junction-to-board characterization parameter 60.7 78.1 28.6 81.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 12.6 N/A °C/W (1) (2) 12 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. This package option is preview for OPA4990. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.7 Electrical Characteristics For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage dVOS/dT Input offset voltage drift PSRR VCM = V– ±0.3 TA = –40°C to 125°C TA = –40°C to 125°C Input offset voltage versus power supply VCM = V–, VS = 4 V to 40 V Channel separation f = 0 Hz VCM = V–, VS = 2.7 V to 40 V(2) ±1.5 ±1.75 ±0.6 TA = –40°C to 125°C mV µV/℃ ±0.1 ±1.3 ±0.75 ±6.6 5 µV/V µV/V INPUT BIAS CURRENT IB Input bias current ±10 pA IOS Input offset current ±5 pA NOISE EN Input voltage noise eN Input voltage noise density iN Input current noise f = 0.1 Hz to 10 Hz 6 µVPP 1 µVRMS f = 1 kHz 30 f = 10 kHz 28 f = 1 kHz 2 nV/√Hz fA/√Hz INPUT VOLTAGE RANGE VCM CMRR Common-mode voltage range Common-mode rejection ratio (V–) – 0.2 (V+) + 0.2 VS = 40 V, (V–) – 0.1 V < VCM < (V+) – 2 V (PMOS pair) 100 115 VS = 4 V, (V–) – 0.1 V < VCM < (V+) – 2 V (PMOS pair) 75 90 70 90 VS = 2.7 V, (V–) – 0.1 V < VCM < (V+) – 2 V (PMOS pair)(2) dB TA = –40°C to 125°C VS = 2.7 – 40 V, (V+) – 1 V < VCM < (V+) + 0.1 V (NMOS pair) (V+) – 2 V < VCM < (V+) – 1 V V 80 See Offset Voltage (Transition Region) in the Typical Characteristics section INPUT CAPACITANCE ZID Differential ZICM Common-mode 540 || 3 GΩ || pF 6 || 1 TΩ || pF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 13 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.7 Electrical Characteristics (continued) For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP 120 145 MAX UNIT OPEN-LOOP GAIN VS = 40 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V AOL Open-loop voltage gain VS = 4 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V VS = 2.7 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V(2) TA = –40°C to 125°C 142 104 TA = –40°C to 125°C dB 130 125 101 TA = –40°C to 125°C 118 dB 117 dB 1.1 MHz 4.5 V/μs FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate tS Settling time VS = 40 V, G = +1, CL = 20 pF To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 4 To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 2 To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 5 To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF THD+N Phase margin G = +1, RL = 10 kΩ, CL = 20 pF Overload recovery time VIN × gain > VS Total harmonic distortion + noise VS = 40 V, VO = 1 VRMS, G = 1, f = 1 kHz µs 3 60 ° 600 ns 0.00162% OUTPUT VS = 40 V, RL = no load Voltage output swing from rail ISC 45 60 VS = 40 V, RL = 2 kΩ 200 300 VS = 2.7 V, RL = no load Capacitive load drive ZO Open-loop output impedance mV 1 VS = 2.7 V, RL = 10 kΩ 5 20 VS = 2.7 V, RL = 2 kΩ 25 50 Short-circuit current CLOAD 14 Positive and negative rail headroom 2 VS = 40 V, RL = 10 kΩ ±80 mA See Small-Signal Overshoot vs Capacitive Load in the Typical Characteristics section f = 1 MHz, IO = 0 A Submit Document Feedback 575 Ω Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.7 Electrical Characteristics (continued) For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 120 150 UNIT POWER SUPPLY Quiescent current per amplifier IQ OPA2990, OPA4990, IO = 0 A OPA990, IO = 0 A TA = –40°C to 125°C 160 130 TA = –40°C to 125°C 170 µA 175 Turn-on time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs 40 IQSD Quiescent current per amplifier VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– + 2 V 20 ZSHDN Output impedance during shutdown VS = 2.7 V to 40 V, amplifier disabled, SHDN = V– + 2 V VIH Logic high threshold voltage (amplifier disabled) For valid input high, the SHDN pin voltage should be greater than the maximum threshold but less than or equal to (V–) + 20 V VIL For valid input low, the SHDN pin voltage should be less Logic low threshold voltage than the minimum threshold but greater than or equal to (amplifier enabled) V– tON Amplifier enable time (1) G = +1, VCM = V–, VO = 0.1 × VS / 2 tOFF Amplifier disable time (1) VCM = V–, VO = VS / 2 SHDN pin input bias current (per pin) VS = 2.7 V to 40 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V 500 VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V 150 μs SHUTDOWN (1) (2) 30 10 || 12 (V–) + 0.8 (V–) + 0.2 µA GΩ || pF (V–) + 1.1 V (V–) + 0.8 V 11 µs 2.5 µs nA Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level. Specified by characterization only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 15 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics 25% 25% 20% 20% Population (%) 15% 10% 15% 10% 5% Offset Voltage (PV) Offset Voltage Drift (PV/qC) Distribution from 15526 amplifiers, TA = 25°C Distribution from 190 amplifiers Figure 6-1. Offset Voltage Production Distribution 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 D001 0.2 1200 900 1050 750 600 450 300 0 150 -150 -300 -450 -600 -750 -900 -1050 -1200 0 5% 0 Population (%) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) D002 Figure 6-2. Offset Voltage Drift Distribution 1000 800 800 600 Offset Voltage (µV) Offset Voltage (µV) 600 400 200 0 -200 -400 400 200 0 -200 -400 -600 -600 -800 -1000 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 -800 -40 140 VCM = V+ Each color represents one sample device. 600 600 400 400 200 0 -200 -600 16 20 -800 16 16.5 17 D005 TA = 25°C Each color represents one sample device. Figure 6-5. Offset Voltage vs Common-Mode Voltage 16 120 140 D004 -200 -600 12 100 0 -400 -8 -4 0 4 8 Common Mode Voltage (V) 40 60 80 Temperature (°C) 200 -400 -12 20 Figure 6-4. Offset Voltage vs Temperature 800 Offset Voltage (µV) Offset Voltage (µV) Figure 6-3. Offset Voltage vs Temperature -16 0 VCM = V– Each color represents one sample device. 800 -800 -20 -20 D003 17.5 18 18.5 19 Common Mode Voltage (V) 19.5 20 D005 TA = 25°C Each color represents one sample device. Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition Region) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics (continued) 1000 800 800 600 600 400 Offset Voltage (µV) 400 200 0 -200 -400 200 0 -200 -400 -600 -600 -800 -800 -1000 -1000 -20 -16 -12 -8 -4 0 4 8 Common Mode Voltage (V) 12 16 -1200 -20 20 -16 -12 D006 TA = 125°C Each color represents one sample device. -8 -4 0 4 8 Common Mode Voltage (V) 16 20 D007 TA = –40°C Each color represents one sample device. Figure 6-7. Offset Voltage vs Common-Mode Voltage Figure 6-8. Offset Voltage vs Common-Mode Voltage 750 100 150 Gain Phase 600 80 450 300 Gain (dB) Offset Voltage (µV) 12 150 0 -150 125 60 100 40 75 20 50 0 25 Phase (q) Offset Voltage (µV) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) -300 -450 -600 -20 100 -750 0 4 8 12 16 20 24 28 Supply Voltage (V) 32 36 40 0 1k 44 10k 100k Frequency (Hz) 1M C002 CL = 20 pF D008 VCM = V– Each color represents one sample device. Figure 6-10. Open-Loop Gain and Phase vs Frequency Figure 6-9. Offset Voltage vs Power Supply 3 70 60 Closed-Loop Gain (dB) 50 40 Input Bias and Offset Current (pA) G=1 G = -1 G = 10 G = 100 G = 1000 30 20 10 0 -10 -20 -30 100 1k 10k 100k Frequency (Hz) 2 IB IB+ IOS 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -20 1M Figure 6-11. Closed-Loop Gain vs Frequency 2.5 -16 -12 C001 -8 -4 0 4 8 Common Mode Voltage (V) 12 16 20 D010 Figure 6-12. Input Bias Current vs Common-Mode Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 17 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) V+ IB IB+ IOS 280 240 V+ Output Voltage (V) Input Bias and Offset Current (pA) 320 200 160 120 80 40 V+ 2V V+ 3V V+ 4V V+ 5V V+ 6V V+ 7V V+ 8V V+ 0 V+ -20 0 20 40 60 80 Temperature (°C) 100 120 9V 10 V 10 20 30 140 D011 Figure 6-13. Input Bias Current vs Temperature 40 50 60 70 Output Current (mA) 80 90 100 D012 Figure 6-14. Output Voltage Swing vs Output Current (Sourcing) 5 V + 10 V -40°C 25°C 85°C 125°C V +9V V +8V -40qC 4.5 4 V +7V Output Voltage (V) Output Voltage (V) -40°C 25°C 85°C 125°C 0 -40 -40 V +6V V +5V V +4V V +3V V +2V 3.5 25qC 125qC 3 2.5 85qC 2 1.5 1 V +1V 0.5 V 0 10 20 30 40 50 60 70 Output Current (mA) 80 90 0 100 0 D012 Figure 6-15. Output Voltage Swing vs Output Current (Sinking) 110 4.5 100 4 90 3 85qC 2.5 125qC 2 1.5 1 25qC 0.5 -40qC 20 30 40 50 60 70 Output Current (mA) 80 90 100 D013 Figure 6-16. Output Voltage Swing vs Output Current (Sourcing) 5 3.5 10 VS = 5 V PSRR and CMRR (dB) Output Voltage (V) 1V PSRR+ PSRRCMRR 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 Output Current (mA) 80 90 100 0 100 1k D013 10k 100k Frequency (Hz) 1M 10M C003 VS = 5 V Figure 6-17. Output Voltage Swing vs Output Current (Sinking) 18 Figure 6-18. CMRR and PSRR vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics (continued) 124 145 120 144 116 Power Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) VS = 40 V VS = 4 V 112 108 104 100 96 92 88 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 143 142 141 140 139 138 137 136 135 -40 140 -20 0 20 D015 f = 0 Hz 140 D016 Input Voltage Noise Spectral Density (nV/rHz) Voltage (1uV/div) 120 110 100 90 80 70 60 50 40 30 20 10 0 10 100 1k Frequency (Hz) C015 Figure 6-21. 0.1-Hz to 10-Hz Noise 10k 100k C017 Figure 6-22. Input Voltage Noise Spectral Density vs Frequency -30 -40 RL = 10 k: RL = 2 k: RL = 600 : RL = 128 : -40 -50 THD+N (dB) THD+N (dB) 120 Figure 6-20. PSRR vs Temperature (dB) Time (1s/Div) -60 100 f = 0 Hz Figure 6-19. CMRR vs Temperature (dB) -50 40 60 80 Temperature (°C) -70 -80 -60 -70 -90 -80 -100 -90 -110 100 1k Frequency (Hz) RL = 10 k: RL = 2 k: RL = 549 : RL = 128 : -100 0.001 10k 0.01 C012 BW = 80 kHz, VOUT = 1 VRMS Figure 6-23. THD+N Ratio vs Frequency 0.1 Amplitude (VRMS) 1 10 20 C023 BW = 80 kHz, f = 1 kHz Figure 6-24. THD+N vs Output Amplitude Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 19 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) 127.5 125 125 120 122.5 Quiescent current (µA) Quiescent current (µA) 130 115 110 105 100 95 120 117.5 115 112.5 110 107.5 90 105 85 102.5 -40 0 4 8 12 16 20 24 28 Supply Voltage (V) 32 36 40 -20 0 20 D021 40 60 80 Temperature (°C) 100 120 140 D022 VCM = V– Figure 6-26. Quiescent Current vs Temperature 146 780 144 720 Open Loop Output Impedance (:) Open Loop Voltage Gain (dB) Figure 6-25. Quiescent Current vs Supply Voltage 142 140 138 136 VS = 40 V VS = 4 V 134 132 130 128 126 124 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 160 140 120 100 80 60 40 20 0 12 16 20 24 28 Supply Voltage (V) 480 420 360 300 240 180 1k 32 36 40 1M 10M C013 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 0 4 8 D026 12 16 20 24 28 Supply Voltage (V) 32 36 40 D026 RL = 2 kΩ RL = 2 kΩ Figure 6-29. Output Swing vs Supply Voltage, Positive Swing 20 10k 100k Frequency (Hz) Figure 6-28. Open-Loop Output Impedance vs Frequency Delta Between Supply and Output Voltage (mV) Delta Between Supply and Output Voltage (mV) 180 8 540 D023 200 4 600 120 100 140 Figure 6-27. Open-Loop Voltage Gain vs Temperature (dB) 0 660 Figure 6-30. Output Swing vs Supply Voltage, Negative Swing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics (continued) Delta Between Supply and Output Voltage (mV) Delta Between Supply and Output Voltage (mV) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) 40 36 32 28 24 20 16 12 8 4 0 0 4 8 12 16 20 24 28 Supply Voltage (V) 32 36 -10 -15 -20 -25 -30 -35 -40 -45 0 40 4 8 12 16 20 24 28 Supply Voltage (V) D027 RL = 10 kΩ Figure 6-31. Output Swing vs Supply Voltage, Positive Swing 55 30 50 27 45 24 40 18 15 36 40 D027 Figure 6-32. Output Swing vs Supply Voltage, Negative Swing 33 21 32 RL = 10 kΩ Overshoot (%) Overshoot (%) 0 -5 12 35 30 25 20 RISO = 0 :, Positive Overshoot RISO = 0 :, Negative Overshoot RISO = 50 :, Positive Overshoot RISO = 50 :, Negative Overshoot 9 6 RISO = 0 :, Positive Overshoot RISO = 0 :, Negative Overshoot RISO = 50 :, Positive Overshoot RISO = 50 :, Negative Overshoot 15 10 3 5 0 40 80 120 160 200 240 Cap Load (pF) 280 320 360 0 40 80 120 C007 G = –1, 10-mV output step 160 200 240 Cap Load (pF) 280 320 360 C008 G = 1, 10-mV output step Figure 6-33. Small-Signal Overshoot vs Capacitive Load Figure 6-34. Small-Signal Overshoot vs Capacitive Load 64 Input Output 60 56 Amplitude (2V/div) Phase Margin (q) 52 48 44 40 36 32 28 24 20 0 100 200 300 400 500 600 Cap Load (pF) 700 800 Time (20µs/Div) 900 1000 C016 C009 VIN = ±20 V; VS = VOUT = ±17 V Figure 6-35. Phase Margin vs Capacitive Load Figure 6-36. No Phase Reversal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 21 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics (continued) Voltage (5V/div) Voltage (5V/div) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) Input Output Input Output Time (500ns/div) Time (500ns/div) C018 C018 G = –10 G = –10 Figure 6-37. Positive Overload Recovery Figure 6-38. Negative Overload Recovery Amplitude (5mV/div) Amplitude (5mV/div) Input Output Input Output Time (1µs/div) Time (2Ps/div) C011 C010 CL = 20 pF, G = –1, 20-mV step response CL = 20 pF, G = 1, 20-mV step response Figure 6-40. Small-Signal Step Response Figure 6-39. Small-Signal Step Response Amplitude (2V/div) Amplitude (2V/div) Input Output Input Output Time (1µs/div) Time (1µs/div) C005 C005 CL = 20 pF, G = 1 Figure 6-41. Large-Signal Step Response (Falling) 22 CL = 20 pF, G = 1 Figure 6-42. Large-Signal Step Response (Rising) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) Large Signal Step Response (2V/div) 100 Short-Circuit Current (mA) 80 Input Output 60 40 20 0 Sourcing Sinking -20 -40 -60 -80 -100 -40 Time (2µs/div) -20 0 C021 20 40 60 80 Temperature (°C) 100 120 140 D038 CL = 20 pF, G = –1 Figure 6-44. Short-Circuit Current vs Temperature Figure 6-43. Large-Signal Step Response -60 20 -70 Channel Seperation (dB) Maximum Output Swing (V) VS = 15 V VS = 2.7 V 15 10 5 -80 -90 -100 -110 -120 0 1k 10k 100k Frequency (Hz) 1M -130 100 10M C020 Figure 6-45. Maximum Output Voltage vs Frequency 1k 10k 100k Frequency (Hz) 1M 10M C014 Figure 6-46. Channel Separation vs Frequency 100 90 EMIRR (dB) 80 70 60 50 40 30 1M 10M 100M Frequency (Hz) 1G C004 Figure 6-47. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 23 OPA990, OPA2990, OPA4990 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 www.ti.com 7 Detailed Description 7.1 Overview The OPAx990 family (OPA990, OPA2990, and OPA4990) is a family of high voltage (40-V) general purpose operational amplifiers. These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset (±300 µV, typ), and low offset drift (±0.6 µV/°C, typ). Unique features such as differential and common-mode input voltage range to the supply rail, high short-circuit current (±80 mA), high slew rate (4.5 V/µs), and shutdown make the OPAx990 an extremely flexible, robust, and high-performance operational amplifier for high-voltage industrial applications. 7.2 Functional Block Diagram 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 7.3 Feature Description 7.3.1 Input Protection Circuitry The OPAx990 uses a unique input architecture to eliminate the requirement for input protection diodes but still provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection schemes that are activated by fast transient step responses and introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling time. V+ V+ VIN+ VIN+ 40 V VOUT OPAx990 VOUT ~0.7 V VIN VIN V OPAx990 Provides Full 40-V Differential Input Range V Conventional Input Protection Limits Differential Input Range Figure 7-1. OPAx990 Input Protection Does Not Limit Differential Input Capability Vn = 10 V RFILT 10 V 1 Ron_mux Sn 1 D 10 V CFILT 2 ~±9.3 V CS CD Vn+1 = ±10 V RFILT ±10 V Ron_mux Sn+1 VIN± 2 ~0.7 V CFILT CS VOUT Idiode_transient ±10 V Input Low-Pass Filter Simplified Mux Model VIN+ Buffer Amplifier Figure 7-2. Back-to-Back Diodes Create Settling Issues The OPAx990 family of operational amplifiers provides a true high-impedance differential input capability for high-voltage applications using a patented input protection architecture that does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The OPA990 tolerates a maximum differential swing (voltage between inverting and non-inverting pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in applications with fast-ramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision Operational Amplifiers for more information. 7.3.2 EMI Rejection The OPAx990 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx990 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 7-3 shows the results of this testing on the OPAx990. Table 7-1 shows the EMIRR IN+ values for the OPAx990 at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 25 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op amps and is available for download from www.ti.com. 100 90 EMIRR (dB) 80 70 60 50 40 30 1M 10M 100M Frequency (Hz) 1G C004 Figure 7-3. EMIRR Testing Table 7-1. OPA990 EMIRR IN+ For Frequencies of Interest FREQUENCY EMIRR IN+ 400 MHz 59.5 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 68.9 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 77.8 dB Bluetooth®, 2.4 GHz 802.11b, 802.11g, 802.11n, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 78.0 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8 dB 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 87.6 dB 5 GHz 26 APPLICATION OR ALLOCATION Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 7.3.3 Thermal Protection VOUT The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the OPAx990 is 150°C. Exceeding this temperature causes damage to the device. The OPAx990 has a thermal protection feature that reduces damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 170°C. Figure 7-4 shows an application example for the OPA990 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-4 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a shutdown and enabled state until the output fault is corrected. 3V TA = 65°C PD = 0.81W 0V JA = 138.7°C/W TJ = 138.7°C/W × 0.81W + 65°C TJ = 177.3°C (expected) 30 V OPA990 + ± + RL 3V 100 Ÿ ± VIN 3V 170ºC Temperature IOUT = 30 mA Figure 7-4. Thermal Protection 7.3.4 Capacitive Load and Stability 55 33 50 30 45 27 40 24 Overshoot (%) Overshoot (%) The OPAx990 features a resistive output stage capable of driving moderate capacitive loads, and by leveraging an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation. 35 30 25 21 18 15 12 20 RISO = 0 :, Positive Overshoot RISO = 0 :, Negative Overshoot RISO = 50 :, Positive Overshoot RISO = 50 :, Negative Overshoot 15 10 RISO = 0 :, Positive Overshoot RISO = 0 :, Negative Overshoot RISO = 50 :, Positive Overshoot RISO = 50 :, Negative Overshoot 9 6 3 5 0 40 80 120 160 200 240 Cap Load (pF) 280 320 360 0 40 80 C008 Figure 7-5. Small-Signal Overshoot vs Capacitive Load (10-mV Output Step, G = 1) 120 160 200 240 Cap Load (pF) 280 320 360 C007 Figure 7-6. Small-Signal Overshoot vs Capacitive Load (10-mV Output Step, G = –1) For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small resistor, RISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 27 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the OPAx990 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin. +Vs Vout Riso + Vin + ± Cload -Vs Figure 7-7. Extending Capacitive Load Drive With the OPA990 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 7.3.5 Common-Mode Voltage Range The OPAx990 is a 40-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 200 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 7-8. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded compared to operation outside this region. Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail. For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With Complementary-Pair Input Stages application note. V+ INPMOS PMOS NMOS IN+ NMOS V- Figure 7-8. Rail-to-Rail Input Stage 7.3.6 Phase Reversal Protection The OPAx990 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPAx990 is a rail-to-rail input op amp; therefore, the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 7-9. For more information on phase reversal, see Op Amps With Complementary-Pair Input Stages application note. Amplitude (2V/div) Input Output Time (20µs/Div) C016 Figure 7-9. No Phase Reversal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 29 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 7.3.7 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 7-10 shows an illustration of the ESD circuits contained in the OPAx990 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. TVS + ± RF +VS VDD R1 RS IN± 100 Ÿ IN+ 100 Ÿ OPAx990 ± + Power-Supply ESD Cell ID VIN RL + ± VSS + ± ±VS TVS Figure 7-10. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level. Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events. 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 7.3.8 Overload Recovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx990 is approximately 600 ns. 7.3.9 Typical Specifications and Distributions Designers often have questions about a typical specification of an amplifier in order to design a more robust circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this information to guardband their system, even when there is not a minimum or maximum specification in the Electrical Characteristics table. 0.00002% 0.00312% 0.13185% 1 -61 1 -51 2.145% 13.59% 34.13% 34.13% 13.59% 2.145% 1 1 -41 -31 1 -21 1 -1 1 1 +1 1 0.13185% 0.00312% 0.00002% 1 1 1 +21 +31 +41 +51 +61 Figure 7-11. Ideal Gaussian Distribution Figure 7-11 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the mean (from µ–σ to µ+σ). Depending on the specification, values listed in the typical column of the Electrical Characteristics table are represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in order to most accurately represent the typical value. You can use this chart to calculate approximate probability of a specification in a unit; for example, for OPAx990, the typical input voltage offset is 300 µV, so 68.2% of all OPAx990 devices are expected to have an offset from Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 31 OPA990, OPA2990, OPA4990 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 www.ti.com –300 µV to +300 µV. At 4 σ (±1200 µV), 99.9937% of the distribution has an offset voltage less than ±1200 µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units. Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits will be removed from production material. For example, the OPAx990 family has a maximum offset voltage of 1.5 mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI assures that any unit with larger offset than 1.5 mV will be removed from production material. For specifications with no value in the minimum or maximum column, consider selecting a sigma value of sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option as a wide guardband to design a system around. In this case, the OPAx990 family does not have a maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.6 µV/°C in the Electrical Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 3.6 µV/°C. When designing for worst-case system conditions, this value can be used to estimate the worst possible offset across temperature without having an actual minimum or maximum value. However, process variation and adjustments over time can shift typical means and standard deviations, and unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a device. This information should be used only to estimate the performance of a device. 7.3.10 Packages With an Exposed Thermal Pad The OPAx990 family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and performance of the device is not assured when doing so. 7.3.11 Shutdown The OPAx990S devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high. The amplifier is enabled when the input to the SHDN pin is a valid logic low. The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.1 V and V– + 20 V. The shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The maximum voltage allowed at the SHDN pins is V– + 20 V or V+, whichever is lower. Exceeding V– + 20V or V+, whichever is lower, will damage the device. The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The typical enable time out of shutdown is 11 µs; disable time is 2.5 µs. When disabled, the output assumes a high-impedance state. This architecture allows the OPAx990S family to operate as a gated amplifier, multiplexer, or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required. If using the OPAx990S without a load, the resulting turnoff time significantly increases. 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 www.ti.com OPA990, OPA2990, OPA4990 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 7.4 Device Functional Modes The OPAx990 has a single functional mode and is operational when the power-supply voltage is greater than or equal to 2.7 V (±1.35 V). The maximum power supply voltage for the OPAx990 is 40 V (±20 V). The OPAx990S devices feature a shutdown pin, which can be used to place the op amp into a low-power mode. See Shutdown section for more information. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 33 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The OPAx990 family offers excellent DC precision and AC performance. These devices operate up to 40-V supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1.1-MHz bandwidth and high output drive. These features make the OPAx990 a robust, high-performance operational amplifier for high-voltage industrial applications. 8.2 Typical Applications 8.2.1 High Voltage Buffered Multiplexer The OPAx990S shutdown devices can be configured to create a high voltage, buffered multiplexer. Outputs can be connected together on a common bus and the shutdown pins can be used to select the desired channel to pass through. Since the amplifier circuitry has been designed such that disable transitions occur significantly faster than enable transitions, the amplifier naturally exhibits a "break before make" switch topology. Amplifier outputs enter a high impedance state when placed in shutdown, so there is no risk of bus contention when connecting multiple channel outputs together. Additionally, because outputs are isolated from inputs, there is no concern about the impedance at the input of each channel interacting undesirably with the impedance at the output, like an amplifier gain stage or ADC driver circuit. Also, because this topology uses amplifiers instead of MOSFET switches, other common issues with multiplexers such as charge injection or signal error due to RON effects are eliminated. Figure 8-1 shows an example topology for a basic 2:1 multiplexer. When SEL is low, channel 1 is selected and active; when SEL is high, channel 2 is selected and active. For more information on how to use the OPAx990S shutdown function, see the shutdown section in the Electrical Characteristics table. ± Channel 1 Channel 1 Input + SEL Channel 2 Input Output + Channel 2 ± Figure 8-1. High Voltage Buffered Multiplexer 8.2.2 Slew Rate Limit for Input Protection In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages. By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output current and slew rate of the OPAx990 make the device an optimal amplifier to achieve slew rate control for both dual- and single-supply systems. Figure 8-2 shows the OPA990 in a slew-rate limit design. 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 Op Amp Gain Stage Slew Rate Limiter C1 470 nF R1 1.69 kŸ VEE VEE + R2 1.6 MŸ VIN OPAx990 V+ VOUT OPAx990 V+ VCC VCC RL 10 kŸ Figure 8-2. Slew Rate Limiter Uses One Op Amp Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 35 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 9 Power Supply Recommendations The OPAx990 is specified for operation from 2.7 V to 40 V (±1.35 V to ±20 V); many specifications apply from –40°C to 125°C or with specific supply voltages and test conditions. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics section. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout section. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 10.2 Layout Example + VIN VOUT RG RF Figure 10-1. Schematic Representation 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF NC NC GND ±IN V+ VIN +IN OUTPUT V± NC Use a low-ESR, ceramic bypass capacitor RG GND VS± GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor GND V+ INPUT Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration GND OUT V- GND Figure 10-3. Example Layout for SC70 (DCK) Package Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 37 OPA990, OPA2990, OPA4990 www.ti.com OUTPUT A SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 GND GND GND V+ INPUT A INPUT B OUTPUT B VGND GND GND GND V+ GND OUT A Figure 10-4. Example Layout for VSSOP-8 (DGK) Package GND OUT B - + + - +IN A V- +IN B GND GND GND Figure 10-5. Example Layout for WSON-8 (DSG) Package 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 OPA990, OPA2990, OPA4990 www.ti.com SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.2 Documentation Support 11.2.1 Related Documentation Texas Instruments, MUX-Friendly, Precision Operational Amplifiers application brief Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report Texas Instruments, Op Amps With Complementary-Pair Input Stages application note 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc. TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc. TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 39 OPA990, OPA2990, OPA4990 SBOS933I – FEBRUARY 2019 – REVISED AUGUST 2021 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA990 OPA2990 OPA4990 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA2990IDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O90F Samples OPA2990IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2H9T Samples OPA2990IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OP2990 Samples OPA2990IDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O29G Samples OPA2990IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O2990P Samples OPA2990SIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OP29 Samples OPA2990SIRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 H9F Samples OPA2990TIDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O90F Samples OPA4990IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OPA4990D Samples OPA4990IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 OPA49PW Samples OPA4990IRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O49RT Samples OPA4990IRUCR ACTIVE QFN RUC 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 FMF Samples OPA4990SIRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O4990S Samples OPA990IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 O90V Samples OPA990IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1FL Samples OPA990SIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O90S Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2023 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

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