OPA991, OPA2991, OPA4991
SBOS969E – OCTOBER 2019 – REVISED MAY 2021
OPAx991 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The OPAx991 family (OPA991, OPA2991, and
OPA4991) is a family of high voltage (40-V) general
purpose operational amplifiers. These devices offer
exceptional DC precision and AC performance,
including rail-to-rail input/output, low offset (±125 µV,
typ), low offset drift (±0.3 µV/°C, typ), low noise (10.5
nV/√ Hz and 1.8 µVPP), and 4.5-MHz bandwidth.
•
•
•
•
Low offset voltage: ±125 µV
Low offset voltage drift: ±0.3 µV/°C
Low noise: 10.8 nV/√ Hz at 1 kHz
High common-mode rejection: 130 dB
Low bias current: ±10 pA
Rail-to-rail input and output
Wide bandwidth: 4.5 MHz GBW
High slew rate: 21 V/µs
High capacitive load drive: 1 nF
MUX-friendly/comparator inputs
– Amplifier operates with differential inputs up to
supply rail
– Amplifier can be used in open-loop or as
comparator
Low quiescent current: 560 µA per amplifier
Wide supply: ±1.35 V to ±20 V, 2.7 V to 40 V
Robust EMIRR performance: EMI/RFI filters on
input and supply pins
Differential and common-mode input voltage range
to supply rail
Unique features such as differential and commonmode input-voltage range to the supply rail, high
output current (±75 mA), high slew rate (21 V/µs),
high capacitive load drive (1 nF), and shutdown
functionality make the OPAx991 a robust, highperformance operational amplifier for high-voltage
industrial applications.
The OPAx991 family of op amps is available in
micro-size packages (such as X2QFN, WSON, and
SOT-553), as well as standard packages (such as
SOT-23, SOIC, and TSSOP), and is specified from
–40°C to 125°C.
Device Information
2 Applications
Low-power audio preamplifier
Multiplexed data-acquisition systems
Test and measurement equipment
ADC driver amplifiers
SAR ADC reference buffers
Programmable logic controllers
High-side and low-side current sensing
PACKAGE
OPA991
OPA2991
OPA4991
(1)
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23-8 (8)
2.90 mm × 1.60 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
2.00 mm × 2.00 mm
X2QFN (10)
2.00 mm × 1.50 mm
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)
5.00 mm × 4.40 mm
WQFN
(16)(2)
X2QFN (14)
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Package is preview only.
(2)
Analog Inputs
REF3140
Bridge Sensor
OPA991
Gain Network
Gain Network
RC Filter
OPA375
RC Filter
Reference Driver
+
MUX509
Thermocouple
+
OPA991
Current Sensing
LED
Photo
Detector
Optical Sensor
High-Voltage Multiplexed Input
REF
OPA991
+
Gain Network
Gain Network
•
•
•
•
•
•
•
PART NUMBER (1)
High-Voltage Level Translation
VINP
Antialiasing
Filter
ADS8860
VINM
VCM
OPAx991 in a High-Voltage, Multiplexed, Data-Acquisition System
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA991, OPA2991, OPA4991
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SBOS969E – OCTOBER 2019 – REVISED MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications................................................................ 11
6.1 Absolute Maximum Ratings ..................................... 11
6.2 ESD Ratings .............................................................11
6.3 Recommended Operating Conditions ...................... 11
6.4 Thermal Information for Single Channel .................. 11
6.5 Thermal Information for Dual Channel .....................12
6.6 Thermal Information for Quad Channel ................... 12
6.7 Electrical Characteristics ..........................................13
6.8 Typical Characteristics.............................................. 16
7 Detailed Description......................................................23
7.1 Overview................................................................... 23
7.2 Functional Block Diagram......................................... 23
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................33
8 Application and Implementation.................................. 34
8.1 Application Information............................................. 34
8.2 Typical Applications.................................................. 34
9 Power Supply Recommendations................................36
10 Layout...........................................................................36
10.1 Layout Guidelines................................................... 36
10.2 Layout Example...................................................... 37
11 Device and Documentation Support..........................38
11.1 Device Support........................................................38
11.2 Documentation Support.......................................... 38
11.3 Related Links.......................................................... 38
11.4 Receiving Notification of Documentation Updates.. 38
11.5 Support Resources................................................. 39
11.6 Trademarks............................................................. 39
11.7 Electrostatic Discharge Caution.............................. 39
11.8 Glossary.................................................................. 39
12 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2020) to Revision E (May 2021)
Page
• Deleted preview notation from X2QFN-14 (RUC) package in Device Information ............................................ 1
• Deleted preview notation from VSSOP-8 (DGK) package in Device Information ..............................................1
• Removed preview notation from X2QFN-14 (RUC) package in Pin Configuration and Functions section ........4
• Removed preview notation from VSSOP-8 (DGK) in Pin Configuration and Functions section ........................4
• Removed Table of Graphs from the Specifications section...............................................................................11
Changes from Revision C (May 2020) to Revision D (July 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Deleted preview notation from SOIC-14 (D) package in Device Information .....................................................1
• Deleted preview notation from SOT-23-5 (DBV) package in Device Information .............................................. 1
• Deleted preview notation from SOT-23-6 (DBV) package in Device Information .............................................. 1
• Deleted preview notation from SC70 (DCK) package in Device Information .....................................................1
• Deleted preview notation from SOT-23-8 (DDF) package in Device Information .............................................. 1
• Deleted preview notation from TSSOP-14 (PW) package in Device Information .............................................. 1
• Removed preview notation on SOT-23-5 (DBV), and SC70 (DCK)....................................................................4
• Clarified SHDN notation in the OPA991S Pin Configuration and Functions section ......................................... 4
• Removed preview notation from SOT-23-6 (DBV) package in Pin Configuration and Functions section ..........4
• Removed preview notation from SOT-23-8 (DDF) package in Pin Configuration and Functions section ..........4
• Clarified SHDN notation in OPA2991S Pin Configuration and Functions section ............................................. 4
• Removed preview notation from SOIC-14 (D) and TSSOP-14 (PW) packages in Pin Configuration and
Functions section ...............................................................................................................................................4
• Clarified SHDN notation in OPA4991S Pin Configuration and Functions section ............................................. 4
Changes from Revision B (May 2020) to Revision C (May 2020)
Page
• Removed preview notation from TSSOP (PW) package in Pin Configuration and Functions section ...............4
• Removed preview notation from X2QFN (RUG) package in Pin Configuration and Functions section .............4
2
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OPA991, OPA2991, OPA4991
SBOS969E – OCTOBER 2019 – REVISED MAY 2021
Changes from Revision A (December 2019) to Revision B (May 2020)
Page
• Added OPA991 and OPA4991 devices to the data sheet...................................................................................1
• Deleted preview notation from WSON (DSG) package in Device Information .................................................. 1
• Changed X2QFN (10) dimension in Device Information section ....................................................................... 1
• Changed formatting of Pin Functions tables to align with data sheet standards................................................ 4
• Deleted preview notation from WSON (DSG) package in Pin Configuration and Functions section .................4
Changes from Revision * (October 2019) to Revision A (December 2019)
Page
• Changed OPA2991 device status from Advance Information to Production Data .............................................1
• Removed preview notation from SOIC (D) package in Device Information .......................................................1
• Removed preview notation from SOIC (D) package in Pin Configuration and Functions section...................... 4
• Added Typical Characteristics section in Specifications section.......................................................................16
• Added additional references in Related Documentation section...................................................................... 38
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SBOS969E – OCTOBER 2019 – REVISED MAY 2021
5 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
A.
5
V+
4
OUT
Not to scale
Figure 5-2. OPA991 DCK Package
5-Pin SC70
Top View
DRL package is preview only.
Figure 5-1. OPA991 DBV, T DCK, and DRL
Package(A)
5-Pin SOT-23, SC70, and SOT-553
Top View
Table 5-1. Pin Functions: OPA991
PIN
NAME
4
DBV, DRL
DCK
IN+
3
1
IN–
4
OUT
1
V+
V–
I/O
DESCRIPTION
I
Noninverting input
3
I
Inverting input
4
O
Output
5
5
—
Positive (highest) power supply
2
2
—
Negative (lowest) power supply
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SBOS969E – OCTOBER 2019 – REVISED MAY 2021
OUT
1
6
V+
V±
2
5
NC
+IN
3
4
±IN
Not to scale
A.
DRL package is preview only.
Figure 5-3. OPA991S DBV and DRL Package(A)
6-Pin SOT-23 and SOT-563
Top View
Table 5-2. Pin Functions: OPA991S
PIN
NAME
NO.
I/O
DESCRIPTION
+IN
3
I
Noninverting input
–IN
4
I
Inverting input
OUT
1
O
Output
Shutdown: low = amplifier enabled, high = amplifier disabled. See Section
7.3.11 for more information.
SHDN
5
I
V+
6
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
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SBOS969E – OCTOBER 2019 – REVISED MAY 2021
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Figure 5-4. OPA2991 D, DDF, DGK, and PW
Package
8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP
Top View
Not to scale
A.
Connect thermal pad to V–. See Section 7.3.10 for more
information.
Figure 5-5. OPA2991 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-3. Pin Functions: OPA2991
PIN
NAME
6
NO.
I/O
DESCRIPTION
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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IN1+
SBOS969E – OCTOBER 2019 – REVISED MAY 2021
1
10
V+
IN1±
2
9
OUT2
IN1+
3
8
IN2±
V±
4
7
IN2+
SHDN1
5
6
SHDN2
V±
1
9
IN1±
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
10
OUT1
Not to scale
Package is preview only.
5
A.
Figure 5-6. OPA2991S DGS Package(A)
10-Pin VSSOP
Top View
IN2±
Not to scale
Figure 5-7. OPA2991S RUG Package
10-Pin X2QFN
Top View
Table 5-4. Pin Functions: OPA2991S
PIN
NAME
I/O
DESCRIPTION
VSSOP
X2QFN
+IN A
3
10
+IN B
7
4
I
Noninverting input, channel B
–IN A
2
9
I
Inverting input, channel A
–IN B
8
5
I
Inverting input, channel B
OUT A
1
8
O
Output, channel A
OUT B
9
6
O
Output, channel B
SHDN1
5
2
I
Shutdown, channel 1: low = amplifier enabled, high = amplifier
disabled. See Section 7.3.11 for more information.
SHDN2
6
3
I
Shutdown, channel 2: low = amplifier enabled, high = amplifier
disabled. See Section 7.3.11 for more information.
V+
10
7
—
Positive (highest) power supply
V–
4
1
—
Negative (lowest) power supply
I
Noninverting input, channel A
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IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN1+
1
V+
2
IN4±
13
13
2
OUT4
IN1±
14
OUT4
OUT1
14
15
1
IN1±
OUT1
16
SBOS969E – OCTOBER 2019 – REVISED MAY 2021
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
8
OUT3
IN2±
4
8
7
OUT3
OUT2
Pad
7
3
NC
IN2+
6
IN3±
NC
9
5
6
OUT2
IN2±
Not to scale
Figure 5-8. OPA4991 D and PW Package
14-Pin SOIC and TSSOP
Top View
A.
Not to scale
Connect thermal pad to V–. See Section 7.3.10 for more
information.
Package is preview only.
B.
IN4±
11
IN4+
V+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
OUT2
7
2
OUT3
IN1+
13
12
14
1
6
IN1±
OUT4
OUT1
Figure 5-9. OPA4991 RTE Package(A)(B)
16-Pin WQFN With Exposed Thermal Pad
Top View
Not to scale
Figure 5-10. OPA4991 RUC Package
14-Pin WQFN With Exposed Thermal Pad
Top View
8
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Table 5-5. Pin Functions: OPA4991
PIN
NAME
SOIC, TSSOP
WQFN
I/O
DESCRIPTION
IN1+
3
1
I
Noninverting input, channel 1
IN1–
2
16
I
Inverting input, channel 1
IN2+
5
3
I
Noninverting input, channel 2
IN2–
6
4
I
Inverting input, channel 2
IN3+
10
10
I
Noninverting input, channel 3
IN3–
9
9
I
Inverting input, channel 3
IN4+
12
12
I
Noninverting input, channel 4
IN4–
13
13
I
Inverting input, channel 4
NC
—
6, 7
—
Do not connect
OUT1
1
15
O
Output, channel 1
OUT2
7
5
O
Output, channel 2
OUT3
8
8
O
Output, channel 3
OUT4
14
14
O
Output, channel 4
V+
4
2
—
Positive (highest) power supply
V–
11
11
—
Negative (lowest) power supply
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IN1+
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
SBOS969E – OCTOBER 2019 – REVISED MAY 2021
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
A.
6
7
8
SHDN34
OUT3
4
SHDN12
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
Package is preview only.
Figure 5-11. OPA4991S RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-6. Pin Functions: OPA4991S
PIN
NAME
NO.
I/O
DESCRIPTION
IN1+
1
I
Noninverting input, channel 1
IN1–
16
I
Inverting input, channel 1
IN2+
3
I
Noninverting input, channel 2
IN2–
4
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
SHDN12
6
I
Shutdown, channel 1 & 2: low = amplifier enabled, high = amplifier disabled.
See Section 7.3.11 for more information.
SHDN34
7
I
Shutdown, channel 3 & 4: low = amplifier enabled, high = amplifier disabled.
See Section 7.3.11 for more information.
VCC+
2
—
Positive (highest) power supply
VCC–
11
—
Negative (lowest) power supply
10
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
42
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage
(3)
Differential voltage (3)
Signal input pins
VS + 0.2
Current (3)
–10
Output short-circuit (2)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device.
These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside
the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating
Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance.
Short-circuit to ground, one amplifier per package. This device has been designed to limit electrical damage due to excessive output
current, but extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual thermal
destruction. See the Thermal Protection section for more information.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
2.7
40
Input voltage range
(V–) – 0.2
(V+) + 0.2
V
VIH
High level input voltage at shutdown pin (amplifier disabled)
(V–) + 1.1
(V–) + 20 V(1)
V
VIL
Low level input voltage at shutdown pin (amplifier enabled)
(V–)
(V–) + 0.2
V
TA
Specified temperature
–40
125
°C
VS
Supply voltage, (V+) – (V–)
VI
(1)
UNIT
V
Cannot exceed V+.
6.4 Thermal Information for Single Channel
OPA991, OPA991S
THERMAL METRIC
DBV
(SOT-23)
(1)
DCK
(SC70)
UNIT
5 PINS
6 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
185.7
167.8
202.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
108.2
107.9
101.5
°C/W
RθJB
Junction-to-board thermal resistance
54.5
49.7
47.8
°C/W
ψJT
Junction-to-top characterization parameter
31.2
33.9
18.8
°C/W
ψJB
Junction-to-board characterization parameter
54.2
49.5
47.4
°C/W
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6.4 Thermal Information for Single Channel (continued)
OPA991, OPA991S
DBV
(SOT-23)
THERMAL METRIC (1)
RθJC(bot)
(1)
DCK
(SC70)
5 PINS
6 PINS
5 PINS
N/A
N/A
N/A
Junction-to-case (bottom) thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information for Dual Channel
OPA2991, OPA2991S
THERMAL METRIC (1)
D
(SOIC)
DDF
(SOT-23-8)
DGK
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
RUG
(X2QFN)
UNIT
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
10 PINS
RθJA
Junction-to-ambient thermal
resistance
130.7
143.5
176.5
77.6
185.1
142.3
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
72.8
79.9
68.1
93.7
74.0
53.5
°C/W
RθJB
Junction-to-board thermal
resistance
74.0
61.6
98.2
43.9
115.7
68.5
°C/W
ψJT
Junction-to-top
characterization parameter
24.0
5.7
12.0
4.4
12.3
1.0
°C/W
ψJB
Junction-to-board
characterization parameter
73.3
61.3
96.7
43.9
114.0
68.4
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
19.0
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
OPA4991, OPA4991S
THERMAL METRIC (1)
D
(SOIC)
PW
(TSSOP)
RUC
(WQFN)
14 PINS
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
101.4
131.4
125.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.6
51.8
39.8
°C/W
RθJB
Junction-to-board thermal resistance
57.3
75.8
68.0
°C/W
ψJT
Junction-to-top characterization parameter
18.5
7.9
0.8
°C/W
ψJB
Junction-to-board characterization parameter
56.9
74.8
67.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
12
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
OPA991, OPA2991
VCM = V–
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
PSRR
Input offset voltage
versus power supply
VCM = V–, VS = 4 V to 40 V
Channel separation
f = 0 Hz
OPA4991
VCM = V–
±125
TA = –40°C to 125°C
±125
TA = –40°C to 125°C
±830
µV
±850
TA = –40°C to 125°C
VCM = V–, VS = 2.7 V to 40 V(2)
±750
±780
±0.3
TA = –40°C to 125°C
µV/℃
±0.3
±1
±1
±5
5
µV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±10
pA
IOS
Input offset current
±10
pA
NOISE
1.8
µVPP
0.3
µVRMS
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
eN
Input voltage noise
density
f = 1 kHz
10.8
f = 10 kHz
9.4
iN
Input current noise
f = 1 kHz
nV/√Hz
2
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
(V–) – 0.1
VS = 40 V, (V–) – 0.1 V < VCM < (V+)
– 2 V (Main input pair)
CMRR
Common-mode rejection
ratio
VS = 4 V, (V–) – 0.1 V < VCM < (V+)
– 2 V (Main input pair)
VS = 2.7 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (Main input pair)(2)
(V+) + 0.1
109
130
84
100
75
95
TA = –40°C to 125°C
VS = 2.7 V to 40 V, (V+) – 1 V < VCM
< (V+) + 0.1 V (Aux input pair)
V
dB
85
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
540 || 9
GΩ || pF
6 || 1
TΩ || pF
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
120
145
104
130
MAX
UNIT
OPEN-LOOP GAIN
VS = 40 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
AOL
Open-loop voltage gain
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
VS = 2.7 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V(2)
TA = –40°C to 125°C
142
TA = –40°C to 125°C
101
TA = –40°C to 125°C
dB
125
120
118
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
4.5
MHz
VS = 40 V, G = +1, CL = 20 pF
21
V/µs
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
2.5
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
1.5
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
2
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
THD+N
Phase margin
G = +1, RL = 10 kΩ
Overload recovery time
VIN × gain > VS
Total harmonic distortion
+ noise
VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz
µs
1
60
°
400
ns
0.00021%
OUTPUT
VS = 40 V, RL = no load(2)
Voltage output swing from
Positive and negative rail headroom
rail
5
10
VS = 40 V, RL = 10 kΩ
50
55
VS = 40 V, RL = 2 kΩ
200
250
1
6
VS = 2.7 V, RL = 10 kΩ
5
12
VS = 2.7 V, RL = 2 kΩ
25
40
VS = 2.7 V, RL = no load(2)
mV
ISC
Short-circuit current
±75
mA
CLOAD
Capacitive load drive
1000
pF
ZO
Open-loop output
impedance
525
Ω
14
f = 1 MHz, IO = 0 A
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
560
Quiescent current per
amplifier
VCM = V–, IO = 0 A
IQSD
Quiescent current per
amplifier
VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– + 2 V
ZSHDN
Output impedance during
VS = 2.7 V to 40 V, amplifier disabled, SHDN = V– + 2 V
shutdown
VIH
Logic high threshold
voltage (amplifier
disabled)
For valid input high, the SHDN pin voltage should be greater than
the maximum threshold but less than or equal to (V–) + 20 V
VIL
Logic low threshold
voltage (amplifier
enabled)
For valid input low, the SHDN pin voltage should be less than the
minimum threshold but greater than or equal to V–
tON
Amplifier enable time
(1)
Amplifier disable time
(1)
IQ
TA = –40°C to 125°C
685
750
µA
SHUTDOWN
tOFF
SHDN pin input bias
current (per pin)
(1)
(2)
30
45
320 || 2
(V–) + 0.8
(V–) + 0.2
µA
MΩ || pF
(V–) + 1.1
V
(V–) + 0.8
V
G = +1, VCM = V-, VO = 0.1 × VS/2
8
µs
VCM = V-, VO = VS/2
3
µs
VS = 2.7 V to 40 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V
500
VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V
150
nA
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Specified by characterization only.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
50
33
30
27
40
Population (%)
Population (%)
24
21
18
15
12
30
20
9
10
6
900
400
700
300
500
Offset Voltage (µV)
100
-100
-300
0.8
0.7
0.6
100
0
-100
-500
-200
-700
-300
-20
0
20
40
60
80
Temperature (°C)
100
120
-400
-40
140
-20
0
20
40
60
80
Temperature (°C)
D004
600
600
400
400
Offset Voltage (µV)
800
200
0
-200
-200
-600
-600
0
VCM
D003
0
-400
-5
140
200
-400
-10
120
Figure 6-4. Offset Voltage vs Temperature
800
-15
100
VCM = V–
Figure 6-3. Offset Voltage vs Temperature
Offset Voltage (µV)
0.5
200
300
VCM = V+
16
0.4
0.3
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
Offset Voltage (µV)
0.2
600
360
240
120
0
-120
-240
-360
-480
-600
480
Distribution from 60 amplifiers
Distribution from 15462 amplifiers, TA = 25°C
-800
-20
D002
Offset Voltage Drift (µV/C)
D001
Offset Voltage (µV)
-900
-40
0.1
0
0
0
3
5
10
15
20
-800
16
16.5
17
D005
17.5
18
VCM
18.5
19
19.5
20
D005
TA = 25°C
TA = 25°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage
Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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6.8 Typical Characteristics (continued)
800
800
600
600
400
400
Offset Voltage (µV)
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-20
-15
-10
-5
0
VCM
5
10
15
-800
-20
20
-15
-10
D006
TA = 125°C
0
VCM
5
10
15
20
D007
TA = –40°C
Figure 6-7. Offset Voltage vs Common-Mode Voltage
Figure 6-8. Offset Voltage vs Common-Mode Voltage
600
100
500
90
400
80
200
Gain (dB) 175
Phase ( )
150
300
70
125
200
60
100
50
75
40
50
30
25
-200
20
0
-300
10
-25
-400
0
-50
-500
-10
-75
-600
-20
100
100
Gain (dB)
Offset Voltage (µV)
-5
0
-100
0
5
10
15
20
25
30
Supply Voltage (V)
35
40
45
1k
10k
100k
Frequency (Hz)
D008
1M
Phase ( )
Offset Voltage (µV)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
-100
10M
C002
CL = 20 pF
Figure 6-9. Offset Voltage vs Power Supply
Figure 6-10. Open-Loop Gain and Phase vs Frequency
80
6
Closed-Loop Gain (dB)
60
50
Input Bias and Offset Current (pA)
G= 1
G=1
G = 10
G = 100
G = 1000
70
40
30
20
10
0
-10
-20
100
1k
10k
100k
Frequency (Hz)
1M
4.5
3
1.5
0
-1.5
-3
-4.5
-7.5
-20
10M
IB
IB+
IOS
-6
-16
-12
-8
-4
0
4
8
Common Mode Voltage (V)
C001
Figure 6-11. Closed-Loop Gain vs Frequency
12
16
20
D010
Figure 6-12. Input Bias Current vs Common-Mode Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
V+
IB
IB+
IOS
125
100
75
Output Voltage (V)
Input Bias and Offset Current (pA)
150
50
25
0
-25
V+
1V
V+
2V
V+
3V
V+
4V
V+
5V
V+
6V
V+
7V
-50
V+
8V
-75
V+
9V
-100
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
V+
10 V
0
20
40
50
60
70
Output Current (mA)
80
90
100
D012
135
-40°C
25°C
125°C
V +7V
CMRR
PSRR+
PSRR
120
CMRR and PSRR (dB)
V +6V
V +5V
V +4V
V +3V
V +2V
V +1V
105
90
75
60
45
30
15
V
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
0
100
100
1M
10M
C003
170
Power Supply Rejection Ratio (dB)
130
125
120
115
PMOS (VCM
NMOS (VCM
V+
V+
1.5 V)
1.5 V)
105
100
95
90
85
-40
10k
100k
Frequency (Hz)
Figure 6-16. CMRR and PSRR vs Frequency
135
110
1k
D012
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
-20
0
20
40
60
80
Temperature (°C)
100
120
140
165
160
155
150
145
140
-40
-20
0
D015
f = 0 Hz
20
40
60
80
Temperature (°C)
100
120
140
D016
f = 0 Hz
Figure 6-17. CMRR vs Temperature (dB)
18
30
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
V +8V
Common-Mode Rejection Ratio (dB)
10
D011
Figure 6-13. Input Bias Current vs Temperature
Output Voltage (V)
-40°C
25°C
125°C
Figure 6-18. PSRR vs Temperature (dB)
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6.8 Typical Characteristics (continued)
Input Voltage Noise Spectral Density (nV/ Hz)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
1
0.8
Amplitude (uV)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
200
100
10
1
1
Time (1s/div)
10
C019
100k
C017
-32
-32
RL = 10 k
RL = 2 k
RL = 604
RL = 128
-40
-48
RL = 128
RL = 604
RL = 2 k
RL = 10 k
-40
-48
-56
THD+N (dB)
-56
THD+N (dB)
10k
Figure 6-20. Input Voltage Noise Spectral Density vs Frequency
Figure 6-19. 0.1-Hz to 10-Hz Noise
-64
-72
-80
-88
-64
-72
-80
-88
-96
-96
-104
-104
-112
0.001
-112
100
1k
Frequency (Hz)
10k
0.01
C012
BW = 80 kHz, VOUT = 1 VRMS
675
560
650
Quiescent current (µA)
700
570
550
540
530
520
510
575
550
525
500
475
480
12
16
20
24
28
Supply Voltage (V)
C023
600
490
8
10 20
625
500
4
1
Figure 6-22. THD+N vs Output Amplitude
580
0
0.1
Amplitude (Vrms)
BW = 80 kHz, f = 1 kHz
Figure 6-21. THD+N Ratio vs Frequency
Quiescent current (µA)
100
1k
Frequency (Hz)
32
36
40
450
-40
-20
0
D021
20
40
60
80
Temperature (°C)
100
120
140
D022
VCM = V–
Figure 6-23. Quiescent Current vs Supply Voltage
Figure 6-24. Quiescent Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
140
700
135
130
125
120
115
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
650
Open-loop output impedance (ohms)
Open Loop Voltage Gain (dB)
VS = 4 V
VS = 40 V
600
550
500
450
400
350
300
250
200
150
100
140
1k
D023
Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)
10k
100k
Frequency (Hz)
1M
10M
C013
Figure 6-26. Open-Loop Output Impedance vs Frequency
80
60
70
50
Overshoot (%)
Overshoot (%)
60
40
30
20
40
30
20
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
50
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
0
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C007
G = –1, 10-mV output step
Figure 6-27. Small-Signal Overshoot vs Capacitive Load
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C008
G = 1, 10-mV output step
Figure 6-28. Small-Signal Overshoot vs Capacitive Load
60
Input
Output
Amplitude (4V/div)
Phase Margin (Degree)
50
40
30
20
10
0
Time (20us/div)
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C009
C016
VIN = ±20 V; VS = VOUT = ±17 V
Figure 6-29. Phase Margin vs Capacitive Load
20
Figure 6-30. No Phase Reversal
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Voltage (5V/div)
Input
Output
Voltage (5V/div)
Input
Output
Time (100ns/div)
Time (100ns/div)
C018
C018
G = –10
G = –10
Figure 6-31. Positive Overload Recovery
Figure 6-32. Negative Overload Recovery
Amplitude (5mV/div)
Amplitude (5mV/div)
Input
Output
Input
Output
Time (1µs/div)
Time (300ns/div)
C011
C010
CL = 20 pF, G = 1, 20-mV step response
CL = 20 pF, G = 1, 20-mV step response
Figure 6-34. Small-Signal Step Response, Falling
Figure 6-33. Small-Signal Step Response, Rising
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Input
Output
Time (300ns/div)
Time (300ns/div)
C005
CL = 20 pF, G = 1
C005
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response (Rising)
Figure 6-36. Large-Signal Step Response (Falling)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Large Signal Step Response (2V/div)
100
80
60
Output Current (mA)
Input
Output
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
-40
Time (2µs/div)
-20
0
C021
20
40
60
80
Temperature (°C)
100
120
140
D014
CL = 20 pF, G = –1
Figure 6-38. Short-Circuit Current vs Temperature
Figure 6-37. Large-Signal Step Response
45
-50
VS = 40 V
VS = 30 V
VS = 15 V
VS = 2.7 V
35
-60
Channel Seperation (dB)
Maximum Output Swing (V)
40
30
25
20
15
10
-80
-90
-100
-110
-120
5
0
1k
-70
10k
100k
Frequency (Hz)
1M
-130
100
10M
C020
Figure 6-39. Maximum Output Voltage vs Frequency
1k
10k
100k
Frequency (Hz)
1M
10M
C014
Figure 6-40. Channel Separation vs Frequency
110
100
Gain(dB)
90
80
70
60
50
40
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
22
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7 Detailed Description
7.1 Overview
The OPAx991 family (OPA991, OPA2991, and OPA4991) is a new generation of 40-V general purpose
operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Unique features such as differential and common-mode input-voltage range to the supply rail, high output current
(±75 mA), high slew rate (21 V/µs), and shutdown functionality make the OPAx991 a robust, high-performance
operational amplifier for high-voltage industrial applications.
7.2 Functional Block Diagram
+
NCH Input
Stage
±
IN+
40-V
Differential
MUX-Friendly
Front End
+
Slew
Boost
Output
Stage
Shutdown
Circuitry
OUT
±
IN-
+
PCH Input
Stage
±
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPAx991 uses a unique input architecture to eliminate the requirement for input protection diodes but still
provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection
schemes that are activated by fast transient step responses and introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling
time.
V+
V+
VIN+
VIN+
VOUT
OPAx991
40 V
VOUT
~0.7 V
VIN
VIN
V
OPAx991 Provides Full 40-V
Differential Input Range
V
Conventional Input Protection
Limits Differential Input Range
Figure 7-1. OPAx991 Input Protection Does Not Limit Differential Input Capability
Vn = 10 V
RFILT
10 V
1
Ron_mux
Sn
1
D
10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Ron_mux
Sn+1
VIN±
2
~0.7 V
CS
CFILT
VOUT
Idiode_transient
±10 V
Input Low-Pass Filter
VIN+
Buffer Amplifier
Simplified Mux Model
Figure 7-2. Back-to-Back Diodes Create Settling Issues
The OPAx991 family of operational amplifiers provides a true high-impedance differential input capability for
high-voltage applications using a patented input protection architecture that does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input
applications. The OPA991 tolerates a maximum differential swing (voltage between inverting and non-inverting
pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in applications
with fast-ramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision
Operational Amplifiers for more information.
7.3.2 EMI Rejection
The OPAx991 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx991 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-3 shows the results of this testing on the OPAx991. Table 7-1 shows the EMIRR IN+ values for the OPAx991 at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
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Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
110
100
Gain(dB)
90
80
70
60
50
40
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 7-3. EMIRR Testing
Table 7-1. OPA991 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
73.2 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
82.5 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
89.7 dB
Bluetooth®,
2.4 GHz
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
93.9 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
95.7 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
98.0 dB
5 GHz
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7.3.3 Thermal Protection
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx991 is 150°C.
Exceeding this temperature causes damage to the device. The OPAx991 has a thermal protection feature that
reduces damage from self heating. The protection works by monitoring the temperature of the device and turning
off the op amp output drive for temperatures above 170°C. Figure 7-4 shows an application example for the
OPA991 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations indicate
that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual device,
however, turns off the output drive to recover towards a safe junction temperature. Figure 7-4 shows how the
circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is
3 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a
shutdown and enabled state until the output fault is corrected.
3V
TA = 65°C
PD = 0.81W
JA = 138.7°C/W
0V
TJ = 138.7°C/W × 0.81W + 65°C
TJ = 177.3°C (expected)
30 V
IOUT = 30 mA
+
–
VIN
3V
+
RL
3V
100 –
Temperature
OPA991
170ºC
Figure 7-4. Thermal Protection
If the device continues to operate at high junction temperatures with high output power over a long period of
time, regardless if the device is or is not entering thermal shutdown, the thermal dissipation of the device can
slowly degrade performance of the device and eventually cause catastrophic destruction. Designers should be
careful to limit output power of the device at high temperatures, or control ambient and junction temperatures
under high output power conditions.
7.3.4 Capacitive Load and Stability
The OPAx991 features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
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80
60
70
50
Overshoot (%)
Overshoot (%)
60
50
40
30
20
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
40
30
20
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C008
0
Figure 7-5. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = 1)
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C007
Figure 7-6. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces ringing
and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the OPAx991 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 7-7. Extending Capacitive Load Drive With the OPA991
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7.3.5 Common-Mode Voltage Range
The OPAx991 is a 40-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 7-8. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region,
typically (V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with
process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance
may be degraded compared to operation outside this region.
Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
INPMOS
PMOS
IN+
NMOS
NMOS
V-
Figure 7-8. Rail-to-Rail Input Stage
7.3.6 Phase Reversal Protection
The OPAx991 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx991 is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 7-9. For more information on phase reversal, see Op
Amps With Complementary-Pair Input Stages application note.
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Amplitude (4V/div)
Input
Output
Time (20us/div)
C016
Figure 7-9. No Phase Reversal
7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-10 shows an illustration of the ESD circuits contained in the OPAx991 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
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TVS
+
±
RF
+VS
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
OPAx990
±
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
VSS
+
±
±VS
TVS
Figure 7-10. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx991 is approximately 500 ns.
7.3.9 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in Section
6.7.
0.00002% 0.00312% 0.13185%
1
-61
1
-51
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1
-41
-31
1
-21
1
-1
1
1
+1
1
0.13185% 0.00312% 0.00002%
1
1
1
+21 +31 +41 +51 +61
Figure 7-11. Ideal Gaussian Distribution
Figure 7-11 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,
or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ–σ to µ+σ).
Depending on the specification, values listed in the typical column of Section 6.7 are represented in different
ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain
bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near
zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in
order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for OPAx991,
the typical input voltage offset is 125 µV, so 68.2% of all OPAx991 devices are expected to have an offset from
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–125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage less than ±500 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the OPAx991 family has a maximum offset voltage of
675 µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely
unlikely, TI assures that any unit with larger offset than 675 µV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the
6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be
an option as a wide guardband to design a system around. In this case, the OPAx991 family does not have
a maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.3 µV/°C in
Section 6.7, it can be calculated that the 6-σ value for offset voltage drift is about 1.8 µV/°C. When designing for
worst-case system conditions, this value can be used to estimate the worst possible offset across temperature
without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.10 Packages With an Exposed Thermal Pad
The OPAx991 family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature
an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically
conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad
must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not
allowed, and performance of the device is not assured when doing so.
7.3.11 Shutdown
The OPAx991S devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V– + 20 V.
The shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the
negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or
driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The
maximum voltage allowed at the SHDN pins is V– + 20 V. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The
typical enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a
high-impedance state. This architecture allows the OPAx991S family to operate as a gated amplifier, multiplexer,
or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load
to midsupply (VS / 2) is required. If using the OPAx991S without a load, the resulting turnoff time significantly
increases.
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7.4 Device Functional Modes
The OPAx991 has a single functional mode and is operational when the power-supply voltage is greater than 2.7
V (±1.35 V). The maximum power supply voltage for the OPAx991 is 40 V (±20 V).
The OPAx991S devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Section 7.3.11 for more information.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx991 family offers excellent DC precision and AC performance. These devices operate up to 40-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 4.5-MHz
bandwidth and high output drive. These features make the OPAx991 a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
Figure 8-1 shows the OPA991 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision
Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
5V
LOAD
+
OPA991
VOUT
–
ILOAD
RSHUNT
100 m
LM7705
RF
360 k
RG
7.5 k
Figure 8-1. OPA991 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
34
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
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8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1:
VOUT
ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2:
RSHUNT
VSHUNT _ MAX
100mV
1A
ILOAD _ MAX
100m:
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the OPA991 to produce an output voltage of 0 V to 4.9 V. The gain needed by the OPA991 to
produce the necessary output voltage is calculated using Equation 3:
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the OPA991 to 49 V/V.
Gain 1
RF
RG
(4)
Choosing R F as 360 kΩ, R G is calculated to be 7.5 kΩ. R F and R G were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.
8.2.1.3 Application Curves
5
Output (V)
4
3
2
1
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 8-2. Low-Side, Current-Sense, Transfer Function
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9 Power Supply Recommendations
The OPAx991 is specified for operation from 2.7 V to 40 V (±1.35 V to ±40 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 6.8.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section
10.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
•
•
36
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 10-1. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration
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OPA991, OPA2991, OPA4991
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SBOS969E – OCTOBER 2019 – REVISED MAY 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
The OPAx991 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers solution guide
Texas Instruments, AN31 Amplifier Circuit Collection application note
Texas Instruments, MUX-Friendly Precision Operational Amplifiers application brief
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
Texas Instruments, Op Amps With Complementary-Pair Input Stages application note
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA991
Click here
Click here
Click here
Click here
Click here
OPA2991
Click here
Click here
Click here
Click here
Click here
OPA4991
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
38
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Product Folder Links: OPA991 OPA2991 OPA4991
OPA991, OPA2991, OPA4991
www.ti.com
SBOS969E – OCTOBER 2019 – REVISED MAY 2021
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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OPA991, OPA2991, OPA4991
SBOS969E – OCTOBER 2019 – REVISED MAY 2021
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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Product Folder Links: OPA991 OPA2991 OPA4991
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2991IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O91F
OPA2991IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
26UT
OPA2991IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OP2991
OPA2991IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O91G
OPA2991IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2991P
OPA2991SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
GFF
OPA4991IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA4991D
OPA4991IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
OP4991PW
OPA4991IRUCR
ACTIVE
QFN
RUC
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I4F
OPA991IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O91V
OPA991IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1HB
OPA991SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O91S
OPA991TIDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1JE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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