PCA9515BDGKR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 PCA9515B Dual Bidirectional I2C Bus and SMBus Repeater 1 Features 2 Applications • • • • • • • 1 • • • • • • • • • Two-Channel Bidirectional Buffers I2C Bus and SMBus Compatible Support for I2C Standard Mode (100-kHz) and Fast Mode (400-kHz) Active-High Repeater-Enable Input Open-Drain I2C Input and Output 5.5-V Tolerant I2C Input and Output and Enable Input Support Mixed-Mode Signal Operation Lockup-Free Operation Accommodates Standard Mode, Fast Mode I2C Devices, and Multiple Masters Supports Arbitration and Clock Stretching Across Repeater Powered-Off High-Impedance I2C Pins Latch-Up Performance Exceeds 100-mA Per JESD 78, Class I ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) Servers Routers (Telecom Switching Equipment) Industrial Equipment Products with Many I2C Slaves and Long PCB Traces 3 Description The PCA9515B is a BiCMOS dual bidirectional buffer integrated circuit intended for I2C bus and SMBus applications. The device contains two identical bidirectional open-drain buffer circuits that enables I2C and similar bus systems to be extended (or add slaves) without degrading system performance. The dual bidirectional I2C buffer is operational at 2.3 V to 3.6 V VCC. The PCA9515B buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, while retaining all the operating modes and features of the I2C system. The device allows two buses, of 400-pF bus capacitance, to be connected in an I2C application. Device Information(1) PART NUMBER PCA9515B PACKAGE VSSOP (8) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VCC VCC VCC VCC I2C or SMBus Master (e.g. Processor) EN SCL0 SCL1 PCA9515B SDA0 I2C Slave Devices SDA1 GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 5 5 5 6 Absolute Maximum Ratings ..................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 9 8.3 Feature Description................................................... 9 8.4 Device Functional Modes........................................ 10 9 Application and Implementation ........................ 11 9.1 Application Information............................................ 11 9.2 Typical Application ................................................. 11 10 Power Supply Recommendations ..................... 12 11 Layout................................................................... 13 11.1 Layout Guidelines ................................................. 13 11.2 Layout Example .................................................... 13 12 Device and Documentation Support ................. 14 12.1 12.2 12.3 12.4 12.5 Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 14 13 Mechanical, Packaging, and Orderable Information ........................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2013) to Revision B Page • Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1 • Deleted the ordering information. See POA at the end of the datasheet............................................................................... 1 Changes from Original (March 2012) to Revision A • 2 Page Updated the VOL and VOL - VILC specifications........................................................................................................................ 5 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B PCA9515B www.ti.com SCPS232B – MARCH 2012 – REVISED MARCH 2016 5 Pin Configuration and Functions DGK Package 8-Pin VSSOP Top View NC 1 8 VCC SCL0 SDA0 2 3 7 6 SCL1 SDA1 GND 4 5 EN NC - No internal connection Pin Functions PIN NO. NAME I/O DESCRIPTION 1 NC — No internal connection 2 SCL0 I/O Serial clock bus 0 3 SDA0 I/O Serial data bus 0 4 GND — Supply ground 5 EN I 6 SDA1 I/O Serial data bus 1 7 SCL1 I/O Serial clock bus 1 8 VCC — Supply power Active-high repeater enable input Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B 3 PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VCC (1) Supply voltage (2) MIN MAX UNIT –0.5 7 V –0.5 7 V –0.5 7 V VI Enable input voltage VI/O I2C bus voltage (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA 150 °C Tstg Storage temperature (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (2) 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions VCC VIH VIL MAX 2.3 3.6 0.7 × VCC 5.5 2 5.5 SDA and SCL inputs –0.5 0.3 × VCC EN input –0.5 0.8 –0.5 0.4 SDA and SCL inputs High-level input voltage (1) EN input Low-level input voltage (1) VILc SDA and SCL low-level input voltage contention IOL Low-level output current TA Operating free-air temperature (1) MIN Supply voltage VCC = 2.3 V 6 VCC = 3 V 6 –40 85 UNIT V V V V mA °C VIL specification is for the EN input and the first low level seen by the SDAx and SCLx lines. VILc is for the second and subsequent low levels seen by the SDAx and SCLx lines. VILc must be at least 70 mV below VOL. 6.4 Thermal Information PCA9515B THERMAL METRIC (1) DGK (VSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance (2) 170.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 62.9 °C/W RθJB Junction-to-board thermal resistance 91.6 °C/W ψJT Junction-to-top characterization parameter 9.5 °C/W ψJB Junction-to-board characterization parameter 90.2 °C/W (1) (2) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B PCA9515B www.ti.com SCPS232B – MARCH 2012 – REVISED MARCH 2016 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS Input diode clamp voltage –1.2 2.3 V to 3.6 V 0.47 2.3 V to 3.6 V 120 Both channels high, SDAx = SCLx = VCC 2.7 V 0.5 3 3.6 V 0.5 3 Both channels low, SDA0 = SCL0 = GND and SDA1 = SCL1 = open; or SDA0 = SCL0 = open and SDA1 = SCL1 = GND 2.7 V 1 4 3.6 V 1 4 In contention, SDAx = SCLx = GND 2.7 V 1 4 3.6 V 1 Low-level output voltage VOL – VILc Low-level input voltage below low-level output voltage SDAx, guaranteed by design SCLx II SDAx, VI = 3.6 V SCLx VI = 0.2 V Input current V 0.52 0.6 V mV mA 4 3 2.3 V to 3.6 V –10 Leakage current SDAx, VI = 3.6 V SCLx VI = GND EN = L or H 0V II(ramp) Leakage current during power up SDAx, VI = 3.6 V SCLx EN = L or H 0 V to 2.3 V Cin Input capacitance μA ±1 VI = 0.2 V Ioff (1) UNIT ±1 VI = VCC EN MAX 2.3 V to 3.6 V VOL Quiescent supply current MIN TYP (1) II = –18 mA SDAx, IOL = 20 μA or 6 mA SCLx ICC VCC –20 0.5 μA 0.5 μA 1 EN 3.3 V 7 9 SDAx, VI = 3 V or GND EN = H SCLx 3.3 V 7 9 MAX pF All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C. 6.6 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) tsu Setup time, EN↑ before Start condition th Hold time, EN↓ after Stop condition VCC MIN 2.5 V ± 0.2 V 100 3.3 V ± 0.3 V 100 2.5 V ± 0.2 V 130 3.3 V ± 0.3 V 100 UNIT ns ns 6.7 Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) tPZL Propagation delay time (2) SDA0, SCL0 or SDA1, SCL1 SDA1, SCL1 or SDA0, SCL0 tPLZ ttHL Output transition time (2) (SDAx, SCLx) ttLH (1) (2) 80% 20% 20% 80% MIN TYP (1) 2.5 V ± 0.2 V 45 82 130 3.3 V ± 0.3 V 45 68 120 2.5 V ± 0.2 V 33 113 190 3.3 V ± 0.3 V 33 102 180 VCC 2.5 V ± 0.2 V MAX UNIT ns 57 3.3 V ± 0.3 V 58 2.5 V ± 0.2 V 148 3.3 V ± 0.3 V 147 ns All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C. Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B 5 PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 www.ti.com 6.8 Typical Characteristics 0.55 Lower-Limit Output Voltage (V) Lower-Limit Output Voltage (V) 0.54 0.52 0.5 0.48 0.46 VCC = 2.3 V VCC = 3.3 V VCC = 5 V 0.44 0 0.001 0.002 0.003 0.004 0.005 Lower-Limit Output Current (A) 0.006 6 0.5 0.475 0.45 0.425 0.4 0.0002 D004 Figure 1. Output Low Voltage (VOL) vs. Output Low Current (IOL) for SCL0 at Different VCC TA = -40qC TA = 25qC TA = 85qC 0.525 0.001 Lower-Limit Output Current (mA) 0.006 D003 Figure 2. Output Low Voltage (VOL) vs. Output Low Current (IOL) for SCL0 at Different Temperatures for VCC= 5 V Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B PCA9515B www.ti.com SCPS232B – MARCH 2012 – REVISED MARCH 2016 7 Parameter Measurement Information VCC VIN VCC VOUT PULSE GENERATOR RL = 1.35 kΩ S1 DUT GND CL = 50 pF (see Note B) RT (see Note A) TEST S1 tPLZ/tPZL VCC TEST CIRCUIT FOR OPEN-DRAIN OUTPUT Input VCC 1.5 V 1.5 V 0V tPZL Output tPLZ 80% 1.5 V 1.5 V 20% 20% 80% ttHL VCC VOL ttLH VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES A. RT termination resistance should be equal to ZOUT of pulse generators. B. CL includes probe and jig capacitance. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 3. Test Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B 7 PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 www.ti.com 8 Detailed Description 8.1 Overview The PCA9515B is a BiCMOS dual bidirectional buffer integrated circuit intended for I2C bus and SMBus applications. The device contains two identical bidirectional open-drain buffer circuits that enables I2C and similar bus systems to be extended without degrading system performance. This device enables I2C and similar bus systems to be extended (and add more slaves) without degradation of performance. The dual bidirectional I2C buffer is operational at 2.3 V to 3.6 V VCC. The PCA9515B buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, while retaining all the operating modes and features of the I2C system. The device allows two buses, of 400-pF bus capacitance, to be connected in an I2C application. The I2C bus capacitance limit of 400 pF restricts the number of slave devices and bus length. Using the PCA9515B, a system designer can capacitively isolate two halves of a bus, thus accommodating more I2C devices and longer trace lengths. The PCA9515B has an active-high enable (EN) input with an internal pull-up. This allows users to select when the repeater is active and isolate malfunctioning slaves on power-up reset. States should never be changed during an I2C operation. Disabling during a bus operation will hang the bus and enabling part way through a bus cycle may confuse the I2C parts being enabled. The EN input should only change state when the global bus and the repeater port are in an idle state to prevent system failures. The PCA9515B can also be used to operate two buses, one at 5 V interface levels and the other at 3.3 V interface levels. The buses may also function at 400-kHz or 100-kHz operating frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be isolated if the operation of the 400-kHz bus is required. If the master is running at 400-kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater. The low level outputs for each internal buffer are approximately 0.5 V; however, the input voltage of each internal buffer must be 70 mV or more below the low level output when the output is driven low internally. This prevents a lockup condition from occurring when the input low condition is released. Two or more PCA9515B devices cannot be used in series. Since there is no direction pin, different valid lowvoltage levels are used to avoid lockup conditions between the input and the output of each repeater. A valid low, applied at the input of a PCA9515B, is propagated as a buffered low with a higher value on the enabled outputs. When this buffered low is applied to another PCA9515B-type device in series, the second device does not recognize it as a valid low and does not propagate it as a buffered low. The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming active until VCC is at a valid level (VCC = 2.3 V). As with the standard I2C system, pullup resistors are required to provide the logic high levels on the buffered bus. The PCA9515B has standard open-collector configuration of the I2C bus. The size of the pullup resistors depend on the system; however, each side of the repeater must have a pullup resistor. The device is designed to work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices only specify a 3 mA termination current in a generic I2C system where Standard Mode devices and multiple masters are possible. Under certain conditions, high termination currents can be used. 8 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B PCA9515B www.ti.com SCPS232B – MARCH 2012 – REVISED MARCH 2016 8.2 Functional Block Diagram VCC 8 PCA9515B SDA0 SCL0 3 6 2 7 SDA1 SCL1 Pullup Resistor EN 5 4 Figure 4. Logic Diagram (Poisitve Logic) 8.3 Feature Description 8.3.1 Two-Channel Bidirectional Buffer The PCA9515B is a two-channel bidirectional buffer for open-drain applications like I2C and SMBus. 8.3.2 Bidirectional Voltage-Level Translation The PCA9515B allows bidirectional voltage-level translation (up-translation and down-translation) between low voltages (down to 2.3 V) and higher voltages (up to 5.5 V). 8.3.3 Active-High Enable Input The PCA9515B has an active-high enable (EN) input with an internal pull-up to VCC. The enable input needs to be pulled to GND to disable the PCA9515B and isolate the I2C buses. Pulling-up the enable pin or floating the enable pin causes the PCA9515B to turn on and buffer the I2C bus. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B 9 PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 www.ti.com 8.4 Device Functional Modes The PCA9515B has an active-high enable (EN) input with an internal pull-up to VCC, which allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It should never change state during an I2C operation, because disabling during a bus operation my hang the bus, and enabling part way through the bus cycles could confuse the I2C parts being enabled. The EN input should only change state when the global bus and repeater port are in the idle state to prevent system failures. Table 1 lists the PCA9515B functions. Table 1. Function Table 10 INPUT EN FUNCTION L Outputs disabled H SDA0 = SDA1, SCL0 = SCL1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B PCA9515B www.ti.com SCPS232B – MARCH 2012 – REVISED MARCH 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The PCA9515B is typically used to buffer an I2C signal, isolating capacitance from two sides of the bus. This allows for longer traces and cables, and a more robust I2C communication. Typical Application section describes how the PCA9515B may be used to isolate a standard mode and fast mode I2C bus, to allow for faster communications when required, but maintaining compatibility with the slower standard mode slave device. It is critical to keep the VOL and VIL requirements in mind when designing with buffers, especially when using multiple buffers/translators on the same node. Care must be taken to not violate the VIL requirement of a buffer, otherwise I2C communication errors will occur. An example of this would be a buffer with a VOL of ~0.5 V, and a device requires a VIL of less than 0.4 V. Such a connection would result in the slave device being unable to recognize the output low signal as a valid low. 9.2 Typical Application A typical application is shown in Figure 5. In this example, the system master is running on a 3.3 V I2C bus, while the slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated. If the slave bus is isolated (by pulling the EN pin low), the master bus can run at 400 kHz. Master devices can be placed on either bus, the PCA9515B does not care which side the master is on. Decoupling capacitors are required, but are not shown in Figure 5 for simplicity. 3.3 V 5V SDA SDA0 SDA1 SDA SCL SCL0 SCL1 SCL PCA9515B I2C BUS MASTER 400 kHz I2C BUS SLAVE 100 kHz EN BUS 0 BUS 1 Figure 5. Typical Application 9.2.1 Design Requirements Table 2 lists the design requirements. Table 2. Design Requirements PARAMETER VALUE Input-side I2C signal 3.3 V 2 Output-side I C signal 5V Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B 11 PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 www.ti.com 9.2.2 Detailed Design Procedure The PCA9515B is 5.5 V tolerant, so it does not require any additional circuitry to translate between the different bus voltages. When one side of the PCA9515B is pulled low by a device on the I2C bus, a CMOS hysteresis-type input detects the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go low. The side driven low by the PCA9515B typically is at VOL = 0.5 V. Figure 6 and Figure 7 show the waveforms that are seen in a typical application. If the bus master in Figure 5 writes to the slave through the PCA9515B, Bus 0 has the waveform shown in Figure 6. The waveform looks like a normal I2C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line (SDA) while the slave pulls it low through the PCA9515B. Because the VOL of the PCA9515B typically is around 0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the data line. On the Bus 1 side of the PCA9515B, the clock and data lines have a positive offset from ground equal to the VOL of the PCA9515B. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very close to ground in the example. 9.2.3 Application Curves 9th Clock Pulse SCL SDA VOL of Master VOL of PCA9515B Figure 6. Bus 0 Waveforms 9th Clock Pulse SCL SDA VOL of PCA9515B VOL of Slave Figure 7. Bus 1 Waveforms 10 Power Supply Recommendations For VCC, a 2.3 V to 3.6 V power supply is required. Standard decoupling capacitors are recommended. These capacitors typically range from 0.1 µF to 1 µF, but the ideal capacitance depends on the amount of noise from the power supply. 12 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B PCA9515B www.ti.com SCPS232B – MARCH 2012 – REVISED MARCH 2016 11 Layout 11.1 Layout Guidelines For printed circuit board (PCB) layout of the PCA9515B, common PCB layout practices should be followed. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a small capacitor to filter out high-frequency ripple. These decoupling capacitors should be placed as close to the VCC pin of PCA9515B as possible. The layout example shown in Figure 8 shows a 4 layer board, which is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and one to power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is connected electrically to the internal layer on the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board. This routing and via is not necessary if VCC and GND are both full planes as opposed to the partial planes depicted. 11.2 Layout Example Via to VCC Plane Via to GND Plane Via to Bottom layer Decoupling Capacitor VC C D N G NC 8 1 SCL0 2 VCC 7 SCL1 PCA9515B SDA0 3 6 SDA1 GND 4 5 EN Figure 8. Layout Schematic Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B 13 PCA9515B SCPS232B – MARCH 2012 – REVISED MARCH 2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • I2C Bus Pullup Resistor Calculation, SLVA689 • Maximum Clock Frequency of I2C Bus Using Repeaters, SLVA695 • Introduction to Logic, SLVA700 • Understanding the I2C Bus, SLVA704 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: PCA9515B PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) PCA9515BDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (7SE, 7SF) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of