PCA9534A
SCPS141J – SEPTEMBER 2006 – REVISEDPCA9534A
MARCH 2021
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
www.ti.com
PCA9534A Remote 8-BIT I2C and SMBus Low-Power I/O Expander With Interrupt
Output And Configuration Registers
1 Features
2 Description
•
•
•
•
This 8-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC operation.
It provides general-purpose remote I/O expansion for
most microcontroller families via the I2C interface
[serial clock (SCL), serial data (SDA)].
•
•
•
•
•
•
•
•
•
•
The PCA9534A consists of one 8-bit configuration
(input or output selection), input port, output port,
and polarity inversion (active high or active low)
register. At power on, the I/Os are configured as
inputs. However, the system master can enable the
I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output
is kept in the corresponding input or output register.
The polarity of the input port register can be inverted
with the polarity inversion register. All registers can be
read by the system master.
The system master can reset the PCA9534A in the
event of a timeout or other improper operation by
utilizing the power-on reset feature, which puts the
registers in their default state and initializes the I2C/
SMBus state machine.
The PCA9534A open-drain interrupt ( INT) output
is activated when any input state differs from its
corresponding input port register state and is used to
indicate to the system master that an input state has
changed.
Device Information
PART NUMBER
PCA9534A
(1)
14
4
13
5
12
6
11
7
10
8
9
4.00 mm × 4.00 mm
QFN (16)
3.00 mm × 3.00 mm
A1
A0
VCC
S DA
VCC
VQFN (16)
RGT PACKAGE
(TOP VIEW)
A2 1
16 15 14 13
12
P0 2
11
P1 3
10
P7
P2 4
9
P6
5
6
7
8
P5
3
VCC
SDA
SCL
INT
P7
P6
P5
P4
P4
15
6.20 mm × 5.30 mm
SDA
A1
16
2
P3
1
GND
A0
A1
A2
P0
P1
P2
P3
GND
BODY SIZE (NOM)
SSOP (16)
For all available packages, see the orderable addendum at
the end of the datasheet.
RGV PACKAGE
(TOP VIEW)
A0
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
PACKAGE(1)
SCL
INT
A2
P0
P1
P2
16 15 14 13
12 SCL
2
11 INT
3
10 P7
1
9 P6
4
5 6 7
8
P3
GND
P4
P5
•
•
•
Low standby current consumption of 1 μA max
I2C to Parallel port expander
Open-drain active-low interrupt output
Operating power-supply voltage range of 2.3 V to
5.5 V
5-V Tolerant I/O ports
400-kHz Fast I2C bus
Three hardware address pins allow up to eight
devices on the I2C/SMBus
Allows up to 16 devices on the I2C/SMBus when
used in conjunction with the PCA9534
See Section 5 for I2C Expander offerings
Input and output configuration register
Polarity inversion register
Internal power-on reset
Power-up with all channels configured as Inputs
No glitch on power-up
Noise filter on SCL and SDA inputs
Latched outputs with high-current drive maximum
capability for directly driving LEDs
Latch-up performance exceeds 100 mA Per JESD
78, Class II
ESD protection exceeds JESD 22
– 2000-V Human-body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-device model (C101)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
Submit
Document
Feedback
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: PCA9534A
1
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Description (Continued)..................................................3
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Resistance Characteristics........................... 6
7.5 Electrical Characteristics.............................................7
7.6 I2C Interface Timing Requirements.............................8
7.7 Switching Characteristics............................................8
7.8 Typical Characteristics................................................ 9
8 Parameter Measurement Information.......................... 12
9 Detailed Description......................................................15
9.1 Functional Block Diagram......................................... 15
9.2 Device Functional Modes..........................................16
9.3 Programming............................................................ 17
10 Application Information Disclaimer........................... 23
10.1 Application Information........................................... 23
11 Power Supply Recommendations..............................25
11.1 Power-On Reset Requirements.............................. 25
12 Device and Documentation Support..........................27
12.1 Trademarks............................................................. 27
12.2 Electrostatic Discharge Caution..............................27
12.3 Glossary..................................................................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
3 Revision History
Changes from Revision I (June 2014) to Revision J (March 2021)
Page
• Moved the "Storage temperature range" to the Absolute Maximum Ratings .................................................... 6
• Moved the "Package thermal impedance" to the Thermal Resistance Characteristic .......................................6
• Changed the VIH High-level input voltage (SDL, SDA) Max value From: 5.5 V To: VCC in the Recommended
Operating Conditions ......................................................................................................................................... 6
• Changed the VIH High-level input voltage (A0, A1, A2, P7–P0) MIN value From: 2 V To: VCC in the
Recommended Operating Conditions ................................................................................................................6
• Changed the VIL Low-level input voltage (A0, A1, A2, P7–P0) MAX value From: 0.8 V To: 0.3 x VCC in the
Recommended Operating Conditions ................................................................................................................6
• Added the Thermal Resistance Characteristics .................................................................................................6
• Changed the VPORR row in the Electrical Characteristics .................................................................................. 7
• Added the VPORF row in the Electrical Characteristics .......................................................................................7
• Changed the ICC Standby mode values in the Electrical Characteristics ...........................................................7
• Changed the Ci SCL Max value From: 5 pF To: 8 pF in the Electrical Characteristics ......................................7
• Changed the Cio SDA Max value From:6.5 pF To: 9.5 pF in the Electrical Characteristics ............................... 7
• Changed the tpv Output data valid MAX values From: 200 ns To 350 ns in the Swirtching Characteristics ...... 8
• Changed the Typical Characteristics graphs...................................................................................................... 9
• Changed the Power Supply Recommendations .............................................................................................. 25
Changes from Revision H (June 2010) to Revision I (June 2014)
Page
• Added Interrupt Errata section. ........................................................................................................................17
• Deleted the 100 kΩ resistor at VCC ..................................................................................................................23
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
4 Description (Continued)
The PCA9534A and PCA9534 are identical, except for their fixed I2C address. This allows for up to 16 of these
devices (8 of each) on the same I2C bus.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9534A can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs. It has low current
consumption.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus.
The PCA9534A is pin-to-pin and I2C address compatible with the PCF8574A. However, software changes are
required due to the enhancements in the PCA9534A over the PCF8574A.
The PCA9534A is a low-power version of the PCA9554A. The only difference between the PCA9534A and
PCA9554A is that the PCA9534A eliminates an internal I/O pullup resistor, which dramatically reduces power
consumption in the standby mode when the I/Os are held low.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
3
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
5 Device Comparison Table
4
DEVICE
MAX
FREQUE
NCY
I2C
ADDRES
S
VCC
RANGE
NO. OF
GPIOs
INTERRU
PT
OUTPUT
RESET
INPUT
CONFIGURATIO
N
REGISTERS
5-V
TOLERA
NT
PUSHPULL
I/O TYPE
OPENDRAIN
I/O TYPE
TCA6408
400
0100 00x
1.65 to 5.5
8
Yes
Yes
Yes
Yes
Yes
No
Power on reset, tf (fall time) > 100 ms and
tr (ramp time) < 10 ms
TCA6408
400
0100 00x
1.65 to 5.5
8
Yes
Yes
Yes
Yes
Yes
No
Unrestricted power on reset ramp/fall time.
Both tf (fall time) and TRT (ramp time) can
be between 0.1 ms and 2000 ms
TCA6416
400
0100 00x
1.65 to 5.5
16
Yes
Yes
Yes
Yes
Yes
No
Power on reset, tf (fall time) > 100 ms and
TRT (ramp time) < 10 ms
TCA6416
A
400
0100 00x
16
Yes
Yes
Yes
Yes
Yes
No
Unrestricted power on reset ramp/fall time.
Both tf (fall time) and TRT (ramp time) can
be between 0.1 ms and 2000ms
TCA6424
400
0100 00x
1.65 to 5.5
24
Yes
Yes
Yes
Yes
Yes
No
Power on reset, tf (fall time) > 100 ms and
TRT (ramp time) < 10 ms
TCA9535
400
0100 xxx
1.65 to 5.5
16
Yes
No
Yes
Yes
Yes
No
TCA9539
400
1110 1xx
1.65 to 5.5
16
Yes
Yes
Yes
Yes
Yes
No
TCA9555
400
0100 xxx
1.65 to 5.5
16
Yes
No
Yes
Yes
Yes
No
Yes
P0 bit
1.65 to 5.5
COMMENT
PCA6107
400
0011 xxx
2.3 to 5.5
8
Yes
Yes
Yes
Yes
Yes
P1―P7
bits
PCA9534
400
0100 xxx
2.3 to 5.5
8
Yes
No
Yes
Yes
Yes
No
PCA9534 has a different slave address as
the PCA9534A, allowing up to 16 devices
'9534 type devices on the same I2C bus
PCA9534
A
400
0111 xxx
2.3 to 5.5
8
Yes
No
Yes
Yes
Yes
No
PCA9534A has a different slave address
as the PCA9534, allowing up to 16 devices
'9534 type devices on the same I2C bus
PCA9535
400
0100 xxx
2.3 to 5.5
16
Yes
No
Yes
Yes
Yes
No
2.3 to 5.5
4
No
No
Yes
Yes
Yes
No
No
1000 001
One open drain output; eight push pull
outputs
PCA9536
400
PCA9538
400
1110 0xx
2.3 to 5.5
8
Yes
Yes
Yes
Yes
Yes
PCA9539
400
1110 1xx
2.3 to 5.5
16
Yes
Yes
Yes
Yes
Yes
No
PCA9554
400
0100 xxx
2.3 to 5.5
8
Yes
No
Yes
Yes
Yes
No
PCA9554
A
400
0111 xxx
2.3 to 5.5
8
Yes
No
Yes
Yes
Yes
No
PCA9555
400
0100 xxx
2.3 to 5.5
16
Yes
No
Yes
Yes
Yes
No
PCA9557
400
0011 xxx
2.3 to 5.5
8
No
Yes
Yes
Yes
Yes
Yes
PCF8574
400
0100 xxx
2.5 to 6.0
8
Yes
No
No
Yes
Yes
No
PCA8574 has a different slave address as
the PCA8574A, allowing up to 16 devices
'9534 type devices on the same I2C bus
PCF8574
A
400
0111 xxx
2.5 to 6.0
8
Yes
No
No
Yes
Yes
No
PCA8574A has a different slave address
as the PCA8574, allowing up to 16 devices
'9534 type devices on the same I2C bus
PCF8575
400
0100 xxx
2.5 to 5.5
16
Yes
No
No
Yes
Yes
No
PCF8575
C
400
0100 xxx
4.5 to 5.5
16
Yes
No
No
Yes
No
Yes
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
6 Pin Configuration and Functions
14
4
13
5
12
6
11
7
10
8
9
A1
A0
VCC
S DA
SDA
RGT PACKAGE
(TOP VIEW)
A2 1
16 15 14 13
12
P0 2
11
INT
P1 3
10
P7
P2 4
9
P6
5
6
7
8
SCL
16 15 14 13
12 SCL
2
11 INT
3
10 P7
1
A2
P0
P1
P2
9 P6
4
5 6 7
8
P3
GND
P4
P5
3
VCC
SDA
SCL
INT
P7
P6
P5
P4
P5
15
P4
16
2
GND
1
P3
A0
A1
A2
P0
P1
P2
P3
GND
VCC
A1
RGV PACKAGE
(TOP VIEW)
A0
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Table 6-1. Pin Functions
PIN
NAME
QSOP (DBQ),
SOIC (DW),
QFN (RGT) AND
SSOP (DB),
QFN (RGV)
TSSOP (PW), AND
TVSOP (DGV)
DESCRIPTION
A0
1
15
Address input. Connect directly to VCC or ground.
A1
2
16
Address input. Connect directly to VCC or ground.
A2
3
1
Address input. Connect directly to VCC or ground.
P0
4
2
P-port input/output. Push-pull design structure.
P1
5
3
P-port input/output. Push-pull design structure.
P2
6
4
P-port input/output. Push-pull design structure.
P3
7
5
P-port input/output. Push-pull design structure.
GND
8
6
Ground
P4
9
7
P-port input/output. Push-pull design structure.
P5
10
8
P-port input/output. Push-pull design structure.
P6
11
9
P-port input/output. Push-pull design structure.
P7
12
10
P-port input/output. Push-pull design structure.
INT
13
11
Interrupt output. Connect to VCC through a pullup resistor.
SCL
14
12
Serial clock bus. Connect to VCC through a pullup resistor.
SDA
15
13
Serial data bus. Connect to VCC through a pullup resistor.
VCC
16
14
Supply voltage
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
5
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6
UNIT
V
range(2)
–0.5
6
V
–0.5
6
V
VI
Input voltage
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
±20
mA
50
mA
–50
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
IOL
Continuous output low current
VO = 0 to VCC
IOH
Continuous output high current
VO = 0 to VCC
ICC
Tstg
(1)
(2)
Continuous current through GND
–250
Continuous current through VCC
160
Storage temperature range
–65
mA
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
MIN
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
VCC
A2–A0, P7–P0
0.7 × VCC
5.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, P7–P0
–0.5
0.3 × VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
UNIT
V
V
V
IOH
High-level output current
P7–P0
–10
mA
IOL
Low-level output current
P7–P0
25
mA
TA
Operating free-air temperature
85
°C
–40
7.4 Thermal Resistance Characteristics
PCA9535
THERMAL METRIC(1)
R θJA
(1)
6
Junction-to-ambient
thermal resistance
DB
(SSOP)
DBQ
(SSOP)
DVG
(TVSOP)
DW
(SOIC)
PW
(TSSOP)
RGT
(VQFN)
RVE
(VQFN)
16 Pins
16 Pins
16 Pins
16 Pins
16 Pins
16 Pins
16 Pins
82
90
86
92.2
122
63.2
51
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPORR
Power-on reset voltage, VCC rising
VI = VCC or GND, IO = 0
VPORF
Power-on reset voltage, VCC falling
VI = VCC or GND, IO = 0
IOH = –8 mA
VOH
P-port high-level output voltage(2)
IOH = –10 mA
SDA
VOL = 0.4 V
VOL = 0.5 V
IOL
P port(3)
VOL = 0.7 V
INT
II
SCL, SDA
A2–A0
VCC
MIN
2.3 V to 5.5 V
–1.2
0.75
2.3 V
1.8
3V
2.6
4.5 V
4.1
4.75 V
4.1
2.3 V
1.7
3V
2.5
3
8
8
10
3V
8
14
4.5 V
8
17
4.75 V
8
35
2.3 V
10
13
3V
10
19
4.5 V
10
24
4.75 V
10
45
VOL = 0.4 V
2.3 V to 5.5 V
3
10
VI = VCC or GND
2.3 V to 5.5 V
VI = GND
2.3 V to 5.5 V
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 400 kHz
Operating mode
CI
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 100 kHz
Cio
(1)
(2)
(3)
SCL
SDA
P port
V
2.3 V
P port
VI = GND, IO = 0,
I/O = inputs, fscl = 0 kHz
One input at VCC – 0.6 V,
Other inputs at VCC or GND
All LED I/Os at VI = 4.3 V,
fscl = 0 kHz
VI = VCC or GND
VIO = VCC or GND
V
1
4
IIL
UNIT
V
2.3 V to 5.5 V
2.3 V to 5.5 V
Additional current in standby mode
1.5
4
VI = VCC
ΔICC
1.2
4.75 V
P port
Standby mode
MAX
4.5 V
IIH
ICC
TYP(1)
mA
±1
±1
1
μA
–1
μA
5.5 V
104
175
3.6 V
50
90
2.7 V
20
65
5.5 V
60
150
3.6 V
15
40
2.7 V
8
20
5.5 V
1.5
8.7
3.6 V
0.9
4
2.7 V
0.6
3
2.3 V to 5.5 V
μA
μA
1.5
mA
5.5 V
2.3 V to 5.5 V
2.3 V to 5.5 V
1
4
8
5.5
9.5
8
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA.
Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7–P0) must be limited to a maximum current of 200 mA.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
7
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
7.6 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 8-1)
STANDARD MODE
I2C BUS
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
tsdh
I2C
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time
tbuf
I2C
tsts
I2C start or repeated start condition setup
tsth
tsps
clock high time
MAX
MIN
MAX
0
100
0
400
4
0.6
μs
1.3
μs
50
50
100
0
input fall time
10-pF to 400-pF bus
bus free time between stop and start
kHz
4.7
250
serial-data hold time
UNIT
MIN
ns
ns
0
ns
1000
20 + 0.1Cb (1)
300
ns
300
20 + 0.1Cb
(1)
300
ns
300
20 + 0.1Cb (1)
300
ns
4.7
1.3
μs
4.7
0.6
μs
I2C start or repeated start condition hold
4
0.6
μs
I2C stop condition setup
4
0.6
μs
50
ns
tvd(data) Valid data time
SCL low to SDA output valid
300
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.3
Cb
I2C bus capacitive load
(1)
FAST MODE
I2C BUS
3.45
0.1
400
0.9
μs
400
ns
Cb = total capacitive of one bus in pF
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 8-2 and Figure 8-3)
PARAMETER
tiv
8
Interrupt valid time
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
STANDARD MODE
I2C BUS
MIN
FAST MODE
I2C BUS
MAX
MIN
4
UNIT
MAX
4
μs
4
4
μs
350
350
ns
tir
Interrupt reset delay time
SCL
INT
tpv
Output data valid
SCL
P7–P0
tps
Input data setup time
P port
SCL
100
100
ns
tph
Input data hold time
P port
SCL
1
1
μs
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
7.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
40
2.2
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
32
Vcc = 5.5V
28
24
20
16
12
8
1.8
Vcc = 5.5V
1.4
1.2
1
0.8
0.6
0.4
-15
10
35
TA - Temperature (°C)
60
0.2
-40
85
-15
D001
Figure 7-1. Supply Current vs Temperature for Different Supply
Voltage (VCC)
10
35
TA - Temperature (°C)
60
85
D002
Figure 7-2. Standby Supply Current vs Temperature for
Different Supply Voltage (VCC)
30
30
-40qC
25qC
85qC
-40qC
25qC
85qC
25
IOL - Sink Current (mA)
25
ICC - Supply Current (µA)
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
1.6
4
0
-40
20
15
10
5
20 VCC = 1.65 V
15
10
5
0
1.5
0
2
2.5
3
3.5
4
4.5
VCC - Supply Voltage (V)
5
5.5
0
0.1
D003
Figure 7-3. Supply Current vs Supply Voltage for Different
Temperature (TA)
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D004
Figure 7-4. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.65 V
60
35
25
IOL - Sink Current (mA)
-40qC
25qC
85qC
30
IOL - Sink Current (mA)
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
2
ICC - Supply Current (µA)
ICC - Supply Current (µA)
36
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
VCC = 1.8 V
20
15
10
50
-40qC
25qC
85qC
40
VCC = 2.5 V
30
20
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
0
D005
Figure 7-5. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.8 V
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D006
Figure 7-6. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 2.5 V
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
9
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
7.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
70
80
-40qC
25qC
85qC
50
VCC = 3.3 V
40
30
20
10
60
VCC = 5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
D007
Figure 7-7. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 3.3 V
0.6
0.7
D009
Figure 7-8. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 5 V
300
90
70
VOL - Output Low Voltage (V)
-40qC
25qC
85qC
80
IOL - Sink Current (mA)
-40qC
25qC
85qC
70
IOL - Sink Current (mA)
IOL - Sink Current (mA)
60
VCC = 5.5 V
60
50
40
30
20
1.8 V, 1 mA
1.8 V, 10 mA
3.3 V, 1mA
250
3.3 V, 10 mA
5 V, 1 mA
5 V, 10 mA
200
150
100
50
10
0
-40
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
Figure 7-9. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 5.5 V
60
85
D011
25
-40qC
25qC
85qC
IOH - Source Current (mA)
IOH - Source Current (mA)
10
35
TA - Temperature (°C)
Figure 7-10. II/O Low Voltage vs Temperature for Different VCC
and IOL
20
15
VCC = 1.65 V
10
5
0
-40qC
25qC
85qC
20
VCC = 1.8 V
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
D012
Figure 7-11. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.65 V
10
-15
D010
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D013
Figure 7-12. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.8 V
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
7.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
60
40
IOH - Source Current (mA)
35
IOH - Source Current (mA)
-40qC
25qC
85qC
30
VCC = 2.5 V
25
20
15
10
0
VCC = 3.3 V
30
20
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
D014
Figure 7-13. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 2.5 V
0.6
0.7
D015
Figure 7-14. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 3.3 V
70
80
-40qC
25qC
85qC
50
-40qC
25qC
85qC
70
IOH - Source Current (mA)
60
IOH - Source Current (mA)
40
10
5
VCC = 5 V
40
30
20
10
60
VCC = 5.5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D017
Figure 7-16. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5.5 V
400
350
0.1
D016
Figure 7-15. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5 V
18
1.65 V, 10 mA
2.5 V, 10 mA
3.6 V, 10 mA
5 V, 10 mA
5.5 V, 10 mA
15
1.65 V
1.8 V
2.5 V
3.3 V
5V
5.5 V
300
Delta ICC (µA)
VCC-VOH - I/O High Voltage (mV)
50
-40qC
25qC
85qC
250
200
150
9
6
3
100
50
-40
12
-15
10
35
TA - Temperature (°C)
60
85
0
-40
D018
Figure 7-17. VCC – VOH Voltage vs Temperature for Different VCC
-15
10
35
TA - Temperature (°C)
60
85
D019
Figure 7-18. Δ ICC vs Temperature for Different VCC (VI = VCC –
0.6 V)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
11
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
8 Parameter Measurement Information
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
tPHL
ticf
tbuf
tsts
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 8-1. I2C Interface Load Circuit And Voltage Waveforms
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
1
1 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
SCL
0.3 × VCC
Data 2
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
View A−A
View B−B
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 8-2. Interrupt Load Circuit And Voltage Waveforms
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
13
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
500 W
Pn
DUT
2 × VCC
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P0
A
P3
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P0
A
tps
P3
0.3 × VCC
tph
0.7 × VCC
Pn
0.3 × VCC
READ MODE (R/W = 1)
A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 8-3. P-Port Load Circuit And Voltage Waveforms
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
9 Detailed Description
9.1 Functional Block Diagram
INT
A0
A1
A2
SCL
SDA
13
Interrupt
Logic
LP Filter
1
2
P7−P0
3
14
15
I2C Bus
Control
Input
Filter
Shift
Register
8 Bits
I/O
Port
Write Pulse
VCC
GND
16
8
Power-On
Reset
Read Pulse
A. Pin numbers shown are for DB, DBQ, DGV, DW, or PW package.
B. All I/Os are set to inputs at reset.
Figure 9-1. Logic Diagram (Positive Logic)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
15
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
Configuration
Register
VCC
Q1
Q
D
FF
Write Configuration
Pulse
Q
D
CK Q
FF
Write Pulse
P0 to P7
CK Q
Q2
Output Port
Register
Input Port
Register
GND
Input Port
Register Data
Q
D
FF
Read Pulse
CK Q
Data From
Shift Register
To INT
Polarity
Register Data
Q
D
ESD Protection
Diode
FF
Write Polarity
Pulse
CK Q
Polarity
Inversion
Register
A. At power-on reset, all registers return to default values.
Figure 9-2. Simplified Schematic Of P0 To P7
9.2 Device Functional Modes
9.2.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9534A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9534A registers and
I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and
then back up to the operating voltage for a power-reset cycle.
9.2.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 9-2) are off, creating a high-impedance input.
The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register.
In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
9.2.3 Interrupt Output ( INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv,
the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the
original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting
of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause
16
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the
pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pull-up resistor to VCC.
9.2.3.1 Interrupt Errata
9.2.3.1.1 Description
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I2C command byte (register pointer) written to the device was 00h.
Note
This generally means the last operation with the device was a Read of the input register. However,
the command byte may have been written with 00h without ever going on to read the input register.
After reading from the device, if no other command byte written, it will remain 00h.
2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high
9.2.3.1.2 System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
9.2.3.1.3 System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9534A device or before reading from another slave device.
Note
Software change will be compatible with other versions (competition and TI redesigns) of this device.
9.3 Programming
9.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 9-3). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 9-4).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 9-3).
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure
9-5). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times
must be met to ensure proper operation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
17
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 9-3. Definition Of Start And Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 9-4. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 9-5. Acknowledgment On I2C Bus
9.3.2 Register Map
Table 9-1. Interface Definition
BYTE
I2C slave address
Px I/O data bus
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
H
H
A2
A1
A0
R/ W
P7
P6
P5
P4
P3
P2
P1
P0
9.3.2.1 Device Address
Figure 9-6 shows the address byte of the PCA9534A.
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
Slave Address
0
1
1
1
A2
A1
A0
R/W
Hardware Selectable
Fixed
Figure 9-6. Pca9534a Address
Table 9-2. Address Reference
INPUTS
A2
A1
A0
L
L
L
I2C BUS SLAVE ADDRESS
56 (decimal), 38 (hexadecimal)
L
L
H
57 (decimal), 39 (hexadecimal)
L
H
L
58 (decimal), 3A (hexadecimal)
L
H
H
59 (decimal), 3B (hexadecimal)
H
L
L
60 (decimal), 3C (hexadecimal)
H
L
H
61 (decimal), 3D (hexadecimal)
H
H
L
62 (decimal), 3E (hexadecimal)
H
H
H
63 (decimal), 3F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
9.3.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte which is
stored in the control register in the PCA9534A. Two bits of this command byte state the operation (read or write)
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can
be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
0
0
0
0
0
0
B1
B0
Figure 9-7. Control Register Bits
Table 9-3. Command Byte
CONTROL
REGISTER BITS
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0x00
Input Port
Read byte
xxxx xxxx
0
1
0x01
Output Port
Read/write byte
1111 1111
1
0
0x02
Polarity Inversion
Read/write byte
0000 0000
1
1
0x03
Configuration
Read/write byte
1111 1111
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
19
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
9.3.2.3 Register Descriptions
The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin
is defined as an input or an output by the configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the
input port register will be accessed next.
Table 9-4. Register 0 (Input Port Register)
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 9-5. Register 1 (Output Port Register)
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
1
1
1
1
1
1
1
1
The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Table 9-6. Register 2 (Polarity Inversion Register)
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
0
0
0
0
0
0
0
0
The configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to
1, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 9-7. Register 3 (Configuration Register)
20
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
9.3.2.4 Bus Transactions
Data is exchanged between the master and PCA9534A through write and read commands.
9.3.2.4.1 Writes
Data is transmitted to the PCA9534A by sending the device address and setting the least-significant bit to a
logic 0 (see Figure 9-6 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte (see Figure 9-8 and Figure 9-9). There is no limitation
on the number of data bytes sent in one write transmission.
SCL
1
2
3
4
5
7
8
9
Slave Address
SDA
S
0
1
1
1
Command Byte
A2
A0
Start Condition
0
R/W
A
0
0
0
0
0
Data to Port
0
ACK From Slave
0
1
Data 1
A
A
ACK From Slave
P
ACK From Slave
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 9-8. Write To Output Port Register
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
1
Start Condition
Command Byte
1 A2 A1 A0 0
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
1 1/0 A
Data
A
ACK From Slave
P
ACK From Slave
Data to
Register
Figure 9-9. Write To Configuration Or Polarity Inversion Registers
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
21
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
9.3.2.4.2 Reads
The bus master first must send the PCA9534A address with the least-significant bit set to a logic 0 (see Figure
9-6 for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9534A (see Figure 9-10 and Figure 9-11).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limitation on the number of data bytes received in one read transmission, but when the final byte is received, the
bus master must not acknowledge the data.
S 0
1
1
ACK From
Slave
ACK From
Slave
Slave Address
1 A2 A1 A0 0
Command Byte
A
ACK From
ACK From
Master
Slave Data from Register
Slave Address
A S 0
1
1
Data
A
Data from Register
NACK From
Master
1 A2 A1 A0 1 A
R/W
R/W
Data
NA P
Last Byte
Figure 9-10. Read From Register
SCL
1
2
3
4
5
6
7
8
9
Data From Port
Slave Address
SDA
S 0
1
1 1 A2 A1 A0 1
Start
Condition
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A. This figure assumes that the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a stop condition.
C. This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address call and the actual
data transfer from the P Port. See Figure 9-10 for these details.
Figure 9-11. Read Input Port Register
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
10 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
10.1.1 Typical Application
Figure 10-1 shows an application in which the PCA9534A can be used.
A.
B.
C.
D.
Device address is configured as 0111100 for this example.
P0, P2, and P3 are configured as outputs.
P1, P4, and P5 are configured as inputs.
P6 and P7 are not used and must be configured as outputs.
Figure 10-1. Typical Application
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
23
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
10.1.1.1 Design Requirements
10.1.1.1.1 Minimizing ICC When The I/O Controls Leds
When the I/Os are used to control LEDs, they normally are connected to VCC through a resistor as shown
in Figure 10-1. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than
VCC. The supply current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical
Characteristics.
For battery-powered applications, it is essential that the voltage of the I/O pins is greater than or equal to VCC
when the LED is off to minimize current consumption. Figure 10-2 shows a high-value resistor in parallel with the
LED. Figure 10-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain
the I/O VIN at or above VCC and prevents additional supply-current consumption when the LED is off.
VCC
LED
100 kW
VCC
LEDx
Figure 10-2. High-Value Resistor In Parallel With The Led
3.3 V
VCC
5V
LED
LEDx
Figure 10-3. Device Supplied By A Lower Voltage
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
11 Power Supply Recommendations
11.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9534A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 11-1 and Figure 11-2.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 11-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 11-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
Table 11-1 specifies the performance of the power-on reset feature for PCA9534A for both types of power-on
reset.
Table 11-1. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 11-1
1
100
ms
VCC_RT
Rise rate
See Figure 11-1
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 11-1
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 11-2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 11-3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 11-3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
(1)
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
the device impedance are factors that affect power-on reset performance. Figure 11-3 and Table 11-1 provide
more information on how to measure these specifications.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
25
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
VCC
VCC_GH
Time
VCC_GW
Figure 11-3. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and
all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR
differs based on the VCC being lowered to or from 0. Figure 11-4 and Table 11-1 provide more details on this
specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 11-4. VPOR
26
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
PCA9534A
www.ti.com
SCPS141J – SEPTEMBER 2006 – REVISED MARCH 2021
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.3 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9534A
27
PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCA9534ADB
ACTIVE
SSOP
DB
16
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD534A
PCA9534ADBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD534A
PCA9534ADGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD534A
PCA9534ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9534A
PCA9534ADWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9534A
PCA9534APWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD534A
PCA9534ARGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZVJ
PCA9534ARGTRG4
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZVJ
PCA9534ARGVR
ACTIVE
VQFN
RGV
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD534A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
