PCA9544A
SCPS146G – OCTOBER 2005 – REVISEDPCA9544A
MARCH 2021
SCPS146G – OCTOBER 2005 – REVISED MARCH 2021
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PCA9544A Low Voltage 4-Channel I2C and SMBus Multiplexer With Interrupt Logic
1 Features
3 Description
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The PCA9544A is a 4-channel, bidirectional
translating multiplexer controlled via the I2C bus. The
SCL/SDA upstream pair fans out to four downstream
pairs, or channels. One SCL/SDA pair can be
selected at a time, and this is determined by the
contents of the programmable control register. Four
interrupt inputs ( INT3– INT0), one for each of the
downstream pairs, are provided. One interrupt output
( INT) acts as an AND of the four interrupt inputs.
•
•
•
•
•
•
•
•
•
•
•
•
1-of-4 Bidirectional translating switches
I2C Bus and SMBus compatible
Four active-low interrupt inputs
Active-low interrupt output
Three address pins, allowing up to eight devices
on the I2C Bus
Channel selection via I2C Bus
Power up with all switch channels deselected
Low RON switches
Allows voltage-level translation between 1.8-V, 2.5V, 3.3-V, and 5-V Buses
No glitch on power up
Supports hot insertion
Low standby current
Operating power-supply voltage range of
2.3 V to 5.5 V
5.5-V Tolerant inputs
0 to 400-kHz Clock frequency
Latch-up performance exceeds 100 mA Per JESD
78
ESD Protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A)
– 1000-V Charged-device model (C101)
2 Applications
•
•
•
•
Servers
Routers (Telecom Switching Equipment)
Factory Automation
Products With I2C Slave Address Conflicts (For
Example, Multiple, Identical Temp Sensors)
A power-on reset function puts the registers in their
default state and initializes the I2C state machine, with
no channel selected.
The pass gates of the switches are constructed such
that the VCC pin can be used to limit the maximum
high voltage, which will be passed by the PCA9544A.
This allows the use of different bus voltages on
each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can
communicate with 5-V parts, without any additional
protection. External pull-up resistors pull the bus up to
the desired voltage level for each channel. All I/O pins
are 5-V tolerant.
Device Information
PACKAGE(1)
PART NUMBER
PCA9544A
(1)
BODY SIZE (NOM)
TVSOP (DGV) (20)
5.00 mm x 4.40 mm
SOIC (DW) (20)
12.8 mm x 7.50 mm
TSSOP (PW) (20)
6.50 mm × 4.40 mm
VQFN (RGY) (20)
4.50 mm x 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Channel 0
SDA
SCL
INT
I2C or SMBus
Master
VCC
SD0
SC0
INT0
SD1
SC1
INT1
(e.g. µProcessor)
PCA9544A
A0
A1
A2
GND
SD2
SC2
INT2
SD3
SC3
INT3
Slaves A0, A1...AN
Channel 1
Slaves B0, B1...BN
Channel 2
Slaves B0, B1...BN
Channel 3
Slaves B0, B1...BN
Simplified Application Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 I2C Interface Timing Requirements.............................6
6.7 Switching Characteristics............................................6
6.8 Interrupt Timing Requirements....................................6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
8.5 Programming.............................................................11
8.6 Register Map.............................................................13
9 Application Information Disclaimer............................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................19
10.1 Power-On Reset Requirements.............................. 19
11 Layout........................................................................... 21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Receiving Notification of Documentation Updates..22
12.2 Support Resources................................................. 22
12.3 Trademarks............................................................. 22
12.4 Electrostatic Discharge Caution..............................22
12.5 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
Changes from Revision F (August 2019) to Revision G (March 2021)
Page
• Changed the PW packgae values in the Thermal Information table...................................................................4
• Added the RGY package values in the Thermal Information table.....................................................................4
• Changed the VPORR row in the Electrical Characteristics .................................................................................. 5
• Added VPORF row to the Electrical Characteristics ............................................................................................ 5
• Changed the ICC Low inputs and High inputs values in the Electrical Characteristics .......................................5
• Changed the ΔICC (INT3–INT0) MAX values From: 15 µA To: 20 µA in the Electrical Characteristics ............. 5
• Changed the Application Curves ..................................................................................................................... 18
• Changed the Power Supply Recommendations .............................................................................................. 19
Changes from Revision E (June 2014) to Revision F (August 2019)
Page
• Changed text From: "The PCA9544A is a quad bidirectional translating switch" To: "The PCA9544A is a 4channel, bidirectional translating multiplexer" in the Description ....................................................................... 1
• Changed the Device Information table............................................................................................................... 1
• Deleted the RGW, GQN, and ZQN packages from the Pin Configuration and Functions section......................3
• Moved Tstg to the Absolute Maximum Ratings .................................................................................................. 4
• Changed the Handling Ratings table to ESD Ratings table................................................................................4
• Added the Thermal Information table................................................................................................................. 4
• Changed the first paragraph of the Overview section.........................................................................................9
• Changed text From: "bidirectional translating switch" To: "bidirectional translating multiplexer"...................... 11
• Changed text from: "One or several SCn/SDn downstream pairs or channels, are selected" To: "Only one
SCn/SDn downstream pair, or channel, can be selected" in the Control Register Definition section............... 14
• Deleted sentence: "If multiple switches will be enabled.." from the second paragraph of the Application
Information section........................................................................................................................................... 16
Changes from Revision D (February 2008) to Revision E (June 2014)
2
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A0
VCC
1
20
5 Pin Configuration and Functions
A0
1
20
VCC
A1
2
19
SDA
A2
3
18
SCL
A1
2
19
SDA
INT0
4
17
INT
A2
3
18
SCL
SD0
5
16
SC3
INT0
4
17
INT
SC0
6
15
SD3
SD0
5
16
SC3
INT1
7
14
INT3
SC0
6
15
SD3
SD1
8
13
SC2
INT1
7
14
INT3
SC1
9
12
SD2
SD1
8
13
SC2
GND
10
11
INT2
SC1
9
12
SD2
Th ermal
11
10
Pad
No t to scale
INT2
GND
Figure 5-1. DGV, DW, or PW Package, TVSOP,
SOIC, TSSOP (20 Pins), Top View
No t to scale
Figure 5-2. RGY Package, VQFN (20 Pins), Top
View
Table 5-1. Pin Functions
PIN
(1)
NO.
NAME
1
A0
FUNCTION
Address input 0. Connect directly to VCC or ground.
2
A1
Address input 1. Connect directly to VCC or ground.
3
A2
Address input 2. Connect directly to VCC or ground.
4
INT0
Active-low interrupt input 0. Connect to VDPU0 (1) through a pull-up resistor.
5
SD0
Serial data 0. Connect to VDPU0 (1) through a pull-up resistor.
6
SC0
Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor.
7
INT1
Active-low interrupt input 1. Connect to VDPU1 (1) through a pull-up resistor.
8
SD1
Serial data 1. Connect to VDPU1 (1) through a pull-up resistor.
9
SC1
Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor.
10
GND
Ground
11
INT2
Active-low interrupt input 2. Connect to VDPU2 (1) through a pull-up resistor.
12
SD2
Serial data 2. Connect to VDPU2 (1) through a pull-up resistor.
13
SC2
Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor.
14
INT3
Active-low interrupt input 3. Connect to VDPU3 (1) through a pull-up resistor.
15
SD3
Serial data 3. Connect to VDPU3 (1) through a pull-up resistor.
16
SC3
Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor.
17
INT
Active-low interrupt output. Connect to VDPUM (1) through a pull-up resistor.
18
SCL
Serial clock line. Connect to VDPUM (1) through a pull-up resistor.
19
SDA
Serial data line. Connect to VDPUM (1) through a pull-up resistor.
20
VCC
Supply power
VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage while VDPU0-VDPU3 are
the slave channel reference voltages.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC
Supply voltage range
–0.5
7
VI
Input voltage range(2)
–0.5
7
II
Input current
IO
Output current
Ptot
UNIT
V
V
±20
mA
±25
mA
Continuous current through VCC
±100
mA
Continuous current through GND
±100
mA
400
mW
Total power dissipation
TA
Operating free-air temperature range
–40
85
°C
Tstg
Storage temperature range
–60
150
°C
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
MIN
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
0
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See (1)
VCC
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
(1)
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
6
A2–A0, INT3– INT0
0.7 × VCC
VCC + 0.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, INT3– INT0
–0.5
0.3 × VCC
–40
85
Supply voltage
UNIT
V
V
V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
PCA9544A
THERMAL METRIC(1)
DW
PW
RGY
20 PINS
20 PINS
20 PINS
20 PINS
92
58
118.2
62.7
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
43.9
41.9
62.7
60.5
°C/W
RθJB
Junction-to-board thermal resistance
64.5
40.3
69.3
39.5
°C/W
ψJT
Junction-to-top characterization parameter
4.2
18.1
7.7
7.2
°C/W
ψJB
Junction-to-board characterization parameter
63.6
40
68.8
39.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
26.6
°C/W
(1)
4
DGV
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VPORR
Power-on reset voltage, VCC
rising(2)
No load,
VI = VCC or GND
VPORF
Power-on reset voltage, VCC
falling(2)
No load,
VI = VCC or GND
VCC
MIN TYP(1)
1.2
0.8
5V
4.5 V to 5.5 V
Vpass
Switch output voltage
VSWin = VCC,
ISWout = –100 μA
2.3 V to 2.7 V
INT
VO = VCC
VOL = 0.6 V
INT
2.3 V to 5.5 V
VOL = 0.4 V
4.5
1.6
2.8
1.1
2
10
3
7
6
10
3
7
SC3–SC0, SD3–SD0
VI = VCC or GND
±1
fSCL = 100 kHz
VI = VCC or GND, IO = 0
VI = GND,
IO = 0
Standby mode
High inputs
INT3– INT0
Supply-current
change
SCL, SDA
A2–A0
Ci
INT3– INT0
Cio(OFF) (3)
RON
(1)
(2)
(3)
μA
±1
Low inputs
ΔICC
mA
±1
2.3 V to 5.5 V
INT3– INT0
ICC
μA
±1
A2–A0
Operating mode
V
1.5
SCL, SDA
II
V
V
1.9
2.3 V to 5.5 V
VOL = 0.4 V
SCL, SDA
IOL
1
2.6
2.5 V
IOH
1.5
3.6
3.3 V
3 V to 3.6 V
MAX UNIT
SCL, SDA
SC3–SC0, SD3–SD0
Switch-on resistance
VI = VCC,
IO = 0
5.5 V
3
3.6 V
3
11
2.7 V
3
10
5.5 V
1.6
2
3.6 V
1
1.3
2.7 V
0.7
1.1
5.5 V
1.6
2
3.6 V
1
1.3
2.7 V
0.7
1.1
8
20
8
20
8
15
8
15
4.5
6
4.5
6
15
19
6
8
4
10
16
3 V to 3.6 V
5
13
20
2.3 V to 2.7 V
7
16
45
One INT3– INT0 input at 0.6 V,
Other inputs at VCC or GND
One INT3– INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
VI = VCC or GND
2.3 V to 5.5 V
VI = VCC or GND, Switch OFF
2.3 V to 5.5 V
IO = 15 mA
VO = 0.4 V,
IO = 10 mA
4.5 V to 5.5 V
μA
μA
SCL or SDA inputs at VCC – 0.6 V,
Other inputs at VCC or GND
VO = 0.4 V,
12
pF
pF
Ω
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
The power-on reset circuit resets the I2C bus logic when VCC < VPORF.
Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
STANDARD-MODE
I2C BUS
FAST-MODE
I2C BUS
MAX
MIN
MAX
0
100
0
400
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
250
100
tsdh
I2C
0(1)
0(1)
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time (10-pF to 400-pF bus)
clock high time
serial-data hold time
0.6
μs
1.3
μs
50
I2C start or repeated start condition setup
bus free time between stop and start
tsth
I2C
tsps
I2C stop condition setup
tvdL(Data)
Valid-data time (high to low)(3)
SCL low to SDA output low valid
tvdH(Data)
Valid-data time (low to high)(3)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
Cb
I2C bus capacitive load
ns
ns
μs
1000 20 + 0.1Cb (2)
300
ns
(2)
300
ns
300 20 + 0.1Cb (2)
300
ns
300 20 + 0.1Cb
tbuf
(2)
(3)
4
input fall time
tsts
kHz
4.7
50
I2C
(1)
UNIT
MIN
4.7
1.3
μs
4.7
0.6
μs
4
0.6
μs
4
0.6
μs
start or repeated start condition hold
1
1
μs
0.6
0.6
μs
1
1
μs
400
400
pF
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
Cb = total bus capacitance of one bus line in pF
Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-1).
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-1)
PARAMETER
tpd (1)
Propagation delay time
tiv
Interrupt valid time(2)
tir
(1)
(2)
Interrupt reset delay
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
time(2)
FROM
(INPUT)
TO
(OUTPUT)
SDA or SCL
SDn or SCn
INTn
INT
4
μs
INTn
INT
2
μs
MIN
MAX
0.3
1
UNIT
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Data taken using a 4.7-kΩ pull-up resistor and 100-pF load (see Figure 7-2).
6.8 Interrupt Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MAX
UNIT
tPWRL
Low-level pulse duration rejection of INTn
1
μs
tPWRH
High-level pulse duration rejection of INTn inputs(1)
0.5
μs
(1)
6
MIN
inputs(1)
Data taken using a 4.7-kΩ pull-up resistor and 100-pF load (see Figure 7-2).
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7 Parameter Measurement Information
VCC
RL = 1 kW
SDn, SCn
DUT
CL = 50 pF
(See Note A)
I2C-Port Load Configuration
Two Bytes for Complete
Device Programming
Stop
Start
Address
Address
Condition Condition
Bit 7
Bit 6
(P)
(S)
(MSB)
BYTE
DESCRIPTION
1
I2C address + R/W
2
Control register data
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
ACK
(A)
Stop
Condition
(P)
tsch
0.7 x VCC
SCL
ticr
ticf
tbuf
tsp
tvd(ACK)
or tvdL
tvdH
0.3 x VCC
tsts
0.7 x VCC
SDA
0.3 x VCC
ticr
ticf
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
Stop
Condition
Voltage Waveforms
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns
C. The outputs are measured one at a time, with one transition per measurement.
Figure 7-1. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
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VCC
RL = 4.7 kW
DUT
INT
CL = 100 pF
(See Note A)
Interrupt Load Configuration
INTn
(input)
0.5 x VCC
INTn
(input)
tir
tiv
INT
(output)
0.5 x VCC
0.5 x VCC
INT
(output)
Voltage Waveforms (t iv)
0.5 x VCC
Voltage Waveforms (t ir)
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns
Figure 7-2. Interrupt Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The PCA9544A is a 4-channel, bidirectional translating I2C multiplexer. The master SCL/SDA signal pair is
directed to one of the four channels of slave devices, SC0/SD0-SC3/SD3. Only one individual downstream
channel can be selected of the four channels at a time. The PCA9544A also supports interrupt signals in
order for the master to detect an interrupt on the INT output pin that can result from any of the slave devices
connected to the INT3- INT0 input pins.
The device can be reset by cycling the power supply, VCC, also known as a power-on reset (POR), which resets
the state machine and allows the PCA9544A to recover should one of the downstream I2C buses get stuck in a
low state. A POR event causes all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0-A2 pins), a single 8-bit control register is written to or read from to determine the selected
channels and state of the interrupts.
The PCA9544A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
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8.2 Functional Block Diagram
PCA9544A
SC0
SC1
SC2
SC3
SD0
SD1
6
9
13
16
5
8
12
SD2
SD3
GND
VCC
SCL
SDA
INT0
INT1
INT2
INT3
15
Switch Control Logic
10
20
Power-on Reset
18
19
1
Input Filter
4
7
11
14
I2C
2
Bus Control
Interrupt Logic
3
Output
Filter
17
A0
A1
A2
INT
A. Pin numbers shown are for DGV, DW, PW, and RGY packages.
10
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8.3 Feature Description
The PCA9544A is a 4-channel, bidirectional translating multiplexer for I2C buses that supports Standard-Mode
(100 kHz) and Fast-Mode (400 kHz) operation. The PCA9544A features I2C control using a single 8-bit control
register in which the three least significant bits control the enabling and disabling of the 4 switch channels of
I2C data flow. The PCA9544A also supports interrupt signals for each slave channel and this data is held in the
four most significant bits of the control register. Depending on the application, voltage translation of the I2C bus
can also be achieved using the PCA9544A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts.
Additionally, in the event that communication on the I2C bus enters a fault state, the PCA9544A can be reset to
resume normal operation by means of a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power is applied to VCC, an internal power-on reset holds the PCA9544A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released, and the PCA9544A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below VPOR to reset the device.
8.5 Programming
8.5.1 I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure
8-1).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 8-1. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 8-2).
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 8-2. Definition of Start and Stop Conditions
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A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master, and the devices that are controlled by the master are the slaves (see Figure
8-3).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Slave
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I2C
Multiplexer
Slave
Figure 8-3. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.
Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the
SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 8-4). Setup and hold
times must be taken into account.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for ACK
Start
Condition
Figure 8-4. Acknowledgment on the I2C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the PCA9544A control register using the write mode shown in Figure 8-5.
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Slave Address
SDA
S
1
1
1
0
Control Register
A2 A1 A0
Start Condition
0
A
X
X
X
X
X
B2 B1 B0
R/W ACK From Slave
A
ACK From Slave
P
Stop Condition
Figure 8-5. Write Control Register
Data is read from the PCA9544A control register using the read mode shown in Figure 8-6.
Slave Address
SDA
S
1
1
1
0
A2
Control Register
A1
Start Condition
A0
1
A
R/W
INT3 INT2 INT1 INT0
B2
0
ACK From Slave
B1
B0
NA
NACK From Master
P
Stop Condition
Figure 8-6. Read Control Register
8.6 Register Map
8.6.1 Control Register
8.6.1.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9544A is shown in Figure 8-7. To conserve power, no internal pull-up resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address
1
1
1
Fixed
0
A2
A1
A0 R/W
Hardware
Selectable
Figure 8-7. PCA9544A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
8.6.1.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9544A,
which is stored in the control register. If multiple bytes are received by the PCA9544A, it saves the last byte
received. This register can be written and read via the I2C bus.
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Channel-Selection Bits
(Read/Write)
Interrupt Bits
(Read Only)
7
6
5
4
INT3 INT2 INT1 INT0
3
2
1
0
X
B2
B1
B0
Enable Bit
INT0
INT1
INT2
INT3
Figure 8-8. Control Register
8.6.1.3 Control Register Definition
Only one SCn/SDn downstream pair, or channel, can be selected by the contents of the control register (see
Table 8-1). This register is written after the PCA9544A has been addressed. The three LSBs of the control byte
are used to determine which channel is to be selected. When a channel is selected, the channel becomes active
after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state
when the channel is made active, so that no false conditions are generated at the time of connection. A stop
condition always must occur right after the acknowledge cycle.
Table 8-1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1)
(1)
14
INT3
INT2
INT1
INT0
D3
B2
B1
B0
COMMAND
X
X
X
X
X
0
X
X
No channel selected
X
X
X
X
X
1
0
0
Channel 0 enabled
X
X
X
X
X
1
0
1
Channel 1 enabled
X
X
X
X
X
1
1
0
Channel 2 enabled
X
X
X
X
X
1
1
1
Channel 3 enabled
0
0
0
0
0
0
0
0
No channel selected,
power-up default state
Only one channel may be selected at a time.
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8.6.1.4 Interrupt Handling
The PCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. When
an interrupt is generated by any device, it is detected by the PCA9544A, and the interrupt output is driven low.
The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (see
Table 8-2).
Bits 4–7 of the control register correspond to channels 0–3 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into
the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0
causes bit 4 of the control register to be set on the read. The master then can address the PCA9544A and read
the contents of the control register to determine which channel contains the device generating the interrupt. The
master can reconfigure the PCA9544A to select this channel and locate the device generating the interrupt and
clear it. Once the device responsible for the interrupt clears, the interrupt clears.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC.
Table 8-2. Control Register Read (Interrupt) (1)
INT3
X
X
X
0
1
(1)
INT2
X
X
0
1
X
INT1
X
INT0
0
D3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
COMMAND
No interrupt on channel 0
Interrupt on channel 0
No interrupt on channel 1
Interrupt on channel 1
No interrupt on channel 2
Interrupt on channel 2
No interrupt on channel 3
Interrupt on channel 3
Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt
on channels 0 and 3, and there is interrupt on channels 1 and 2.
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Applications of the PCA9544A contain an I2C (or SMBus) master device and up to four I2C slave devices. The
downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical digital
temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2, and
3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled and
all other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus contains many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across multiple channels.
9.2 Typical Application
A typical application of the PCA9544A contains anywhere from 1 to 5 separate data pull-up voltages, VDPUX ,
one for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the
event where the master device and all slave devices operate at the same voltage, then the pass voltage, Vpass =
VDPUX. Once the maximum Vpass is known, Vcc can be selected using Figure 9-2. In an application where voltage
translation is necessary, additional design requirements must be considered (See Design Requirements).
Figure 9-1 shows an application in which the PCA9544A can be used.
VDPUM = 2.3 V to 5.5 V
VCC = 2.3 V to 5.5 V
VDPU0 = 2.3 V to 5.5 V
20
SDA
I2C/SMBus
SCL
Master
VCC
19
SD0
5
SC0
6
4
SDA
18
17
SCL
INT
INT0
Channel 0
VDPU1 = 2.3 V to 5.5 V
SD1
SC1
INT1
8
9
7
VDPU2 = 2.3 V to 5.5 V
PCA9544A
SD2
SC2
Channel 1
12
13
Channel 2
11
INT2
3
A2
2
A1
1
A0
10
GND
SD3
SC3
INT3
VDPU3 = 2.3 V to 5.5 V
15
16
Channel 3
14
Figure 9-1. Typical Application
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9.2.1 Design Requirements
The pull-up resistors on the INT3- INT0 terminals in the application schematic are not required in all applications.
If the device generating the interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is
required. If the device generating the interrupt has a push-pull output structure and cannot be tri-stated, a pull-up
resistor is not required. The interrupt inputs should not be left floating in the application.
The A0 and A1 terminals are hardware selectable to control the slave address of the PCA9544A. These
terminals may be tied directly to GND or VCC in the application.
If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side are the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the PCA9544A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 9-2 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated
using data specified in the Electrical Characteristics section of this data sheet). In order for the PCA9544A to act
as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example,
if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or
below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 9-2, Vpass(max) is 2.7 V when
the PCA9544A supply voltage is 4 V or lower, so the PCA9544A supply voltage could be set to 3.3 V. pull-up
resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 9-1).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL:
Rp(min) =
VDPUX - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
= 400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the PCA9544A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels
are activated simultaneously, each of the slaves on all channels contributes to total bus capacitance.
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9.2.3 Application Curves
5
25
20
Rp(max) (kOhm)
4
Vpass (V)
Standard-mode
Fast-mode
25ºC (Room Temperature)
85ºC
-40ºC
3
2
15
10
5
1
0
0
0
0.5
1
Space spacespace
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
0
50
100
150
D007
200
250
Cb (pF)
Standard-mode (fSCL= 100
kHz, tr = 1 µs)
Space spacespace
Figure 9-2. Pass-Gate Voltage (Vpass) vs Supply
Voltage (VCC) at Three Temperature Points
300
350
400
450
D008
Fast-mode (fSCL= 400 kHz, tr=
300 ns)
Figure 9-3. Maximum Pull-up resistance (Rp(max))
vs Bus Capacitance (Cb)
1.8
1.6
Rp(min) (kOhm)
1.4
1.2
1
0.8
0.6
0.4
VDPUX > 2V
VDPUX 2 V
Figure 9-4. Minimum Pull-up Resistance (Rp(min)) vs Pull-up Reference Voltage (VDPUX)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9544A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 10-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 10-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
Table 10-1 specifies the performance of the power-on reset feature for PCA9544A for both types of power-on
reset.
Table 10-1. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 10-1
1
100
ms
VCC_RT
Rise rate
See Figure 10-1
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 10-1
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 10-2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 10-3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 10-3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
(1)
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide
more information on how to measure these specifications.
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VCC
VCC_GH
Time
VCC_GW
Figure 10-3. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and
all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR
differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this
specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 10-4. VPOR
20
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11 Layout
11.1 Layout Guidelines
For PCB layout of the PCA9544A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and terminals that
are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon
pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the
VCC terminal, using a larger capacitor to provide additional power in the event of a short power supply glitch and
a smaller capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the
same layer of the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be
a short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper
weight).
11.2 Layout Example
LEGEND
Partial Power Plane
Polygonal
Copper Pour
To I2C Master
VIA to Power Plane
VIA to GND Plane (Inner Layer)
VDPUM
By-pass/De-coupling
capacitors
A0
VCC
A1
SDA
A2
SCL
INT0
SD0
SC0
VDPU3
INT
SC3
SD3
INT3
SD1
SC2
SC1
SD2
GND
INT2
GND
VDPU2
To Slave Channel 2
To Slave Channel 1
INT1
VDPU1
VCC
PCA9544A
VDPU0
To Slave Channel 3
To Slave Channel 0
GND
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following packaging information and addendum reflect the most current data available for the designated
devices. This data is subject to change without notice and revision of this document.The following packaging
information and addendum reflect the most current data available for the designated devices. This data is
subject to change without notice and revision of this document.
22
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCA9544ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9544A
PCA9544ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9544A
PCA9544APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544APWT
LIFEBUY
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD544A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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