PCA9546APW

PCA9546A SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 PCA9546A Low Voltage 4-Channel I2C and SMBus Switch with Reset Function 1 Features 3 Description • • • • The PCA9546A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. • • • • • • • • • • • • 1-of-4 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Three Address Pins, Allowing up to Eight PCA9546A Devices on the I2C Bus Channel Selection Via I2C Bus, in Any Combination Power-up With All Switch Channels Deselected Low RON Switches Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.3-V, and 5-V Buses No Glitch on Power-up Supports Hot Insertion Low Standby Current Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5.5 V Tolerant Inputs 0 to 400-kHz Clock Frequency Latch-Up Performance Exceeds 100 mA Per JESD 78 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) An active-low reset ( RESET) input allows the PCA9546A to recover from a situation in which one of the downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all the channels to be deselected, as does the internal power-on reset function. The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage, which will be passed by the PCA9546A. This allows the use of different bus voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant. Packaging Information 2 Applications • • • • Servers Routers (Telecom Switching Equipment) Factory Automation Products With I2C Slave Address Conflicts (For Example, Multiple, Identical Temp Sensors) PACKAGE(1) PART NUMBER PCA9546A (1) BODY SIZE (NOM) SOIC (D) (16) 9.90 mm x 3.91 mm TVSOP (DGV) (16) 3.60 mm x 4.40 mm SOIC (DW) (16) 10.3 mm x 7.50 mm TSSOP (PW) (16) 5.00 mm x 4.40 mm VQFN (RGV) (16) 4.00 mm x 4.00 mm VQFN (RGY) (16) 4.50 mm x 3.50 mm For all available packages, see the orderable addendum at the end of the datasheet. SDA SCL I2C or SMBus VCC Channel 0 SD0 Slaves A0, A1...AN SC0 Master Channel 1 (e.g. Processor) SD1 RESET Slaves B0, B1...BN SC1 PCA9546A Channel 2 A0 A1 SD2 A2 GND Slaves C0, C1...CN SC2 Channel 3 SD3 Slaves D0, D1...DN SC3 Copyright © 2016, Texas Instruments Incorporated Simplified Application Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 I2C Interface Timing Requirements.............................6 6.7 Interrupt and Reset Timing Requirements.................. 7 6.8 Switching Characteristics............................................7 7 Parameter Measurement Information............................ 8 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................11 8.4 Device Functional Modes..........................................11 8.5 Programming.............................................................11 8.6 Control Register........................................................ 14 9 Application Information Disclaimer............................. 16 9.1 Application Information............................................. 16 9.2 Typical Application.................................................... 16 10 Power Supply Recommendations..............................19 10.1 Power-On Reset Requirements.............................. 19 11 Layout........................................................................... 21 11.1 Layout Guidelines................................................... 21 11.2 Layout Example...................................................... 21 12 Device and Documentation Support..........................22 12.1 Receiving Notification of Documentation Updates..22 12.2 Support Resources................................................. 22 12.3 Trademarks............................................................. 22 12.4 Electrostatic Discharge Caution..............................22 12.5 Glossary..................................................................22 13 Mechanical, Packaging, and Orderable Information.................................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (March 2021) to Revision I (June 2022) Page • Changed TSSOP (PW) (16) From: 9.70 mm x 4.40 mm To: 5.00 mm x 4.40 mm in the Packaging Information table.................................................................................................................................................................... 1 Changes from Revision G (May 2016) to Revision H (March 2021) Page • Changed the Packaging Information table..........................................................................................................1 • Moved the Package thermal impedance to the Thermal Information table........................................................ 4 • Added the Thermal Information table................................................................................................................. 4 • Changed the VPORR row in the Electrical Characteristics .................................................................................. 5 • Added VPORF row to the Electrical Characteristics ............................................................................................ 5 • Changed the ICC Low inputs and High inputs values in the Electrical Characteristics .......................................5 • Changed the Ron (4.5 V to 5.5 V) TYP value From: 9 Ω To: 10 Ω in the Electrical Characteristics ................... 5 • Changed the Ron (3 V to 3.6 V) TYP value From: 11 Ω To: 13 Ω in the Electrical Characteristics .................... 5 • Changed the Power Supply Recommendations .............................................................................................. 19 Changes from Revision F (April 2014) to Revision G (May 2016) Page • Revised pack material addendum; pin 1 quadrant .......................................................................................... 22 Changes from Revision E (January 2008) to Revision F (April 2014) Page • Added RESET Errata section............................................................................................................................11 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 5 Pin Configuration and Functions 5 12 6 11 7 10 8 9 11 A2 SC0 3 10 SC3 SD1 4 9 5 6 7 8 SD3 VCC SDA SD0 2 A1 RESET SD0 SC0 SD1 SC1 1 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 SD2 13 16 15 14 13 12 SCL A0 14 4 RESET 1 RGY PACKAGE (TOP VIEW) GND 3 VCC SDA SCL A2 SC3 SD3 SC2 SD2 SC2 15 SD2 2 GND 16 VCC A1 1 SC1 A0 A1 RESET SD0 SC0 SD1 SC1 GND A0 RGV PACKAGE (TOP VIEW) D, DGV, DW, OR PW PACKAGE (TOP VIEW) SDA SCL A2 SC3 SD3 SC2 Table 5-1. Pin Functions PIN NO. NAME DESCRIPTION D, DGV, DW, PW, AND RGY RGV A0 1 15 Address input 0. Connect directly to VCC or ground A1 2 16 Address input 1. Connect directly to VCC or ground A2 13 11 Address input 2. Connect directly to VCC or ground GND 8 6 Ground RESET 3 1 Active low reset input. Connect to VDPUM (1) through a pull-up resistor, if not used. SD0 4 2 Serial data 0. Connect to VDPU0 (1) through a pull-up resistor SC0 5 3 Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor SD1 6 4 Serial data 1. Connect to VDPU1 (1) through a pull-up resistor SC1 7 5 Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor SD2 9 7 Serial data 2. Connect to VDPU2 (1) through a pull-up resistor SC2 10 8 Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor SD3 11 9 Serial data 3. Connect to VDPU3 (1) through a pull-up resistor. SC3 12 10 Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor SCL 14 12 Serial clock line. Connect to VDPUM (1) through a pull-up resistor SDA 15 13 Serial data line. Connect to VDPUM (1) through a pull-up resistor VCC 16 14 Supply power (1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage while VDPU0 - VDPU3 are the slave channel reference voltages. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 3 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VI Input voltage II Input current IO (2) MIN MAX UNIT –0.5 7 V –0.5 7 V ±20 mA Output current ±25 mA Continuous current through VCC ±100 mA Continuous current through GND ±100 mA Ptot Total power dissipation 400 mW TA Operating free-air temperature –40 85 °C Tstg Storage temperature –65 150 (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101(2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See (1) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature (1) MIN MAX 2.3 5.5 SCL, SDA 0.7 × VCC 6 A2–A0, RESET 0.7 × VCC VCC + 0.5 SCL, SDA –0.5 0.3 × VCC A2–A0, RESET –0.5 0.3 × VCC –40 85 UNIT V V V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information PCA9546A THERMAL METRIC(1) RθJA (1) 4 Junction-to-ambient thermal resistance DGV DW PW RGV RGY D 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 120 57 122.3 50 92.3 63.2 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VPORR Power-on reset voltage, VCC rising No load, VI = VCC or GND VPORF Power-on reset voltage, VCC falling(2) VI = VCC or GND No load, VCC MIN TYP(1) 1.2 0.8 5V 4.5 V to 5.5 V Vpass Switch output voltage VSWin = VCC, 3 V to 3.6 V IOL VOL = 0.4 V SCL, SDA 2.3 V to 5.5 V VOL = 0.6 V 1.9 1.6 2.8 A2–A0 1.5 1.1 2 3 7 6 10 VI = VCC or GND ±1 fSCL = 100 kHz VI = VCC or GND, VI = GND, IO = 0 IO = 0 Standby mode High inputs ΔICC RESET Cio(OFF) (3) RON (1) (2) (3) (4) SCL, SDA A2–A0 Ci μA ±1 Low inputs Supply-current change mA ±1 2.3 V to 5.5 V RESET (4) ICC V ±1 SC3–SC0, SD3–SD0 Operating mode V 4.5 SCL, SDA II V 3.6 2.5 V 2.3 V to 2.7 V 1.5 1 2.6 3.3 V ISWout = –100 μA MAX UNIT SCL, SDA SC3–SC0, SD3–SD0 Switch on-state resistance VI = VCC, IO = 0 5.5 V 3 12 3.6 V 3 11 2.7 V 3 10 5.5 V 1.6 2 3.6 V 1 1.3 2.7 V 0.7 1.1 5.5 V 1.6 2 3.6 V 1 1.3 2.7 V 0.7 1.1 8 15 8 15 SCL or SDA input at 0.6 V, Other inputs at VCC or GND μA SCL or SDA input at VCC – 0.6 V, Other inputs at VCC or GND 2.3 V to 5.5 V VI = VCC or GND 2.3 V to 5.5 V VI = VCC or GND, Switch OFF VO = 0.4 V, IO = 15 mA VO = 0.4 V, IO = 10 mA μA 2.3 V to 5.5 V 4.5 6 4.5 5.5 15 19 6 8 4.5 V to 5.5 V 4 10 16 3 V to 3.6 V 5 13 20 2.3 V to 2.7 V 7 16 45 pF pF Ω All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C. The power-on reset circuit resets the I2C bus logic with VCC < VPORF. Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON. RESET = VCC (held high) when all other input voltages, VI = GND. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 5 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 6.6 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) MIN MAX UNIT 100 kHz I2C BUS—STANDARD MODE fscl I2C clock frequency 0 tsch I2C clock high time 4 tscl I2C tsp I2C spike time tsds I2C serial-data setup time 250 tsdh I2C serial-data hold time 0(1) ticr I2C input rise time ticf I2C tocf I2C output fall time tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C start or repeated start condition hold 4 µs tsps I2C tvdL(Data) Valid data time (high to low)(2) SCL low to SDA output low valid tvdH(Data) Valid data time (low to high)(2) SCL low to SDA output high valid tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low Cb I2C bus capacitive load (1) (2) clock low time µs 4.7 µs 50 input fall time 10-pF to 400-pF bus stop condition setup ns ns ns 1000 ns 300 ns 300 4 ns µs 1 µs 0.6 µs 1 µs 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-1) MIN MAX UNIT 0 400 kHz I2C BUS—FAST MODE fscl I2C clock frequency tsch I2C clock high time 0.6 tscl I2C clock low time 1.3 tsp I2C spike time tsds I2C tsdh I2C serial-data hold time ticr I2C input rise time 20 + 0.1Cb (2) 300 ns ticf I2C input fall time 20 + 0.1Cb (2) 300 ns tocf I2C output fall time 20 + 0.1Cb (2) 300 ns tbuf I2C 1.3 µs tsts I2C start or repeated start condition setup 0.6 µs tsth I2C start or repeated start condition hold 0.6 µs tsps I2C stop condition setup 0.6 tvdL(Data) Valid data time (high to low)(3) tvdH(Data) high)(3) Cb I2C 6 SCL low to SDA output low valid SCL low to SDA output high valid ACK signal from SCL low to SDA (out) low bus capacitive load ns ns 0(1) bus free time between stop and start Valid data time of ACK condition (2) (3) 100 10-pF to 400-pF bus tvd(ack) (1) µs 50 serial-data setup time Valid data time (low to µs ns µs 1 µs 0.6 1 µs 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. Cb = total bus capacitance of one bus line in pF Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-1) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 6.7 Interrupt and Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tWL Pulse duration, RESET low trst (1) RESET time (SDA clear) tREC(STA) Recovery time from RESET to start (1) MIN MAX UNIT 6 ns 500 ns 0 ns trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition. It must be a minimum of tWL. 6.8 Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-1) PARAMETER tpd (1) (1) Propagation delay time RON = 20 Ω, CL = 15 pF RON = 20 Ω, CL = 50 pF FROM (INPUT) TO (OUTPUT) SDA or SCL SDn or SCn MIN MAX 0.3 1 UNIT ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 7 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 7 Parameter Measurement Information VCC RL = 1 kΩ SDn, SCn DUT CL = 50 pF (See Note 1) Copyright © 2016, Texas Instruments Incorporated I2C PORT LOAD CONFIGURATION Two Bytes for Complete Device Programming Stop Start Address Address Condition Condition Bit 7 Bit 6 (P) (S) (MSB) BYTE DESCRIPTION 1 I2C address + R/W 2 Control register data Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) Stop Condition (P) tsch 0.7 × VCC SCL ticr ticf tbuf tsp tvd(ACK) or tvdL tvdH 0.3 × VCC tsts 0.7 × VCC SDA 0.3 × VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS A. B. C. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. The outputs are measured one at a time, with one transition per measurement. Figure 7-1. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 Start ACK or Read Cycle SCL SDA 30% trst 50% RESET tREC tWL Figure 7-2. Reset Timing Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 9 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 8 Detailed Description 8.1 Overview The PCA9546A is a 4-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to four channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well as any combination of the four channels. The device offers an active-low RESET input which resets the state machine and allows the PCA9546A to recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function and a POR will cause all channels to be deselected. The connections of the I2C data path are controlled by the same I2C master device that is switched to communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected channels. The PCA9546A may also be used for voltage translation, allowing the use of different bus voltages on each SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel. 8.2 Functional Block Diagram PCA9546A 5 SC0 7 SC1 10 SC2 12 SC3 4 SD0 6 SD1 9 SD2 11 SD3 8 Switch Control Logic GND VCC RESET 16 3 Power-On Reset 14 SCL 15 SDA Input Filter 2 I C Bus Control 1 2 13 A0 A1 A2 Copyright © 2016, Texas Instruments Incorporated 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 8.3 Feature Description The PCA9546A is a 4-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100 kHz) and Fast-Mode (400 kHz) operation. The PCA9546A features I2C control using a single 8-bit control register in which the four least significant bits control the enabling and disabling of the 4 switch channels of I2C data flow. Depending on the application, voltage translation of the I2C bus can also be achieved using the PCA9546A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on the I2C bus enters a fault state, the PCA9546A can be reset to resume normal operation using the RESET pin feature or by a power-on reset which results from cycling power to the device. 8.4 Device Functional Modes 8.4.1 RESET Input The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal is asserted low for a minimum of tWL, the PCA9546A resets its registers and I2C state machine and deselects all channels. The RESET input must be connected to VCC through a pull-up resistor. 8.4.1.1 RESET Errata If RESET voltage set higher than VCC, current will flow from RESET pin to VCC pin. System Impact VCC will be pulled above its regular voltage level System Workaround Design such that RESET voltage is same or lower than VCC 8.4.2 Power-On Reset When power is applied to VCC, an internal power-on reset holds the PCA9546A in a reset condition until VCC has reached VPOR. At this point, the reset condition is released, and the PCA9546A registers and I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below VPOR to reset the device. 8.5 Programming 8.5.1 I2C Interface The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 8-1). SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 8-1. Bit Transfer Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 11 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 8-2). SDA SCL S P Start Condition Stop Condition Figure 8-2. Definition of Start and Stop Conditions A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master, and the devices that are controlled by the master are the slaves (see Figure 8-3). SDA SCL Master Transmitter/ Receiver Slave Receiver Slave Transmitter/ Receiver Master Transmitter Master Transmitter/ Receiver I2C Multiplexer Slave Figure 8-3. System Configuration The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA line before the receiver can send an ACK bit. When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 8-4). Setup and hold times must be taken into account. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for ACK Start Condition Figure 8-4. Acknowledgment on the I2C Bus Data is transmitted to the PCA9546A control register using the write mode shown in Figure 8-5. Slave Address SDA S 1 1 1 0 Control Register A2 A1 A0 Start Condition 0 A X X X X B3 B2 B1 B0 R/W ACK From Slave A ACK From Slave P Stop Condition Figure 8-5. Write Control Register Data is read from the PCA9546A control register using the read mode shown in Figure 8-6. Slave Address SDA S 1 1 1 0 Start Condition Control Register A2 A1 A0 1 R/W A 0 0 0 0 ACK From Slave B3 B2 B1 B0 NA NACK From Master P Stop Condition Figure 8-6. Read Control Register Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 13 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 8.6 Control Register 8.6.1 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the PCA9546A is shown in Figure 8-7. To conserve power, no internal pull-up resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. Slave Address 1 1 0 1 A2 A1 A0 R/W Hardware Selectable Fixed Figure 8-7. PCA9546A Address The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected, while a logic 0 selects a write operation. 8.6.2 Control Register Description Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9546A, which is stored in the control register (see Figure 8-8). If multiple bytes are received by the PCA9546A, it will save the last byte received. This register can be written and read via the I2C bus. Channel Selection Bits (Read/Write) 7 6 X X 5 X 4 3 2 1 0 X B3 B2 B1 B0 Channel 0 Channel 1 Channel 2 Channel 3 Figure 8-8. Control Register 8.6.3 Control Register Definition One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see Table 8-1). This register is written after the PCA9546A has been addressed. The four LSBs of the control byte are used to determine which channel or channels are to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur right after the acknowledge cycle. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 Table 8-1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1) B7 X X X (1) B6 X X X B5 X X X B4 X X X X X X X 0 0 0 0 B3 X X X 0 1 0 B2 X X 0 1 B1 X 0 1 X B0 COMMAND 0 Channel 0 disabled 1 Channel 0 enabled X X X X X 0 0 0 Channel 1 disabled Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled Channel 3 enabled No channel selected, power-up/reset default state Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are disabled, and channels 1 and 2 are enabled. Care must be taken not to exceed the maximum bus capacity. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 15 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 9 Application Information Disclaimer Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information Applications of the PCA9546A will contain an I2C (or SMBus) master device and up to four I2C slave devices. The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2, and 3. When the temperature at a specific location must be read, the appropriate channel can be enabled and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the next channel. In an application where the I2C bus will contain many additional slave devices that do not result in I2C slave address conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance across multiple channels. If multiple switches will be enabled simultaneously, additional design requirements must be considered (See Design Requirements and Detailed Design Procedure). 9.2 Typical Application A typical application of the PCA9546A will contain anywhere from 1 to 5 separate data pull-up voltages, VDPUX , one for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the event where the master device and all slave devices operate at the same voltage, then the pass voltage, Vpass = VDPUX. Once the maximum Vpass is known, VCC can be selected easily using Figure 9-2. In an application where voltage translation is necessary, additional design requirements must be considered (See Design Requirements). Figure 9-1 shows an application in which the PCA9546A can be used. VDPUM = 2.3 V to 5.5 V VCC = 3.3 V VDPU0 = 2.3 V to 5.5 V 16 VCC I2C/SMBus Master SDA SCL 15 14 3 SDA SD0 SCL SC0 4 5 Channel 0 VDPU1 = 2.3 V to 5.5 V RESET SD1 6 SC1 7 Channel 1 VDPU2 = 2.3 V to 5.5 V PCA9546A SD2 SC2 9 10 Channel 2 VDPU3 = 2.3 V to 5.5 V 13 2 1 8 A2 A1 A0 SD3 GND SC3 11 12 Channel 3 Copyright © 2016, Texas Instruments Incorporated Figure 9-1. PCA9546A Typical Application Schematic 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 9.2.1 Design Requirements The A0, A1, and A2 pins are hardware selectable to control the slave address of the PCA9546A. These pins may be tied directly to GND or VCC in the application. If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to GND on the master side will be the sum of the currents through all pull-up resistors, Rp. The pass-gate transistors of the PCA9546A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another. Figure 9-2 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the Electrical Characteristics section of this data sheet). In order for the PCA9546A to act as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 9-2, Vpass(max) is 2.7 V when the PCA9546A supply voltage is 4 V or lower, so the PCA9546A supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 9-1). 9.2.2 Detailed Design Procedure Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a function of VDPUX, VOL,(max), and IOL as shown in Equation 1: Rp(min) = VDPUX - VOL(max) IOL (1) The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL = 400 kHz) and bus capacitance, Cb as shown in Equation 2: Rp(max) = tr 0.8473 ´ Cb (2) The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the PCA9546A, Cio(OFF), the capacitance of wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 17 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 9.2.3 Application Curves 5 25 20 Rp(max) (kOhm) 4 Vpass (V) Standard-mode Fast-mode 25ºC (Room Temperature) 85ºC -40ºC 3 2 15 10 5 1 0 0 0 0.5 1 1.5 2 2.5 3 VCC (V) Standard-mode (fSCL kHz, tr 3.5 4 4.5 5 5.5 0 50 100 150 D007 SPACE (fSCL kHz, tr) Figure 9-2. Pass-Gate Voltage (Vpass) vs Supply Voltage (VCC) at Three Temperature Points 200 250 Cb (pF) Standard-mode (fSCL= 100 kHz, tr = 1 µs) 300 350 400 450 D008 Fast-mode (fSCL= 400 kHz, tr= 300 ns) Figure 9-3. Maximum Pull-Up resistance (Rp(max)) vs Bus Capacitance (Cb) 1.8 1.6 Rp(min) (kOhm) 1.4 1.2 1 0.8 0.6 0.4 VDPUX > 2V VDPUX 2 V Figure 9-4. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX) 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 10 Power Supply Recommendations 10.1 Power-On Reset Requirements In the event of a glitch or data corruption, PCA9546A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 10-1 and Figure 10-2. VCC Ramp-Up Re-Ramp-Up Ramp-Down VCC_TRR_GND Time VCC_RT VCC_FT Time to Re-Ramp VCC_RT Figure 10-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC VCC Ramp-Down Ramp-Up VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 10-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC Table 10-1 specifies the performance of the power-on reset feature for PCA9546A for both types of power-on reset. Table 10-1. Recommended Supply Sequencing And Ramp Rates(1) PARAMETER MIN MAX UNIT 1 100 ms See Figure 10-1 0.01 100 ms See Figure 10-1 0.001 ms Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 10-2 0.001 ms VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs See Figure 10-3 VCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx See Figure 10-3 VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V VPORR Voltage trip point of POR on rising VCC 1.033 1.428 V VCC_FT Fall rate See Figure 10-1 VCC_RT Rise rate VCC_TRR_GND Time to re-ramp (when VCC drops to GND) VCC_TRR_POR50 (1) TYP 1.2 V μs TA = –40°C to 85°C (unless otherwise noted) Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide more information on how to measure these specifications. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 19 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 VCC VCC_GH Time VCC_GW Figure 10-3. Glitch Width And Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this specification. VCC VPOR VPORF Time POR Time Figure 10-4. VPOR 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 11 Layout 11.1 Layout Guidelines For PCB layout of the PCA9546A, common PCB layout practices must be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the same layer of the board with split planes to isolate different voltage potentials. To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short as possible and the widths of the traces must also be minimized (e.g. 5-10 mils depending on copper weight). 11.2 Layout Example LEGEND Partial Power Plane VIA to Power Plane Polygonal Copper Pour To I2C Master VIA to GND Plane (Inner Layer) VDPUM By-pass/De-coupling capacitors GND VCC A1 SDA RESET SCL SD0 SD1 SC1 VDPU3 A2 SC3 SD3 SC2 SD2 GND VDPU1 VDPU2 To Slave Channel 2 GND PCA9546A A0 SC0 To Slave Channel 1 VCC To Slave Channel 3 To Slave Channel 0 VDPU0 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A 21 PCA9546A www.ti.com SCPS148I – OCTOBER 2005 – REVISED JUNE 2022 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: PCA9546A PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) PCA9546ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A Samples PCA9546ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A Samples PCA9546ADW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A Samples PCA9546ADWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A Samples PCA9546APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A Samples PCA9546APWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A Samples PCA9546APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A Samples PCA9546ARGVR ACTIVE VQFN RGV 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PD546A Samples PCA9546ARGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PD546A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of