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PCA9548A
SCPS143E – JUNE 2009 – REVISED FEBRUARY 2015
PCA9548A Low Voltage 8-Channel I2C Switch With Reset
1 Features
2 Applications
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1-of-8 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Active-Low Reset Input
Three Hardware Address Pins for Use of up to
Eight PCA9548A Devices on the I2C Bus
Channel Selection Via I2C Bus
Power-Up with All Switch Channels Deselected
Low RON Switches
Allows Voltage-Level Translation Between 1.8-V,
2.5-V, 3.3-V, and 5-V Buses
No Glitch on Power Up
Supports Hot Insertion
Low Standby Current
Operating Power-Supply Voltage Range of 2.3
V to 5.5 V
5-V Tolerant Inputs
0 to 400-kHz Clock Frequency
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Servers
Routers (Telecom Switching Equipment)
Factory Automation
Products With I2C Slave Address Conflicts (e.g.
Multiple, Identical Temp Sensors)
3 Description
The PCA9548A has eight bidirectional translating
switches that can be controlled via the I2C bus. The
SCL/SDA upstream pair fans out to eight downstream
pairs, or channels. Any individual SCx/SDx channel
or combination of channels can be selected,
determined by the contents of the programmable
control register.
The system master can reset the PCA9548A in the
event of a timeout or other improper operation by
asserting a low in the RESET input. Similarly, the
power-on reset deselects all channels and initializes
the I2C/SMBus state machine. Asserting RESET
causes the same reset/initialization to occur without
powering down the part.
Device Information(1)
DEVICE NAME
PCA9548A
PACKAGE
BODY SIZE (NOM)
TSSOP (24)
7.80 mm × 4.40 mm
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCC
I2C or SMBus
Master
Channel 0
SDA
SCL
SD0
SC0
RESET
SD1
SC1
(processor)
Slaves A0, A1...AN
Channel 1
Slaves B0, B1...BN
PCA9548A
A0
A1
A2
GND
SD2
SC2
Channel 2
Slaves C0, C1...CN
Channel 7
SD7
SC7
Slaves H0, H1...HN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9548A
SCPS143E – JUNE 2009 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Switching Characteristics ..........................................
Reset Timing Requirements .....................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2
9.3
9.4
9.5
9.6
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Map...........................................................
10
11
11
11
13
10 Application and Implementation........................ 16
10.1 Application Information.......................................... 16
10.2 Typical Application ................................................ 16
11 Power Supply Recommendations ..................... 20
11.1 Power-On Reset Errata......................................... 20
12 Layout................................................................... 20
12.1 Layout Guidelines ................................................. 20
12.2 Layout Example .................................................... 21
13 Device and Documentation Support ................. 22
13.1 Trademarks ........................................................... 22
13.2 Electrostatic Discharge Caution ............................ 22
13.3 Glossary ................................................................ 22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2014) to Revision E
Page
•
Changed front page image. .................................................................................................................................................... 1
•
Added Thermal Information. ................................................................................................................................................... 4
•
Added Layout Example. ....................................................................................................................................................... 21
Changes from Revision C (June 2007) to Revision D
Page
•
Added RESET Errata section. .............................................................................................................................................. 11
•
Updated Typical Application schematic. .............................................................................................................................. 17
•
Added Power-On Reset Errata section. .............................................................................................................................. 20
2
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5 Description (continued)
The pass gates of the switches are constructed so that the VCC pin can be used to limit the maximum high
voltage, which is passed by the PCA9548A. This allows the use of different bus voltages on each pair, so that
1.8-V or 2.5-V or 3.3-V parts can communicate with 5-V parts, without any additional protection. External pull-up
resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.
6 Pin Configuration and Functions
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
RESET
A1
A0
VCC
1
VCC
SDA
SCL
A2
SC7
SD7
SC6
SD6
SC5
SD5
SC4
SD4
24 23 22 21 20 19
SD0
SC0
SD1
SC1
SD2
SC2
18 A2
17 SC7
1
2
16 SD7
15 SC6
3
4
5
14 SD6
13 SC5
6
7 8 9 10 11 12
SD3
SC3
GND
SD4
SC4
SD5
A0
A1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
GND
SDA
SCL
RGE PACKAGE
(TOP VIEW)
DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
DESCRIPTION
NAME
DW, DB, TPW, AND
DGV
QFN (RGE)
A0
1
22
Address input 0. Connect directly to VCC or ground.
A1
2
23
Address input 1. Connect directly to VCC or ground.
RESET
3
24
Active-low reset input. Connect to VCC through a pull-up resistor, if not used.
SD0
4
1
Serial data 0. Connect to VCC through a pull-up resistor.
SC0
5
2
Serial clock 0. Connect to VCC through a pull-up resistor.
SD1
6
3
Serial data 1. Connect to VCC through a pull-up resistor.
SC1
7
4
Serial clock 1. Connect to VCC through a pull-up resistor.
SC2
8
5
Serial data 2. Connect to VCC through a pull-up resistor.
SC2
9
6
Serial clock 2. Connect to VCC through a pull-up resistor.
SD3
10
7
Serial data 3. Connect to VCC through a pull-up resistor.
SC3
11
8
Serial clock 3. Connect to VCC through a pull-up resistor.
GND
12
9
Ground
SD4
13
10
Serial data 4. Connect to VCC through a pull-up resistor.
SC4
14
11
Serial clock 4. Connect to VCC through a pull-up resistor.
SD5
15
12
Serial data 5. Connect to VCC through a pull-up resistor.
SC5
16
13
Serial clock 5. Connect to VCC through a pull-up resistor.
SD6
17
14
Serial data 6. Connect to VCC through a pull-up resistor.
SC6
18
15
Serial clock 6. Connect to VCC through a pull-up resistor.
SD7
19
16
Serial data 7. Connect to VCC through a pull-up resistor.
SC7
20
17
Serial clock 7. Connect to VCC through a pull-up resistor.
A2
21
18
Address input 2. Connect directly to VCC or ground.
SCL
22
19
Serial clock bus. Connect to VCC through a pull-up resistor.
SDA
23
20
Serial data bus. Connect to VCC through a pull-up resistor.
VCC
24
21
Supply voltage
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SCPS143E – JUNE 2009 – REVISED FEBRUARY 2015
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage
–0.5
7
(2)
–0.5
V
VI
Input voltage
II
Input current
±20
mA
IO
Output current
±25
mA
ICC
Supply current
±100
mA
Tstg
Storage temperature range
150
°C
(1)
(2)
7
UNIT
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
(1)
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
6
A2–A0, RESET
0.7 × VCC
VCC + 0.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, RESET
–0.5
0.3 × VCC
–40
85
UNIT
V
V
V
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
PCA9548A
THERMAL METRIC
(1)
DB
DGV
DW
PW
RGE
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
89.1
99.6
73.2
100.6
49.5
RθJC(to
Junction-to-case (top) thermal resistance
51.1
31.1
41.3
46.2
53.2
RθJB
Junction-to-board thermal resistance
46.6
53.1
42.9
54.5
26.4
ψJT
Junction-to-top characterization parameter
18.5
0.9
15.3
6.8
1.7
ψJB
Junction-to-board characterization parameter
46.3
52.6
42.6
54.0
26.4
RθJC(b
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
N/A
8.5
p)
°C/W
ot)
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SCPS143E – JUNE 2009 – REVISED FEBRUARY 2015
7.5 Electrical Characteristics
VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Power-on reset voltage (2)
VPOR
TEST CONDITIONS
No load, VI = VCC or GND
VCC
MIN TYP (1)
MAX
VPOR
1.6
2.1
5V
Switch output voltage
Vi(sw) = VCC, ISWout = –100 μA
2.6
3.3 V
3 V to 3.6 V
VOL = 0.4 V
SDA
VOL = 0.6 V
2.3 V to 5.5 V
4.5
1.9
1.6
2.5 V
2.3 V to 2.7 V
IOL
2.8
2
3
6
6
9
A2–A0
VI = VCC or GND
±1
2.3 V to 5.5 V
±1
RESET
VI = VCC or GND, IO = 0
Operating mode
fSCL = 100 kHz
VI = VCC or GND, IO = 0
ICC
Low inputs
VI = GND, IO = 0
Standby mode
High inputs
SCL, SDA
A2–A0
Ci
RESET
SCL
Cio(off)
RON
(3)
SDA
SC7–SC0, SD7–SD0
Switch-on resistance
VI = VCC, IO = 0
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
5.5 V
50
80
3.6 V
20
35
2.7 V
11
20
5.5 V
9
30
3.6 V
6
15
2.7 V
4
8
5.5 V
0.2
1
3.6 V
0.1
1
2.7 V
0.1
1
5.5 V
0.2
1
3.6 V
0.1
1
2.7 V
0.1
1
3
20
3
20
4
5
4
5
20
28
VI = VCC or GND, Switch OFF
VO = 0.4 V, IO = 15 mA
μA
μA
2.3 V to 5.5 V
2.3 V to 5.5 V
VI = VCC or GND, Switch OFF
VO = 0.4 V, IO = 10 mA
(1)
(2)
(3)
μA
±1
fSCL = 400 kHz
Supply-current
change
mA
±1
SC7–SC0, SD7–SD0
ΔICC
V
1.5
1.1
SCL, SDA
II
V
3.6
4.5 V to 5.5 V
Vo(sw)
UNIT
2.3 V to 5.5 V
20
28
5.5
7.5
4.5 V to 5.5 V
4
10
20
3 V to 3.6 V
5
12
30
2.3 V to 2.7 V
7
15
45
pF
pF
Ω
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device.
Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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7.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
FAST MODE
I2C BUS
MAX
0
400
50
250
100
(1)
(1)
0
μs
1.3
50
ns
ns
μs
tsdh
I C serial-data hold time
ticr
I2C input rise time
1000
20 + 0.1Cb
(2)
300
ns
ticf
I2C input fall time
300
20 + 0.1Cb
(2)
300
ns
tocf
I2C output (SDn) fall time (10-pF to 400-pF bus)
300
20 + 0.1Cb
(2)
300
ns
2
0
kHz
μs
0.6
4.7
2
UNIT
MIN
tbuf
I C bus free time between stop and start
4.7
1.3
μs
tsts
I2C start or repeated start condition setup
4.7
0.6
μs
tsth
I2C start or repeated start condition hold
4
0.6
μs
2
tsps
I C stop condition setup
tvdL(Data)
Valid-data time (high to low) (3)
SCL low to SDA output low valid
tvdH(Data)
Valid-data time (low to high) (3)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
2
Cb
(1)
(2)
(3)
4
I C bus capacitive load
μs
0.6
1
1
μs
0.6
0.6
μs
1
1
μs
400
400
pF
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
Cb = total bus capacitance of one bus line in pF
Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 2)
7.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
(1)
trst
(2)
(1)
(2)
Propagation delay time
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
RESET time (SDA clear)
FROM
(INPUT)
TO
(OUTPUT)
SDA or SCL
SDn or SCn
RESET
SDA
MIN
MAX
0.3
1
500
UNIT
ns
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.
7.8 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
tW(L)
Pulse duration, RESET low
6
ns
tREC(STA)
Recovery time from RESET to start
0
ns
6
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8 Parameter Measurement Information
VCC
R L = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Address
Stop
Start
Bit 7 Address
Condition Condition
Bit 6
(MSB)
(P)
(S)
R/W
Bit 0
(LSB)
Address
Bit 1
tscl
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCC
SCL
0.3 ´ VCC
ticr
tvd(ack)
ticf
tbuf
tsp
tsts
tvdH(Data)
0.7 ´ VCC
SDA
0.3 ´ VCC
ticr
ticf
tsth
tvdL(Data)
tsdh
tsds
tsps
Repeat Start
Condition
Start or
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I C address
2, 3
P-port data
2
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
Not all parameters and waveforms are applicable to all devices.
Figure 1. I2C Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
RL = 1 kW
DUT
SDA
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3
VCC
tRESET
RESET
VCC/2
tREC
tw
SDn, SCn
0.3
VCC
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
I/Os are configured as inputs.
D.
Not all parameters and waveforms are applicable to all devices.
Figure 2. Reset Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The PCA9548A is a 8-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to
eight channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well
as any combination of the eight channels.
The device offers an active-low RESET input which resets the state machine and allows the PCA9548A to
recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can
also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function
and a POR will cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected
channels.
The PCA9548A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
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9.2 Functional Block Diagram
PCA9548A
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Switch Control Logic
GND
VCC
RESET
SCL
Reset Circuit
A0
Input Filter
SDA
2
I C Bus Control
A1
A2
10
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9.3 Feature Description
The PCA9548A is an 8-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The PCA9548A features I2C control using a single 8-bit control register
in which each bit controls the enabling and disabling for one of the 8 switch channels of I2C data flow. Depending
on the application, voltage translation of the I2C bus can also be achieved using the PCA9548A to allow 1.8-V,
2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on the I2C bus
enters a fault state, the PCA9548A can be reset to resume normal operation using the RESET pin feature or by
a power-on reset which results from cycling power to the device.
9.4 Device Functional Modes
9.4.1
RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the PCA9548A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to VCC through a pull-up resistor.
9.4.1.1 RESET Errata
If RESET voltage set higher than VCC, current will flow from RESET pin to VCC pin.
System Impact
VCC will be pulled above its regular voltage level
System Workaround
Design such that RESET voltage is same or lower than VCC
9.4.2 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9548A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9548A registers and I2C
state machine initialize to their default states. After that, VCC must be lowered to below VPOR and then back up to
the operating voltage for a power-reset cycle.
Refer to the Power-On Reset Errata section.
9.5 Programming
9.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 3). After the start condition, the device address byte
is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 4).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 3).
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Programming (continued)
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 5). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 3. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 4. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 5. Acknowledgment on I2C Bus
12
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9.6 Register Map
9.6.1 Device Address
Figure 6 shows the address byte of the PCA9548A.
Slave Address
1
1
1
Fixed
0
A2
A1
A0 R/W
Hardware
Selectable
Figure 6. PCA9548A Address
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
Table 1. Address Reference
INPUTS
A0
I2C BUS SLAVE ADDRESS
A2
A1
L
L
L
112 (decimal), 70 (hexadecimal)
L
L
H
113 (decimal), 71 (hexadecimal)
L
H
L
114 (decimal), 72 (hexadecimal)
L
H
H
115 (decimal), 73 (hexadecimal)
H
L
L
116 (decimal), 74 (hexadecimal)
H
L
H
117 (decimal), 75 (hexadecimal)
H
H
L
118 (decimal), 76 (hexadecimal)
H
H
H
119 (decimal), 77 (hexadecimal)
9.6.2 Control Register
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9548A (see Figure 7). This register can be written and read via the I2C
bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel.
Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are
received by the PCA9548A, it saves the last byte received.
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Channel Selection Bits (Read/Write)
B7
B6
B5
B4
B3
B2
B1
B0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Figure 7. Control Register
Table 2. Command Byte Definition
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
X
X
0
Channel 0 enabled
X
X
1
1
X
X
0
Channel 0 disabled
X
X
X
0
1
X
0
1
0
1
X
0
1
0
1
1
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COMMAND
0
X
X
X
X
0
B0
Channel 1 disabled
Channel 1 enabled
Channel 2 disabled
Channel 2 enabled
Channel 3 disabled
Channel 3 enabled
Channel 4 disabled
Channel 4 enabled
Channel 5 disabled
Channel 5 enabled
Channel 6 disabled
Channel 6 enabled
Channel 7 disabled
Channel 7 enabled
No channel selected, power-up/reset
default state
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9.6.3 Bus Transactions
Data is exchanged between the master and PCA9548A through write and read commands.
9.6.3.1 Writes
Data is transmitted to the PCA9548A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 6 for device address). The command byte is sent after the address and determines which
SCn/SDn channel receives the data that follows the command byte (see Figure 8). There is no limitation on the
number of data bytes sent in one write transmission.
Slave Address
SDA
S
1
1
1
0
Control Register
A2 A1 A0
Start Condition
0
A
B7
B6 B5
B4 B3 B2 B1 B0
R/W ACK From Slave
A
ACK From Slave
P
Stop Condition
Figure 8. Write to Control Register
9.6.3.2 Reads
The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see Figure 6 for device
address). The command byte is sent after the address and determines which SCn/SDn channel is accessed.
After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the SCn/SDn
channel defined by the command byte then is sent by the PCA9548A (see Figure 9). After a restart, the value of
the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed when the
restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse. There is
no limitation on the number of data bytes received in one read transmission, but when the final byte is received,
the bus master must not acknowledge the data.
Slave Address
SDA
S
1
1
1
0
Control Register
A2 A1 A0
Start Condition
1
R/W
A
B7
B6 B5
B4 B3
ACK From Slave
B2 B1 B0 NA
NACK From Master
P
Stop Condition
Figure 9. Read From Control Register
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Applications of the PCA9548A will contain an I2C (or SMBus) master device and up to eight I2C slave devices.
The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if eight identical
digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2,
and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled
and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus will contain many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across multiple channels. If multiple switches will be enabled simultaneously, additional design
requirements must be considered (See Design Requirements and Detailed Design Procedure).
10.2 Typical Application
A typical application of the PCA9548A will contain 1 or many separate data pull-up voltages, VCC , one for the
master device and one for each of the selectable slave channels, 0 through 7. In the event where the master
device and all slave devices operate at the same voltage, then the VCC pin can be connected to this supply
voltage. In an application where voltage translation is necessary, additional design requirements must be
considered (See Design Requirements).
Figure 10 shows an application in which the PCA9548A can be used.
16
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Typical Application (continued)
VCC = 2.7 V to 5.5 V
VCC = 3.3 V
VCC = 2.7 V to 5.5 V
24
I2C/SMBus
Master
SDA
SCL
RESET
23
22
3
See Note A
SDA
SD0
SCL
SC0
4
Channel 0
5
VCC = 2.7 V to 5.5 V
RESET
See Note A
SD1
6
SC1
7
Channel 1
VCC = 2.7 V to 5.5 V
See Note A
SD2
SC2
8
Channel 2
9
VCC = 2.7 V to 5.5 V
See Note A
SD3
SC3
10
Channel 3
11
VCC = 2.7 V to 5.5 V
PCA9548A
See Note A
SD4
SC4
13
Channel 4
14
VCC = 2.7 V to 5.5 V
See Note A
SD5
15
SC5
16
Channel 5
VCC = 2.7 V to 5.5 V
See Note A
SD6
SC6
21
2
1
12
A.
17
Channel 6
18
VCC = 2.7 V to 5.5 V
A2
See Note A
A1
A0
SD7
GND
SC7
19
Channel 7
20
Pin numbers shown are for the PW and RTW packages.
Figure 10. PCA9548A Typical Application Schematic
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Typical Application (continued)
10.2.1 Design Requirements
The A0, A1, and A2 pins are hardware selectable to control the slave address of the PCA9548A. These pins may
be tied directly to GND or VCC in the application.
If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side will be the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 11 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics section of this data sheet). In order for the PCA9548A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 11, Vpass(max) is 2.7 V when the PCA9548A
supply voltage is 4 V or lower, so the PCA9548A supply voltage could be set to 3.3 V. Pull-up resistors then can
be used to bring the bus voltages to their appropriate levels (see Figure 10).
10.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of the reference voltage of the specific I2C channel (VDPUX), VOL,(max), and IOL:
VDPUX - VOL(max)
Rp(min) =
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the PCA9548A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels
will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance.
18
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Typical Application (continued)
10.2.3 PCA9548A Application Curves
25
5
Standard-mode
Fast-mode
4.5
ISWout = -100 mA
20
Maximum
Rp(max) (kOhm)
4
Vpass (V)
3.5
Typical
3
2.5
2
15
10
Minimum
5
1.5
1
2
2.5
3
3.5
4
4.5
5
5.5
Space
spacespace
0
0
VCC (V)
Space
spacespace
50
100
150
200
250
Cb (pF)
Standard-mode
(fSCL= 100 kHz, tr = 1 µs)
Figure 11. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
300
350
400
450
D008
Fast-mode
(fSCL= 400 kHz, tr= 300 ns)
Figure 12. Maximum Pull-Up resistance (Rp(max)) vs Bus
Capacitance (Cb)
1.8
1.6
Rp(min) (kOhm)
1.4
1.2
1
0.8
0.6
0.4
VDPUX > 2V
VDPUX 2 V
Figure 13. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX)
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11 Power Supply Recommendations
The operating power-supply voltage range of the PCA9548A is 2.3 V to 5.5 V applied at the VCC pin. When the
PCA9548A is powered on for the first time or anytime the device needs to be reset by cycling the power supply,
the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly.
11.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
12 Layout
12.1 Layout Guidelines
For PCB layout of the PCA9548A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours
and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM and VDPU0-VDPU7 may all be on the same layer of the
board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) should be a short as
possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper weight).
20
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12.2 Layout Example
LEGEND
Partial Power Plane
(inner layer)
To I2C Master
Copper Pour
(outer layer)
Via to Power Plane
Via to GND Plane
By-pass/de-coupling
capacitors
VDPU2
2
23
SDA
RESET
3
22
SCL
SD0
4
21
A2
SC0
5
20
SC7
SD1
6
19
SD7
SC1
7
18
SC6
SD2
8
17
SD6
SC2
9
16
SC5
SD3
10
15
SD5
SC3
11
14
SC4
GND
12
13
SD4
A1
PW package
PCA9548A
To Slave Channel 1
VDPU1
VCC
1
VDPU7
VDPU6
VDPU5
To Slave Channel 5
To Slave Channel 2
VDPU0
24
A0
To Slave Channel 6
VDPU3
GND
VDPU4
To Slave Channel 4
To Slave Channel 3
VCC
GND
To Slave Channel 7
To Slave Channel 0
VDPUM
Figure 14. Layout Example
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13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCA9548ADB
ACTIVE
SSOP
DB
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADBG4
ACTIVE
SSOP
DB
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADBR
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADGV
NRND
TVSOP
DGV
24
TBD
Call TI
Call TI
-40 to 85
PCA9548ADGVR
ACTIVE
TVSOP
DGV
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9548A
PCA9548ADWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9548A
PCA9548ADWR
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9548A
PCA9548APW
NRND
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548APWR
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548APWRG4
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ARGER
NRND
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD548A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.8
2.5
12.0
16.0
Q1
PCA9548ADBR
SSOP
DB
24
2000
330.0
16.4
PCA9548ADGVR
TVSOP
DGV
24
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
PCA9548ADWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
PCA9548APWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
PCA9548ARGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9548ADBR
SSOP
DB
24
2000
367.0
367.0
38.0
PCA9548ADGVR
TVSOP
DGV
24
2000
367.0
367.0
35.0
PCA9548ADWR
SOIC
DW
24
2000
367.0
367.0
45.0
PCA9548APWR
TSSOP
PW
24
2000
367.0
367.0
38.0
PCA9548ARGER
VQFN
RGE
24
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 2.5
2.1±0.1
(0.2) TYP
12
7
20X 0.5
6
13
25
2X
2.5
SYMM
1
PIN 1 ID
(OPTIONAL)
18
24X 0.30
0.18
24
19
SYMM
24X 0.50
0.30
0.1
0.05
C A B
C
4224376 / A 07/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
(
2.1)
19
24
24X (0.6)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.8)
2X
(0.8)
(Ø0.2) VIA
TYP
6
13
(R0.05)
12
7
2X(0.8)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224376 / A 07/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(0.19)
4X ( 0.94)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.8)
(0.57)
TYP
6
13
(R0.05) TYP
METAL
TYP
25
7
SYMM
12
(0.57)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
4224376 / A 07/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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