PCA9554
PCA9554
SCPS128D – JULY 2006 – REVISED MARCH
2021
SCPS128D – JULY 2006 – REVISED MARCH 2021
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PCA9554 Remote 8-Bit I2C AND SMBus I/O Expander With Interrupt Output and
Configuration Registers
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 Description
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
Operating Power-Supply Voltage Range of 2.3 V to
5.5 V
5-V Tolerant I/Os
400-kHz Fast I2C Bus
Three Hardware Address Pins Allow up to Eight
Devices on the I2C/SMBus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power-Up With All Channels Configured as Inputs
No Glitch On Power Up
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per JESD
78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This 8-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC operation.
It provides general-purpose remote I/O expansion for
most microcontroller families via the I2C interface
[serial clock (SCL), serial data (SDA)].
The PCA9554 consists of one 8-bit Configuration
(input or output selection), Input, Output, and Polarity
Inversion (active high or active low) registers. At
power on, the I/Os are configured as inputs with a
weak pullup to VCC. However, the system master can
enable the I/Os as either inputs or outputs by writing
to the I/O configuration bits. The data for each input
or output is kept in the corresponding Input or Output
register. The polarity of the Input Port register can
be inverted with the Polarity Inversion register. All
registers can be read by the system master.
The system master can reset the PCA9554 in the
event of a timeout or other improper operation by
utilizing the power-on reset feature, which puts the
registers in their default state and initializes the I2C/
SMBus state machine.
The PCA9554 open-drain interrupt ( INT) output
is activated when any input state differs from its
corresponding Input Port register state and is used to
indicate to the system master that an input state has
changed.
Device Information (1)
PART NUMBER
PACKAGE
PCA9554
14
4
13
5
12
6
11
7
10
8
9
3.00 mm × 3.00 mm
RGT PACKAGE
(TOP VIEW)
SDA
A0
VCC
4.00 mm × 4.00 mm
QFN (16)
A1
A0
VCC
SDA
3
VCC
SDA
SCL
INT
P7
P6
P5
P4
16 15 14 13
A2 1
12 SCL
P0 2
11
P1 3
10 P7
P2 4
INT
9 P6
5
6
7
8
P5
15
P4
16
2
P3
1
GND
A0
A1
A2
P0
P1
P2
P3
GND
VQFN (16)
For all available packages, see the orderable addendum at
the end of the datasheet.
RGV PACKAGE
(TOP VIEW)
A1
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
6.20 mm × 5.30 mm
A2
P0
P1
P2
16 15 14 13
12 SCL
11 INT
2
3
10 P7
9 P6
4
5 6 7 8
1
P3
GND
P4
P5
(1)
BODY SIZE (NOM)
SSOP (16)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SCPS128D – JULY 2006 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Description (Continued)..................................................3
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 I2C Interface Timing Requirements.............................8
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................14
8.1 Functional Block Diagram......................................... 14
8.2 Device Functional Modes..........................................15
8.3 Programming............................................................ 16
9 Application Information Disclaimer............................. 22
9.1 Application Information............................................. 22
10 Power Supply Recommendations..............................24
10.1 Power-On Reset Requirements.............................. 24
11 Device and Documentation Support..........................26
11.1 Receiving Notification of Documentation Updates.. 26
11.2 Support Resources................................................. 26
11.3 Trademarks............................................................. 26
11.4 Electrostatic Discharge Caution.............................. 26
11.5 Glossary.................................................................. 26
12 Mechanical, Packaging, and Orderable
Information.................................................................... 26
3 Revision History
Changes from Revision C (May 2021) to Revision D (March 2021)
Page
• Moved the "Storage temperature range" to the Absolute Maximum Ratings .................................................... 5
• Moved the "Package thermal impedance" to the Thermal Resistance Characteristic .......................................5
• Changed the VIH High-level input voltage (SDL, SDA) Max value From: 5.5 V To: VCC in the Recommended
Operating Conditions ......................................................................................................................................... 5
• Changed the VIH High-level input voltage (A0, A1, A2, P7–P0) MIN value From: 5.5 V To: 0.7 x VCC in the
Recommended Operating Conditions ................................................................................................................5
• Changed the VIL Low-level input voltage (A0, A1, A2, P7–P0) MAX value From: 0.8 V To: 0.3 x VCC in the
Recommended Operating Conditions ................................................................................................................5
• Added the Thermal Information table................................................................................................................. 6
• Changed VPORR in the Electrical Characteristics ...............................................................................................6
• Added VPORF to the Electrical Characteristics ................................................................................................... 6
• Changed the ICC Standby mode values in the Electrical Characteristics ...........................................................6
• Changed the Ci SCL Max value From: 5 pF To: 8 pF in the Electrical Characteristics ......................................6
• Changed the Cio SDA Max value From: 6.5 pF To: 9.5 pF in the Electrical Characteristics .............................. 6
• Changed the tpv Output data valid MAX values From: 200 ns To 350 ns in the Swirtching Characteristics ...... 8
• Changed the Typical Characteristics graphs...................................................................................................... 9
• Changed the Power Supply Recommendations .............................................................................................. 24
Changes from Revision B (August 2008) to Revision C (May 2014)
Page
• Added Interrupt Errata section..........................................................................................................................16
2
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4 Description (Continued)
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9554 can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current
consumption.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus.
The PCA9554 is pin-to-pin and I2C address compatible with the PCF8574. However, software changes are
required, due to the enhancements in the PCA9554 over the PCF8574.
The PCA9554 and PCA9554A are identical except for their fixed I2C address. This allows for up to 16 of these
devices (eight of each) on the same I2C/SMBus.
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SCPS128D – JULY 2006 – REVISED MARCH 2021
5 Pin Configuration and Functions
4
13
5
12
6
11
7
10
8
9
SDA
VCC
A1
A0
VCC
SDA
14
RGT PACKAGE
(TOP VIEW)
16 15 14 13
A2 1
12 SCL
P0 2
11
P1 3
10 P7
P2 4
INT
9 P6
5
6
7
8
A2
P0
P1
P2
16 15 14 13
12 SCL
11 INT
2
3
10 P7
9 P6
4
5 6 7 8
1
P3
GND
P4
P5
3
VCC
SDA
SCL
INT
P7
P6
P5
P4
P5
15
P4
16
2
GND
1
P3
A0
A1
A2
P0
P1
P2
P3
GND
A0
RGV PACKAGE
(TOP VIEW)
A1
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Table 5-1. Pin Functions
PIN
NAME
4
QSOP (DBQ)
SOIC (DW),
SSOP (DB),
TSSOP (PW), AND
TVSOP (DGV)
DESCRIPTION
QFN (RGT) AND
QFN (RGV)
A0
1
15
Address input. Connect directly to VCC or ground.
A1
2
16
Address input. Connect directly to VCC or ground.
A2
3
1
Address input. Connect directly to VCC or ground.
P0
4
2
P-port input/output. Push-pull design structure.
P1
5
3
P-port input/output. Push-pull design structure.
P2
6
4
P-port input/output. Push-pull design structure.
P3
7
5
P-port input/output. Push-pull design structure.
GND
8
6
Ground
P4
9
7
P-port input/output. Push-pull design structure.
P5
10
8
P-port input/output. Push-pull design structure.
P6
11
9
P-port input/output. Push-pull design structure.
P7
12
10
P-port input/output. Push-pull design structure.
INT
13
11
Interrupt output. Connect to VCC through a pullup resistor.
SCL
14
12
Serial clock bus. Connect to VCC through a pullup resistor.
SDA
15
13
Serial data bus. Connect to VCC through a pullup resistor.
VCC
16
14
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6
UNIT
V
range(2)
–0.5
6
V
–0.5
6
V
VI
Input voltage
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
ICC
Tstg
(1)
(2)
–50
mA
Continuous current through GND
–250
mA
Continuous current through VCC
160
mA
150
°C
Storage temperature range
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
MIN
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
Supply voltage
SCL, SDA
MIN
MAX
2.3
5.5
0.7 × VCC
(1)
VCC
UNIT
V
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P7–P0
–10
mA
IOL
Low-level output current
P7–P0
25
mA
TA
Operating free-air temperature
85
°C
(1)
A2–A0, P7–P0
2
VCC
SCL, SDA
–0.5
0.3 × VCC
A2–A0, P7–P0
–0.5
0.3 × VCC
–40
V
V
For voltages applied above VCC, an increase in ICC will result.
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6.4 Thermal Information
PCA9538
DB
(SSOP)
DBQ
(SSOP)
DGV
(TVSOP)
16 PINS
16 PINS
16 PINS
113.2
121.7
120
THERMAL METRIC(1)
RθJA
(1)
Junction-to-ambient thermal resistance
DW
(SOIC)
PW
(TSSOP)
16 PINS
16 PINS
57
UNIT
63.2
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage II = –18 mA
VPORR
Power-on reset voltage,
VCC rising
VI = VCC or GND, IO = 0
VPORF
Power-on reset voltage,
VCC falling
VI = VCC or GND, IO = 0
IOH = –8 mA
VOH
P-port high-level output
voltage(2)
IOH = –10 mA
SDA
VOL = 0.4 V
VOL = 0.5 V
IOL
P port(3)
VOL = 0.7 V
INT
II
6
SCL, SDA
A2–A0
VCC
MIN
2.3 V to 5.5 V
–1.2
TYP(1)
2.3 V
1.8
3V
2.6
4.5 V
3.1
4.75 V
4.1
2.3 V
1.7
3V
2.5
4.5 V
3
UNIT
V
1.2
0.75
MAX
1.5
1
V
V
V
4.75 V
4
2.3 V to 5.5 V
3
8
2.3 V
8
10
3V
8
14
4.5 V
8
17
4.75 V
8
35
2.3 V
10
13
3V
10
19
4.5 V
10
24
4.75 V
10
45
VOL = 0.4 V
2.3 V to 5.5 V
3
10
VI = VCC or GND
2.3 V to 5.5 V
mA
±1
±1
μA
IIH
P port
VI = VCC
2.3 V to 5.5 V
1
μA
IIL
P port
VI = GND
2.3 V to 5.5 V
–100
μA
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = VCC, IO = 0, I/O = inputs,
fscl = 400 kHz, No load
Operating mode
VI = VCC, IO = 0, I/O = inputs,
fscl = 100 kHz, No load
ICC
VI = GND, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
Standby mode
VI = VCC, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
ΔICC
Ci
Cio
(1)
(2)
(3)
Additional current in
standby mode
SCL
SDA
P port
TYP(1)
MAX
5.5 V
104
175
3.6 V
50
90
2.7 V
20
65
5.5 V
60
150
3.6 V
15
40
VCC
2.7 V
8
20
5.5 V
450
700
3.6 V
300
600
2.7 V
225
500
5.5 V
1.9
3.5
3.6 V
1.1
1.8
2.7 V
1
1.6
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
Every LED I/O at VI = 4.3 V,
fscl = 0 kHz
5.5 V
VI = VCC or GND
VIO = VCC or GND
MIN
UNIT
μA
1.5
mA
2.3 V to 5.5 V
2.3 V to 5.5 V
1
4
8
5.5
9.5
8
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA.
Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200
mA.
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6.6 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
STANDARD MODE
I2C BUS
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
tsdh
I2C serial-data hold time
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time
clock high time
FAST MODE
I2C BUS
MAX
MIN
MAX
0
100
0
400
4
0.6
μs
1.3
μs
50
50
100
0
input fall time
10-pF to 400-pF bus
tbuf
tsts
I2C start or repeated start condition setup
tsth
ns
ns
0
ns
1000
20 + 0.1Cb (1)
300
ns
300
20 + 0.1Cb
(1)
300
ns
300
20 + 0.1Cb (1)
300
ns
4.7
1.3
μs
4.7
0.6
μs
I2C start or repeated start condition hold
4
0.6
μs
tsps
I2C stop condition setup
4
0.6
μs
tvd(data)
Valid data time
SCL low to SDA output
valid
300
50
ns
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low
to SDA (out) low
0.3
Cb
I2C bus capacitive load
(1)
bus free time between stop and start
kHz
4.7
250
I2C
UNIT
MIN
3.45
0.1
400
0.9
μs
400
ns
Cb = Total capacitive load of one bus in pF
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 7-2 and Figure 7-3)
PARAMETER
8
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
4
4
μs
SCL
INT
4
4
μs
350
ns
MIN
MAX
MIN
UNIT
MAX
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid
SCL
P7–P0
tps
Input data setup time
P port
SCL
100
100
ns
tph
Input data hold time
P port
SCL
1
1
μs
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
22
1.8
1.8 V
2.5 V
3.3 V
5V
ICC - Supply Current (µA)
18
16
1.6
ICC - Supply Current (µA)
20
14
12
10
8
6
4
0
-40
-15
10
35
60
TA - Free-Air Temperature (°C)
fSCL = 400 kHz
1
0.8
1.8 V
2.5 V
3.3 V
5V
0.6
0.4
0
-40
85
-15
D001
fSCL = 0 kHz
I/Os = High or Low Inputs
10
35
60
TA - Free-Air Temperature (°C)
85
D002
I/Os = High Inputs
Figure 6-2. Supply Current (ICC, Standby Mode) vs Temperature
(TA) at Four Supply Voltages
Figure 6-1. Supply Current (ICC, Operating Mode) vs
Temperature (TA) at Four Supply Voltages
25
250
VOL - Output Low Voltage (mV)
ICC - Supply Current (µA)
1.2
0.2
2
20
15
10
5
0
0.5
1
fSCL = 400 kHz
1.5
2
2.5
3
3.5
4
VCC - Supply Voltage (V)
I/Os = High or Low
Inputs
4.5
5
200
150
100
VCC
VCC
VCC
VCC
50
0
-40
0
5.5
-15
D003
=
=
=
=
1.8 V, IOL = 8 mA
5 V, IOL = 8 mA
1.8 V, IOL = 10 mA
5 V, IOL = 10 mA
10
35
60
TA - Free-Air Temperature (°C)
85
D004
I/Os = High or Low Inputs
TA = 25°C
Figure 6-3. Supply Current (ICC, Operating Mode) vs Supply
Voltage (VCC)
Figure 6-4. Output Low Voltage (VOL) vs Temperature (TA) for
P-Port I/Os
80
500
1.8 V
2.5 V
3.3 V
5V
70
60
(VCC - VOH) - Output High Voltage (mV)
IOL - Output Sink Current (mA)
1.4
50
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VOL - Output Low Voltage - (V)
0.7
0.8
450
400
VCC
VCC
VCC
VCC
=
=
=
=
1.8 V, IOH = 8 mA
5 V, IOH = 8 mA
1.65 V, IOH = 10 mA
5 V, IOH = 10 mA
350
300
250
200
150
100
50
0
-40
D005
-15
10
35
60
TA - Free-Air Temperature (°C)
85
D006
Figure 6-6. Output High Voltage (VCC – VOH) vs Temperature (TA)
for P-Ports
TA = 25°C
Figure 6-5. Sink Current (IOL) vs Output Low Voltage (VOL) for
P-Ports at Four Supply Voltages
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
6
1.8 V
2.5 V
3.3 V
5V
60
50
VOH - Output High Voltage (V)
IOH - Output Source Current (mA)
70
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
(VCC - VOH) - Output High Voltage (V)
0.7
5
4
3
2
1
IOH = -8 mA
IOH = -10 mA
0
0.8
0
1
TA = 25°C
5
6
D008
TA = 25°C
Figure 6-7. Source Current (IOH) vs Output High Voltage (VOH)
for P-Ports at Four Supply Voltages
Figure 6-8. Output High Voltage (VOH) vs Supply Voltage (VCC)
for P-Ports
18
600
550
500
15
450
400
Delta ICC (µA)
ICC Supply Current (PA)
2
3
4
VCC - Supply Voltage (V)
D007
350
300
250
200
150
25qC
85qC
-40qC
100
50
1.65 V
1.8 V
2.5 V
3.3 V
5V
5.5 V
12
9
6
3
0
0
1
2
3
4
5
6
Number of I/Os Held Low (#)
7
8
D001
VCC = 5 V
Figure 6-9. Supply Current (ICC) vs Number of I/Os Held Low (#)
10
0
-40
-15
10
35
TA - Temperature (°C)
60
85
D019
Figure 6-10. Δ ICC vs Temperature for Different VCC (VI = VCC –
0.6 V)
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
tPHL
ticf
tbuf
tsts
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 7-1. I2C Interface Load Circuit And Voltage Waveforms
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VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Bytes)
From Port
R/W
Slave Address
S
0
1
0
0 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
SCL
0.3 × VCC
Data 2
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
1.5 V
0.3 × VCC
INT
0.3 × VCC
View A−A
View B−B
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 7-2. Interrupt Load Circuit And Voltage Waveforms
12
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500 W
Pn
2 × VCC
DUT
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P0
A
P7
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P0
A
tps
P7
0.3 × VCC
tph
0.7 × VCC
1.5 V
0.3 × VCC
Pn
READ MODE (R/W = 1)
A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
tpv is measured from 0.7 × VCC on SCL to 50% I/O pin output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 7-3. P-Port Load Circuit And Voltage Waveforms
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8 Detailed Description
8.1 Functional Block Diagram
INT
A0
A1
A2
SCL
SDA
13
Interrupt
Logic
LP Filter
1
2
3
14
15
Input
Filter
I2C Bus
Control
P7−P0
Shift
Register
8 Bits
I/O
Port
Write Pulse
VCC
GND
16
8
Power-On
Reset
Read Pulse
A. Pin numbers shown are for the DB, DBQ, DGV, DW, N, or PW package.
B. All I/Os are set to inputs at reset.
Figure 8-1. Logic Diagram
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Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
Configuration
Register
VCC
Q1
Q
D
FF
Write Configuration
Pulse
100 kW
D
CK Q
Q
FF
Write Pulse
P0 to P7
CK Q
Q2
Output Port
Register
Input Port
Register
D
Q
FF
Read Pulse
GND
Input Port
Register Data
CK Q
INT
Data From
Shift Register
D
Q
Polarity
Register Data
FF
Write Polarity
Pulse
CK Q
Polarity
Inversion
Register
A. At power-on reset, all registers return to default values.
Figure 8-2. Simplified Schematic Of P0 To P7
8.2 Device Functional Modes
8.2.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9554 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9554 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
8.2.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 8-2) are off, which creates a high-impedance
input with a weak pullup (100 kΩ typ) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register.
In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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8.2.3 Interrupt Output ( INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv,
the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the
original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting
of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause
an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the
pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC.
8.2.3.1 Interrupt Errata
Description
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I2C command byte (register pointer) written to the device was 00h.
Note
This generally means the last operation with the device was a Read of the input register. However,
the command byte may have been written with 00h without ever going on to read the input register.
After reading from the device, if no other command byte written, it will remain 00h.
2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high
8.2.3.1.1
System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
8.2.3.1.2
System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9554 device or before reading from another slave device.
Note
Software change will be compatible with other versions (competition and TI redesigns) of this device.
8.3 Programming
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 8-3). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
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On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 8-4).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 8-3).
Any number of data bytes can be transferred from the transmitter to the receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure
8-5). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times
must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 8-3. Definition Of Start And Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 8-4. Bit Transfer
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Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 8-5. Acknowledgment On The I2C Bus
8.3.2 Register Map
Table 8-1. Interface Definition
BYTE
I2C
BIT
7 (MSB)
slave address
Px I/O data bus
6
5
4
3
2
1
0 (LSB)
L
H
L
L
A2
A1
A0
R/ W
P7
P6
P5
P4
P3
P2
P1
P0
8.3.2.1 Device Address
Figure 8-6 shows the address byte for the PCA9554.
Slave Address
0
1
0
Fixed
0
A2
A1
A0 R/W
Hardware
Selectable
Figure 8-6. PCA9554 Address
Table 8-2. Address Reference
INPUTS
A0
I2C BUS SLAVE ADDRESS
A2
A1
L
L
L
32 (decimal), 20 (hexadecimal)
L
L
H
33 (decimal), 21 (hexadecimal)
L
H
L
34 (decimal), 22 (hexadecimal)
L
H
H
35 (decimal), 23 (hexadecimal)
H
L
L
36 (decimal), 24 (hexadecimal)
H
L
H
37 (decimal), 25 (hexadecimal)
H
H
L
38 (decimal), 26 (hexadecimal)
H
H
H
39 (decimal), 27 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
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8.3.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9554. Two bits of this command byte state the operation (read or write)
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can
be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by readsuntil a
new command byte has been sent.
0
0
0
0
0
0
B1
B0
Figure 8-7. Control Register Bits
Table 8-3. Command Byte
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0x00
Input Port Register
Read byte
XXXX XXXX
0
1
0x01
Output Port Register
Read/write byte
1111 1111
1
0
0x02
Polarity Inversion Register
Read/write byte
0000 0000
1
1
0x03
Configuration Register
Read/write byte
1111 1111
8.3.2.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin
is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Table 8-4. Register 0 (Input Port Register) Table
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 8-5. Register 1 (Output Port Register) Table
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Table 8-6. Register 2 (Polarity Inversion Register) Table
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
0
0
0
0
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to
1, the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
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Table 8-7. Register 3 (Configuration Register) Table
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
8.3.2.4 Bus Transactions
Data is exchanged between the master and PCA9554 through write and read commands.
8.3.2.4.1 Writes
Data is transmitted to the PCA9554 by sending the device address and setting the least-significant bit to a
logic 0 (see Figure 8-6 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
0
Command Byte
0 A2 A1 A0 0
A
0
0
0
0
0
0
0
1
Data 1
A
A
P
ACK From Slave
ACK From Slave
R/W ACK From Slave
Start Condition
Data to Port
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 8-8. Write To Output Port Register
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
0
Command Byte
0 A2 A1 A0 0
Start Condition
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
1 1/0 A
Data
ACK From Slave
A
P
ACK From Slave
Data to
Register
Figure 8-9. Write To Configuration Or Polarity Inversion Registers
8.3.2.4.2 Reads
The bus master first must send the PCA9554 address with the least-significant bit set to a logic 0 (see Figure
8-6 for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9554 (see Figure 8-10 and Figure 8-11).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limitation on the number of data bytes received in one read transmission, but when the final byte is received, the
bus master must not acknowledge the data
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S 0
1
0
ACK From
Slave
ACK From
Slave
Slave Address
0 A2 A1 A0 0
Command Byte
A
A S 0
ACK From
ACK From
Master
Slave Data from Register
Slave Address
1
0
Data
A
Data from Register
NACK From
Master
0 A2 A1 A0 1 A
R/W
R/W
Data
NA P
Last Byte
Figure 8-10. Read From Register
SCL
1
2
3
4
5
6
7
8
9
Data From Port
Slave Address
SDA
S 0
0
1
Start
Condition
0 A2 A1 A0 1
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A. This figure assumes the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data
transfer from P port. See Figure 8-10 for these details.
Figure 8-11. Read From Input Port Register
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Typical Application
Figure 9-1 shows an application in which the PCA9554 can be used.
VCC
(5 V)
VCC
Master
Controller
10 kW
10 kW
100 kW
(y3)
2 kW
10 kW
VCC
SDA
SDA
SCL
SCL
INT
INT
P0
Subsystem 1
(e.g., temperature sensor)
P1
INT
P2
RESET
GND
P3
Subsystem 2
(e.g., counter)
PCA9554
P4
A
P5
A2
Controlled Device
(e.g., CBT device)
P6
ENABLE
A1
P7
B
A0
GND
ALARM
Subsystem 3
(e.g., alarm system)
VCC
A.
B.
C.
D.
Device address is configured as 0100000 for this example.
P0, P2, and P3 are configured as outputs.
P1, P4, and P5 are configured as inputs.
P6 and P7 are not used and and have internal 100-kΩ pullup resistors to protect them from floating.
Figure 9-1. Typical Application
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9.1.1.1 Design Requirements
9.1.1.1.1 Minimizing ICC When I/Os Control Leds
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in
Figure 9-1. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. ΔICC in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC.
For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when
the LED is off to minimize current consumption. Figure 9-2 shows a high-value resistor in parallel with the LED.
Figure 9-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VIN at or above VCC and prevent additional supply-current consumption when the LED is off.
VCC
LED
100 kW
VCC
LEDx
Figure 9-2. High-Value Resistor In Parallel With Led
3.3 V
VCC
5V
LED
LEDx
Figure 9-3. Device Supplied By A Lower Voltage
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9554 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 10-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 10-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
Table 10-1 specifies the performance of the power-on reset feature for PCA9554 for both types of power-on
reset.
Table 10-1. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 10-1
1
100
ms
VCC_RT
Rise rate
See Figure 10-1
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 10-1
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 10-2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 10-3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 10-3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
(1)
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide
more information on how to measure these specifications.
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Product Folder Links: PCA9554
PCA9554
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SCPS128D – JULY 2006 – REVISED MARCH 2021
VCC
VCC_GH
Time
VCC_GW
Figure 10-3. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and
all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR
differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this
specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 10-4. VPOR
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PCA9554
www.ti.com
SCPS128D – JULY 2006 – REVISED MARCH 2021
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCA9554DB
ACTIVE
SSOP
DB
16
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
Samples
PCA9554DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
Samples
PCA9554DGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
Samples
PCA9554DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9554
Samples
PCA9554DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9554
Samples
PCA9554PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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