PCA9555
PCA9555
SCPS131J – AUGUST 2005 – REVISED MARCH
2021
SCPS131J – AUGUST 2005 – REVISED MARCH 2021
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PCA9555 Remote 16-bit I2C and SMBus I/O Expander with Interrupt Output and
Configuration Registers
1 Features
3 Description
•
•
•
•
•
•
•
This 16-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC operation.
It provides general-purpose remote I/O expansion for
most microcontroller families via the I2C interface
[serial clock (SCL), serial data (SDA)].
•
•
•
•
Low Standby-Current Consumption of 1 μA Max
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
5-V Tolerant I/O Ports
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
Address by Three Hardware Address Pins for Use
of up to Eight Devices
Polarity Inversion Register
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The PCA9555 consists of two 8-bit Configuration
(input or output selection), Input Port, Output Port,
and Polarity Inversion (active high or active low
operation) registers. At power on, the I/Os are
configured as inputs. The system master can enable
the I/Os as either inputs or outputs by writing to the
I/O configuration bits. The data for each input or
output is kept in the corresponding Input or Output
register. The polarity of the Input Port register can
be inverted with the Polarity Inversion register. All
registers can be read by the system master.
Device Information (1)
PART NUMBER
2 Applications
•
•
•
•
•
•
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics
Industrial Automation Equipment
Products with GPIO-Limited Processors
INT
A0
A1
A2
SCL
SDA
PCA9555
(1)
PACKAGE
BODY SIZE (NOM)
SSOP (24) DB
8.20 mm × 5.30 mm
SSOP (24) DBQ
8.65 mm × 3.90 mm
TVSOP (24) DGV
5.00 mm x 4.40 mm
SOIC (24) DW
15.4 mm x 7.50 mm
SSOP (24) PW
7.80 mm x 4.40 mm
VQFN (24) RGE
4.00 mm x 4.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
PCA9555
1
Interrupt
Logic
LP Filter
21
2
P07−P00
3
22
23
Input
Filter
I2C Bus
Control
Shift
Register
16 Bits
I/O
Port
P17−P10
Write Pulse
VCC
GND
24
12
Read Pulse
Power-On
Reset
Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SCPS131J – AUGUST 2005 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 I2C Interface Timing Requirements.............................7
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 12
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Device Features........................................................15
8.4 Device Functional Modes..........................................16
8.5 Programming............................................................ 17
9 Application Information Disclaimer............................. 24
9.1 Application Information............................................. 24
10 Power Supply Recommendations..............................27
10.1 Power-On Reset Requirements.............................. 27
11 Layout........................................................................... 29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................30
12.1 Receiving Notification of Documentation Updates..30
12.2 Support Resources................................................. 30
12.3 Trademarks............................................................. 30
12.4 Electrostatic Discharge Caution..............................30
12.5 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
Changes from Revision I (April 2019) to Revision J (March 2021)
Page
• Changed the VIH High-level input voltage (SDL, SDA) Max value From: 5.5 V To: VCC in the Recommended
Operating Conditions ......................................................................................................................................... 5
• Changed the values for the DB, PW, and RGE packages in the Thermal Information table.............................. 6
• Changed the VPORR row in the Electrical Characteristics .................................................................................. 7
• Added the VPORF row in the Electrical Characteristics .......................................................................................7
• Changed the ICC Standby mode (High Inputs) values in the Electrical Characteristics ..................................... 7
• Changed the Ci SCL Max value From: 7 pF To: 8 pF in the Electrical Characteristics ......................................7
• Changed the Cio SDA Max value From: 7 pF To: 9.5 pF in the Electrical Characteristics ................................. 7
• Changed the Typical characteristic graphs.........................................................................................................9
• Changed the Power Supply Recommendations .............................................................................................. 27
Changes from Revision H (April 2019) to Revision I (April 2019)
Page
• Changed the I2C Interface Timing Requirements table...................................................................................... 7
Changes from Revision G (March 2018) to Revision H (April 2019)
Page
• Changed the Device Information table............................................................................................................... 1
• Added the DW package to the Thermal Information table..................................................................................6
Changes from Revision F (June 2014) to Revision G (March 2018)
Page
• Added the Applications list .................................................................................................................................1
• Removed the Thermal Information from the Absolute Maximum Ratings ......................................................... 5
• Added Storage temperature range to the Absolute Maximum Ratings ............................................................. 5
• Changed the Handling Ratings table to the ESD Ratings table..........................................................................5
• Added the Thermal Information table ................................................................................................................ 6
• Added the Design Requirements section ........................................................................................................ 25
• Added the Application Curves section ............................................................................................................. 26
• Added the Layout section ................................................................................................................................ 29
2
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SCPS131J – AUGUST 2005 – REVISED MARCH 2021
Changes from Revision E (May 2008) to Revision F (June 2014)
Page
• Added Interrupt Errata section..........................................................................................................................16
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SCPS131J – AUGUST 2005 – REVISED MARCH 2021
A0
P01
5
20
P17
P02
6
19
P16
P03
7
18
P15
P04
8
17
P14
P05
9
16
P13
P06
10
15
P12
P07
11
14
P11
GND
12
13
P10
SCL
21
SDA
4
19
P00
VCC
SCL
20
22
INT
3
21
SDA
A2
A1
VCC
23
22
24
2
A2
1
A1
23
INT
24
5 Pin Configuration and Functions
P00
1
18
A0
P01
2
17
P17
P02
3
16
P16
Thermal
Pad
10
11
12
P11
P12
P13
P10
13
9
6
GND
P14
P05
8
P15
14
7
15
5
P07
4
P04
P06
P03
Not to scale
Figure 5-2. RGE Package, 24 Pin (QFN), (Top View)
Not to scale
Figure 5-1. DB, DBQ, DGV, DW or PW Package, 24
Pin (SOP), (Top View)
Table 5-1. Pin Functions
PIN
4
NAME
SSOP (DB),
QSOP (DBQ),
TSSOP (PW), AND
TVSOP (DGV)
QFN (RGE)
INT
1
22
DESCRIPTION
Interrupt output. Connect to VCC through a pullup resistor.
A1
2
23
Address input 1. Connect directly to VCC or ground.
A2
3
24
Address input 2. Connect directly to VCC or ground.
P00
4
1
P-port input/output. Push-pull design structure.
P01
5
2
P-port input/output. Push-pull design structure.
P02
6
3
P-port input/output. Push-pull design structure.
P03
7
4
P-port input/output. Push-pull design structure.
P04
8
5
P-port input/output. Push-pull design structure.
P05
9
6
P-port input/output. Push-pull design structure.
P06
10
7
P-port input/output. Push-pull design structure.
P07
11
8
P-port input/output. Push-pull design structure.
GND
12
9
Ground
P10
13
10
P-port input/output. Push-pull design structure.
P11
14
11
P-port input/output. Push-pull design structure.
P12
15
12
P-port input/output. Push-pull design structure.
P13
16
13
P-port input/output. Push-pull design structure.
P14
17
14
P-port input/output. Push-pull design structure.
P15
18
15
P-port input/output. Push-pull design structure.
P16
19
16
P-port input/output. Push-pull design structure.
P17
20
17
P-port input/output. Push-pull design structure.
A0
21
18
Address input 0. Connect directly to VCC or ground.
SCL
22
19
Serial clock bus. Connect to VCC through a pullup resistor.
SDA
23
20
Serial data bus. Connect to VCC through a pullup resistor.
VCC
24
21
Supply voltage
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SCPS131J – AUGUST 2005 – REVISED MARCH 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6
V
VI
Input voltage range(2)
–0.5
6
V
range(2)
VO
Output voltage
IIK
Input clamp current
–0.5
6
VI < 0
–20
V
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
Tstg
(1)
(2)
Continuous current through GND
–250
Continuous current through VCC
160
Storage temperature range
–65
150
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
MIN
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002, all pins(2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC
Supply voltage
2.3
5.5
SCL, SDA
0.7 × VCC
VCC (1)
A2–A0, P07–P00, P17–P10
0.7 × VCC
5.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, P07–P00, P17–P10
–0.5
0.3 × VCC
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P07–P00, P17–P10
IOL
Low-level output current
P07–P00, P17–P10
TA
Operating free-air temperature
(1)
MAX
–40
UNIT
V
V
V
–10
mA
25
mA
85
°C
For voltages applied above VCC, an increase in ICC will result.
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6.4 Thermal Information
PCA9555
THERMAL METRIC(1)
DBQ
(QSOP)
DGV
(TVSOP)
DW
(SOIC)
PW
(TSSOP)
RGE
(QFN)
UNIT
24 PINS
24 PINS
24 PINS
24 PINS
24 PINS
24 PINS
RθJA
Junction-to-ambient thermal resistance
92.9
81.8
105.4
66.7
108.8
48.4
°C/W
Rθ
Junction-to-case (top) thermal resistance
53.5
39.3
36.7
36.7
54
58.1
°C/W
RθJB
Junction-to-board thermal resistance
50.4
36.0
50.8
36.7
62.8
27.1
°C/W
ψJT
Junction-to-top characterization parameter
21.9
7.6
2.4
13.1
11.1
3.3
°C/W
ψJB
Junction-to-board characterization parameter
50.1
35.6
50.3
62.3
62.3
27.2
°C/W
n/a
n/a
n/a
15.3
°C/W
JC(top)
Rθ
JC(bot)
(1)
6
DB
(SSOP)
Junction-to-case (bottom) thermal resistance
n/a
n/a
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPORR
Power-on reset voltage, VCC rising
VI = VCC or GND, IO = 0
VPORF
Power-on reset voltage, VCC
falling
VI = VCC or GND, IO = 0
IOH = –8 mA
P-port high-level output voltage(2)
VOH
IOH = –10 mA
VCC
MIN
2.3 V to 5.5 V
–1.2
1.8
3V
2.6
4.75 V
4.1
2.3 V
1.7
3V
2.5
4.75 V
SDA
P port(3)
IOL
A2–A0
1.5
1
V
V
V
3
VOL = 0.5 V
8
20
10
24
2.3 V to 5.5 V
UNIT
4
VOL = 0.4 V
SCL, SDA
II
1.2
VOL = 0.4 V
VOL = 0.7 V
INT
MAX
V
0.75
2.3 V
TYP(1)
mA
3
VI = VCC or GND
2.3 V to 5.5 V
±1
±1
μA
IIH
P port
VI = VCC
2.3 V to 5.5 V
1
μA
IIL
P port
VI = GND
2.3 V to 5.5 V
–100
μA
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz, No load
Operating mode
ICC
Low inputs
VI = GND, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load
Standby mode
High inputs
VI = VCC, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load
5.5 V
100
200
3.6 V
30
75
2.7 V
20
50
5.5 V
1.1
1.5
3.6 V
0.7
1.3
2.7 V
0.5
1
5.5 V
2.5
3.5
3.6 V
1
1.8
2.7 V
0.7
1.6
ΔICC
Additional current in standby mode
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
CI
SCL
VI = VCC or GND
2.3 V to 5.5 V
VIO = VCC or GND
2.3 V to 5.5 V
Cio
(1)
(2)
(3)
SDA
P port
μA
mA
μA
1.5
mA
3
8
pF
3
9.5
3.7
9.5
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
I2C
BUS—STANDARD MODE
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C
tsds
I2C serial-data setup time
tsdh
I2C
clock high time
MIN
MAX
UNIT
0
100
kHz
4
µs
4.7
µs
spike time
50
serial-data hold time
ns
250
ns
0
ns
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6.6 I2C Interface Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MIN
MAX
UNIT
1000
ns
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time
tbuf
I2C bus free time between stop and start
4.7
µs
tsts
I2C start or repeated start condition setup
4.7
µs
tsth
I2C start or repeated start condition hold
4
µs
tsps
I2C stop condition setup
4
µs
tvd(data)
Valid data time
SCL low to SDA output valid
3.45
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
3.45
µs
Cb (1)
I2C bus capacitive load
400
pF
400
kHz
I2C
input fall time
10-pF to 400-pF bus
300
ns
300
ns
BUS—FAST MODE
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
0
clock high time
tsp
I2C
tsds
I2C serial-data setup time
tsdh
I2C
ticr
I2C input rise time
ticf
I2C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between stop and start
0.6
µs
1.3
µs
spike time
50
100
serial-data hold time
ns
0
10-pF to 400-pF bus
ns
ns
20
300
ns
20 × (VCC /
5.5 V)
300
ns
20 × (VCC /
5.5 V)
300
ns
1.3
µs
tsts
I2C
tsth
I2C start or repeated start condition hold
tsps
I2C stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
0.9
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.9
µs
Cb (1)
I2C bus capacitive load
400
pF
(1)
start or repeated start condition setup
0.6
µs
0.6
µs
0.6
µs
Cb = total capacitance of one bus line in pF.
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-1 and Figure
7-2)
PARAMETER
8
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
4
μs
SCL
INT
4
μs
200
ns
MIN
MAX
UNIT
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid
SCL
P port
tps
Input data setup time
P port
SCL
150
ns
tph
Input data hold time
P port
SCL
1
μs
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
40
2.2
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
32
Vcc = 5.5V
28
24
20
16
12
8
1.8
Vcc = 5.5V
1.4
1.2
1
0.8
0.6
0.4
-15
10
35
TA - Temperature (°C)
60
0.2
-40
85
-15
D001
Figure 6-1. Supply Current vs Temperature for Different Supply
Voltage (VCC)
10
35
TA - Temperature (°C)
60
85
D002
Figure 6-2. Standby Supply Current vs Temperature for
Different Supply Voltage (VCC)
30
30
-40qC
25qC
85qC
-40qC
25qC
85qC
25
IOL - Sink Current (mA)
25
ICC - Supply Current (µA)
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
1.6
4
0
-40
20
15
10
5
20 VCC = 1.65 V
15
10
5
0
1.5
0
2
2.5
3
3.5
4
4.5
VCC - Supply Voltage (V)
5
5.5
0
0.1
D003
Figure 6-3. Supply Current vs Supply Voltage for Different
Temperature (TA)
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D004
Figure 6-4. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.65 V
60
35
25
IOL - Sink Current (mA)
-40qC
25qC
85qC
30
IOL - Sink Current (mA)
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
2
ICC - Supply Current (µA)
ICC - Supply Current (µA)
36
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
VCC = 1.8 V
20
15
10
50
-40qC
25qC
85qC
40
VCC = 2.5 V
30
20
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
0
D005
Figure 6-5. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.8 V
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D006
Figure 6-6. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 2.5 V
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
70
80
-40qC
25qC
85qC
50
VCC = 3.3 V
40
30
20
10
60
VCC = 5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
D007
Figure 6-7. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 3.3 V
0.6
0.7
D009
Figure 6-8. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 5 V
300
90
70
VOL - Output Low Voltage (V)
-40qC
25qC
85qC
80
IOL - Sink Current (mA)
-40qC
25qC
85qC
70
IOL - Sink Current (mA)
IOL - Sink Current (mA)
60
VCC = 5.5 V
60
50
40
30
20
1.8 V, 1 mA
1.8 V, 10 mA
3.3 V, 1mA
250
3.3 V, 10 mA
5 V, 1 mA
5 V, 10 mA
200
150
100
50
10
0
-40
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
Figure 6-9. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 5.5 V
60
85
D011
25
-40qC
25qC
85qC
IOH - Source Current (mA)
IOH - Source Current (mA)
10
35
TA - Temperature (°C)
Figure 6-10. I/O Low Voltage vs Temperature for Different VCC
and IOL
20
15
VCC = 1.65 V
10
5
0
-40qC
25qC
85qC
20
VCC = 1.8 V
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
D012
Figure 6-11. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.65 V
10
-15
D010
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D013
Figure 6-12. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.8 V
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
60
40
IOH - Source Current (mA)
35
IOH - Source Current (mA)
-40qC
25qC
85qC
30
VCC = 2.5 V
25
20
15
10
0
VCC = 3.3 V
30
20
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
D014
Figure 6-13. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 2.5 V
0.6
0.7
D015
Figure 6-14. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 3.3 V
70
80
-40qC
25qC
85qC
50
-40qC
25qC
85qC
70
IOH - Source Current (mA)
60
IOH - Source Current (mA)
40
10
5
VCC = 5 V
40
30
20
10
60
VCC = 5.5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
D016
Figure 6-15. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5 V
350
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D017
Figure 6-16. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5.5 V
400
18
1.65 V, 10 mA
2.5 V, 10 mA
3.6 V, 10 mA
5 V, 10 mA
5.5 V, 10 mA
15
1.65 V
1.8 V
2.5 V
3.3 V
5V
5.5 V
300
Delta ICC (µA)
VCC-VOH - I/O High Voltage (mV)
50
-40qC
25qC
85qC
250
200
150
9
6
3
100
50
-40
12
-15
10
35
TA - Temperature (°C)
60
85
0
-40
D018
Figure 6-17. VCC – VOH Voltage vs Temperature for Different VCC
-15
10
35
TA - Temperature (°C)
60
85
D019
Figure 6-18. Δ ICC vs Temperature for Different VCC (VI = VCC –
0.6 V)
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7 Parameter Measurement Information
VCC
RL = 1 kW
SDA
DUT
CL = 50 pF
SDA LOAD CONFIGURA TION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Condition
(S)
Address
Address
Bit 7
Bit 6
(MSB)
Address
Bit 1
t scl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
t sch
0.7 × VCC
SCL
0.3 × VCC
t icr
t icf
t buf
t sts
t PHL
t PLH
t sp
0.7 × VCC
SDA
0.3 × VCC
t icf
t icr
t sth
t sdh
t sds
Start or
Repeat
Start
Condition
t sps
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 7-1. I2C Interface Load Circuit And Voltage Waveforms
12
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DUT
Pn
CL = 100 pF
GND
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P00
A
P17
0.3 × VCC
Slave
ACK
SDA
tpv
(see Note A)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P00
A
tps
P17
0.3 × VCC
tph
0.7 × VCC
Pn
0.3 × VCC
READ MODE (R/W = 1)
A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 7-2. P-Port Load Circuit And Voltage Waveforms
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8 Detailed Description
8.1 Overview
The system master can reset the PCA9555 in the event of a timeout or other improper operation by utilizing
the power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state
machine.
The PCA9555 open-drain interrupt ( INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9555 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs.
Although pin-to-pin and I2C-address is compatible with the PCF8575, software changes are required due to the
enhancements.
The PCA9555 is identical to the PCA9535, except for the inclusion of the internal I/O pullup resistor, which pulls
the I/O to a default high when configured as an input and undriven.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to
eight devices to share the same I2C bus or SMBus. The fixed I2C address of the PCA9555 is the same as
the PCF8575, PCF8575C, and PCF8574, allowing up to eight of these devices in any combination to share the
same I2C bus or SMBus.
8.2 Functional Block Diagram
INT
A0
A1
A2
SCL
SDA
PCA9555
1
Interrupt
Logic
LP Filter
21
2
P07−P00
3
22
23
Input
Filter
I2C Bus
Control
Shift
Register
16 Bits
I/O
Port
P17−P10
Write Pulse
VCC
GND
24
12
Read Pulse
Power-On
Reset
A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
B. All I/Os are set to inputs at reset.
Figure 8-1. Logic Diagram
14
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Data From
Shift Register
Output Port
Register Data
Configuration
Register
Data From
Shift Register
D
Q
100 k
FF
Write Configuration
Pulse
VCC
Q1
D
CLK Q
Q
FF
I/O Pin
CLK Q
Write Pulse
Output Port
Register
Q2
Input Port
Register
D
Q
FF
Read Pulse
GND
Input Port
Register Data
CLK Q
To INT
Data From
Shift Register
D
Q
Polarity
Register Data
FF
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
A. At power-on reset, all registers return to default values.
Figure 8-2. Simplified Schematic Of P-Port I/Os
8.3 Device Features
8.3.1 Power-On Reset (POR)
When power (from 0 V) is applied to VCC, an internal power-on reset circuit holds the PCA9555 in a reset
condition until VCC has reached VPOR. At that time, the reset condition is released, and the PCA9555 registers
and I2C-SMBus state machine initialize to their default states. After that, VCC must be lowered to below VPORF
and back up to the operating voltage for a power-reset cycle.
8.3.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 8-2) are off, creating a high-impedance input.
The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register.
In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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8.4 Device Functional Modes
8.4.1 Interrupt ( INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv,
the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the
original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting
of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause
an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the
pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC.
8.4.1.1 Interrupt Errata
8.4.1.1.1 INT Description
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I2C command byte (register pointer) written to the device was 00h.
Note
This generally means the last operation with the device was a Read of the input register. However,
the command byte may have been written with 00h without ever going on to read the input register.
After reading from the device, if no other command byte written, it will remain 00h.
2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high
8.4.1.1.2 System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
8.4.1.1.3 System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9555 device or before reading from another slave device.
Note
Software change will be compatible with other versions (competition and TI redesigns) of this device.
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8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 8-3). After the Start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address.
After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during
the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed
between the Start and Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 8-4).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 8-3).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure
8-5). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times
must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 8-3. Definition Of Start And Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 8-4. Bit Transfer
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Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 8-5. Acknowledgment On I2C Bus
8.5.2 Register Map
Table 8-1. Interface Definition
BYTE
I2C
18
slave address
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
A2
A1
A0
R/ W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
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8.5.2.1 Device Address
Figure 8-6 shows the address byte of the PCA9555.
R/W
Slave Address
0
1
0
Fixed
0
A2 A1 A0
Programmable
Figure 8-6. PCA9555 Address
Table 8-2. Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
A1
A0
L
L
L
32 (decimal), 20 (hexadecimal)
L
L
H
33 (decimal), 21 (hexadecimal)
L
H
L
34 (decimal), 22 (hexadecimal)
L
H
H
35 (decimal), 23 (hexadecimal)
H
L
L
36 (decimal), 24 (hexadecimal)
H
L
H
37 (decimal), 25 (hexadecimal)
H
H
L
38 (decimal), 26 (hexadecimal)
H
H
H
39 (decimal), 27 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.5.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9555. Three bits of this data byte state the operation (read or write) and
the internal register (input, output, polarity inversion, or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
Figure 8-7. Control Register Bits
7
6
5
4
3
2
1
0
0
0
0
0
0
B2
B1
B0
Table 8-3. Command Byte
CONTROL REGISTER BITS
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0
0x00
Input Port 0
Read byte
xxxx xxxx
0
0
1
0x01
Input Port 1
Read byte
xxxx xxxx
0
1
0
0x02
Output Port 0
Read/write byte
1111 1111
0
1
1
0x03
Output Port 1
Read/write byte
1111 1111
1
0
0
0x04
Polarity Inversion Port 0
Read/write byte
0000 0000
1
0
1
0x05
Polarity Inversion Port 1
Read/write byte
0000 0000
1
1
0
0x06
Configuration Port 0
Read/write byte
1111 1111
1
1
1
0x07
Configuration Port 1
Read/write byte
1111 1111
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8.5.2.3 Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether
the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to
these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Table 8-4. Registers 0 And 1 (Input Port Registers)
Bit
I0.7
Default
Bit
Default
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
X
X
X
X
X
X
X
X
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 8-5. Registers 2 And 3 (Output Port Registers)
Bit
O0.7
Default
Bit
Default
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
1
1
1
1
1
1
1
1
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
1
1
1
1
1
1
1
1
The Polarity Inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Table 8-6. Registers 4 And 5 (Polarity Inversion Registers)
Bit
Default
Bit
Default
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
0
0
0
0
0
0
0
0
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
0
0
0
0
0
0
0
0
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this
register is cleared to 0, the corresponding port pin is enabled as an output.
Table 8-7. Registers 6 And 7 (Configuration Registers)
Bit
Default
Bit
Default
20
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
1
1
1
1
1
1
1
1
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
1
1
1
1
1
1
1
1
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8.5.2.4 Bus Transactions
Data is exchanged between the master and the PCA9555 through write and read commands.
8.5.2.4.1 Writes
Data is transmitted to the PCA9555 by sending the device address and setting the least-significant bit to a
logic 0 (see Figure 8-6 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte.
The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are input
ports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 8-8 and Figure 8-9). For example, if the first byte is
sent to output port (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
1
SCL
2
3
4
5
6
7
8
9
Command Byte
Slave Address
SDA
S
0
1
0
0
A2 A1 A0
Start Condition
0
0
A
0
0
0
0
Data to Port 0
0
1
0
0.7
A
Data to Port 1
0.0
Data 0
Acknowledge
From Slave
R/W Acknowledge
From Slave
1.7
A
1.0
Data 1
A
P
Acknowledge
From Slave
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 8-8. Write To Output Port Registers
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Slave Address
SDA
S
0
1
Start Condition
0
0
A2 A1 A0
4
5
6
7
8
9
1
2
R/W
A
0
0
Acknowledge
From Slave
0
0
0
1
4
5
6
7
8
9
1
2
Data to Register
Command Byte
0
3
1
0
A MSB
Data 0
3
4
5
Data to Register
LSB
Acknowledge
From Slave
A MSB
Data 1
LSB
A
P
Acknowledge
From Slave
Figure 8-9. Write To Configuration Registers
8.5.2.4.2 Reads
The bus master first must send the PCA9555 address with the least-significant bit set to a logic 0 (see Figure
8-6 for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9555 (see Figure 8-10 through Figure
8-12).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
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Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Slave Address
S
0
1
0
0
A2
Acknowledge
From Slave
Acknowledge
From Slave
A1 A0
0
Command Byte
A
A
S
Slave Address
0
1
0
0
A2 A1 A0
1
Acknowledge
From Master
Data
A MSB
LSB
A
First Byte
At this moment, master transmitter
becomes master receiver , and
slave-receiver becomes
slave-transmitter.
R/W
Data From Lower
or Upper Byte
of Register
Acknowledge
From Slave
R/W
Data From Upper
or Lower Byte
of Register
MSB
No Acknowledge
From Master
LSB NA
Data
P
Last Byte
Figure 8-10. Read From Register
1
SCL
2
3
4
5
6
7
8
9
I0.x
SDA
S
0
1
0
0
A2
A1
A0
1
R/W
A
7
6
5
Acknowledge
From Slave
4
3
I1.x
2
1
0
A
7
6
Acknowledge
From Master
5
4
3
I0.x
2
1
0
A
7
6
5
4
3
I1.x
2
1
0
A
7
Acknowledge
From Master
Acknowledge
From Master
6
5
4
3
2
1
0
1
P
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
t iv
t ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid
(output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data
transfer from the P port (see Figure 8-10 for these details).
Figure 8-11. Read Input Port Register, Scenario 1
22
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1
SCL
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2
3
4
5
6
7
8
9
I0.x
SDA
S
0
1
0
0
A2
A1
A0
1
R/W
A
00
I1.x
A
10
A
03
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Slave
I0.x
I1.x
A
12
P
No Acknowledge
From Master
tps
tph
1
Acknowledge
From Master
Read From Port 0
Data Into Port 0
Data 00
Data 01
Data 02
Data 03
tph
Read From Port 1
Data 10
Data Into Port 1
tps
Data 11
Data 12
INT
t iv
t ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid
(output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data
transfer from the P port (see Figure 8-10 for these details).
Figure 8-12. Read Input Port Register, Scenario 2
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Typical Application
Figure 9-1 shows an application in which the PCA9555 can be used.
Subsystem 1
(e.g., Temperature
Sensor)
INT
VCC
(5 V)
VCC
Master
Controller
10 k
10 k
SCL
SDA
INT
10 k
24
10 k
22
23
1
Subsystem 2
(e.g., Counter)
2k
VCC
SCL
SDA
INT
P00
P01
P02
P03
GND
P04
P05
RESET
4
5
A
6
7
ENABLE
8
9
B
PCA9555
VCC
P06
P07
3
A2
P10
P11
2
A1
P12
P13
21
A0
P14
P15
P16
GND P17
12
A.
B.
C.
D.
10
11
13
14
15
16
17
18
19
20
Controlled Switch
(e.g., CBT Device)
ALARM
Keypad
Subsystem 3
(e.g., Alarm)
Device address is configured as 0100100 for this example.
P00, P02, and P03 are configured as outputs.
P01, P04–P07, and P10–P17 are configured as inputs.
Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
Figure 9-1. Typical Application
24
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9.1.1.1 Design Requirements
For this design example, use the parameters shown in Table 9-1.
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
I2C and Subsystem Voltage (VCC)
5V
Output current rating, P-port sinking (IOL)
25 mA
I2C bus clock (SCL) speed
400 kHz
9.1.1.2 Design Requirements
9.1.1.2.1 Minimizing ICC When I/O Is Used To Control Led
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure
9-1. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The
ΔICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For
battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when the
LED is off to minimize current consumption.
Figure 9-2 shows a high-value resistor in parallel with the LED. Figure 9-3 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
VCC
LED
100 k
VCC
Pn
Figure 9-2. High-Value Resistor In Parallel With Led
3.3 V
VCC
5V
LED
Pn
Figure 9-3. Device Supplied By Lower Voltage
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9.1.1.3 Application Curves
1.8
Standard-Mode
Fast-Mode
Minimum Pull-Up Resistance (k:)
Maximum Pull-Up Resistance (k:)
25
20
15
10
5
VDPUX > 2 V
VDUPX 2 V
Figure 9-4. Maximum Pull-Up Resistance (Rp(max))
vs Bus Capacitance (Cb)
26
4.5
5
5.5
D009
Figure 9-5. Minimum Pull-Up Resistance (Rp(min))
vs Pull-up Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9555 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 10-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 10-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
Table 10-1 specifies the performance of the power-on reset feature for PCA9555 for both types of power-on
reset.
Table 10-1. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 10-1
1
100
ms
VCC_RT
Rise rate
See Figure 10-1
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 10-1
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 10-2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 10-3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 10-3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
(1)
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide
more information on how to measure these specifications.
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VCC
VCC_GH
Time
VCC_GW
Figure 10-3. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and
all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR
differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this
specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 10-4. VPOR
28
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the PCA9555, common PCB layout practices must be followed, but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power
in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors must be placed as close to the PCA9555 as possible. These best practices are shown in the Section
11.2.
For the layout example provided in the Section 11.2, it is possible to fabricate a PCB with only 2 layers by
using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND).
However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it
is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and
dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and
ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC, or GND
and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when
a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in the
Section 11.2.
11.2 Layout Example
Figure 11-1. PCA9555 Example Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCA9555DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PCA9555
Samples
PCA9555DBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9555
Samples
PCA9555DGVR
ACTIVE
TVSOP
DGV
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9555
Samples
PCA9555DW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9555
Samples
PCA9555DWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9555
Samples
PCA9555PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9555
Samples
PCA9555PWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9555
Samples
PCA9555RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD9555
Samples
PCA9555RGERG4
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD9555
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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