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PCA9557
SCPS133J – DECEMBER 2005 – REVISED JUNE 2014
PCA9557 Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Reset and
Configuration Registers
1 Features
•
•
The device outputs (latched) have high-current drive
capability for directly driving LEDs. The device has
low current consumption.
Device Information(1)
PART NUMBEr
PCA9557
RESET
P7
P6
P5
P4
P3
P2
14
13
12
11
10
9
RESET
SDA
SCL
VCC
A0
A1
A2
P0
VQFN (16)
4.00 mm × 4.00 mm
RGY PACKAGE
(TOP VIEW)
16 15 14 13
1
2
3
12
11
10
9
4
5
6
7
8
P2
6
7
8
VCC
15
P3
4
5
16
P1
1
2
3
GND
SCL
SDA
A0
A1
A2
P0
P1
GND
BODY SIZE (NOM)
6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
RGV PACKAGE
(TOP VIEW)
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
PACKAGE
SSOP (16)
P7
P6
P5
P4
SDA
A0
A1
A2
P0
P1
2
3
4
5
6
7
VCC
•
•
•
•
•
•
•
•
•
1
16 15
14
13
12
11
9 10
8
RESET
P7
P6
P5
P4
P3
P2
•
The PCA9557 consists of one 8-bit configuration
(input or output selection), input port, output port, and
polarity inversion (active-high) registers. At power on,
the I/Os are configured as inputs. However, the
system master can enable the I/Os as either inputs or
outputs by writing to the I/O configuration bits. The
data for each input or output is kept in the
corresponding input or output register. The polarity of
the input port register can be inverted with the polarity
inversion register. All registers can be read by the
system master.
SCL
•
•
•
This 8-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC
operation. The device provides general-purpose
remote I/O expansion for most microcontroller
families via the I2C interface [serial clock (SCL) and
serial data (SDA)].
Low Standby Current Consumption of 1 μA Max
I2C to Parallel Port Expander
Operating Power-Supply Voltage Range of 2.3 V
to 5.5 V
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Three Hardware Address Pins Allow for Use of up
to Eight Devices on I2C/SMBus
Lower-Voltage Higher-Performance Migration
Path for PCA9556
Input/Output Configuration Register
Polarity Inversion Register
Active-Low Reset Input
Internal Power-On Reset
High-Impedance Open Drain on P0
Power Up With All Channels Configured as Inputs
No Glitch on Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
GND
•
•
•
1
2 Description
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9557
SCPS133J – DECEMBER 2005 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
2
3
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
6
6
6
7
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Reset Timing Requirements .....................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Functional Block Diagram .......................................
Device Functional Modes........................................
Programming...........................................................
Bus Transactions ....................................................
12
14
15
19
Application And Implementation........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 22
10.1 Power-On Reset Errata......................................... 22
11 Device and Documentation Support ................. 23
11.1 Trademarks ........................................................... 23
11.2 Electrostatic Discharge Caution ............................ 23
11.3 Glossary ................................................................ 23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
3 Revision History
Changes from Revision I (June 2008) to Revision J
Page
•
Added RESET Errata section. .............................................................................................................................................. 14
•
Added Power-On Reset Errata section. ............................................................................................................................... 22
2
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SCPS133J – DECEMBER 2005 – REVISED JUNE 2014
4 Description (Continued)
The system master can reset the PCA9557 in the event of a timeout or other improper operation by asserting a
low in the active-low reset (RESET) input. The power-on reset puts the registers in their default state and
initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without
depowering the part.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, allowing up to eight
devices to share the same I2C bus or SMBus.
5 Pin Configuration and Functions
RGV PACKAGE
(TOP VIEW)
9
RESET
1
2
3
12
11
10
9
4
5
6
7
8
P7
P6
P5
P4
2
3
4
5
6
7
VCC
A0
A1
A2
P0
SDA
A0
A1
A2
P0
P1
1
16 15
14
13
12
11
9 10
8
RESET
P7
P6
P5
P4
P3
P2
12
11
10
16 15 14 13
SCL
14
13
RGY PACKAGE
(TOP VIEW)
GND
RESET
P7
P6
P5
P4
P3
P2
P3
6
7
8
VCC
15
P2
4
5
16
GND
1
2
3
P1
SCL
SDA
A0
A1
A2
P0
P1
GND
SDA
SCL
VCC
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NAME
QFN (RGY)
SOIC (D),
SSOP (DB),
TSSOP (PW),
AND
TVSOP (DGV)
QFN (RGV)
DESCRIPTION
SCL
1
15
Serial clock bus. Connect to VCC through a pullup resistor.
SDA
2
16
Serial data bus. Connect to VCC through a pullup resistor.
A0
3
1
Address input. Connect directly to VCC or ground.
A1
4
2
Address input. Connect directly to VCC or ground.
A2
5
3
Address input. Connect directly to VCC or ground.
P0
6
4
P-port input/output. High impedance open-drain design structure. Connect to
VCC through a pullup resistor.
P1
7
5
P-port input/output. Push-pull design structure.
GND
8
6
Ground
P2
9
7
P-port input/output. Push-pull design structure.
P3
10
8
P-port input/output. Push-pull design structure.
P4
11
9
P-port input/output. Push-pull design structure.
P5
12
10
P-port input/output. Push-pull design structure.
P6
13
11
P-port input/output. Push-pull design structure.
P7
14
12
P-port input/output. Push-pull design structure.
RESET
15
13
Active-low reset input. Connect to VCC through a pullup resistor if no active
connection is used.
VCC
16
14
Supply voltage
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PCA9557
SCPS133J – DECEMBER 2005 – REVISED JUNE 2014
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6
UNIT
V
(2)
–0.5
6
V
–0.5
6
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
–20
μA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
Continuous current through GND
–250
Continuous current through VCC
160
D package
Package thermal impedance (3)
(1)
(2)
(3)
mA
73
DB package
θJA
V
82
DGV package
120
PW package
108
RGV package
51
RGY package
47
°C/W
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
2.3
5.5
0.7 × VCC
5.5
2
5.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, P7–P0, RESET
–0.5
0.8
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P7–P1
–10
mA
IOL
Low-level output current
P7–P0
25
mA
TA
Operating free-air temperature
85
°C
4
SCL, SDA
A2–A0, P7–P0, RESET
–40
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V
V
V
Copyright © 2005–2014, Texas Instruments Incorporated
Product Folder Links: PCA9557
PCA9557
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SCPS133J – DECEMBER 2005 – REVISED JUNE 2014
6.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
IOH = –8 mA
P-port high-level output voltage (2)
VOH
IOH = –10 mA
SDA
VOL = 0.4 V
VCC
MIN
2.3 V to 5.5 V
–1.2
VPOR
2.3 V
1.8
3V
2.6
4.5 V
3
4.75 V
4.1
2.3 V
1.5
3V
2.5
4.5 V
3
4.75 V
4
2.3 V to 5.5 V
3
VOL = 0.5 V
IOL
P port (3)
VOL = 0.55 V
2.3 V to 5.5 V
VOL = 0.7 V
P port, except for P0
IOH
(3)
P0 (3)
SCL, SDA
II
A2–A0, RESET
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 100 kHz
(1)
(2)
(3)
P port
24
2.3 V to 5.5 V
Operating mode
Cio
10
mA
VI = VCC or GND
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz
SDA
20
1
2.3 V to 5.5 V
SCL
20
8
3.3 V to 5.5 V
VI = GND
CI
8
VOH = 3.3 V
P port
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 0 kHz
–4
mA
±1
±1
μA
μA
1
μA
5.5 V
19
25
3.6 V
12
22
2.7 V
8
20
5.5 V
1.5
5
3.6 V
1
4
2.7 V
0.6
3
5.5 V
0.25
1
3.6 V
0.25
0.9
2.7 V
0.2
0.8
2.3 V to 5.5 V
0.2
Every LED I/O at VI = 4.3 V,
fSCL = 0 kHz
5.5 V
0.4
VIO = VCC or GND
μA
1
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
V
V
1
IIL
UNIT
V
4.6 V to 5.5 V
2.3 V to 5.5 V
Additional current in Standby mode
2.1
2.3 V to 5.5 V
VI = VCC
ΔICC
1.65
VOH = 4.6 V
P port
Standby mode
MAX
VOH = 2.3 V
IIH
ICC
TYP (1)
μA
mA
2.3 V to 5.5 V
2.3 V to 5.5 V
4
6
5.5
8
7.5
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA per bit.
Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7–P0) must be limited to a maximum current of 200 mA.
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PCA9557
SCPS133J – DECEMBER 2005 – REVISED JUNE 2014
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6.5 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
FAST MODE
I2C BUS
UNIT
MIN
MAX
0
400
4.7
μs
1.3
50
50
250
2
100
0
kHz
μs
0.6
ns
ns
tsdh
I C serial data hold time
ticr
I2C input rise time
1000
20 + 0.1Cb
(1)
300
ns
ticf
I2C input fall time
300
20 + 0.1Cb
(1)
300
ns
tocf
I2C output fall time, 10-pF to 400-pF bus
300
20 + 0.1Cb
(1)
300
ns
2
0
ns
tbuf
I C bus free time between Stop and Start
4.7
1.3
μs
tsts
I2C Start or repeated Start condition setup time
4.7
0.6
μs
tsth
I2C Start or repeated Start condition hold time
4
0.6
μs
2
I C Stop condition setup time
tvd(data)
Valid data time, SCL low to SDA output valid
1
0.9
μs
tvd(ack)
Valid data time of ACK condition, ACK signal from SCL low to
SDA (out) low
1
0.9
μs
Cb
I2C bus capacitive load
400
400
pF
(1)
4
μs
tsps
0.6
Cb = total capacitance of one bus line in pF
6.6 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 15)
STANDARD MODE
I2C BUS
MIN
tW
Reset pulse duration (1)
tREC
Reset recovery time
tRESET
Time to reset (2)
(1)
(2)
MAX
16
FAST MODE
I2C BUS
MIN
UNIT
MAX
16
ns
0
0
ns
400
400
ns
A pulse duration of 16 ns minimum must be applied to RESET to return the PCA9557 to its default state.
The PCA9557 requires a minimum of 400 ns to be reset.
6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
PARAMETER
FROM
TO
STANDARD MODE
I2C BUS
MIN
MIN
UNIT
MAX
SCL
P0
250
250
SCL
P1–P7
200
200
Input data setup time
P port
SCL
0
0
ns
Input data hold time
P port
SCL
200
200
ns
tpv
Output data valid
tps
tph
6
MAX
FAST MODE
I2C BUS
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6.8 Typical Characteristics
20
60
55
SCL = VCC
VCC = 5 V
45
40
ICC - Standby Supply Current - nA
ICC - Supply Current - µA
50
f SCL = 400 kHz
I/Os unloaded
35
30
25
VCC = 3.3 V
20
15
10
VCC = 2.5 V
15
VCC = 5 V
10
VCC = 3.3 V
5
VCC = 2.5 V
5
0
-50
-25
0
25
50
75
0
-50
100
-25
Figure 1. Supply Current vs Temperature
50
75
100
30
VCC = 2.5 V
f SCL = 400 kHz
I/Os unloaded
25
ISINK – I/O Sink Current – mA
60
ICC – Supply Current – µA
25
Figure 2. Standby Supply Current vs Temperature
70
50
40
30
20
TA = –40°C
20
TA = 25°C
15
10
TA = 85°C
5
10
0
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
0.0
5.5
0.1
0.2
0.3
0.4
0.5
0.6
VCC – Supply Voltage – V
VOL – Output Low Voltage – V
Figure 3. Supply Current vs Supply Voltage
Figure 4. I/O Sink Current vs Output Low Voltage
50
40
VCC = 3.3 V
VCC = 5 V
45
30
ISINK – I/O Sink Current – mA
35
ISINK – I/O Sink Current – mA
0
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
TA = –40°C
25
TA = 25°C
20
15
10
TA = 85°C
TA = –40°C
40
35
30
TA = 25°C
25
20
15
10
5
TA = 85°C
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
Figure 5. I/O Sink Current vs Output Low Voltage
Figure 6. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
20
30
VCC = 3.3 V
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA
VCC = 2.5 V
TA = –40°C
15
TA = 25°C
10
5
TA = 85°C
25
TA = –40°C
20
TA = 25°C
15
10
TA = 85°C
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
Figure 7. I/O Source Current vs Output High Voltage (P7–P1)
Figure 8. I/O Source Current vs Output High Voltage (P7–P1)
40
6
VCC = 5 V
TA = 25°C
5
TA = –40°C
VOH – Output High Voltage – V
ISOURCE – I/O Source Current – mA
35
30
25
TA = 25°C
20
15
10
TA = 85°C
5
0
4
IOH = –4 mA
3
IOH = –8 mA
2
IOH = –10 mA
1
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
2.3
2.7
3.1
(VCC – VOH) – Output High Voltage – V
4.3
4.7
5.1
5.5
300
450
400
350
300
250
VCC = 5 V, ISOURCE = 10
200
150
VCC = 2.5 V, ISOURCE = 1 mA
100
0
-50
250
225
200
175
150
-25
0
25
50
75
VCC = 5 V, ISINK = 10 mA
125
100
VCC = 5 V, ISOURCE = 1 mA
50
VCC = 2.5 V, ISINK = 10 mA
275
VCC = 2.5 V, ISOURCE = 10
VOL – Output Low Voltage – mV
(V CC – V OH ) – Output High Voltage – mV
500
3.9
Figure 10. Output High Voltage vs Supply Voltage (P7–P1)
600
550
3.5
VCC – Supply Voltage – V
Figure 9. I/O Source Current vs Output High Voltage (P7–P1)
8
0.3
(VCC – VOH) – Output High Voltage – V
VCC = 2.5 V, ISINK = 1 mA
75
50
VCC = 5 V, ISINK = 1 mA
25
0
-50
100
-25
0
25
50
75
100
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 11. Output High Voltage vs Temperature (P7–P1)
Figure 12. Output Low Voltage vs Temperature
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tPHL
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 13. I2C Interface Load Circuit And Voltage Waveforms
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Parameter Measurement Information (continued)
500 W
Pn
2 × VCC
DUT
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P0
A
P7
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P0
A
tps
P7
0.3 × VCC
tph
0.7 × VCC
1.5 V
0.3 × VCC
Pn
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 14. P-Port Load Circuit And Voltage Waveforms
10
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Parameter Measurement Information (continued)
VCC
RL = 1 kΩ
DUT
500 W
Pn
SDA
2 × VCC
DUT
CL = 50 pF
(see Note A)
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y VCC
tRESET
RESET
VCC/2
tREC
tw
Pn
VCC/2
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
I/Os are configured as inputs.
D.
All parameters and waveforms are not applicable to all devices.
Figure 15. Reset Load Circuits And Voltage Waveforms
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8 Detailed Description
8.1 Functional Block Diagram
A0
A1
A2
SCL
SDA
3
4
5
1
2
P7−P0
I2C-Bus
Control
Input
Filter
Shift
Register
8 Bits
I/O
Port
Write Pulse
VCC
RESET
GND
Read Pulse
16
15
Power-On
Reset
8
A.
Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
B.
All I/Os are set to inputs at reset.
Figure 16. Logic Diagram (Positive Logic)
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Functional Block Diagram (continued)
Data From
Shift Register
Data From
Shift Register
Configuration
Register
Q
D
Output Port
Register Data
FF
Write Configuration
Pulse
CK Q
D
Q
FF
Write Pulse
P0
CK Q
Output
Port
Register
ESD Protection Diode
Input
Port
Register
D
GND
Input Port
Register Data
Q
FF
Read Pulse
CK Q
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity Pulse
CK Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
Figure 17. Simplified Schematic Diagram Of P0
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Functional Block Diagram (continued)
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
VCC
Configuration
Register
D
Q
FF
Write Configuration
Pulse
D
CK Q
Write Pulse
Q
FF
P7−P1
CK Q
Output
Port
Register
ESD Protection Diode
Input
Port
Register
D
GND
Input Port
Register Data
Q
FF
Read Pulse
CK Q
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity Pulse
CK Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
Figure 18. Simplified Schematic Diagram Of P7–P1
8.2 Device Functional Modes
8.2.1
RESET
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9557 registers and
I2C/SMBus state machine are held in their default states until RESET again is high. This input requires a pullup
resistor to VCC if no active connection is used.
8.2.1.1 RESET Errata
If RESET voltage set higher than VCC, current will flow from RESET pin to VCC pin.
System Impact
VCC will be pulled above its regular voltage level.
System Workaround
Design such that RESET voltage is same or lower than VCC.
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Device Functional Modes (continued)
8.2.2 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9557 in a reset condition until
VCC has reached VPOR. At that time, the reset condition is released, and the PCA9557 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and back up to the
operating voltage for a power-reset cycle. The RESET input can be asserted to reset the system, while keeping
the VCC at its operating level.
Refer to the Power-On Reset Errata section.
8.3 Programming
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 19). After the start condition, the device address
byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (A2–A0) inputs of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 20).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 19).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 21). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 19. Definition Of Start And Stop Conditions
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Programming (continued)
SDA
SCL
Data Line
Change
Figure 20. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Condition
Clock Pulse for
Acknowledgment
Figure 21. Acknowledgment On The I2C Bus
8.3.2 Register Map
Table 1. Interface Definition
BYTE
BIT
7 (MSB)
2
6
5
4
3
2
1
0 (LSB)
I C slave address
L
L
H
H
A2
A1
A0
R/W
Px I/O data bus
P7
P6
P5
P4
P3
P2
P1
P0
8.3.2.1 Device Address
The address of the PCA9557 is shown in Figure 22.
Slave Address
0
0
1
Fixed
1 A2 A1 A0 R/W
Programmable
Figure 22. Pca9557 Address
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Table 2. Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
A1
A0
L
L
L
L
L
H
25 (decimal), 19 (hexadecimal)
L
H
L
26 (decimal), 1A (hexadecimal)
L
H
H
27 (decimal), 1B (hexadecimal)
H
L
L
28 (decimal), 1C (hexadecimal)
H
L
H
29 (decimal), 1D (hexadecimal)
H
H
L
30 (decimal), 1E (hexadecimal)
H
H
H
31 (decimal), 1F (hexadecimal)
24 (decimal), 18 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.3.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9557. Two bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a new command byte has been sent, the register that was addressed continues to be accessed by reads
until a new command byte has been sent.
0
0
0
0
0
0
B1
B0
Figure 23. Control Register Bits
Table 3. Command Byte
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
0
0
0x00
Input Port
Read byte
xxxx xxxx
0
1
0x01
Output Port
Read/write byte
0000 0000
1
0
0x02
Polarity Inversion
Read/write byte
1111 0000
1
1
0x03
Configuration
Read/write byte
1111 1111
REGISTER
PROTOCOL
POWER-UP
DEFAULT
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8.3.2.3 Register Descriptions
The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to signal the I2C device that the
input port register will be accessed next.
Table 4. Register 0 (Input Port Register)
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 5. Register 1 (Output Port Register)
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
0
0
0
0
0
0
0
0
The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Table 6. Register 2 (Polarity Inversion Register)
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
1
1
1
1
0
0
0
0
The configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Register 3 (Configuration Register)
18
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
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8.4 Bus Transactions
Data is exchanged between the master and PCA9557 through write and read commands.
8.4.1 Writes
Data is transmitted to the PCA9557 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 22 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission (see Figure 24 and Figure 25).
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
0 1
Command Byte
1 A2 A1 A0 0
Start Condition
A
0
0
0
0
0
0
Data to Port
0
1
A
R/W ACK From Slave
Data 1
A
ACK From Slave
P
ACK From Slave
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 24. Write To Output Port Register
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
0
1
Command Byte
1 A2 A1 A0 0
Start Condition
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
0 1/0 A
Data
ACK From Slave
A
P
ACK From Slave
Figure 25. Write To Configuration Or Polarity Inversion Registers
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Bus Transactions (continued)
8.4.2 Reads
The bus master first must send the PCA9557 address with the LSB set to a logic 0 (see Figure 22 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the PCA9557 (see Figure 26 and Figure 27). After a restart, the value of the
register defined by the command byte matches the register being accessed when the restart occurred. Data is
clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data
bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
ACK From
Slave
Slave Address
S 0
0
1
1 A2 A1 A0 0
ACK From
Slave
Command Byte
A
R/W
A S 0
ACK From
ACK From
Master
Slave Data from Register
Slave Address
0
1
1 A2 A1 A0 1 A
At this moment, master-transmitter
becomes master-receiver, and
slave-receiver becomes
slave-transmitter
A
Data
First Byte
R/W
Data from Register
NACK From
Master
Data
NA P
Last Byte
Figure 26. Read From Register
SCL
1
2
3
4
5
6
7
8
9
Data From Port
Slave Address
SDA
S 0
0
1
1 A2 A1 A0 1
Start
Condition
R/W
Data 1
A
Data From Port
A
Data 4
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
A.
This figure assumes the command byte has been previously programmed with 00h.
B.
Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last
acknowledge phase is valid (output mode). Input data is lost.
C.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 26).
Figure 27. Read Input Port Register
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9 Application And Implementation
9.1 Application Information
9.2 Typical Application
Figure 28 shows an application in which the PCA9557 can be used.
VCC
(5 V)
VCC
Master
Controller
1.8 kΩ
1.8 kΩ
620 Ω
2 kΩ
2 kΩ
100 kΩ (X 5)
VCC
SCL
SCL
SDA
SDA
P0
Subsystem 1
INT
P1
RESET
RESET
P2
RESET
P3
GND
Subsystem 2
(e.g., Counter)
PCA9557
P4
P5
A2
A
Controlled Switch
(e.g., CBT Device)
P6
A1
P7
A0
ENABLE
B
GND
ALARM
Subsystem 3
(e.g., Alarm System)
GND
10 kΩ
A.
Device address is configured as 0011100 for this example.
B.
P1, P4, and P5 are configured as inputs.
C.
P0, P2, and P3 are configured as outputs.
D.
P6 and P7 are not used and must be configured as outputs.
Figure 28. Typical Application
9.2.1 Design Requirements
9.2.1.1 Minimizing ICC When I/O Is Used To Control Led
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 28.
The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC parameter in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs needing to minimize
current consumption, such as battery power applications, should consider maintaining the I/O pins greater than
or equal to VCC when the LED is off.
Figure 29 shows a high-value resistor in parallel with the LED. Figure 30 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply-current consumption when the LED is off.
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Typical Application (continued)
VCC
100 kW
LED
VCC
Pn
Figure 29. High-Value Resistor In Parallel With The Led
3.3 V
VCC
5V
LED
Pn
Figure 30. Device Supplied By A Low Voltage
10 Power Supply Recommendations
10.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
22
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCA9557D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9557
PCA9557DB
ACTIVE
SSOP
DB
16
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD557
PCA9557DBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD557
PCA9557DGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD557
PCA9557DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9557
PCA9557DT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9557
PCA9557PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD557
PCA9557PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD557
PCA9557PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD557
PCA9557PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD557
PCA9557RGVR
ACTIVE
VQFN
RGV
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD557
PCA9557RGVRG4
ACTIVE
VQFN
RGV
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD557
PCA9557RGYR
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD557
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Oct-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.6
2.5
12.0
16.0
Q1
PCA9557DBR
SSOP
DB
16
2000
330.0
16.4
8.2
PCA9557DGVR
TVSOP
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
PCA9557DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
PCA9557DT
SOIC
D
16
250
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
PCA9557PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
PCA9557PWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
PCA9557RGVR
VQFN
RGV
16
2500
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
PCA9557RGYR
VQFN
RGY
16
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Oct-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9557DBR
SSOP
DB
16
2000
367.0
367.0
38.0
PCA9557DGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
PCA9557DR
SOIC
D
16
2500
367.0
367.0
38.0
PCA9557DT
SOIC
D
16
250
367.0
367.0
38.0
PCA9557PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
PCA9557PWT
TSSOP
PW
16
250
367.0
367.0
35.0
PCA9557RGVR
VQFN
RGV
16
2500
367.0
367.0
35.0
PCA9557RGYR
VQFN
RGY
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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