PCF8574A
SCPS069G – JULY 2001 – REVISED AUGUST 2021
PCF8574A Remote 8-Bit I/O Expander for I2C Bus
1 Features
3 Description
•
•
•
•
•
This 8-bit input/output (I/O) expander for the two-line
bidirectional bus (I2C) is designed for 2.5-V to 6-V VCC
operation.
•
Low standby-current consumption of 10 μA max
I2C to parallel-port expander
Open-drain interrupt output
Compatible with most microcontrollers
Latched outputs with high-current drive capability
for directly driving LEDs
Latch-up performance exceeds 100 mA Per JESD
78, Class II
The device features an 8-bit quasi-bidirectional I/O
port (P0–P7), including latched outputs with highcurrent drive capability for directly driving LEDs. Each
quasi-bidirectional I/O can be used as an input or
output without the use of a data-direction control
signal. At power on, the I/Os are high. In this mode,
only a current source to VCC is active.
2 Applications
•
•
•
•
•
•
•
The PCF8574A device provides general-purpose
remote I/O expansion for most microcontroller families
via the I2C interface [serial clock (SCL), serial data
(SDA)].
Telecom shelters: filter units
Servers
Routers (telecom switching equipment)
Personal computers
Personal electronics
Industrial automation
Products with GPIO-Limited Processors
Device Information
PART NUMBER
PCF8574A
(1)
PACKAGE(1)
BODY SIZE (NOM)
VQFN (20)
4.50 mm × 3.50 mm
PDIP (16)
19.30 mm × 6.35 mm
SOIC (16)
10.30 mm × 7.50 mm
TSSOP (20)
6.50 mm × 4.40 mm
TVSOP (20)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
I2C or
SMBus Commander
(e.g. Processor)
SDA
SCL
INT
PCF8574A
A0
A1
A2
GND
P0
P1
P2
P3
P4
P5
P6
P7
Peripheral Devices
RESET, ENABLE,
or control inputs
INT or status
outputs
LEDs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCF8574A
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SCPS069G – JULY 2001 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 I2C Interface Timing Requirements.............................6
6.7 Switching Characteristics............................................6
6.8 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................14
9 Application Information Disclaimer............................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................19
10.1 Power-On Reset Requirements.............................. 19
11 Layout........................................................................... 21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Documentation Support.......................................... 22
12.2 Receiving Notification of Documentation Updates..22
12.3 Support Resources................................................. 22
12.4 Trademarks............................................................. 22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
Changes from Revision F (January 2015) to Revision G (August 2021)
Page
• Globally changed instances of legacy terminology to commander and responder where mentioned................ 1
• Changed the Thermal Information table............................................................................................................. 5
• Changed Figure 7-2 Responder address from: S0100 To: S0111...................................................................... 9
• Changed Figure 8-1 .........................................................................................................................................14
• Changed Note B from: configured as 0100000to: configured as 0111000....................................................... 16
Changes from Revision E (January 2015) to Revision F (January 2015)
Page
• Added Junction temperature to the Absolute Maximum Ratings .......................................................................4
• Changed Supply Current (A) To: Supply Current (µA) and fSCL = 400 kHz to fSCL = 100 kHz in Supply Current
vs Temperature .................................................................................................................................................. 7
• Changed Supply Current (A) To: Supply Current (µA) in Standby Supply Current vs Temperature .................. 7
• Changed Supply Current (A) To: Supply Current (µA) and fSCL = 400 kHz to fSCL = 100 kHz in Supply Current
vs Supply Voltage .............................................................................................................................................. 7
Changes from Revision D (October 2005) to Revision E (January 2015)
Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table.....................................................................................................................1
2
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16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
SDA
SCL
INT
P7
P6
P5
P4
SCL
NC
SDA
VCC
A0
A1
NC
A2
Figure 5-1. DW or N Package 16 Pins Top View
P7
1
1
20
19 P6
18 NC
2
3
17 P5
16 P4
4
5
15 GND
14 P3
6
7
13 NC
12 P2
8
9
P0
10
11
P1
A0
A1
A2
P0
P1
P2
P3
GND
INT
5 Pin Configuration and Functions
Figure 5-2. RGY Package 20 Pins Top View
INT
SCL
NC
SDA
VCC
A0
A1
NC
A2
P0
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
P7
P6
NC
P5
P4
GND
P3
NC
P2
P1
Figure 5-3. DGV or PW Package 20 Pins Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
1, 2, 3
I
Address inputs 0 through 2. Connect directly to VCC or ground. Pullup
resistors are not needed.
15
8
—
Ground
1
13
O
Interrupt output. Connect to VCC through a pullup resistor.
3, 8, 13, 18
-
—
Do not connect
10, 11, 12, 14,
16, 17, 19, 20
10, 11, 12, 14,
16, 17, 19, 20
4, 5, 6, 7,
9, 10, 11,
12
I/O
P-port input/output. Push-pull design structure.
SCL
2
2
14
I
Serial clock line. Connect to VCC through a pullup resistor
SDA
4
4
15
I/O
Serial data line. Connect to VCC through a pullup resistor.
VCC
5
5
16
—
Voltage supply
NAME
RGY
DGV or PW
DW or N
A[0..2]
6, 7, 9
6, 7, 9
GND
15
INT
1
NC
3, 8, 13, 18
P[0..7]
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
range(2)
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IOK
Input/output clamp current
VO < 0 or VO > VCC
IOL
Continuous output low current
VO = 0 to VCC
IOH
Continuous output high current
VO = 0 to VCC
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
(1)
(2)
–65
±400
μA
50
mA
–4
mA
±100
mA
150
°C
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
V(ESD)
(1)
(2)
Electrostatic discharge
pins(1)
Charged device model (CDM), per JEDEC specification JESD22C101, all pins(2)
UNIT
1000
V
1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
4
MAX
UNIT
VCC
Supply voltage
2.5
6
V
VIH
High-level input voltage
0.7 × VCC
VCC + 0.5
V
VIL
Low-level input voltage
–0.5
0.3 × VCC
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
–40
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V
–1
mA
25
mA
85
°C
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6.4 Thermal Information
PCF8574
THERMAL METRIC(1)
DGV
DW
N
PW
RGY
UNIT
20 PINS
16 PINS
16 PINS
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
112.2
79.7
48.3
99.5
41.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.2
42.5
35.6
34.5
42.5
°C/W
RθJB
Junction-to-board thermal resistance
53.4
44.4
28.2
50.5
16.9
°C/W
ψJT
Junction-to-top characterization parameter
1.8
14.8
20.5
2.0
0.8
°C/W
ψJB
Junction-to-board characterization parameter
52.8
43.8
28.1
49.9
16.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
5.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage(2)
VI = VCC or GND,
IOH
P port
VO = GND
IOHT
P-port transient pullup current
High during acknowledge, VOH = GND
SDA
VO = 0.4 V
P port
VO = 1 V
INT
VO = 0.4 V
IOL
VCC
2.5 V to 6 V
IO = 0
MIN TYP(1)
–1.2
6V
2.5 V to 6 V
30
2.5 V
2.5 V to 6 V
3
5V
10
2.5 V to 6 V
1.6
INT
ICC
Ci
Cio
300
VI = VCC or GND
(1)
(2)
μA
mA
25
mA
2.5 V to 6 V
±5
μA
±5
VI ≥ VCC or VI ≤ GND
Operating mode
VI = VCC or GND,
IO = 0,
Standby mode
VI = VCC or GND,
IO = 0
SCL
VI = VCC or GND
2.5 V to 6 V
VIO = VCC or GND
2.5 V to 6 V
P port
V
±5
P port
SDA
2.4
–1
A0, A1, A2
IIHL
UNIT
V
1.3
SCL, SDA
II
MAX
2.5 V to 6 V
fSCL = 100 kHz
6V
±400
40
100
2.5
10
1.5
7
3
7
4
10
μA
μA
pF
pF
All typical values are at VCC = 5 V, TA = 25°C.
The power-on reset circuit resets the I2C-bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).
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6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MIN
MAX
UNIT
100
kHz
fscl
I2C
tsch
I2C clock high time
tscl
I2C
tsp
I2C spike time
tsds
I2C
tsdh
I2C serial-data hold time
ticr
I2C
ticf
I2C input fall time
tocf
I2C
tbuf
I2C bus free time between stop and start
4.7
μs
tsts
I2C start or repeated start condition setup
4.7
μs
tsth
I2C
4
μs
tsps
I2C stop-condition setup
4
μs
tvd
Valid-data time
Cb
I2C bus capacitive load
clock frequency
4
clock low time
μs
4.7
μs
100
serial-data setup time
250
ns
0
ns
input rise time
output fall time (10-pF to 400-pF bus)
1
μs
0.3
μs
300
start or repeated start condition hold
ns
SCL low to SDA output valid
ns
3.4
μs
400
pF
MAX
UNIT
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-2)
PARAMETER
6
FROM
(INPUT)
TO
(OUTPUT)
SCL
P port
MIN
tpv
Output data valid
tsu
Input data setup time
P port
SCL
0
μs
th
Input data hold time
P port
SCL
4
μs
tiv
Interrupt valid time
P port
INT
4
μs
tir
Interrupt reset delay time
SCL
INT
4
μs
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4
μs
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
120
SCL = VCC
VCC = 5 V
Supply Current (mA)
Supply Current (mA)
100
90
fSCL = 100 kHz
All I/Os unloaded
80
60
40
VCC = 3.3 V
20
0
25
50
75
60
50
40
VCC = 2.5 V
30
VCC = 3.3 V
20
0
−50 −25
100 125
0
Temperature (°C)
20
fSCL = 100 kHz
90 All I/Os unloaded
80
18
70
14
50
40
TA = −40ºC
TA = 25ºC
12
10
8
30
6
20
4
10
2
TA = 85ºC
0
0.0
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.1
0.2
Figure 6-3. Supply Current vs Supply Voltage
TA = −40°C
TA = 25°C
10
0
0.0
0.5
0.6
VCC = 5 V
TA = −40ºC
30
ISINK (mA)
ISINK (mA)
35
25
TA = 25ºC
20
15
10
TA = 85°C
5
0.4
Figure 6-4. I/O Sink Current vs Output Low Voltage
VCC = 3.3 V
15
0.3
Vol (V)
Supply Voltage (V)
20
75 100 125
VCC = 2.5 V
16
60
25
50
Figure 6-2. Standby Supply Current vs Temperature
ISINK (mA)
Supply Current (mA)
25
Temperature (°C)
Figure 6-1. Supply Current vs Temperature
100
VCC = 5 V
10
VCC = 2.5 V
0
−50 −25
80 All I/Os unloaded
70
TA = 85ºC
5
0.1
0.2
0.3
0.4
0.5
0
0.0
0.6
0.1
0.2
0.3
0.4
0.5
0.6
VOL (V)
VOL (V)
Figure 6-5. I/O Sink Current vs Output Low Voltage
Figure 6-6. I/O Sink Current vs Output Low Voltage
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
600
40
VCC = 5 V, ISINK = 10 mA
300
VCC = 2.5 V, ISINK = 10 mA
200
100
VCC = 5 V,
ISINK = 1 mA
VCC = 2.5 V,
ISINK = 1mA
VCC = 2.5 V
35
400
ISOURCE (mA)
VOL (mV)
500
45
TA = 25ºC
30
25
20
15
TA = 85°C
10
5
0
−50 −25 0
25
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
75 100 125
VCC − VOH (V)
Temperature (°C)
Figure 6-8. I/O Source Current vs Output High Voltage
Figure 6-7. I/O Output Low Voltage vs Temperature
45
45
ISOURCE (mA)
35
VCC = 3.3 V
TA = 25ºC
40
TA = −40ºC
30
25
20
15
TA = 85ºC
10
VCC = 5 V
35
ISOURCE (mA)
40
TA = −40ºC
30
TA = −40ºC
TA = 25ºC
25
20
15
TA = 85ºC
10
5
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VCC − VOH (V)
VCC − VOH (V)
Figure 6-10. I/O Source Current vs Output High Voltage
Figure 6-9. I/O Source Current vs Output High Voltage
VCC − VOH (V)
350
300
VCC = 5 V
250
VCC = 3.3 V
200
VCC = 2.5 V
150
100
50
0
−50 −25 0
25
50
75 100 125
Temperature (ºC)
Figure 6-11. I/O High Voltage vs Temperature
8
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
DUT
Pn
CL = 10 pF to 400 pF
LOAD CIRCUIT
2 Bytes for Complete Device
Programming
Stop
Condition
(P)
Start
Condition
(S)
Bit 7
MSB
Bit 0
LSB
(R/W)
Bit 6
tscl
Acknowledge
(A)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
tPHL
ticf
tbuf
tsts
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticr
ticf
tsth
tsdh
tsds
Start or
Repeat
Start
Condition
tsps
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
Figure 7-1.
I2C
Interface Load Circuit and Voltage Waveforms
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Acknowledge
From Responder
Start
Condition
Responder Address
S
Acknowledge
From Responder
R/W
0
1
1
1
1
2
3
4
Data From Port
A2 A1 A0
5
6
7
A
8
Data From Port
Data 1
A
A
Data 3
1
P
A
t ir
t ir
B
B
INT
A
t iv
t sps
A
Data
Into
Port
Data 1
Data 2
0.7 × V CC
INT
Data 3
0.7 × V CC
SCL
R/W
0.3 × V CC
A
t iv
0.3 × V CC
t ir
0.7 × V CC
Pn
0.7 × V CC
INT
0.3 × V CC
0.3 × V CC
View A−A
View B−B
Figure 7-2. Interrupt Voltage Waveforms
SCL
0.7 × VCC
W
A
D
0.3 × VCC
Responder
Acknowledge
SDA
tpv
Pn
Unstable
Data
Last Stable Bit
Figure 7-3. I2C Write Voltage Waveforms
10
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VCC
VCC
RL = 1 kΩ
DUT
RL = 4.7 kΩ
SDA
DUT
INT
CL = 10 pF to 400 pF
CL = 10 pF to 400 pF
GND
GND
SDA LOAD CONFIGURATION
INTERRUPT LOAD CONFIGURATION
Figure 7-4. Load Circuits
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8 Detailed Description
8.1 Overview
The PCF8574A device provides general-purpose remote I/O expansion for most microcontroller families via the
I2C interface [serial clock (SCL), serial data (SDA)].
The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high-current
drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without
the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to
VCC is active. An additional strong pullup to VCC allows fast rising edges into heavily loaded outputs. This device
turns on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be high
before being used as inputs.
The PCF8574A device provides an open-drain output ( INT) that can be connected to the interrupt input of a
microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After
time, tiv, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed
to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs
in the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the
acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge
clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of
the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or
writing to, another device does not affect the interrupt circuit.
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming
data on its ports without having to communicate via the I2C bus. Therefore, the PCF8574A device can remain a
simple responder device.
8.2 Functional Block Diagram
8.2.1 Simplified Block Diagram of Device
PCF8574A
INT
A0
A1
A2
13
Interrupt
Logic
LP Filter
1
4
2
5
3
6
14
SCL
SDA
15
Input
Filter
I2C Bus
Control
7
Shift
Register
8 Bit
I/O
Port
9
10
11
12
P0
P1
P2
P3
P4
P5
P6
P7
Write Pulse
VCC
GND
Read Pulse
16
8
Power-On
Reset
Pin numbers shown are for the DW and N packages.
12
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8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output
VCC
Write Pulse
100 µA
Data From
Shift Register
D
Q
FF
P0−P7
CI
S
Power-On
Reset
D
Q
GND
FF
CI
Read Pulse
S
To Interrupt
Logic
Data to
Shift Register
8.3 Feature Description
8.3.1 I2C Interface
I2C communication with this device is initiated by a commander sending a start condition, a high-to-low transition
on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, mostsignificant bit (MSB) first, including the data direction bit (R/ W). This device does not respond to the general call
address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA
I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the responder device
must not be changed between the start and the stop conditions.
The data byte follows the address acknowledge. If the R/ W bit is high, the data from this device are the values
read from the P port. If the R/ W bit is low, the data are from the commander, to be output to the P port. The
data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the commander,
following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received
and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during
the clock cycle for the acknowledge.
A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the commander.
8.3.2 Interface Definition
BYTE
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
H
H
A2
A1
A0
R/ W
P7
P6
P5
P4
P3
P2
P1
P0
I2C
responder
address
I/O data bus
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8.3.3 Address Reference
INPUTS
I2C BUS responder
8-BIT WRITE
ADDRESS
A2
A1
A0
I2C BUS responder 8-BIT
READ ADDRESS
L
L
L
113 (dec), 71 (hex)
112 (dec), 70 (hex)
L
L
H
115 (dec), 73 (hex)
114 (dec), 72 (hex)
L
H
L
117 (dec), 75 (hex)
116 (dec), 74 (hex)
L
H
H
119 (dec), 77 (hex)
118 (dec), 76 (hex)
H
L
L
121 (dec), 79 (hex)
120 (dec), 78 (hex)
H
L
H
123 (dec), 7B (hex)
122 (dec), 7A (hex)
H
H
L
125 (dec), 7D (hex)
124 (dec), 7C (hex)
H
H
H
127 (dec), 7F (hex)
126 (dec), 7E (hex)
8.4 Device Functional Modes
Figure 8-1 and Figure 8-2 show the address and timing diagrams for the write and read modes, respectively.
SCL
1
2
3
4
5
6
7
8
9
data 1
respon der address
S
SDA
A6
A5
A4
A3
A2
A1
START condition
A0
0
R/W
A
P7
P6
acknowledge
from re spo nder
1
P4
P3
data 2
P2
P1
P0
A
P7
P6
acknowledge
from re spo nder
P5
0
P4
P3
P2
P0
A
acknowledge
from re spo nder
P5
write to port
tV(Q)
data output from port
tV(Q)
DATA 1 VA LID
DATA 2 VA LID
P5 output voltage
Itrt(p u)
P5 pull-up output curr ent
IOH
INT
td(rst)
Figure 8-1. Write Mode (Output)
14
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SCL
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1
2
3
4
5
6
7
8
R/W
SDA S
0
1
1
1 A2
A1
A0 1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
ACK
From Commander
ACK
From Responder
A
1
P7 P6 P5 P4 P3 P2 P1
P0
A P7
P6 P5 P4
ACK
From Commander
P3 P2
P1 P0
A P7 P6
Read From
Port
Data Into
Port
P7 to P0
P7 to P0
th
tsu
INT
tiv
A.
tir
tir
A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any
moment bya stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.
Figure 8-2. Read Mode (Input)
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Figure 9-1 shows an application in which the PCF8574A device can be used.
9.2 Typical Application
VCC
(1)
VCC
10 kΩ
(1)
10 kΩ
2 kΩ
16
10 kΩ
VCC
15
4
SDA
SDA
Commander
SCL
Controller
14
INT
13
P0
SCL
5
P1
Subsystem 1
(e.g., temperature sensor)
INT
INT
P2
P3
GND
100 kΩ
(x 3)
PCF8574A
P4
6
7
RESET
9
Subsystem 2
(e.g., counter)
10
P5
3
A2
P6
A
ENABLE
A1
1
Controlled Device
(e.g., CBT device)
11
2
P7
12
A0
GND
B
ALARM
8
Subsystem 3
(e.g., alarm system)
VCC
A.
B.
C.
D.
E.
The SCL and SDA pins must be pulled up to VCC because if SCL and SDA are pulled up to an auxiliary power supply that could be
powered on while VCC is powered off, then the supply current, ICC, will increase as a result.
Device address is configured as 0111000 for this example.
P0, P2, and P3 are configured as outputs.
P1, P4, and P5 are configured as inputs.
P6 and P7 are not used and must be configured as outputs.
Figure 9-1. Application Schematic
16
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9.2.1 Design Requirements
9.2.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 11-1. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a
diode, with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VI is a VT
drop below VCC.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 9-2 shows
a high-value resistor in parallel with the LED. Figure 9-3 shows VCC less than the LED supply voltage by at
least VT. Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current
consumption when the P-port is configured as an input and the LED is off.
VCC
LED
100 kΩ
VCC
LEDx
Figure 9-2. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
LEDx
Figure 9-3. Device Supplied by a Lower Voltage
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9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all responders on the I2C bus. The minimum pull-up resistance is a
function of VCC, VOL,(max), and IOL:
Rp(min) =
VCC - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
= 400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the PCF8574A device, Ci for
SCL or Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional responders
on the bus.
9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC 2 V
Figure 9-5. Minimum Pull-Up Resistance (Rp(min))
vs Pull-Up Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCF8574A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 10-1. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 10-2. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 10-1 specifies the performance of the power-on reset feature for PCF8574A for both types of power-on
reset.
Table 10-1. Recommended Supply Sequencing and Ramp Rates(1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 10-1
1
100
ms
VCC_RT
Rise rate
See Figure 10-1
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 10-1
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 10-2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 10-3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 10-3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on fising VCC
1.033
1.428
V
(1)
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide more
information on how to measure these specifications.
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VCC
VCC_GH
Time
VCC_GW
Figure 10-3. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and
all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR
differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this
specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 10-4. VPOR
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of PCF8574A, common PCB layout practices should be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power
in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors should be placed as close to the PCF8574A device as possible. These best practices are shown in
Figure 11-1.
For the layout example provided in Figure 11-1, it would be possible to fabricate a PCB with only 2 layers
by using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground
(GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB,
it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and
dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and
ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC or GND
and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when
a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in
Figure 11-1.
11.2 Layout Example
Figure 11-1. Layout Example for PCF8574A
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
22
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCF8574ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF574A
Samples
PCF8574ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8574A
Samples
PCF8574ADWE4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8574A
Samples
PCF8574ADWG4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8574A
Samples
PCF8574ADWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8574A
Samples
PCF8574AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
PCF8574AN
Samples
PCF8574ANE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
PCF8574AN
Samples
PCF8574APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF574A
Samples
PCF8574APWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF574A
Samples
PCF8574APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF574A
Samples
PCF8574APWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF574A
Samples
PCF8574APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF574A
Samples
PCF8574ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PF574A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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