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PCF8575C
SCPS123F – MARCH 2005 – REVISED JANUARY 2015
PCF8575C Remote 16-Bit I2C AND SMBus Low-Power I/O Expander
with Interrupt Output
1 Features
•
•
•
1
•
•
•
•
•
•
3 Description
This 16-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 4.5-V to 5.5-V VCC
operation.
2
I C to Parallel-Port Expander
Open-Drain Interrupt Output
Low Standby-Current Consumption of
10 μA Maximum
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
Address by Three Hardware Address Pins for Use
of up to Eight Devices
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
The PCF8575C provides general-purpose remote I/O
expansion for most microcontroller families via the I2C
interface serial clock (SCL) and serial data (SDA).
The device features a 16-bit quasi-bidirectional
input/output (I/O) port (P07–P00, P17–P10), including
latched outputs with high-current drive capability for
directly driving LEDs. Each quasi-bidirectional I/O can
be used as an input or output without the use of a
data-direction control signal. At power on, the I/Os
are in 3-state mode. The strong pullup to VCC allows
fast-rising edges into heavily loaded outputs. This
device turns on when an output is written high and is
switched off by the negative edge of SCL. The I/Os
should be high before being used as inputs. After
power on, as all the I/Os are set to 3-state, all of them
can be used as inputs. Any change in setting of the
I/Os as either inputs or outputs can be done with the
write mode. If a high is applied externally to an I/O
that has been written earlier to low, a large current
(IOL) flows to GND.
2 Applications
•
•
•
•
•
•
•
Telecom Shelters: Filter Units
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics
Industrial Automation
Products with GPIO-Limited Processors
Device Information(1)
PART NUMBER
PCF8575C
PACKAGE (PIN)
BODY SIZE
SSOP (24)
8.20 mm × 5.30 mm
QSOP (24)
8.65 mm × 3.90
TVSOP (24)
5.00 mm × 4.50 mm
SOIC (24)
15.40 mm × 7.50 mm
TSSOP (24)
7.80 mm × 4.40 mm
QFN (24)
4.0 mm × 4.0 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
I2C or SMBus Master
(e.g. Processor)
SDA
SCL
INT
A0
A1
A2
GND
P00
P01
P02
P03
P04
P05
P06
P07
Peripheral Devices
RESET, ENABLE,
or control inputs
INT or status
outputs
LEDs
P10
P11
P12
P13
P14
P15
P16
P17
Peripheral Devices
RESET, ENABLE,
or control inputs
INT or status
outputs
LEDs
PCF8575C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCF8575C
SCPS123F – MARCH 2005 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration...................................................
Specifications.........................................................
1
1
1
2
3
4
6.1 Absolute Maximum Ratings .....................................
6.2 ESD Ratings..............................................................
6.3 Recommended Operating Conditions......................
6.4 Thermal Information ..................................................
6.5 Electrical Characteristics..........................................
6.6 I2C Interface Timing Requirements..........................
6.7 Switching Characteristics.........................................
6.8 Typical Characteristics ..............................................
4
4
4
4
5
5
6
6
Parameter Measurement Information .................. 8
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 20
10.1 Power-On Reset Requirements ........................... 20
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1 Trademarks ........................................................... 24
12.2 Electrostatic Discharge Caution ............................ 24
12.3 Glossary ................................................................ 24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision E (October 2007) to Revision F
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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SCPS123F – MARCH 2005 – REVISED JANUARY 2015
5 Pin Configuration
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
24 23 22 21 20 19
P00
1
18 A0
P01
2
17 P17
P03
3
16 P16
P03
4
15 P15
P04
5
14 P14
P05
6
13 P13
7 8 9 10 11 12
P12
24
2
A2
A1
INT
VCC
1
P06
P07
GND
P10
P11
INT
A1
A2
P00
P01
P02
P03
P04
P05
P06
P07
GND
SDA
SCL
RGE PACKAGE
(TOP VIEW)
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
DB, DBQ, DGV,
DW, AND PW
RGE
INT
1
22
I
Interrupt output. Connect to VCC through a pullup resistor.
A1
2
23
I
Address input 1. Connect directly to VCC or ground. Pullup resistors are not needed.
A2
3
24
I
Address input 2. Connect directly to VCC or ground. Pullup resistors are not needed.
P00
4
1
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P01
5
2
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P02
6
3
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P03
7
4
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P04
8
5
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P05
9
6
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P06
10
7
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P07
11
8
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
GND
12
9
—
Ground
P10
13
10
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P11
14
11
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P12
15
12
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P13
16
13
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P14
17
14
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P15
18
15
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P16
19
16
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
P17
20
17
I/O
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
A0
21
18
I
Address input 0. Connect directly to VCC or ground. Pullup resistors are not needed.
SCL
22
19
I
Serial clock line. Connect to VCC through a pullup resistor
SDA
23
20
I/O
Serial data line. Connect to VCC through a pullup resistor.
VCC
24
21
—
Supply voltage
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SCPS123F – MARCH 2005 – REVISED JANUARY 2015
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6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
V
(2)
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IOK
Input/output clamp current
VO < 0 or VO > VCC
IOL
Continuous output low current
VO = 0 to VCC
IOH
Continuous output high current
VO = 0 to VCC
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature range
UNIT
V
–20
mA
–20
mA
±400
μA
50
mA
–4
mA
±100
mA
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
6.3
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
2000
Charged device model (CDM), per JEDEC specification JESD22C101, all pins
1000
UNIT
V
Recommended Operating Conditions
VCC
MIN
MAX
4.5
5.5
A0, A1, A2, SDA, and SCL
0.7 × VCC
VCC + 0.5
P07–P00 and P17–P10
0.8 × VCC
VCC + 0.5
A0, A1, A2, SDA, and SCL
–0.5
0.3 × VCC
P07–P00 and P17–P10
–0.5
0.6 × VCC
Supply voltage
UNIT
V
VIH
High-level input voltage
VIL
Low-level input voltage
IOHT
P-port transient pullup current
–10
mA
IOL
P-port low-level output current
25
mA
TA
Operating free-air temperature
85
°C
–40
V
V
6.4 Thermal Information
PCF8575
THERMAL METRIC
(1)
DB
DBQ
DGV
DW
PW
RGE
UNIT
88
53
°C/W
24 PINS
RθJA
(1)
4
Junction-to-ambient thermal resistance
63
61
86
46
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5
SCPS123F – MARCH 2005 – REVISED JANUARY 2015
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input diode clamp voltage
VPOR Power-on reset voltage
IOHT
(2)
II = –18 mA
VI = VCC or GND,
IO = 0
P-port transient pullup current
High during ACK VOH = GND
SDA
VOL = 0.4 V
VCC
MIN
4.5 V to
5.5 V
–1.2
VPOR
VOL = 0.4 V
VOL = 1 V
VOL = 0.4 V
4.5 V to
5.5 V
VI = VCC or GND
4.5 V to
5.5 V
P port
VI ≥ VCC or VI ≤ GND
4.5 V to
5.5 V
Operating mode
VI = VCC or GND,
IO = 0, fSCL = 400 kHz
Standby mode
VI = VCC or GND,
IO = 0, fSCL = 0 kHz
ΔICC
Supply current increase
One input at VCC – 0.6 V,
Other inputs at VCC or GND
4.5 V to
5.5 V
Ci
SCL
VI = VCC or GND
4.5 V to
5.5 V
VIO = VCC or GND
4.5 V to
5.5 V
P port
INT
SCL, SDA
II
A0, A1, A2
IIHL
ICC
Cio
(1)
(2)
6.6
SDA
P port
–0.5
4.5 V to
5.5 V
MAX
UNIT
V
1.2
4.5 V
4.5 V to
5.5 V
IOL
TYP (1)
1.8
–1
V
mA
3
5
15
10
25
mA
1.6
±2
±1
±400
5.5 V
100
200
2.5
10
μA
μA
μA
200
μA
3
7
pF
3
7
4
10
pF
All typical values are at VCC = 5 V, TA = 25°C.
The power-on reset circuit resets the I2C bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7)
MIN
MAX
UNIT
400
kHz
fscl
I2C clock frequency
tsch
I2C clock high time
0.6
μs
tscl
I2C clock low time
1.3
μs
2
tsp
I C spike time
tsds
I2C serial-data setup time
tsdh
I2C serial-data hold time
50
2
ns
0
ns
ticr
I C input rise time
20 + 0.1Cb
(1)
ticf
I2C input fall time
20 + 0.1Cb
(1)
tocf
I2C output fall time (10-pF to 400-pF bus)
2
ns
100
300
ns
300
ns
300
ns
tbuf
I C bus free time between stop and start
1.3
μs
tsts
I2C start or repeated start condition setup
0.6
μs
tsth
I2C start or repeated start condition hold
0.6
μs
tsps
I2C stop condition setup
0.6
μs
tvd
Valid-data time
Cb
I2C bus capacitive load
(1)
SCL low to SDA output valid
1.2
μs
400
pF
Cb = total bus capacitance of one bus line in pF
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SCPS123F – MARCH 2005 – REVISED JANUARY 2015
6.7
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Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 8 and Figure 9)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
tiv
Interrupt valid time
P port
INT
4
μs
tir
Interrupt reset delay time
SCL
INT
4
μs
tpv
Output data valid
SCL
P port
4
μs
tsu
Input data setup time
P port
SCL
0
μs
th
Input data hold time
P port
SCL
4
μs
6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
9
100
fSCL = 400 kHz
All I/Os unloaded
Supply Current (mA)
80
VCC = 5 V
70
60
50
40
30
6
VCC = 5 V
5
4
3
2
10
1
0
−50
−25
0
25 50 75
Temperature (°C)
−50 −25
100 125
Figure 1. Supply Current vs Temperature
90
0
25 50 75
Temperature (°C)
35
fSCL = 400 kHz
All I/Os unloaded
VCC = 5 V
TA = −40ºC
30
80
ISINK (mA)
70
60
50
40
100 125
Figure 2. Standby Supply Current vs Temperature
100
Supply Current (mA)
7
20
0
30
25
TA = 25ºC
20
15
10
20
TA = 85ºC
5
10
0
0.0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.1
0.2
0.3
0.4
0.5
0.6
VOL (V)
Supply Voltage (V)
Figure 3. Supply Current vs Supply Voltage
6
SCL = VCC
All I/Os unloaded
8
Supply Current (mA)
90
Figure 4. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
500
400
VCC = 5 V,I SINK= 10 mA
300
VOL (mV)
400
VCC − VOH (V)
350
250
200
300
200
150
100
100
VCC = 5 V,ISINK = 1mA
VCC = 5 V, ISOURCE = 10 mA
50
0
−50
0
−25
0
25
50
75
100 125
−50
Temperature (°C)
Figure 5. I/O Output Low Voltage vs Temperature
−25
0
25 50 75
Temperature (°C)
100 125
Figure 6. I/O High Voltage vs Temperature
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7 Parameter Measurement Information
VCC
RL = 1 kW
DUT
SDA
CL = 50 pF
SDA LOAD CONFIGURATION
3 Bytes for Complete Device
Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
tPHL
ticf
tbuf
tsts
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
Figure 7. I2C Interface Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
16 Bits
(2 Data Bytes)
From Port
R/W
Slave Address (PCF8575)
S
0
1
0
0 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data 2
Data From Port
A
Data 3
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
SCL
0.3 × VCC
Data 2
Data 3
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
View A−A
View B−B
Figure 8. Interrupt Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
VCC
RL = 1 kΩ
DUT
RL = 4.7 kΩ
SDA
DUT
INT
DUT
CL = 50 pF
CL = 100 pF
GND
CL = 100 pF
GND
SDA LOAD CONFIGURATION
SCL
Pn
GND
INTERRUPT LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
0.7 × VCC
P00
A
P17
0.3 × VCC
Slave
ACK
SDA
tpv
Pn
Unstable
Data
Last Stable Bit
Write-Mode Timing (R/W = 0)
SCL
0.7 × VCC
P00
A
tsu
P17
0.3 × VCC
th
0.7 × VCC
Pn
0.3 × VCC
Read-Mode Timing (R/W = 1)
Figure 9. P-Port Load Circuits and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The PCF8575C provides an open-drain interrupt (INT) output, which can be connected to the interrupt input of a
microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After
time (tiv), the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port
is changed to the original setting, or data is read from or written to the port that generated the interrupt. Resetting
occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal or in the write
mode at the ACK bit after the falling edge of the SCL signal. Interrupts that occur during the ACK clock pulse can
be lost (or be very short), due to the resetting of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the
interrupt circuit.
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports, without having to communicate via the I2C bus. Thus, the PCF8575C can remain a simple slave
device.
Every data transmission to or from the PCF8575C must consist of an even number of bytes. The first data byte
in every pair refers to port 0 (P07–P00), and the second data byte in every pair refers to port 1 (P17–P10). To
write to the ports (output mode), the master first addresses the slave device, setting the last bit of the byte
containing the slave address to logic 0. The PCF8575C acknowledges and the master sends the first data byte
for P07–P00. After the first data byte is acknowledged by the PCF8575C, the second data byte (P17–P10) is
sent by the master. Once again, the PCF8575C acknowledges the receipt of the data, after which this 16-bit data
is presented on the port lines.
The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is
overwritten. When the PCF8575C receives the pairs of data bytes, the first byte is referred to as P07–P00 and
the second byte as P17–P10. The third byte is referred to as P07–P00, the fourth byte as P17–P10, and so on.
Before reading from the PCF8575C, all ports desired as input should be set to logic 1. To read from the ports
(input mode), the master first addresses the slave device, setting the last bit of the byte containing the slave
address to logic 1. The data bytes that follow on the SDA are the values on the ports. If the data on the input port
changes faster than the master can read, this data may be lost.
When power is applied to VCC, an internal power-on reset holds the PCF8575C in a reset state until VCC has
reached VPOR. At that time, the reset condition is released, and the device I2C-bus state machine initializes the
bus to its default state.
The hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, and allow up to eight
devices to share the same I2C bus or SMBus. The fixed I2C address of the PCF8575C is the same as the
PCF8575, PCF8574, PCA9535, and PCA9555, allowing up to eight of these devices, in any combination, to
share the same I2C bus or SMBus.
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8.2 Functional Block Diagram
8.2.1 Simplified Block Diagram of Device
INT
A0
A1
A2
SCL
SDA
PCF8575C
1
Interrupt
Logic
LP Filter
21
2
P07−P00
3
22
23
I2C Bus
Control
Input
Filter
Shift
Register
I/O
Port
16 Bits
P17−P10
Write Pulse
VCC
GND
24
12
Read Pulse
Power-On
Reset
8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output
VCC
Write Pulse
IOHT
Data From
Shift Register
D
Q
FF
P07−P00
CI
IOL
S
Power-On
Reset
D
P17−P10
Q
GND
FF
Read Pulse
CI
S
To Interrupt
Logic
Data To
Shift Register
12
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8.3 Feature Description
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 10). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output
during the high of the ACK-related clock pulse. The address inputs (A2–A0) of the slave device must not be
changed between the start and the stop conditions.
The data byte follows the address ACK. If the R/W bit is high, the data from this device are the values read from
the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed
by an ACK sent from this device. If other data bytes are sent from the master, following the ACK, they are
ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data is
valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 11).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 10).
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
A slave receiver that is addressed must generate an ACK after the reception of each byte. Also, a master must
generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device
that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low
during the high pulse of the ACK-related clock period (see Figure 12). Setup and hold times must be taken into
account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 10. Definition of Start and Stop Conditions
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Feature Description (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 11. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL from
Master
1
2
89
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 12. Acknowledgment on I2C Bus
8.3.2 Interface Definition
BYTE
2
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I C slave address
L
H
L
L
A2
A1
A0
R/W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
14
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8.3.3 Address Reference
INPUTS
I2C BUS SLAVE
8-BIT READ
ADDRESS
I2C BUS SLAVE
8-BIT WRITE
ADDRESS
A2
A1
A0
L
L
L
65 (decimal), 41
(hexadecimal)
64 (decimal), 40
(hexadecimal)
L
L
H
67 (decimal), 43
(hexadecimal)
66 (decimal), 42
(hexadecimal)
L
H
L
69 (decimal), 45
(hexadecimal)
68 (decimal), 44
(hexadecimal)
L
H
H
71 (decimal), 47
(hexadecimal)
70 (decimal), 46
(hexadecimal)
H
L
L
73 (decimal), 49
(hexadecimal)
72 (decimal), 48
(hexadecimal)
H
L
H
75 (decimal), 4B
(hexadecimal)
74 (decimal), 4A
(hexadecimal)
H
H
L
77 (decimal), 4D
(hexadecimal)
76 (decimal), 4C
(hexadecimal)
H
H
H
79 (decimal), 4F
(hexadecimal)
78 (decimal), 4E
(hexadecimal)
8.4 Device Functional Modes
Figure 13 and Figure 14 show the address and timing diagrams for the write and read modes, respectively.
Integral Multiples of Two Bytes
SCL
1
2
3
4
5
6
7
8
1
2
3
4
5
ACK
From Slave
Start
Condition
R/W
S
0
1
0
0
7
8
1
Data
A2 A1 A0
0
A
P7
2
3
4
5
6
7
8
ACK
From Slave
ACK
From Slave
Slave Address
SDA
6
P6
1
Data
P0
A P7
P0
A
P5
Write to
Port
Data A0
and B0
Valid
Data Output
Voltage
tpv
P5 Output
Voltage
IOH
P5 Pullup
Output
Current
IOHT
INT
tir
Figure 13. Write Mode (Output)
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Device Functional Modes (continued)
SCL
1
2
3
4
5
6
7
8
R/W
SDA S
0
1
0
0 A2
A1
A0 1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
ACK
From Master
ACK
From Slave
A
1
P7 P6 P5 P4 P3 P2 P1
P0
A P7
ACK
From Master
P6 P5 P4
P3 P2
P1 P0
A P7 P6
Read From
Port
Data Into
Port
P7 to P0
P7 to P0
th
tsu
INT
tiv
tir
tir
Figure 14. Read Mode (Input)
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 15 shows an application in which the PCF8575C can be used.
9.2 Typical Application
VCC
(1)
VCC
10 kΩ
4
SDA
SDA
100 kΩ
(x 3)
VCC
23
Master
Controller
2 kΩ
24
10 kΩ(1) 10 kΩ
P00
Subsystem 1
(e.g., temperature sensor)
22
SCL
SCL
1
INT
5
P01
INT
INT
P02
P03
GND
6
RESET
7
Subsystem 2
(e.g., counter)
PCF8575C
8
P04
9
P05
3
A2
P06 10
A1
P07 11
A0
P10 13
2
21
A
Controlled Device
(e.g., CBT device)
ENABLE
B
P11 14
ALARM
P12 15
P13 16
Subsystem 3
(e.g., alarm system)
P14 17
VCC
P15 18
P16 19
P17 20
GND
12
(1)
The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply
that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result.
A.
Device address is configured as 0100000 for this example.
B.
P0, P2, and P3 are configured as outputs.
C.
P1, P4, and P5 are configured as inputs.
D.
P6 and P7 are not used and must be configured as outputs.
Figure 15. Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 15. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode,
with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VI is a VT drop
below VCC.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 16 shows a highvalue resistor in parallel with the LED. Figure 17 shows VCC less than the LED supply voltage by at least VT.
Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption
when the P-port is configured as an input and the LED is off.
VCC
LED
100 kΩ
VCC
LEDx
Figure 16. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
LEDx
Figure 17. Device Supplied by a Lower Voltage
18
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL:
Rp(min) =
VCC - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9534, Ci for SCL or
Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus.
9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC 2 V
Figure 19. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCF8575C can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 20 and Figure 21.
VCC
Ramp-Up
Ramp-Down
Re-Ramp-Up
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 20. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 21. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 1 specifies the performance of the power-on reset feature for PCF8575C for both types of power-on reset.
Table 1. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES (1)
MAX
UNIT
VCC_FT
Fall rate
PARAMETER
See Figure 20
1
100
ms
VCC_RT
Rise rate
See Figure 20
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 20
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 21
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 22
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 22
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on fising VCC
1.033
1.428
V
(1)
20
MIN
TYP
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 22 and Table 1 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
Figure 22. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 23 and Table 1 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 23. VPOR
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the PCF8575C device, common PCB layout practices should be
followed but additional concerns related to high-speed data transfer such as matched impedances and
differential pairs are not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors should be placed as close to the PCF8575C as possible. These best practices are shown in
Figure 24.
For the layout example provided in Figure 24, it would be possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However,
a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to
route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other
internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are
placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is
connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace
needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 24.
22
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11.2 Layout Example
LEGEND
To I2C Master
To I2C Master
Power or GND Plane
VCC
VIA to Power Plane
VIA to GND Plane
INT
VCC
24
2
A1
SDA
23
3
A2
SCL
22
4
P00
A0
21
5
P01
P17
20
P16
19
P15
18
P14
17
02
7
P03
8
P04
9
P05
P13
16
10
P06
P12
15
11
P07
P11
14
12
GND
P10
13
To I/Os
To I/Os
6P
PCF8575C
1
To I/Os
To I/Os
By-pass/De-coupling
capacitors
GND
Figure 24. Layout Example for PCF8575C
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
24
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCF8575CDB
ACTIVE
SSOP
DB
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575C
Samples
PCF8575CDBE4
ACTIVE
SSOP
DB
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575C
Samples
PCF8575CDBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PCF8575C
Samples
PCF8575CDBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575C
Samples
PCF8575CDGVR
ACTIVE
TVSOP
DGV
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575C
Samples
PCF8575CDW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8575C
Samples
PCF8575CDWE4
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8575C
Samples
PCF8575CDWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8575C
Samples
PCF8575CPW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575C
Samples
PCF8575CPWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575C
Samples
PCF8575CRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PF575C
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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