PCM1602A
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SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
24-Bit, 192-kHz Sampling, 6-Channel, Enhanced Multilevel,
Delta-Sigma Digital-to-Analog Converter
Check for Samples: PCM1602A
FEATURES
1
• 24-Bit Resolution
• Analog Performance:
– Dynamic Range: 105 dB, Typical
– SNR: 105 dB, Typical
– THD+N: 0.002%, Typical
– Full-Scale Output: 3.1 VPP, Typical
• 4×/8× Oversampling Interpolation Filter:
– Stop-Band Attenuation: –55 dB
– Pass-Band Ripple: ±0.03 dB
• Sampling Frequency:
– 5 kHz to 200 kHz (Channels 1 and 2)
– 5 kHz to 100 kHz (Channels 3, 4, 5, and 6)
• Accepts 16-, 18-, 20-, and 24-Bit Audio Data
• Data Formats: Standard, I2S™, and
Left-Justified
• System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512
fS, or 768 fS
• User-Programmable Functions:
– Digital Attenuation: 0 dB to –63 dB,
0.5 dB/Step
– Soft Mute
– Zero Flags Can Be Used As GeneralPurpose Logic Output
– Digital De-Emphasis
– Digital Filter Rolloff: Sharp or Slow
• Dual-Supply Operation:
– 5-V Analog
– 3.3-V Digital
• 5-V Tolerant Digital Logic Inputs
• Package: LQFP-48
2345
APPLICATIONS
•
•
•
•
•
•
•
Integrated A/V Receivers
DVD Movie and Audio Players
HDTV Receivers
Car Audio Systems
DVD Add-On Cards for High-End PCs
Digital Audio Workstations
Other Multichannel Audio Systems
DESCRIPTION
The PCM1602A is a CMOS, monolithic integrated
circuit that features six 24-bit audio digital-to-analog
converters (DACs) and support circuitry in a small
LQFP-48 package. The DACs use Texas Instruments'
enhanced multilevel, delta-sigma architecture that
employs fourth-order noise shaping and 8-level
amplitude
quantization
to
achieve
excellent
signal-to-noise performance and a high tolerance to
clock jitter.
The PCM1602A accepts industry-standard audio data
formats with 16- to 24-bit audio data. Sampling rates
up to 200 kHz (channels 1 and 2) or 100 kHz
(channels 3, 4, 5, and 6) are supported. A full set of
user-programmable functions is accessible through a
4-wire serial control port that supports register write
and read functions.
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
I2S is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2010, Texas Instruments Incorporated
PCM1602A
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
VDD
–0.3 V to 4 V
Power supply voltage
VCC
VCC, VDD
–0.3 V to 6.5 V
Supply voltage difference
VCC – VDD < 3 V
Ground voltage differences
±0.1 V
Digital input voltage
–0.3 V to 6.5 V
Input current (except power supply pins)
(1)
±10 mA
Operating temperature under bias
–40°C to 125°C
Storage temperature
–55°C to 150°C
Junction temperature
150°C
Package temperature (reflow, peak)
260°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range.
Digital supply voltage, VDD
Analog supply voltage, VCC
MIN
NOM
MAX
3
3.3
3.6
V
5
5.5
V
4.5
Digital input logic family
TTL
System clock
Digital input clock frequency
UNIT
8.192
36.864
Sampling clock, VOUT1, VOUT2
32
192
Sampling clock, VOUT3, VOUT4, VOUT5, VOUT6
32
96
Analog output load resistance
5
MHz
kHz
kΩ
Analog output load capacitance
50
pF
Digital output load capacitance
20
pF
85
°C
Operating free-air temperature, TA
2
–25
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ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, system clock = 384 fS (fS = 44.1 kHz), and 24-bit data, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
UNIT
24
Bits
DATA FORMAT
Standard, I2S, left-justified
Audio data interface formats
Audio data bit length
16-, 18-, 20-, 24-bit, selectable
Audio data format
fS
Sampling frequency
MSB-first, binary 2s complement
VOUT1, VOUT2
5
200
VOUT3, VOUT4, VOUT5, VOUT6
5
100
kHz
128 fS, 192 fS, 256 fS,
384 fS, 512 fS, 768 fS
System clock frequency
DIGITAL INPUT/OUTPUT
Logic family
VIH
TTL-compatible
2
Input logic level
VIL
IIH (1)
VIN = VDD
10
IIL (1)
VIN = 0 V
–10
IIH (2)
Input logic current
VIN = VDD
IIL (2)
VIN = 0 V
VOH
IOH = –4 mA
Output logic level
VOL
Vdc
0.8
65
mA
100
–10
2.4
IOL = 4 mA
Vdc
1
DYNAMIC PERFORMANCE (3) (4)
THD+N
Total harmonic distortion + noise
VOUT = 0 dB, fS = 44.1 kHz
0.002%
VOUT = 0 dB, fS = 96 kHz
0.004%
VOUT = 0 dB, fS = 192 kHz
0.005%
VOUT = –60 dB, fS = 44.1 kHz
0.7%
VOUT = –60 dB, fS = 96 kHz
0.9%
VOUT = –60 dB, fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Dynamic range
Signal-to-noise ratio
Level linearity error
99
105
103
A-weighted, fS = 192 kHz
102
99
103
A-weighted, fS = 192 kHz
102
96
dB
105
A-weighted, fS = 96 kHz
fS = 44.1 kHz
Channel separation
1%
A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 44.1 kHz
SNR
0.007%
dB
103
fS = 96 kHz
101
fS = 192 kHz
100
VOUT = –90 dB
±0.5
dB
dB
DC ACCURACY
Gain error
±1
±6
% of FSR
Gain mismatch, channel-to-channel
±1
±3
% of FSR
±30
±60
mV
Bipolar zero error
(1)
(2)
(3)
(4)
VOUT = 0.5 VCC at bipolar zero
Pins 38, 40, 41, 45–47 (SCKI, BCK, LRCK, DATA1, DATA2, DATA3)
Pins 34–37 (MDI, MC, ML, RST)
Analog performance specifications are tested using a System Two™ Cascade audio measurement system by Audio Precision™ in the
averaging mode. The load connected to the analog output is 5 kΩ or larger, via capacitive loading.
Conditions in 192-kHz operation are: system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS
in register 12.
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, system clock = 384 fS (fS = 44.1 kHz), and 24-bit data, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
Output voltage
Full scale (–0 dB)
Center voltage
Load impedance
AC load
0.62 VCC
VPP
0.5 VCC
Vdc
5
kΩ
DIGITAL FILTER PERFORMANCE
Group delay time
20/fS
De-emphasis error
±0.1
dB
Filter Characteristics 1, Sharp Rolloff
Pass band
±0.03 dB
Pass band
–3 dB
Stop band
0.454 fS
0.487 fS
0.546 fS
Pass-band ripple
±0.03
dB
Stop-band attenuation
Stop band = 0.546 fS
–50
dB
Stop-band attenuation
Stop band = 0.567 fS
–55
dB
Filter Characteristics 2, Slow Rolloff
Pass band
±0.5 dB
Pass band
–3 dB
Stop band
0.198 fS
0.39 fS
0.884 fS
Pass-band ripple
Stop-band attenuation
±0.5
Stop band = 0.884 fS
–40
dB
dB
ANALOG FILTER PERFORMANCE
Frequency response
f = 20 kHz
–0.03
f = 44 kHz
–0.2
dB
POWER-SUPPLY REQUIREMENTS (5)
VDD
3
3.3
3.6
4.5
5
5.5
fS = 44.1 kHz
11
15
fS = 96 kHz
24
fS = 192 kHz
19
fS = 44.1 kHz
27
fS = 96 kHz
28
fS = 192 kHz
28
fS = 44.1 kHz
171
fS = 96 kHz
219
fS = 192 kHz
203
Voltage range
VCC
IDD (6)
Supply current
ICC
Power dissipation
38
Vdc
mA
240
mW
TEMPERATURE RANGE
TA
Operation temperature
qJA
Thermal resistance
(5)
(6)
4
–25
85
100
°C
°C/W
Conditions in 192-kHz operation are: system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS
in register 12.
SCKO is disabled.
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FUNCTIONAL BLOCK DIAGRAM
BCK
DAC
Output Amp and
Low-Pass Filter
VOUT1
Output Amp and
VOUT2
LRCK
DATA1 (1,2)
Serial
Input
I/F
DAC
Low-Pass Filter
DATA2 (3,4)
4× / 8×
Oversampling
Digital Filter
With
Function
Controller
DATA3 (5,6)
TEST
Enhanced
Multilevel
Delta-Sigma
Modulator
DAC
Output Amp and
Low-Pass Filter
VOUT3
DAC
Output Amp and
Low-Pass Filter
VOUT4
DAC
Output Amp and
Low-Pass Filter
VOUT5
DAC
Output Amp and
Low-Pass Filter
VOUT6
RST
ML
MC
Function
Control
I/F
MDI
MDO
VCOM
System Clock
AGND1−6
VCC1−5
DGND
ZERO6/GPO6
Power Supply
ZERO5/GPO5
ZERO4/GPO4
ZERO3/GPO3
ZERO1/GPO1
ZEROA
ZERO2/GPO2
Zero Detect
Manager
VDD
System Clock
SCKO
SCKI
B0033-02
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ML
MC
MDI
MDO
NC
NC
NC
NC
VCC1
AGND1
VCC2
AGND2
PT PACKAGE
(TOP VIEW)
36
35
34
33
32
31
30
29
28
27
26
25
RST 37
24 VCC3
SCKI 38
23 AGND3
SCKO 39
22 VCC4
BCK 40
21 AGND4
LRCK 41
20 NC
TEST 42
19 AGND6
PCM1602A
VDD 43
18 VCC5
1
2
3
4
5
6
7
8
9
10
11
12
VOUT5
VOUT4
VOUT3
13 VOUT2
VOUT6
ZEROA 48
NC
14 VOUT1
NC
DATA3 47
ZERO6/GPO6
15 VCOM
ZERO5/GPO5
DATA2 46
ZERO4/GPO4
16 NC
ZERO3/GPO3
DATA1 45
ZERO2/GPO2
17 AGND5
ZERO1/GPO1
DGND 44
P0028-04
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
27
–
Analog ground
25
–
Analog ground
AGND3
23
–
Analog ground
AGND4
21
–
Analog ground
AGND5
17
–
Analog ground
AGND6
19
–
Analog ground
BCK
40
I
Shift clock input for serial audio data. Clock must be one of 32 fS, 48 fS, or 64 fS.
NAME
NO.
AGND1
AGND2
DATA1
45
I
Serial audio data input for VOUT1 and VOUT2
(1)
DATA2
46
I
Serial audio data input for VOUT3 and VOUT4
(1)
DATA3
47
I
Serial audio data input for VOUT5 and VOUT6
(1)
DGND
44
–
Digital ground
LRCK
41
I
Left and right clock input. This clock is equal to the sampling rate, fS.
35
I
Shift clock for serial control port
MDI
34
I
Serial data input for serial control port
MDO
33
O
Serial data output for serial control port
(1)
(2)
(3)
6
36
I
(1)
(2)
MC
ML
(1)
Latch enable for serial control port
(2)
(3)
(2)
Schmitt-trigger input, 5-V tolerant
Schmitt-trigger input with internal pulldown, 5-V tolerant
3-state output
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NC
7, 8, 16, 20, 29,
30, 31, 32
–
No connection
RST
37
I
System reset, active-low
SCKI
38
I
System clock input. Input frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.
SCKO
39
O
Buffered clock output. Output frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or
768 fS, or one-half of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.
TEST
42
–
Test pin. This pin should be connected to DGND.
VCC1
28
–
Analog power supply, 5-V
VCC2
26
–
Analog power supply, 5-V
VCC3
24
–
Analog power supply, 5-V
VCC4
22
–
Analog power supply, 5-V
VCC5
18
–
Analog power supply, 5-V
VCOM
15
O
Common voltage output. This pin should be bypassed with a 10-mF capacitor to AGND.
VDD
43
–
Digital power supply, 3.3-V
VOUT1
14
O
Voltage output of audio signal corresponding to Lch on DATA1. Up to 192 kHz.
VOUT2
13
O
Voltage output of audio signal corresponding to Rch on DATA1. Up to 192 kHz.
VOUT3
12
O
Voltage output of audio signal corresponding to Lch on DATA2. Up to 96 kHz.
VOUT4
11
O
Voltage output of audio signal corresponding to Rch on DATA2. Up to 96 kHz.
VOUT5
10
O
Voltage output of audio signal corresponding to Lch on DATA3. Up to 96 kHz.
VOUT6
9
O
Voltage output of audio signal corresponding to Rch on DATA3. Up to 96 kHz.
ZERO1/GPO1
1
O
Zero-data flag for VOUT1. Can also be used as GPO pin.
ZERO2/GPO2
2
O
Zero-data flag for VOUT2. Can also be used as GPO pin.
ZERO3/GPO3
3
O
Zero-data flag for VOUT3. Can also be used as GPO pin.
ZERO4/GPO4
4
O
Zero-data flag for VOUT4. Can also be used as GPO pin.
ZERO5/GPO5
5
O
Zero-data flag for VOUT5. Can also be used as GPO pin.
ZERO6/GPO6
6
O
Zero-data flag for VOUT6. Can also be used as GPO pin.
ZEROA
48
O
Zero-data flag. Logical AND of ZERO1 through ZERO6
(2)
(1)
(2)
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TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless
otherwise noted
Digital Filter (De-Emphasis Off)
FREQUENCY RESPONSE
(SHARP ROLLOFF)
PASS-BAND FREQUENCY RESPONSE
(SHARP ROLLOFF)
0.05
0
0.04
−20
Amplitude − dB
Amplitude − dB
0.03
−40
−60
−80
−100
0.02
0.01
0.00
−0.01
−0.02
−0.03
−120
−0.04
−0.05
0.0
−140
0
1
2
3
Frequency [× fS]
4
0.1
0.2
0.3
0.4
Frequency [× fS]
G001
G002
Figure 1.
Figure 2.
FREQUENCY RESPONSE
(SLOW ROLLOFF)
TRANSITION CHARACTERISTICS
(SLOW ROLLOFF)
0
0.5
5
4
−20
Amplitude − dB
Amplitude − dB
3
−40
−60
−80
−100
2
1
0
−1
−2
−3
−120
−4
−140
0
1
2
Frequency [× fS]
3
4
−5
0.0
G003
Figure 3.
8
0.1
0.2
0.3
Frequency [× fS]
0.4
0.5
G004
Figure 4.
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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless
otherwise noted
Digital Filter (De-Emphasis Curves)
DE-EMPHASIS ERROR
(fS = 32 kHz)
0
0.5
−1
0.4
−2
0.3
−3
0.2
Error − dB
Level − dB
DE-EMPHASIS
(fS = 32 kHz)
−4
−5
−6
0.0
−0.1
−7
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
f − Frequency − kHz
0
2
4
6
8
10
Figure 6.
DE-EMPHASIS
(fS = 44.1 kHz)
DE-EMPHASIS ERROR
(fS = 44.1 kHz)
0
0.5
−1
0.4
−2
0.3
−3
0.2
−5
−6
0.1
0.0
−0.1
−7
−0.2
−8
−0.3
−9
−0.4
−10
14
G006
Figure 5.
−4
12
f − Frequency − kHz
G005
Error − dB
Level − dB
0.1
−0.5
0
2
4
6
8
10
12
14
f − Frequency − kHz
16
18
20
0
2
G007
Figure 7.
4
6
8
10
12
14
16
18
20
f − Frequency − kHz
G008
Figure 8.
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TYPICAL PERFORMANCE CURVES (continued) (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless
otherwise noted
DE-EMPHASIS ERROR
(fS = 48 kHz)
0
0.5
−1
0.4
−2
0.3
−3
0.2
Error − dB
Level − dB
DE-EMPHASIS
(fS = 48 kHz)
−4
−5
−6
0.1
0.0
−0.1
−7
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
16
18
20
22
f − Frequency − kHz
0
2
4
6
8
10
12
14
16
18
f − Frequency − kHz
G009
Figure 9.
20
22
G010
Figure 10.
TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz
operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS (set by OVER
bit in register 12).
Supply-Voltage Characteristics
DYNAMIC RANGE
vs
VCC (VDD = 3.3 V)
110
10
108
−60 dB/192 kHz, 128 fS −60 dB/96 kHz, 384 fS
Dynamic Range − dB
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
VCC (VDD = 3.3 V)
1
−60 dB/44.1 kHz, 384 fS
0.1
0 dB/192 kHz, 128 fS
0.01
0 dB/96 kHz, 384 fS
0 dB/44.1 kHz, 384 fS
4.5
5.0
VCC − Supply Voltage − V
102
192 kHz, 128 fS
100
96
4.0
5.5
6.0
4.5
5.0
VCC − Supply Voltage − V
5.5
6.0
G012
G011
Figure 11.
10
96 kHz, 384 fS
104
98
0.001
0.0001
4.0
44.1 kHz, 384 fS
106
Figure 12.
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TYPICAL PERFORMANCE CURVES (continued) (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz
operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS (set by OVER
bit in register 12).
CHANNEL SEPARATION
vs
VCC (VDD = 3.3 V)
110
110
108
108
Channel Separation − dB
SNR − Signal-to-Noise Ratio − dB
SIGNAL-TO-NOISE RATIO
vs
VCC (VDD = 3.3 V)
44.1 kHz, 384 fS
106
96 kHz, 384 fS
104
102
192 kHz, 128 fS
100
98
96
4.0
106
44.1 kHz, 384 fS
104
96 kHz, 384 fS
102
100
192 kHz, 128 fS
98
4.5
5.0
5.5
VCC − Supply Voltage − V
6.0
96
4.0
G013
Figure 13.
4.5
5.0
5.5
6.0
VCC − Supply Voltage − V
G014
Figure 14.
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TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz
operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS (set by OVER
bit in register 12).
Temperature Characteristics
110
10
−60 dB/96 kHz, 384 fS
108
−60 dB/192 kHz, 128 fS
1
−60 dB/44.1 kHz, 384 fS
0.1
0 dB/96 kHz, 384 fS
0 dB/192 kHz, 128 fS
0.01
0 dB/44.1 kHz, 384 fS
0.0001
−50
106
104
−25
0
25
50
192 kHz, 128 fS
100
96
−50
75
−25
100
0
25
50
SIGNAL-TO-NOISE RATIO
vs
TEMPERATURE (TA)
CHANNEL SEPARATION
vs
TEMPERATURE (TA)
108
108
104
96 kHz, 384 fS
Channel Separation − dB
110
44.1 kHz, 384 fS
102
192 kHz, 128 fS
100
100
G016
G015
Figure 16.
106
75
TA − Free-Air Temperature − °C
Figure 15.
106
104
44.1 kHz, 384 fS
102
96 kHz, 384 fS
100
192 kHz, 128 fS
98
98
−25
0
25
50
TA − Free-Air Temperature − °C
75
100
96
−50
G017
Figure 17.
12
96 kHz, 384 fS
102
110
96
−50
44.1 kHz, 384 fS
98
0.001
TA − Free-Air Temperature − °C
SNR − Signal-to-Noise Ratio − dB
DYNAMIC RANGE
vs
TEMPERATURE (TA)
Dynamic Range − dB
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
TEMPERATURE (TA)
−25
0
25
50
TA − Free-Air Temperature − °C
75
100
G018
Figure 18.
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SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1602A requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI input (pin 38). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. The PLL170x multiclock generator from Texas Instruments is
an excellent choice for providing the PCM1602A system clock.
The 192-kHz sampling frequency operation is available on DATA1 for VOUT1 and VOUT2. It is recommended that
VOUT3, VOUT4, VOUT5, and VOUT6 be forced to the bipolar zero level using the DAC3, DAC4, DAC5, and DAC6
bits of register 8 when operating at 192 kHz.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
128 fS
256 fS
384 fS
512 fS
768 fS
8
(1)
(1)
2.048
3.072
4.096
6.144
16
(1)
(1)
4.096
6.144
8.192
12.288
32
(1)
(1)
8.192
12.288
16.384
24.576
44.1
(1)
(1)
11.2896
16.9344
22.5792
33.8688
48
(1)
(1)
12.288
18.432
24.576
36.864
96
(1)
(1)
24.576
36.864
49.152
192
(1)
192 fS
24.576
36.864
(1)
(1)
(1)
(1)
(1)
This system clock is not supported for the given sampling frequency.
tw(SCKH)
H
2V
System Clock
0.8 V
L
System Clock
Pulse Cycle
Time(1)
tw(SCKL)
T0005A08
SYMBOL
PARAMETER
MIN
MAX
UNIT
tw(SCKH)
System clock pulse duration, HIGH
7
ns
tw(SCKL)
System clock pulse duration, LOW
7
ns
(1)
1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, and 1/768 fS.
Figure 19. System Clock Timing
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at the SCKO output (pin 39). SCKO can operate at
either full (fSCKI) or half (fSCKI/2) rate. The SCKO output frequency can be programmed using the CLKD bit of
register 9. The SCKO output pin can also be enabled or disabled using the CLKE bit of register 9. If the SCKO
output is not required, it is recommended to disable it using the CLKE bit. The default is SCKO enabled.
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POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1602A includes a power-on-reset function, as shown in Figure 20. With the system clock active, and
VDD > 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires
1024 system clocks from the time VDD > 2 V. After the initialization period, the PCM1602A is set to its reset
default state, as described in the Mode Control Registers section of this data sheet.
The PCM1602A also includes an external reset capability using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1602A to initialize to its reset default state. For normal
operation, RST should be set to a logic-1.
The external reset operation and timing is shown in Figure 21. The RST pin is set to logic-0 for a minimum of
20 ns. After the initialization sequence is completed, the PCM1602A is set to its reset default state, as described
in the Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level (or VCC/2).
After the reset period, the internal registers are initialized in the next 1/fS period and, if SCKI, BCK, and LRCK
are provided continuously, the PCM1602A provides proper analog output with the group delay time given in the
Electrical Characteristics section of this data sheet.
The external reset is especially useful in applications where there is a delay between PCM1602A power-up and
system-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock has
been activated.
VDD
2.4 V
2V
1.6 V
0V
Reset
Reset Removal
Internal Reset
Don’t Care
1024 System Clocks
System Clock
T0014-08
Figure 20. Power-On-Reset Timing
RST
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
T0015-06
Figure 21. External Reset Timing
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AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1602A consists of a 5-wire synchronous serial port. It includes LRCK (pin
41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), and DATA3 (pin 47). BCK is the serial audio bit clock, and is
used to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift register.
Serial data is clocked into the PCM1602A on the rising edge of BCK. LRCK is the serial audio left/right clock. It is
used to latch serial data into the serial audio interface internal registers.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input, SCKI. LRCK is operated at the sampling frequency (fS). BCK can be
operated at 32, 48, or 64 times the sampling frequency (I2S format does not support BCK = 32 fS).
Internal operation of the PCM1602A is synchronized with LRCK. Accordingly, internal operation of the device is
suspended when the sampling rate clock (LRCK) is changed, or when SCKI and/or BCK is interrupted at least for
a 3-bit clock cycle. If SCKI, BCK, and LRCK are provided continuously after this suspended state, the internal
operation is resynchronized automatically within a period of less than 3/fS. During this resynchronization period
and for a 3/fS time thereafter, the analog outputs are forced to the bipolar zero level, VCC/2. External resetting is
not required.
AUDIO DATA FORMATS AND TIMING
The PCM1602A supports industry-standard audio data formats, including standard, I2S, and left-justified (see
Figure 22). Data formats are selected using the format bits, FMT[2:0], in register 9. The default data format is
24-bit standard. All formats require binary 2s complement, MSB-first audio data. See Figure 23 for a detailed
timing diagram of the serial audio interface.
DATA1, DATA2, and DATA3 each carry two audio channels, designated as the left and right channels. The
left-channel data always precedes the right-channel data in the serial data stream for all data formats. Table 2
shows the mapping of the digital input data to the analog output pins.
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(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
16-Bit Right-Justified, BCK = 32 fS
DATA
14 15 16
1
2
3
14 15 16
1
3
14 15 16
MSB
LSB
MSB
2
LSB
16-Bit Right-Justified, BCK = 48 fS or 64 fS
DATA
14 15 16
1
2
3
MSB
14 15 16
1
2
3
MSB
LSB
14 15 16
LSB
18-Bit Right-Justified
DATA
16 17 18
1
2
3
16 17 18
MSB
1
LSB
2
3
16 17 18
MSB
LSB
20-Bit Right-Justified
DATA
18 19 20
1
2
3
18 19 20
MSB
1
LSB
2
3
18 19 20
MSB
LSB
24-Bit Right-Justified
DATA
22 23 24
1
2
3
22 23 24
MSB
1
2
LSB
3
22 23 24
MSB
LSB
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48 fS, or 64 fS)
DATA
1
2
3
N–2 N–1
MSB
LSB
N
1
2
3
N–2 N–1
MSB
LSB
N
1
2
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48 fS, or 64 fS)
DATA
1
2
3
N–2 N–1
MSB
LSB
N
1
2
3
N–2 N–1
MSB
LSB
N
1
2
T0009-05
Figure 22. Audio Data Input Formats
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1.4 V
LRCK
t(BCH)
t(LB)
t(BCL)
1.4 V
BCK
t(BCY)
t(BL)
DATA1, DATA2,
DATA3
1.4 V
t(DS)
t(DH)
T0010-06
SYMBOL
PARAMETER
MIN
MAX
UNITS
t(BCY)
BCK pulse cycle time
t(BCH)
BCK high-level time
35
ns
t(BCL)
BCK low-level time
35
ns
t(BL)
BCK rising edge to LRCK edge
10
ns
t(LB)
LRCK falling edge to BCK rising edge
10
ns
t(DS)
DATA setup time
10
ns
t(DH)
DATA hold time
10
ns
(1)
1/(64 fS )
fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.)
Figure 23. Audio Interface Timing
Table 2. Audio Input Data to Analog Output Mapping
(1)
(2)
DATA INPUT
CHANNEL
DATA1
Left
ANALOG OUTPUT
VOUT1
(1)
DATA1
Right
VOUT2
(1)
DATA2
Left
VOUT3
(2)
DATA2
Right
VOUT4
(2)
DATA3
Left
VOUT5
(2)
DATA3
Right
VOUT6
(2)
Up to 192 kHz
Up to 96 kHz
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SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio
interface. The serial control interface is used to program and read the on-chip mode registers. The control
interface includes MDO (pin 33), MDI (pin 34), MC (pin 35), and ML (pin 36). MDO is the serial data output, used
to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers;
MC is the serial bit clock, used to shift data in and out of the control port; and ML is the control port latch clock.
REGISTER WRITE OPERATION
All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data word
format. The most significant bit is the read/write R/W) bit. When set to 0, this bit indicates a write operation.
Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eight
bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].
Figure 25 shows the functional timing diagram for writing to the serial control port. ML is held at a logic-1 state
until a register is to be written. To start the register write cycle, ML is set to logic-0. Sixteen clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MDI. After the sixteenth clock cycle has
completed, ML is set to logic-1 to latch the data into the indexed mode control register.
MSB
R/W
LSB
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
D7
D6
D5
Register Index (or Address)
D4
D3
D2
D1
D0
Register Data
Read/Write Operation
0 = Write Operation
1 = Read Operation (Register Index is Ignored)
R0001-02
Figure 24. Control Data Word Format for MDI
ML
MC
MDI
X
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
R/W IDX6
T0048-02
Figure 25. Write Operation Timing
SINGLE REGISTER READ OPERATION
Read operations use the 16-bit control word format shown in Figure 24. For read operations, the R/W bit is set
to 1. Read operations ignore the index bits, IDX[6:0], of the control data word. Instead, the REG[6:0] bits in
control register 11 are used to set the index of the register that is to be read during the read operation. Bits
IDX[6:0] should be set to 00h for read operations.
The details of the read operation are shown in Figure 26. First, control register 11 must be written with the index
of the register to be read back. Additionally, the INC bit must be set to logic-0 in order to disable the
auto-increment read function. The read cycle is then initiated by setting ML to logic-0 and setting the R/W bit of
the control data word to logic-1, indicating a read operation. MDO remains in a high-impedance state until the
last eight bits of the 16-bit read cycle, which correspond to the eight data bits of the register indexed by the
REG[6:0] bits of control register 11. The read cycle is completed when ML is set to 1, immediately after the MC
clock cycle for the least-significant bit of the indexed control register has completed.
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INC = 1 (Auto-Increment Read)
ML
MC
MDI
1
0
0
0
0
0
0
0
High Impedance
MDO
X
X
X
X
X
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
INDEX “N”
ML
MC
MDI
MDO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
INDEX “N + 1”
High Impedance
INDEX “Y”
INC = 0 (Single-Register Read)
ML
MC
MDI
MDO
1
0
0
0
0
0
High Impedance
0
0
X
X
X
X
X
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
INDEX “N”
T0075-01
NOTES: X = Don’t care
w
Y = Last register to be read
w
In single-register read (INC = 0), the index which indicates the register to be read in read operation can be set by
REG[6:0] in register 11. For example, setting REG[6:0] = 000 1001b means reading from register 9.
In auto-increment read (INC = 1), the index REG[6:0] indicates the first register to be read. For example, setting
REG[6:0] = 000 1001b means reading registers from 9 to Y. Y is determined by the low-to-high transition of ML in
serial mode control.
Figure 26. Read Operation Timing
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AUTO-INCREMENT READ OPERATION
The auto-increment read function allows for multiple registers to be read sequentially. The auto-increment read
function is enabled by setting the INC bit of control register 11 to 1. The sequence always starts with the register
indexed by the REG[6:0] bits in control register 11, and ends by the ML setting to 1 after MC clock cycle for the
least-significant bit of last register.
Figure 26 shows the timing of the auto-increment read operation. The operation begins by writing control register
11, setting INC to 1, and setting REG[6:0] to the first register to be read in the sequence. The actual read
operation starts on the next HIGH-to-LOW transition of the ML pin.
The read cycle starts by setting the R/W bit of the control word to 1, and setting all of the IDX[6:0] bits to 0. All
subsequent bits input on MDI are ignored while ML is set to 0. For the first eight clocks of the read cycle, MDO is
set to the high-impedance state. This is followed by a sequence of 8-bit words, each corresponding to the data
contained in control registers N through Y, where N is defined by the REG[6:0] bits in control register 11, and
where Y is the last register to be read. The read cycle is completed when ML is set to 1, immediately after the
MC clock cycle for the least-significant bit of the last register has completed. If ML is held low and the MC clock
continues beyond the last physical register (register 12), the read operation returns to control register 1 and
subsequent control registers, continuing until ML is set to 1.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 27 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup and
hold times, as well as t(MLS) and t(MLH), which define minimum delays between the edges of the ML and MC
clocks. These timing parameters are critical for proper control-port operation.
t(MHH)
ML
1.4 V
t(MLS)
t(MCL)
t(MCH)
t(MLH)
MC
1.4 V
t(MCY)
LSB
MDI
1.4 V
t(MDS)
t(MOS)
t(MDH)
LSB
MDO
50% of VDD
T0013-05
SYMBOL
PARAMETER
MIN
MAX
UNITS
t(MCY)
MC pulse cycle time
100
ns
t(MCL)
MC low-level time
50
ns
t(MCH)
MC high-level time
50
ns
t(MHH)
ML high-level time
300
ns
t(MLS)
ML falling edge to MC rising edge
20
ns
t(MLH)
ML hold time
20
ns
t(MDH)
MDI hold time
15
ns
t(MDS)
MDL setup time
20
t(MOS)
MC falling edge to MDO stable
(1)
ns
30
ns
MC rising edge for LSB to ML rising edge.
Figure 27. Control Interface Timing
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MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1602A includes a number of user-programmable functions that are accessed via control registers. The
registers are programmed using the serial control interface that is previously discussed in this data sheet.
Table 3 lists the available mode control functions, along with their reset default conditions and associated register
index.
Table 3. User-Programmable Mode Controls
FUNCTION
RESET DEFAULT
CONTROL
REGISTER
BIT(S) LABEL
1 through 6
AT1[7:0], AT2[7:0],
AT3[7:0], AT4[7:0],
AT51[7:0], AT6[7:0]
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps
0 dB, no attenuation
Soft mute control
Mute disabled
7
MUT[6:1]
DAC1–DAC6 operation control
DAC1–DAC6 enabled
8
DAC[6:1]
Audio data format control
24-bit standard format
9
FMT[2:0]
Digital filter rolloff control
Sharp rolloff
9
FLT
SCKO frequency selection
Full rate (= fSCKI)
9
CLKD
SCKO output enable
SCKO enabled
9
CLKE
De-emphasis all-channel function control
De-emphasis, all channels
disabled
10
DMC
De-emphasis all-channel sample rate selection
44.1 kHz
10
DMF[1:0]
Output phase select
Normal phase
10
DREV
Zero-flag polarity select
High
10
ZREV
Read-register index control
REG[6:0] = 01h
11
REG[6:0]
Read auto-increment control
Auto-increment disabled
11
INC
General-purpose output enable
Zero-flag enabled
12
GPOE
General-purpose output bits (GPO1–GPO6)
Disabled
12
GPO[6:1]
Oversampling rate control
64×
12
OVER
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Reserved Registers
Register 0 is reserved for factory use. To ensure proper operation, the user should not write to or read from
these registers.
Register Map
The mode control register map is shown in Table 4. Each register includes an R/W bit that determines whether a
register read R/W = 1) or write R/W = 0) operation is performed. Each register also includes an index (or
address) indicated by the IDX[6:0] bits.
Table 4. Mode Control Register Map
IDX
(B14–
B8)
REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
01h
1
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
02h
2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
03h
3
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
04h
4
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
05h
5
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT57
AT56
AT55
AT54
AT53
AT52
AT51
AT50
06h
6
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT67
AT66
AT65
AT64
AT63
AT62
AT61
AT60
RSV (1
RSV (1
)
)
MUT6
MUT5
MUT4
MUT3
MUT2
MUT1
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
)
FLT
CLKD
CLKE
FMT2
FMT1
FMT0
ZREV
DREV
DMF1
DMF0
DMC
DMC
DMC
07h
08h
7
8
R/W
R/W
IDX6
IDX6
IDX5
IDX5
IDX4
IDX4
IDX3
IDX3
IDX2
IDX2
IDX1
IDX1
IDX0
IDX0
RSV
(1
)
RSV
RSV
(1
)
(1
RSV
(1
09h
9
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
0Ah
10
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
0Bh
11
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6
REG5
REG4
REG3
REG2
REG1
REG0
0Ch
12
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
OVER
GPOE
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1
(1)
22
)
RSV (1
)
Reserved for test operation. It should be set to 0 during normal operation.
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Register Definitions
REGISTER 1
B15
R/W
B14 B13 B12 B11 B10
B9
B8
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
B7
AT17
B6
AT16
B5
AT15
B4
AT14
B3
AT13
B2
AT12
B1
AT11
B0
AT10
REGISTER 2
R/W
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
REGISTER 3
R/W
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
REGISTER 4
R/W
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
REGISTER 5
R/W
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
AT57
AT56
AT55
AT54
AT53
AT52
AT51
AT50
REGISTER 6
R/W
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
AT67
AT66
AT65
AT64
AT63
AT62
AT61
AT60
R/W – Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATx[7:0] – Digital Attenuation Level Setting
where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are read/write.
Default value: 1111 1111b
Each DAC output, VOUT1 through VOUT6, includes a digital attenuator function. The attenuation level can be set
from 0 dB to –63 dB in 0.5-dB steps. Changes in attenuation levels are made by incrementing or decrementing
by one step (0.5 dB) for every 8/fS time interval until the programmed attenuator setting is reached. Alternatively,
the attenuation level can be set to infinite attenuation, or mute.
The attenuation level is calculated using the following formula:
Attenuation level (dB) = 0.5 (ATx[7:0]DEC – 255)
where ATx[7:0]DEC = 0 through 255.
For ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuation levels for various settings.
ATx[7:0]
DECIMAL VALUE
ATTENUATOR LEVEL SETTING
1111 1111b
255
0 dB, no attenuation (default)
1111 1110b
254
–0.5 dB
1111 1101b
253
–1 dB
:
:
:
1000 0011b
131
–62 dB
1000 0010b
130
–62.5 dB
1000 0001b
129
–63 dB
1000 0000b
128
Mute
:
:
:
0000 0000b
0
Mute
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REGISTER 7
B15
R/W
www.ti.com
B14 B13 B12 B11 B10
B9
B8
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
B7
RSV
B6
RSV
B5
MUT6
B4
MUT5
B3
MUT4
B2
MUT3
B1
MUT2
B0
MUT1
R/W – Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
MUTx – Soft Mute Control
Where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are read/write.
Default value: 0
MUTx = 0
Mute disabled (default)
MUTx = 1
Mute enabled
The mute bits, MUT1 through MUT6, are used to enable or disable the soft mute function for the corresponding
DAC outputs, VOUT1 through VOUT6. The soft mute function is incorporated into the digital attenuators. When
mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting
MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite
attenuation setting, one attenuator step (0.5 dB) at a time. This provides a quiet, pop-free muting of the DAC
output. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to the
previously programmed attenuation level.
REGISTER 8
B15
R/W
B14 B13 B12 B11 B10
B9
B8
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
B7
RSV
B6
RSV
B5
DAC6
B4
DAC5
B3
DAC4
B2
DAC3
B1
DAC2
B0
DAC1
R/W – Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
DACx – DAC Operation Control
Where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are read/write.
Default value: 0
DACx = 0
DAC operation enabled (default)
DACx = 1
DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs, VOUT1 through VOUT6. When
DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input
is switched to the dc common-mode voltage (VCOM), equal to VCC/2.
24
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REGISTER 9
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
B15
R/W
B14 B13 B12 B11 B10
B9
B8
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
B7
RSV
B6
RSV
B5
FLT
B4
CLKD
B3
CLKE
B2
FMT2
B1
FMT1
B0
FMT0
R/W – Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
FLT – Digital Filter Rolloff Control
This bit is read/write.
Default value: 0
FLT = 0
Sharp rolloff (default)
FLT = 1
Slow rolloff
The FLT bit allows users to select the digital filter rolloff that is best suited to their application. Two filter rolloff
selections are available: sharp or slow. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.
CLKD – SCKO Frequency Selection
This bit is read/write.
Default value: 0
CLKD = 0
Full-rate, fSCKO = fSCKI (default)
CLKD = 1
Half-rate, fSCKO = fSCKI/2
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.
CLKE – SCKO Output Enable
This bit is read/write.
Default value: 0
CLKE = 0
SCKO enabled (default)
CLKE = 1
SCKO disabled
The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it outputs
either a full- or half-rate clock, based on the setting of the CLKD bit. When SCKO is disabled, it is set to a LOW
level.
FMT[2:0] – Audio Interface Data Format
These bits are read/write.
Default value: 000b
FMT[2:0]
Audio Data Format Selection
000
24-bit standard format, right-justified data (default)
001
20-bit standard format, right-justified data
010
18-bit standard format, right-justified data
011
16-bit standard format, right-justified data
100
I2S format, 16- to 24-bit
101
Left-justified format, 16- to 24-bit
110
Reserved
111
Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
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REGISTER 10
B15
R/W
www.ti.com
B14 B13 B12 B11 B10
B9
B8
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
B7
RSV
B6
ZREV
B5
DREV
B4
DMF1
B3
DMF0
B2
DMC
B1
DMC
B0
DMC
R/W – Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ZREV – Zero-Flag Polarity Select
Default value: 0
ZREV = 0
Zero-flag pins HIGH at a zero detect (default)
ZREV = 1
Zero-flag pins LOW at a zero detect
The ZREV bit allows the user to select the polarity of zero-flag pins.
DREV – Output Phase Select
Default value: 0
DREV = 0
Normal output (default)
DREV = 1
Inverted output
The DREV bit allows the user to select the phase of the analog output signal.
DMF[1:0] – Sampling Frequency Selection for the De-Emphasis Function
These bits are read/write.
Default value: 00b
DMF[1:0]
De-Emphasis Sample Rate Selection
00
44.1 kHz (default)
01
48 kHz
10
32 kHz
11
Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is
enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet. The
preceding table shows the available sampling frequencies.
DMC – Digital De-Emphasis, All-Channel Function Control
This bit is read/write.
Default value: 0
DMC = 0
De-emphasis disabled for all channels (default)
DMC = 1
De-emphasis enabled for all channels
The DMC bits are used to enable or disable the de-emphasis function for all channels. The three DMC bits are
ORed together. Setting any one DMC bit, any combination of two DMC bits, or all three DMC bits to 1 enables
digital de-emphasis for all channels. Setting all three DMC bits to 0 disables digital de-emphasis for all channels.
26
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REGISTER 11
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
B15
R/W
B14 B13 B12 B11 B10
B9
B8
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
B7
INC
B6
REG6
B5
REG5
B4
REG4
B3
REG3
B2
REG2
B1
REG1
B0
REG0
R/W – Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
INC – Auto-Increment Read Control
This bit is read/write.
Default value: 0
INC = 0
Auto-increment read disabled (default)
INC = 1
Auto-increment read enabled
The INC bit is used to enable or disable the auto-increment read feature of the serial control interface. See the
Serial Control Interface section of this data sheet for details regarding auto-increment read operation.
REG[6:0] – Read Register Index
These bits are read/write.
Default value: 01h
The REG[6:0] bits are used to set the index of the register to be read when performing the single-register read
operation. In the case of an auto-increment read operation, the REG[6:0] bits indicate the index of the last
register to be read in the auto-increment read sequence. For example, if registers 1 through 6 are to be read
during an auto-increment read operation, the REG[6:0] bits would be set to 06h. See the Serial Control Interface
section of this data sheet for details regarding the single-register and auto-increment read operations.
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REGISTER 12
B15
R/W
www.ti.com
B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6
B4
B3
B2
GPO5 GPO4 GPO3
B1
B0
GPO2 GPO1
R/W – Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
OVER – Oversampling Rate Control
These bits are read/write.
Default value: 0
x
System clock rate = 256 fS, 384 fS, 512 fS, or 768 fS:
OVER = 0
64× oversampling (default)
OVER = 1
128× oversampling
x
System clock rate = 128 fS or 192 fS:
OVER = 0
32× oversampling (default)
OVER = 1
64× oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting is
recommended when the oversampling rate is 192 kHz (system clock rate is 128 fS or 192 fS).
GPOE – General-Purpose Output Enable
This bit is read/write.
Default value: 0
GPOE = 0
General-purpose outputs disabled (default)
Pins default to zero-flag function (ZERO1 through ZERO6).
GPOE = 1
General-purpose outputs enabled
Data written to GPO1 through GPO6 appears at the corresponding pins.
GPOx – General-Purpose Logic Output
Where: x = 1 through 6, corresponding pins GPO1 through GPO6.
These bits are read/write.
Default value: 0
GPOx = 0
Set GPOx to 0 (default)
GPOx = 1
Set GPOx to 1
The general-purpose output pins, GPO1 through GPO6, are enabled by setting GPOE = 1. These pins are used
as general-purpose outputs for controlling user-defined logic functions. When general-purpose outputs are
disabled (GPOE = 0), they default to the zero-flag function, ZERO1 through ZERO6.
28
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ANALOG OUTPUTS
The PCM1602A includes six independent output channels, VOUT1 through VOUT6. These are unbalanced outputs,
each capable of driving 3.1 VPP typical into a 5-kΩ ac load with VCC = 5 V. The internal output amplifiers for
VOUT1 through VOUT6 are dc biased to the common-mode (or bipolar zero) voltage, equal to VCC/2.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise-shaping characteristics of the PCM1602A delta-sigma DACs. The
frequency response of this filter is shown in Figure 28. By itself, this filter is not enough to attenuate the
out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide
sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application
Information section of this data sheet.
20
0
Level − dB
−20
−40
−60
−80
−100
1
10
100
1k
10k
100k
f − Frequency − Hz
1M
10M
G019
Figure 28. Output-Filter Frequency Response
VCOM OUTPUT
One unbuffered, common-mode voltage output pin, VCOM (pin 15), is brought out for decoupling purposes. This
pin is nominally biased to a dc voltage level equal to VCC/2. If this pin is to be used to bias external circuitry, a
voltage follower is required for buffering purposes. Figure 29 shows an example of using the VCOM pin for
external biasing applications.
PCM1602A
4
VCOM
15
3
+
–
OPA337
1
VBIAS +
VCC
2
+
10 µF
S0054-05
Figure 29. Biasing External Circuits Using the VCOM Pin
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ZERO FLAG
Zero-Detect Condition
Zero detection for each output channel is independent from the others. If the data for a given channel remains at
a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.
Zero Output Flags
Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are set
to a logic-1 state. Each channel, ZERO1 through ZERO6 (pins 1 through 6), has zero-flag pins. In addition, all six
zero flags are logically ANDed together, and the result is provided at the ZEROA pin (pin 48), which is set to a
logic-1 state when all channels indicate a zero-detect condition. The zero-flag pins can be used to operate
external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally
controlled function.
The active polarity of the zero-flag output can be inverted by setting to 1 the ZREV bit of control register 10. The
reset default is active-high output, or ZREV = 0.
30
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APPLICATION INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram with the necessary power-supply bypassing and decoupling components is shown in
Figure 30. Texas Instruments recommends using the component values shown in Figure 30 for all designs.
ML
PLL170x
Microcontroller
MC
SCKO3
MD
5-V Power Supply
10 µF
RST
35
34
33
32
31
30
29
28
27
26
25
MC
MDO
NC
NC
NC
NC
VCC1
AGND1
VCC2
AGND2
ML
36
MDI
Regulator
VCC3 24
37 RST
38 SCKI
AGND3 23
39 SCKO
BCK
LRCK
VCC4 22
40 BCK
AGND4 21
41 LRCK
NC 20
42 TEST
10 µF
AGND6 19
PCM1602A
43 VDD
VCC5 18
44 DGND
AGND5 17
DATA1
45 DATA1
NC 16
DATA2
46 DATA2
DATA3
47 DATA3
ZERO6/GPO6
NC
NC
VOUT6
3
4
5
6
7
8
9
VOUT3
ZERO5/GPO5
2
VOUT5
ZERO4/GPO4
1
VOUT4
ZERO3/GPO3
ZEROA
ZERO2/GPO2
48
ZERO1/GPO1
ZEROA
VCOM
10
11
12
10 µF
15
VOUT1 14
LPF
VOUT1
VOUT2 13
LPF
VOUT2
LPF
VOUT3
ZERO1−6
LPF
VOUT4
LPF
VOUT5
LPF
VOUT6
S0090-04
Figure 30. Basic Connection Diagram
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PCM1602A
S0091-04
CTR
RS
LS
VOUT5
VCC1
VOUT6
10 µF
10 µF
10 µF
9
AGND1
11
VCC2
10
VOUT3
VOUT4
12
VOUT2
13
15
14
VOUT1
NC
VCOM
16
17
VCC5
AGND5
18
19
AGND6
20
NC
21
AGND4
22
AGND2
NC
PCM1602A
8
NC
NC
7
NC
ZERO6/GPO6
6
NC
ZERO5/GPO5
MDO
ZERO4/GPO4
MDI
ZERO2/GPO3
MC
ZERO3/GPO2
ML
ZERO1/GPO1
1
ZEROA
DATA3
Zero Flag or
General-Purpose
Outputs
for Mute Circuits,
Microcontroller, or
DSP/Decoder
47
RS
48
46
RS
DATA2
DATA1
45
DGND
RS
VDD
44
C11 +
10 µF
Audio DSP
or
Decoder
27-MHz
Master Clock
XT1
SCKO3(2)
PLL170x
µC/µP(1)
Buffer
RS(3)
3.3 V
for VDD
C10
0.1 µF
43
TEST
LRCK
42
41
RS
BCK
40
39
RS
RST
38
37
SCKO
2
3
4
5
NC
SCKI
25
26
27
28
29
30
31
32
33
34
35
VCC4
AGND3
VCC3
24
23
+
36
10 µF
Output
Low-Pass
Filters(4)
LF
10 µF
10 µF
10 µF
5-V Analog
REG1117
3.3 V
+
+
10 µF
+
0.1 µF
+
3.3 V for VDD
+
ANALOG SECTION
+
+
DIGITAL SECTION
SUB
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RF
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
(1)
Serial control and reset functions can be provided by DSP/decoder GPIO pins.
(2)
Actual clock output used is determined by the application.
(3)
RS = 22 Ω to 100 Ω.
(4)
See the Application Information section of this datasheet for more information.
Figure 31. Typical Application Diagram
32
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A typical application diagram is shown in Figure 31. The REG1117-3.3 from Texas Instruments is used to
generate 3.3 V for VDD from the 5-V analog power supply. The PLL170x from Texas Instruments is used to
generate the system clock input at SCKI, as well as generating the clock for the audio signal processor.
Series resistors (22-Ω to 100-Ω) are recommended for SCKI, LRCK, BCK, DATA1, DATA2, and DATA3. The
series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which removes
high-frequency noise from the digital signal, thus reducing high-frequency emission.
POWER SUPPLIES AND GROUNDING
The PCM1602A requires a 5-V analog supply and a 3.3-V digital supply. The 5-V supply is used to power the
DAC analog and output filter circuitry, whereas the 3.3-V supply is used to power the digital filter and serial
interface circuitry. For best performance, the 3.3-V supply should be derived from the 5-V supply using a linear
regulator (see Figure 31).
Two capacitors are required for supply bypassing (see Figure 30). These capacitors should be located as close
as possible to the PCM1602A package. The 10-mF capacitors should be tantalum or aluminum electrolytic,
whereas the 0.1-mF capacitors are ceramic (X7R type is recommended for surface-mount applications).
DAC OUTPUT FILTER CIRCUITS
Delta-sigma DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at
the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band
noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a
combination of on-chip and external low-pass filtering.
Figure 32 and Figure 33 show the recommended external low-pass active filter circuits for dual- and
single-supply applications. These circuits are second-order Butterworth filters using the multiple feedback (MFB)
circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature.
For more information regarding MFB active filter design, see the FilterPro™ MFB and Sallen-Key Low-Pass Filter
Design Program application report (SBFA001), available from the TI Web site (www.ti.com).
Because the overall system performance is defined by the quality of the DACs and their associated analog
output circuitry, high-quality audio operational amplifiers are recommended for the active filters. The OPA2134
and OPA2353 dual operational amplifiers from Texas Instruments are shown in Figure 32 and Figure 33, and are
recommended for use with the PCM1602A.
R2
R1
VIN
C2
AV + *
C1
R3
2
3
–
OPA2134
1
R4
VOUT
+
R2
R1
S0053-02
Figure 32. Dual-Supply Filter Circuit
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AV + *
C1
R2
R1
R2
R1
R3
2
VIN
–
1
OPA2134
3
C2
PCM1602A
+
VCOM
+
VOUT
+
To Additional
Low-Pass
Filter Circuits
OPA337
C3
10 µF
R4
−
S0056-05
Figure 33. Single-Supply Filter Circuit
PCB LAYOUT GUIDELINES
A typical PCB floor plan for the PCM1602A is shown in Figure 34. A ground plane is recommended, with the
analog and digital sections being isolated from one another using a split or cut in the circuit board. The
PCM1602A should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct
connections to the digital audio interface and control signals originating from the digital section of the board.
Digital Power
+VD
DGND
Analog Power
AGND +5VA
+VS
−VS
REG
VCC
Digital Logic
and
Audio
Processor
VDD
Output
Circuits
DGND
Digital
Ground
PCM1602A
AGND
Digital Section
Analog Section
Return Path for Digital Signals
Analog
Ground
B0031-06
Figure 34. Recommended PCB Layout
34
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Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the DACs. In cases where a common 5-V supply must be used for the analog and
digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V
supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 35 shows the
recommended approach for single-supply applications.
Power Supplies
RF Choke or Ferrite Bead
+5V AGND
+VS
−VS
REG
VCC
VDD
Digital Logic
and
Audio
Processor
VDD
DGND
Output
Circuits
PCM1602A
AGND
Digital Section
Analog Section
Common
Ground
B0032-06
Figure 35. Single-Supply PCB Layout
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THEORY OF OPERATION
The DAC section of the PCM1602A is based on a multi-bit delta-sigma architecture. This architecture uses a
fourth-order noise shaper and an 8-level amplitude quantizer, followed by an analog low-pass filter. A block
diagram of the delta-sigma modulator is shown in Figure 36. This architecture has the advantage of stability and
improved jitter tolerance, when compared to traditional 1-bit (2-level) delta-sigma designs.
−
+
IN
8 fS
+
+
−
+
Z–1
+
Z–1
+
+
+
Z–1
+ +
+
+
Z–1
+
8-Level Quantizer
OUT
64 fS
B0008-03
Figure 36. Eight-Level Delta-Sigma Modulator
The combined oversampling rate of the digital interpolation filter and the delta-sigma modulator is 32 fS, 64 fS, or
128 fS. The total oversampling rate is determined by the desired sampling frequency. If fS ≤ 96 kHz, then the
OVER bit in register 12 can be set to an oversampling rate of 64 fS or 128 fS. If fS > 96 kHz, then the OVER bit
can be used to set the oversampling rate to 32 fS or 64 fS. Figure 37 shows the out-of-band quantization-noise
plots for both the 64× and 128× oversampling scenarios. Notice that the 128× oversampling plot shows
significantly improved out-of-band noise performance, allowing for a simplified low-pass filter to be used at the
output of the DAC.
36
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QUANTIZATION NOISE SPECTRUM
vs
(128× OVERSAMPLING)
0
0
−20
−20
−40
−40
−60
−60
Amplitude − dB
Amplitude − dB
QUANTIZATION NOISE SPECTRUM
(64× OVERSAMPLING)
−80
−100
−120
−80
−100
−120
−140
−140
−160
−160
−180
−180
0
1
2
3
4
5
6
7
Frequency [fS]
0
8
1
2
3
4
5
6
7
Frequency [fS]
G021
8
G022
Figure 37. Quantization-Noise Spectrum
Figure 38 illustrates the simulated jitter sensitivity of the PCM1602A. To achieve best performance, the system
clock jitter should be less than 300 picoseconds. This is easily achieved using a quality clock generation IC, like
the PLL170x from Texas Instruments.
JITTER DEPENDENCE
(64× OVERSAMPLING)
125
Dynamic Range − dB
120
115
110
105
100
95
90
0
100
200
300
400
500
Jitter − ps
600
G020
Figure 38. Jitter Sensitivity
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KEY PERFORMANCE PARAMETERS AND MEASUREMENT
This section provides information on how to measure key dynamic performance parameters for the PCM1602A.
In all cases, a System Two Cascade audio measurement system by Audio Precision or equivalent is used to
perform the testing.
TOTAL HARMONIC DISTORTION + NOISE
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio DACs, because it takes into
account both harmonic distortion and all noise sources within a specified measurement bandwidth. The true RMS
value of the distortion and noise is referred to as THD+N. The test setup for THD+N measurements is shown in
Figure 39.
Evaluation Board
DEM-DAI1602A
S/PDIF
Receiver
2nd-Order
Low-Pass
Filter
PCM1602A
f–3 dB = 54 kHz
Digital
Generator
S/PDIF
Output
100% Full-Scale
24-Bit, 1-kHz
Sine Wave
Analyzer
and
Display
rms Mode
Band Limit
Notch Filter
fC = 1 kHz
HPF = 22 Hz(1)
LPF = 30 kHz(1)
Option = 20-kHz Apogee Filter(2)
B0062-04
(1)
There is little difference in measured THD+N when using the various settings for these filters.
(2)
Required for THD+N test
Figure 39. Test Setup for THD+N Measurements
For the PCM1602A DACs, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at
the input of the DAC. The digital generator is set to a 24-bit audio word length and a sampling frequency of 44.1
kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement
system. The S/PDIF data is transmitted via coaxial cable to the digital audio receiver on the DEM-DAI1602
demonstration board. The receiver is then configured to output 24-bit data in either I2S or left-justified data
format. The DAC audio interface format is programmed to match the receiver output format. The analog output is
then taken from the DAC post filter and connected to the analog analyzer input of the measurement system. The
analog input is band-limited, using filters resident in the analyzer. The resulting THD+N is measured by the
analyzer and displayed by the measurement system.
38
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DYNAMIC RANGE
Dynamic range is specified as A-weighted THD+N measured with a –60-dBFS, 1-kHz digital sine wave stimulus
at the input of the DAC. This measurement is designed to give a good indication of how the DAC performs, given
a low-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 40, and is similar to the THD+N
test setup discussed previously. The differences include the band-limit filter selection, the additional A-weighting
filter, and the –60-dBFS input level.
Evaluation Board
DEM-DAI1602A
S/PDIF
Receiver
PCM1602A(1)
2nd-Order
Low-Pass
Filter
f–3 dB = 54 kHz
S/PDIF
Output
Digital
Generator
0% Full-Scale,
Dither Off (SNR)
–60 dB FS,
1-kHz Sine Wave
(Dynamic Range)
Analyzer
and
Display
A-Weight
Filter(1)
rms Mode
Band Limit
Notch Filter
HPF = 22 Hz
fC = 1 kHz
LPF = 22 kHz
Option = A-Weighting(2)
B0063-04
(1)
Infinite-zero-detect mute disabled
(2)
Results without A-weighting are approximately 3 dB worse.
Figure 40. Test Setup for Dynamic Range and SNR Measurements
IDLE-CHANNEL SIGNAL-TO-NOISE RATIO
The SNR test provides a measure of the noise of the DAC. The input to the DAC is in all-0s data, and the DAC
infinite-zero-detect mute function must be disabled (default condition at power up for the PCM1602A). This
ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if
present) can be observed at the output. The dither function of the digital signal generator must also be disabled
to ensure an all-0s data stream at the input of the DAC.
The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input
signal level (see the notes provided in Figure 40).
DIFFERENCES BETWEEN THE PCM1602APTR AND PCM1602AMPTR
While the two devices are identical, the key difference between both orderable versions is the physical
orientation of the devices in the reel. See the appended Package Materials Information sheet for more details on
the orientation of the devices in the reels. When changing the orderable part number, remember to update the
tooling program to compensate for the different orientation.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August, 2005) to Revision A
Page
•
Deleted lead temperature specification from Absolute Maximum Ratings table .................................................................. 2
•
Added Differences Between the PCM1602APTR and PCM1602AMPTR section ............................................................. 39
40
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1602APT
ACTIVE
LQFP
PT
48
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-25 to 85
PCM1602A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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