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49% FPO
PCM1712U
Stereo Audio DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 16-BIT RESOLUTION q COMPLETE STEREO DAC: 8X Oversampling Digital Filter Multi-Level Delta-Sigma DAC Analog Low Pass Filter Output Amplifier q HIGH PERFORMANCE: –87dB THD + N 94dB Dynamic Range 98dB SNR q SYSTEM CLOCK: 384fs q SINGLE +5V POWER SUPPLY q ON-CHIP DIGITAL FILTER: Soft Mute and Attenuation Digital De-emphasis Double Speed Dubbing Mode q SMALL 28-PIN SOIC PACKAGE
DESCRIPTION
The PCM1712 is a complete low cost stereo, audio digital-to-analog converter, including digital interpolation filter, 3rd-order delta-sigma DAC, and analog output amplifiers. PCM1712 accepts 16-bit normal input data (MSB first, right justified), or 16-bit IIS data (32-bits per word, continuous clock). The digital filter performs an 8X interpolation function, as well as special functions such as soft mute, digital attenuation, de-emphasis and double-speed dubbing. PCM1712 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. Its low cost, small size and single +5V power supply make it ideal for automotive CD players, bookshelf CD players, BS tuners, keyboards, MPEG audio, MIDI applications, set-top boxes, CD-ROM drives, CD-Interactive and CD-Karaoke systems. PCM1712 has the same pinout functions as PCM1710.
Lch/Rch ATT Control
Digital In
Input Interface and Attentuator
Oversampling Digital Filter
3rd-Order Multi-Level Delta Sigma
Lch OUT DAC Low-Pass Filter Output Op Amp Rch OUT
Mode Control
System Clock
International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1994 Burr-Brown Corporation
PDS-1245B
Printed in U.S.A. June, 1995
SPECIFICATIONS
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit data, SYSCLK = 384fs, unless otherwise noted. PCM1712U PARAMETER RESOLUTION DIGITAL INPUT/OUTPUT Logic Family Input Logic Level (pins 1 to 3) VIH VIL Input Logic Current (pins 1 to 3) II Input Logic Level (pins 24 to 28) VIH VIL Input Logic Level (pins 24 to 28) II Input Logic Level (XTI) VIH VIL Input Logic Current (XTI) II Output Logic Level (CLKO): VOH VOL Output Logic Current IO Data Format Data Bit Sampling Frequency System Clock Frequency DC ACCURACY Gain Error Gain Mis-Match Channel-To-Channel Bipolar Zero Error Gain Drift Bipolar Gain Drift DYNAMIC PERFORMANCE(1) THD+N at F/S (0dB) THD+N at –60fdB Dynamic Range S/N Ratio Channel Separation DIGITAL FILTER PERFORMANCE Pass Band Ripple Pass Band Ripple Stop Band Attenuation Stop Band Attenuation Pass Band Pass Band Stop Band Stop Band De-emphasis Error ANALOG OUTPUT Voltage Range Load Impedance Center Voltage POWER SUPPLY REQUIREMENTS Voltage Range: +VCC +VDD Supply Current +ICC +IDD Power Dissipation TEMPERATURE RANGE Operation Storage CONDITIONS MIN TYP 16 MAX UNITS Bits
2.0 0.8 –200 3.5 1.5 –200 3.2 1.4 –120 4.5 0.5 ±10 Normal/IIS (see Timing) SELECTABLE 16-Bit/MSB First, Two’s Complement 32 44.1 48 12.288 16.934 18.432 ±1.0 ±1.0 ±20 ±50 ±20 –82 –87 –34 94 98 96 ±0.17 ±0.22 –35 –34 0.4535 0.4535 0.5465 0.5465 –0.2 3.1 5k +1/2VCC +4.5 +4.5 +VCC = +VDD = +5.0V +VCC = +VDD = +5.0V –25 –55 +5.0 +5.0 28 140 +5.5 +5.5 40 200 +85 +100 +0.55 ±5.0 ±5.0
VDC VDC µA VDC VDC µA VDC VDC µA VDC VDC mA
384fs
kHz MHz % of FSR % of FSR mV ppm of FSR/°C ppm of FSR/°C dB dB dB dB dB dB dB dB dB fs fs fs fs dB Vp-p Ω V VDC VDC mA mW °C °C
VO = 1/2VCC at Bipolar Zero
fIN = 991Hz fIN = 991kHz EIAJ A-weighted EIAJ A-weighted fIN = 991Hz Normal Mode Double Speed Mode Normal Mode Double Speed Mode Normal Mode Double Speed Mode Normal Mode Double Speed Mode (fS 32kHz ~ 48kHz)
92 90
NOTE: (1) Tested with Shibasoku #725 THD. Meter 400Hz HPF, 30kHz LPF On, Average Mode with 20kHz bandwidth limiting. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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PIN ASSIGNMENTS
PIN NAME NUMBER FUNCTION
Input Interface Pins
LRCIN DIN BCKIN 1 2 3 Sample Rate Clock Input. Controls the update rate (fs). Serial Data Input. MSB first, right justified format contains a frame of 16-bit or 20-bit data. Bit Clock Input. Clocks in the data present on DIN input.
Mode Controls and Clock Signals
CLKO XTI XTO MODE MUTE MD/DM1 MC/DM2 ML/DSD 4 5 6 24 25 26 27 28 Buffered Output of Oscillator. Equivalent to fs. Oscillator Input (External Clock Input). For an internal clock, tie XTI to one side of the crystal oscillator. For an external clock, tie XTI to the output of the chosen external clock. Oscillator Output. When using the internal clock, tie to the opposite side (from pin 5) of the crystal oscillator. When using an external clock, leave XTO open. Operation Mode Select. For serial mode, tie MODE “High”. For parallel mode, tie MODE “Low”. Mute Control. To disable soft mute, tie MUTE “High”. To enable soft mute, tie MUTE “Low”. Mode Control for Data/De-emphasis. See “Mode Control Functions” on page 10. Mode Control for BCKIN/De-emphasis. See “Mode Control Functions” on page 10. Mode Control for WDCK/Double speed dubbing. See “Mode Control Functions” on page 10.
Analog Functions
VOUTR VOUTL 13 16 Right Channel Analog Output. Left Channel Analog Output.
Power Supply Connections
DGND VDD VCC2R AGND2R EXT1R EXT2R AGND VCC EXT2L EXT1L AGND2L VCC2L NC 7, 22 8, 21 9 10 11 12 14 15 17 18 19 20 23 Digital Ground. Digital Power Supply (+5V). Analog Power Supply (+5V), Right Channel DAC. Analog Ground (DAC), Right Channel. Output Amplifier Common, Right Channel. Bypass to ground with a 10µF capacitor. Output Amplifier Bias, Right Channel. Connect to EXT1R. Analog Ground. Analog Power Supply (+5V). Output Amplifier Bias, Left Channel. Connect to EXT1L. Output Amplifier Common, Left Channel. Bypass to ground with a 10µF capacitor. Analog Ground (DAC), Left Channel. Analog Power Supply (+5V), Left Channel DAC. No Connection.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ....................................................................... +6.5V +VCC to VDD Voltage ......................................................................... ±0.1V Input Logic Voltage ......................................................... –0.3V~VDD+0.3V Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature Range .......................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C
PACKAGE INFORMATION
MODEL PCM1712U PACKAGE 28-Pin SOIC PACKAGE DRAWING NUMBER(1) 217
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
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PCM1712
CONNECTION DIAGRAM
1 Serial Data Input(3) 2 3 4
10pF ~ 22pF x 2
Input Interface Digital Filter Timing Control Mode Control
28 27 26 25 24 Noise Shaper 23 22
(1)
Mode Control(3)
5 6
(1)
7 8 5-Level ∆Σ DAC Right Low-Pass Filter Right 5-Level ∆Σ DAC Left Low-Pass Filter Left
21 20 19
10µF
(1)
(1)
9 10
10µF
+
11 12 CMOS Amp Right CMOS Amp Left
18 17 16 15
+
DAC Rch OUT
13 14
DAC Lch OUT
(1)
100µF
+5V Power Supply
10kΩ
10kΩ 680pF
1500pF 10kΩ 100pF
Rch OUT
10kΩ
10kΩ 680pF
1500pF 10kΩ 100pF
Lch OUT
3rd ORDER LPF(2)
NOTE: (1) Bypass Capacitor :1µF ~ 10µF. (2) Typical application circuit. To obtain guaranteed specifications, required 20kHz bandwidth limitation by low pass filter. (3) Input pins require pull-up resistors.
3rd ORDER LPF(2)
PIN CONFIGURATION
LRCIN DIN BCKIN CLKO XTI XTO DGND VDD VCC2R AGND2R EXT1R EXT2R VOUTR AGND1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Input Interface Digital Filter Timing Control Mode Control
28 27 26 25 24 Noise Shaper 23 22
ML/DSD MC/DM2 MD/DM1 MUTE MODE NC DGND VDD VCC2L AGND2L EXT1L EXT2L VOUTL VCC1
5-Level ∆Σ DAC Right
5-Level ∆Σ DAC Left Low-Pass Filter-Left
21 20 19 18
CMOS Amp Left
17 16 15
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DATA INPUT TIMING
1 f/s Left-channel Data MSB DIN 1 2 14 15 LSB 16 MSB 1 2 14 15 Right-channel Data LSB 16
BCKIN
LRCIN
FIGURE 1. Normal Format, 16-Bit (LRCIN H: Lch).
1 f/s Left-channel Data MSB DIN 16 1 2 3 13 14 LSB MSB 15 16 1 2 3 13 14 Right-channel Data LSB 15 16
BCKIN
LRCIN
FIGURE 2 . IIS Format, 16-Bit (32 BCKIN/fs, continuous data).
BCKIN tBCWH tBCY tBCWL
DIN tDH tDS
tBL
tLB
LRCIN
FIGURE 3. Data Input Timing.
BCK Pulsewidth (H Level) BCK Pulsewidth (L Level BCK Pulse Cycle Time DIN Setup Time DIN Hold Time BCK Rising Edge → LRCI Edge LRC I Edge → BCK Rising Edge tBCWH tBCWL tBCY tDS tDH tBL tLB 70ns (min) 70ns (min) 140ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min)
TABLE I. Data Input Timing Specifications.
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PCM1712
MC tMCWH tMCY tMCWL
MD tMH tMS
tMCS
tMCH
ML tMLY
FIGURE 4. Serial Mode Control Timing.
MC Pulsewidth (H Level) MC Pulsewidth (L Level) MC Pulse Cycle Time MD Setup Time MD Hold Time ML Setup Time ML Hold Time ML Low-Level Time
tMCWH tMCWL tMCY tMS tMH tMCS tMCH tMLY
50ns (min) 50ns (min) 100ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) 1/sysclk + 20ns (min)
TABLE II. Serial Mode Control Timing Specifications (Refer to Figure 5).
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TYPICAL PERFORMANCE CURVES
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, fSYS = 384fs, and 16-bit data, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTICS NORMAL MODE (De-emphasis: OFF) 0
0
PASSBAND RIPPLE CHARACTERISTIC NORMAL MODE (De-emphasis: OFF)
–20
–0.2
–40
dB dB
–0.4
–60
–0.6
–80
–0.8
–100 0 20k 40k 60k 80k 100k 120k 140k 160k 180k Frequency (Hz)
–1 0 5k 10k Frequency (Hz) 15k 20k
OVERALL FREQUENCY CHARACTERISTICS DOUBLE-SPEED MODE (De-emphasis: OFF) 0
PASSBAND RIPPLE FREQUENCY CHARACTERISTIC DOUBLE-SPEED MODE (De-emphasis: OFF) 0
–20
–0.2
–40
dB
dB
–0.4
–60
–0.6
–80
–0.8
–100 0 20k 40k 60k 80k 100k 120k 140k 160k 180k Frequency (Hz)
–1 0 5k 10k 15k 20k 25k 30k 35k 40k Frequency (Hz)
DE-EMPHASIS CHARACTERISTIC DOUBLE-SPEED MODE 0 –2 –4 0 –2 –4
DE-EMPHASIS CHARACTERISTIC NORMAL MODE
dB
–6 –8 –10 –12 0 10k 20k 30k 40k 50k Frequency (Hz)
dB
–6 –8 –10 –12 0 5k 10k 15k 20k 25k Frequency (Hz)
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PCM1712
TYPICAL PERFORMANCE CURVES (CONT)
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, fSYS = 384fs, and 16-bit data, unless otherwise noted.
DYNAMIC PERFORMANCE (Based on 200 piece sample from 3 diffusion runs)
BPZ ERROR vs TEMPERATURE 50 45 40
BPZ Error (mV)
THD FS vs TEMPERATURE –82 –83 –84 Maximum
THD FS (%)
35 30 25 20 15 10 5 0 –25 0 25 50 70 Average
Maximum Average Minimum
–86 –88 –90 –94 –100 0
Minimum
85
90
–25
0
25
50
70
85
90
Temperature (°C)
Temperature (°C)
THD –60dB vs TEMPERATURE –30.5 –31 –31.7
SNR vs TEMPERATURE 100 99 98 97 Average
Maximum
Maximum
THD –60dB (%)
–32.4 Average
S/N (dB)
–33 –34 –35 –36 –37 –38.4 –40 –25 0 25 50 70
96 95 94 93 Minimum
Minimum
92 91 90
85
90
–25
0
25
50
70
85
90
Temperature (°C)
Temperature (°C)
BPZ ERROR vs SUPPLY VOLTAGE 50 45 40
BPZ Error (mV)
THD+N AT FS vs SUPPLY VOLTAGE –82 –83 –25°C –84
THD FS (dB)
35 30 25 20 15 10 5 0 4.5 5.0 Voltage (V) –25°C
+85°C
+85°C 25°C
–86 –88 25°C –90 –94 –100 0
5.5
4.5
5.0 Voltage (V)
5.5
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TYPICAL PERFORMANCE CURVES (CONT)
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, fSYS = 384fs, and 16-bit data, unless otherwise noted.
DYNAMIC PERFORMANCE (Based on 200 piece sample from 3 diffusion runs)
THD+N AT –60dB vs SUPPLY VOLTAGE –30.5 –31.0 –31.7
THD –60dB (dB)
SNR vs SUPPLY VOLTAGE 100 99 98 97 85°C –25°C 25°C
–32.4 +85C°C 25°C
–34.0 –35.0 –36.0 –37.0 –38.4 –40.0 4.5 5.0 Voltage (V) 5.5
S/N (dB)
–33.0
–25°C
96 95 94 93 92 91 90 4.5 5.0 Voltage (V)
5.5
CAUTION: Minimum and maximum values on typical performance curves are not meant to imply a guarantee. Curves should be used for reference only. Refer to specifications for guaranteed performance.
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PCM1712
FUNCTIONAL DESCRIPTION
PCM1712 has several built-in functions including digital attenuation, digital de-emphasis and soft mute. These functions are software controlled. PCM1712 can be operated in two different modes, Serial or Parallel. Serial Mode is a three-wire interface using pin 26 (MD), pin 27 (MC), and pin 28 (ML). Data on these pins are used to control deemphasis modes, mute, double-speed dubbing, input resolution and input formats. PCM1712 can also be operated in parallel mode, where static control signals are used on pins 26 (DM1), pin 27 (DM2), and pin 28 (DSD). Operation of both of these modes are covered in detail in the next sections. CAUTION: Mode control signals operate on level triggered logic. The minimum timing conditions detailed in Figures 4 and 5 MUST be observed. MODE CONTROL: SERIAL/PARALLEL SELECTION
MODE = H MODE = L Serial Mode Parallel Mode
PARALLEL-MODE: DOUBLE-SPEED DUBBING CONTROL (PIN 24 [MODE] = L)
DSD = H DSD = L Normal Mode Double Speed Dubbing Mode
TABLE VI. DSD (Pin 28). In the parallel mode, double-speed dubbing can be enabled by holding pin 28 (DSD) at logic “low”. SERIAL MODE CONTROL In order to use all of PCM1712’s functionality, the serial mode control should be used. PCM1712 must be addressed three separate times to set all of the various registers and flags that control these functions. Table VII together with Figure 6 details the control of the PCM1712 in the serial mode. Internal latches are used to hold this serial data until the PCM1712 is enabled to use the data. The serial mode is used by applying clocked data to the following pins:
NAME MC ML MD PIN 27 28 26 FUNCTION Clock for Strobing in Data Latches Data into the Registers 8-bit Data Word Defining Operation
TABLE III. Serial and Parallel Mode are Selectable by MODE Pin (Pin 24). MODE CONTROL: SELECTABLE FUNCTIONS
FUNCTION Input Data Format Selection Input LRCI Polarity Selection De-emphasis Control Mute Attenuation Double-Speed Dubbing SERIAL MODE (MODE = H) 0 0 0 0 0 0 PARALLEL MODE (MODE = L) X (Normal Mode Fixed) X 0 0 X 0
DIGITAL ATTENUATION One of the functions which can be implemented through use of the serial mode control is attenuation. This function allows the user to control the level of the output, independent of the input level set by the actual input data supplied to the DAC. Referring to Figure 5, when the first data bit (B0) on MD (pin 26) is low, the attenuation function is enabled. The next seven bits (B1 - B6) define a binary value, ATT_DATA, that indicates the desired level of attenuation. The attenuation level is given by: Level = 20log10 (1 - ATT_DATA/127) dB When all 7 bits of the ATT_DATA word are high (ATT_DATA = 127), attenuation is infinite and the output of PCM1712 will be zero.
NOTE: 0: Selectable, X: Not Selectable.
TABLE IV. Selectable Functions in Serial Mode and Parallel Mode. Table IV indicates which functions are selectable within the user’s chosen mode. All of the functions shown are selectable within the serial mode, but only de-emphasis control, mute and double-speed dubbing may be selected when using PCM1712 in the parallel mode. PARALLEL-MODE: DE-EMPHASIS CONTROL (PIN 24 [MODE] = L)
DM1 (Pin 26) L H L H DM2 (Pin 27) L L H H De-emphasis OFF 32kHz 48kHz 44.1kHz
TABLE V. De-emphasis (Pins 26 and 27). In the parallel mode, de-emphasis conditions are controlled by the logic levels on pin 26 (DM1) and pin 27 (DM2). For PCM1712, de-emphasis can operate at 32kHz, 44.1kHz, 48kHz, or disabled.
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B0
B1
B2
BIT NO. B3 B4
MODE FLAG DEEM2 DEEM1
FUNCTION MODE SELECTION MODE Sampling Frequency for De-emphasis DEEM1 0 1 0 1 0 1 0 1 BIT VALUE SELECTED FUNCTION DEEM2 0 32kHz 1 48kHz 44.1kHz
MODE BY DEFAULT
44.1kHz OFF OFF OFF
Mode 1
1
0
0
B5 B6 B7 B3 B4
IIR MUTE DSD
De-emphasis Mute Double-Speed Not Assigned Not Assigned Not Assigned
De-emphasis OFF De-emphasis ON Mute OFF Mute ON Double-speed OFF Double-speed ON
Mode 2
1
0
1
B5 B6 B7 LRPL IIS
Polarity for LRCI Input Format
0 1 0 1
Lch:high/Rch:low Lch:low/Rch:high Normal IIS
Lch:HIGH Rch:LOW Normal
TABLE VII. Serial-Mode Control Input Format (MODE: H, Pin 24).
MC
ML ATT_DATA Alternation Mode MD Mode 1 L D6 D5 D4 D3 D2 D1 D0
H
L
L
DEEM2
DEEM1
IIR
MUTE
DSD
Mode 2
H
L
H
LRPL
IIS
Bit#
B0
B1
B2
B3
B4
B5
B6
B7
(NOTE: Cycle Time for Model Control—Cycle time for mode control must be set over 192 times of minimum system clock.)
FIGURE 5. Mode Control Input Format, Serial Mode.
MODE 1 CONTROLS
This mode can be enabled with the sequence of 1, 0, 0 as the first three bits on MD (pin 26). This mode allows for the following functions:
De-emphasis De-emphasis Frequency Soft Mute Double-Speed Dubbing On/Off 32kHz, 44.1kHz, 48kHz On/Off On/Off
B3 0 0 1 1
B4 0 1 0 1
FREQUENCY OFF 48kHz 32kHz 44.1kHz
Once the reset has been established on pin 27 (MC), the deemphasis frequency defaults to 44.1kHz. B5 can be used to override B3 and B4; a logic low on B5 disables de-emphasis, and a logic high on B5 forces de-emphasis at 44.1kHz. SOFT MUTE Soft mute is enabled when B6 is high. The soft mute occurs gradually, unlike the forced infinite zero detection. When the mute data bit is high, complete muting will occur in 127/fs seconds.
DIGITAL DE-EMPHASIS PCM1712 allows three different sampling rates for digital de-emphasis. B3 and B4 are used for binary control of the de-emphasis frequency:
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DOUBLE-SPEED DUBBING Double-speed dubbing is enabled when B7 is high. Since fS is set at 44.1kHz, the system clock in double-speed mode is at 192fs.
SYSTEM CLOCK
SAMPLING FREQUENCY 32kHz 44.1kHz 48kHz SYSTEM CLOCK 384fs 384fs 384fs FREQUENCY 12.2880MHz 16.9344MHz 18.4320MHz
MODE 2 CONTROLS
This mode is enabled when the first three bits on MD are 1, 0, 1. Mode 2 allows for the following functions:
LR Polarity Input Format Controls Left/Right Channel Select Normal/IIS (Philips format)
NORMAL/DOUBLE-SPEED DUBBING For most CD playback applications operating at 384fs, the system clock frequency must be 16.9344MHz, in both the normal mode and double-speed dubbing mode. Table VIII illustrates the relationship between fs and output clock frequency in both modes.
DSD L (Double Speed) 192fs 16.9344MHz (fS = 88.2kHz) 192fs
SAMPLE RATE CLOCK POLARITY B6 controls the polarity of the sample rate clock (LRCIN) polarity. When B6 is low, data will be accepted on the left channel when LRCIN is high, and on the right channel when LRCIN is low. When B6 is high, data will be accepted on the right channel when LRCIN is high, and on the left channel when LRCIN is low. INPUT FORMAT Normal input mode for PCM1712 is MSB first, right justified. PCM1712 may also be operated with IIS input format. When B7 is low, the input format is “normal”. When B7 is high, the input format is “IIS”. DEFAULT MODE At initial power-on, default settings for PCM1712 are 44.1kHz fS, de-emphasis off, mute off, double speed off, infinite zero detect on, 16-bit input LRCIN left channel high, and normal input mode.
PARAMETER XTI Input Clock Frequency XTI Frequency CLKO Output Clock Frequency
H (Normal) 384fs 16.9344MHz (fS = 44.1kHz) 384fs
TABLE VIII. Relationship Between Normal/Double Speed and fs. EXTERNAL SYSTEM CLOCK Figure 7 is a diagram showing the internal clock in conjunction with an external crystal oscillator.
Internal System Clock
VIH > 0.64VDD VIL < 0.28VDD TH > 10ns TL < 10ns
C1, C2: 10pF ~ 22pF Crystal C1 C2 CLKO (XTI) XTI XTO
TH VIH
FIGURE 7. External Crystal Oscillator.
VIIL TL
Figure 8 is a diagram showing the internal clock with an external clock source, instead of an oscillator. An external system clock (input to XTI) must meet timing requirement which is shown in Figure 6.
In case of system clock inputs to XTI from external, system clock should be input with the following condition.
FIGURE 6. Timing Requirement for External System Clock (XTi).
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Digital Power Supply
Analog Power Supply
Internal System Clock
VDD DGND
VCC AGND
CLKO (XTI)
XTI
XTO(1)
FIGURE 9. Latch-up Prevention Circuit.
External System Clock Input
NOTE: (1) XTO must be open.
FIGURE 8. Latch-up Prevention Circuit.
BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. Refer to Figure 16 for optimal values of bypass capacitors. For applications which require very high performance at low levels (such as keyboards, synthesizers, etc.), it may be beneficial to provide additional bypassing on pin 15 (VCC1) with a low ESR 100µF capacitor. This will eliminate stray tones which may be above the noise floor.
POWER SUPPLY CONNECTIONS
PCM1712 has two power supply connections: digital (VDD) and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.6V. An application circuit to avoid a latch-up condition is shown in Figure 9.
THEORY OF OPERATION
The delta-sigma section of PCM1712 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled 16-bit input data to 5-level delta-sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 10. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator.
+ In 8fs 16 Bit + – Z–1 +
+ Z–1 – +
+ Z–1
+ + 5-level Quantizer 4 Out 48fs 3 2 1 0 +
FIGURE 10. 5 Level ∆Σ Modulator Block Diagram.
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The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 48fs. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 11.
THIRD-ORDER ∆Σ MODULATOR 20 0 –20 –40
Gain (–dB)
OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1712 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD + N, etc. to 20kHz. Failure to use such a filter will result in higher THD + N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. The performance of the internal low pass filter from DC to 24kHz is shown in Figure 12. The higher frequency rolloff of the filter is shown in Figure 13. If the user’s application has the PCM1712 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 14. For some applications, a passive RC filter or 2nd-order filter may be adequate.
–60 –80 –100 –120 –140 –160 0 5 10 15 20 25 Frequency (kHz)
SIMULATED ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0
FIGURE 11. Quantization Noise Spectrum.
APPLICATION CONSIDERATIONS
DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1712: TD = 12.625 x 1/fs For fS = 44.1kHz, TD = 12.625/44.1kHz = 286.28µs Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. INTERNAL RESET When power is first applied to PCM1712, an automatic reset function occurs after 64 cycles of LRCIN.
0.5
dB
0
–0.5
–1.0 20 100 1k Frequency (Hz) 10k 24k
FIGURE 12. Low Pass Filter Frequency Response.
SIMULATED ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M 10M Frequency (Hz)
FIGURE 13. Low Pass Filter Frequency Response.
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14
dB
TEST CONDITIONS Figure 15 illustrates the actual test conditions applied to PCM1712 in production. The 11th-order filter is necessary in the production environment for the removal of noise resulting from the relatively long physical distance between the unit and the test analyzer. In most actual applications, the third-order filter shown in Figure 14 is adequate. Under normal conditions, THD+N typical performance is –70dB with a 30kHz low pass filter (shown here on the THD meter), improving to –92dB when the external 20kHz second-order filter is used.
EVALUATION FIXTURES An evaluation fixture is available for PCM1712. DEM-PCM1712 This evaluation fixture is primarily intended for quick evaluation of the PCM1712’s performance. DEM-PCM1712 can accept either an external clock or a user-installed crystal oscillator. All of the functions can be controlled by on-board switches. DEM-PCM1712 does not contain a receiver chip or an external low pass filter. DEM-PCM1712 requires a single +5V power supply.
1 1500pF 4 + VSIN – 10kΩ 5 10kΩ 680pF 3 10kΩ 100pF 2
GAIN vs FREQUENCY 6 Gain –14 0 90
Gain (dB)
–54 Phase –74
–180
–270
–94 100 1k 10k Frequency (Hz) 100k 1M
–360
FIGURE 14. 3rd-Order LPF.
Phase (°)
–34
–90
Test Disk Through Lch CD Player DAI Digital DEMPCM1712 Rch PGA
Shibasoku #725
11th-order 20kHz LPF
THD Meter
0dB/60dB
30KHz LPF on
For test of S/N ratio and Dynamic Range, A-filter ON.
FIGURE 15. Test Block Diagram.
®
15
PCM1712
CN1
DS LRCIN DIN BCKIN CLKO XTI XTO
(2)
1 2 3 4 5 6 7 8 9
(2)
28 27 26 25 24 23 22 PCM1712U 21 20 19 18 17 16 15
(1) (2) (2)
DSD DM2 DM1 MODE CKSL
10 11
ML 10µF C N 2 MC MD GND +VCC
(2)
10µF
12 13 14
+
+
+ C O U T • R D OG UN TD • R
+ 100µF
+ NOTE: (1) Bypass Capacitor. 0.1µF Ceramic. (2) Bypass Capacitor 1µF ~ 10µF Tantalum. CN3 D O U T • L C O U T • L
FIGURE 16. DEM-PCM1712 Schematic Circuit Diagram.
®
PCM1712
16
