®
49%
173
9
FPO
PCM
PCM1739
For most current data sheet and other product
information, visit www.burr-brown.com
24-Bit, 192kHz Sampling,
Enhanced Multi-Level, Delta-Sigma, Audio
DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
APPLICATIONS
● 24-BIT RESOLUTION
● A/V RECEIVERS
● ANALOG PERFORMANCE (VCC = +5V):
Dynamic Range: 106dB typ
SNR: 105dB typ
THD+N: 0.0015% typ
Full-Scale Output: 3.1Vp-p typ
● DVD AUDIO AND MOVIE PLAYERS
● 4x/8x OVERSAMPLING DIGITAL FILTER:
Passband: 0.454fS
Stopband: 0.546fS
Stopband Attenuation: –82dB
Passband Ripple: ±0.002dB
● SAMPLING FREQUENCY: 10kHz to 192kHz
● SYSTEM CLOCK: 128fS, 192fS, 256fS, 384fS,
512fS, or 768fS with Auto Detect
● ACCEPTS 24- or 16-BIT AUDIO DATA
● DATA FORMATS: Standard, I2S
● MODE CONTROLS
Digital De-Emphasis
Soft Mute
Zero Flags for Each Output
● DUAL SUPPLY OPERATION:
+5V Analog, +3.3V Digital
● DVD ADD-ON CARDS FOR ENTERTAINMENT
PCs
● HDTV RECEIVERS
● CAR AUDIO SYSTEMS
● OTHER APPLICATIONS REQUIRING
24-BIT AUDIO
DESCRIPTION
The PCM1739 is a CMOS, monolithic, integrated
circuit which includes stereo 24-bit audio digital-toanalog converters and support circuitry in a small
SSOP-28 package. The data converters utilize BurrBrown’s enhanced multi-level delta-sigma architecture, which employs 4th-order noise shaping and
8-level amplitude quantization to achieve excellent
dynamic performance and improved tolerance to clock
jitter. The PCM1739 accepts industry-standard audio
data formats with 16- or 24-bit data, providing easy
interfacing to audio DSP and decoder chips. Sampling
rates up to 192kHz are supported.
● 5V TOLERANT DIGITAL INPUTS
● SMALL SSOP-28 PACKAGE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
SBAS133
PDS-1560C
Printed in U.S.A. March, 2000
SPECIFICATIONS
All specifications at TA = +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.
PCM1739E
PARAMETER
CONDITIONS
MIN
RESOLUTION
TYP
MAX
24
DATA FORMAT
Audio Data Interface Formats
Audio Data Bit Length
Audio Data Format
System Clock Frequency
Sampling Frequency (fS)
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level
VIH
VIL
Input Logic Current
IIH
IIL
IIH(1)
IIL(1)
Output Logic Level
VOH(2)
VOL(2)
VOH(3)
VOL(3)
DYNAMIC PERFORMANCE(4)
THD+N, VOUT = 0dB
VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio(5)
Channel Separation
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
DIGITAL FILTER PERFORMANCE
Filter Characteristics
Passband
Stopband
Passband Ripple
Stopband Attenuation
User Selectable
User Selectable
Cut-Off Frequency
Standard/I2S
16 or 24 Bits
MSB-First, Binary Two's Complement
128, 192, 256, 384, 512, 768fS
10
200
2.0
VIN = VDD
VIN = 0V
VIN = VDD
VIN = 0V
65
IOH = –2mA
IOL = +2mA
IOH = –4mA
IOL = +4mA
kHz
0.8
VDC
VDC
0.1
–0.1
100
–0.1
µA
µA
µA
µA
2.4
1.0
2.4
1.0
fS = 44.1kHz, 384fS
fS = 96kHz, 256fS
fS = 192kHz, 128fS
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
102
100
98
100
100
100
100
98
96
VOUT = 0.5VCC at BPZ
Full Scale (–0dB)
AC Load
0.0035
0.0050
0.0060
0.8
1.0
1.2
%
%
%
%
%
%
dB
dB
dB
dB
dB
dB
dB
dB
dB
±1.0
±1.0
±30
±3.0
±3.0
±60
% of FSR
% of FSR
mV
Vp-p
VDC
kΩ
62% of VCC
50% of VCC
±0.002dB
–3dB
34/fS
±0.1
Hz
Hz
Hz
dB
dB
dB
sec
dB
–0.03
–0.20
190
dB
dB
kHz
0.454fS
0.490fS
0.546fs
Stopband = 0.546fS
Stopband = 0.567fS
At 20kHz
At 44kHz
–3dB
2
VDC
VDC
VDC
VDC
0.0015
0.0020
0.25
0.6
0.7
0.8
106
105
104
105
104
104
104
103
102
5
®
PCM1739
Bits
TTL-Compatible
Delay Time
De-Emphasis Error
ANALOG FILTER PERFORMANCE
Frequency Response
UNITS
±0.002
–75
–82
SPECIFICATIONS (cont.)
All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.
PCM1739E
PARAMETER
CONDITONS
POWER SUPPLY REQUIREMENTS
Voltage Range
VDD
VCC
Supply Current
IDD(6)
MIN
TYP
MAX
UNITS
+3.0
+3.3
+3.6
VDC
+4.5
+5.0
+5.5
VDC
8.5
16.5
19.5
12.0
mA
mA
mA
13.0
14.0
14.5
18.0
mA
mA
mA
93
124
137
130
mW
mW
mW
70
+125
°C
°C
°C/W
VDD = 3.3V
fS = 44.1 kHz
fS = 96kHz, 256fS
fS = 192kHz, 128fS
VCC = 5.0V
fS = 44.1kHz
fS = 96kHz, 256fS
fS = 192kHz, 128fS
VDD = 3.3V, VCC = 5.0V
fS = 44.1kHz
fS = 96kHz, 256fS
fS = 192kHz, 128fS
ICC
Power Dissipation
TEMPERATURE RANGE
Operation
Storage
Thermal Resistance θJA
0
–55
100
NOTES: (1) Pins 8, 9, 26, 27, 28 (TEST1, IBIT, DEM0 DEM1, FORM). (2) Pins 23, 24 (ZEROL, ZEROR). (3) Pin 4 (CLKO). (4) Analog performance specs are
tested with Shibasoku #725 THD Meter 400Hz HPF, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load connected to the analog output is 5kΩ
or larger, AC-coupled. (5) SNR is tested with Infinite Zero Detection off. (6) CLKO is disabled.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply Voltage, VDD .............................................................. +4.0V
VCC .............................................................. +6.5V
Input Current (except power supply pins) ....................................... ±10mA
Supply Voltage Difference ................................................................ ±0.1V
GND Voltage Difference ................................................................... ±0.1V
Digital Input Voltage ........................................................... –0.2V to +5.5V
Digital Output Voltage .............................................. –0.2V to (VDD + 0.2V)
Power Dissipation .......................................................................... 650mW
Operating Temperature Range ............................................. 0°C to +70°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) ................................................ +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM1739E
"
28-Lead SSOP
"
324
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
0°C to +70°C
"
PCM1739E
"
PCM1739E
PCM1739E/2K
Rails
Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1739E/2K” will get a single 2000-piece Tape and Reel.
®
3
PCM1739
BLOCK DIAGRAM
PCM1739
BCK
Audio
Serial
I/F
LRCK
VOUTL
Output Amp and
Low-Pass Filter
DAC
DATA
4x/8x
Oversampling
Digital Filter
with
Function
Controller
TEST
IBIT
VCOML
Enhanced
Multi-level
Delta-Sigma
Modulator
RSTB
Mode
Control
I/F
FORM
DEM1
VOUTR
Output Amp and
Low-Pass Filter
DAC
VCOMR
DEM0
MUTE
FILT
System Clock
PIN ASSIGNMENTS
VCCR
GNDR
VCCL
GNDL
VCCA
VSS
VDD
ZEROR
CLKO
GNDA
Power Supply
Zero Detect
ZEROL
System Clock
Manager
SCLK
PIN CONFIGURATION
PIN
NAME
TYPE
1
LRCK
IN
DESCRIPTION
Left/Right Word Clock(1)
2
DATA
IN
Data In for Left and Right Channels(1)
Bit Clock(1)
3
BCLK
IN
4
CLKO
OUT
System Clock Output
5
SCLK
IN
System Clock Input(1)
6
VSS
—
Digital Ground
7
VDD
—
Digital Supply, +3.3V.
8
TEST1
IN
Test Pin. Must be connected to VDD(2).
9
IBIT
IN
Audio Data Word Length Select(2)
10
VCCR
—
Analog Supply for Right Channel, +5V.
11
GNDR
—
Analog Ground for Right Channel
12
VCOMR
—
Common for Right Channel
13
VOUTR
OUT
14
GNDA
—
Analog Ground
Analog Supply, +5V.
Top View
Analog Output for Right Channel
SSOP
LRCK
1
28
FORM
DATA
2
27
DEM1
BCLK
3
26
DEM0
CLKO
4
25
NC
SCLK
5
24
ZEROR
VSS
6
23
ZEROL
VDD
7
22
RSTB
TEST1
8
21
MUTE
IBIT
9
20
FILT
VCCR
10
19
VCCL
PCM1739E
15
VCCA
—
16
VOUTL
OUT
17
VCOML
—
Common for Left Channel
18
GNDL
—
Analog Ground for Left Channel
19
VCCL
—
Analog Supply for Left Channel, +5V.
20
FILT
IN
4x/8x Interpolation Filter Select(2)
GNDR
11
18
GNDL
21
MUTE
IN
Digital Mute for Left and Right Channels(2)
VCOMR
12
17
VCOML
22
RSTB
IN
Reset, Active Low(1).
23
ZEROL
OUT
Zero Flag for Left Channel
VOUTR
13
16
VOUTL
24
ZEROR
OUT
Zero Flag for Right Channel
GNDA
14
15
VCCA
25
NC
—
No Connect
26
DEM0
IN
De-Emphasis Filter Select 0(2)
27
DEM1
IN
De-Emphasis Filter Select 1(2)
28
FORM
IN
Audio Data Format Select(2)
Analog Ouput for Left Channel
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant.
(2) Schmitt-Trigger input, 5V tolerant.
®
PCM1739
4
TYPICAL PERFORMANCE CURVES
All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
PASSBAND RIPPLE
FREQUENCY RESPONSE
0
0.003
–20
0.002
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
0.001
0
–0.001
–120
–0.002
–140
–160
–0.003
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
DIGITAL FILTER
DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz)
0
–2
–4
–6
–8
–10
Level (dB)
Level (dB)
De-Emphasis Error
0
2
4
6
8
10
12
DE-EMPHASIS ERROR (fS = 32kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
14
0
2
4
DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz)
0
–2
–4
–6
–8
–10
0
2
4
6
8
10
12
14
16
18
20
0
Level (dB)
Level (dB)
2
4
6
8
10
12
14
10
12
14
2
4
6
8
10
12
14
16
18
20
20
22
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz)
0
8
DE-EMPHASIS ERROR (fS = 44.1kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
Frequency (kHz)
0
–2
–4
–6
–8
–10
6
Frequency (kHz)
Level (dB)
Level (dB)
Frequency (kHz)
16
18
20
22
DE-EMPHASIS ERR0R (fS = 48kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
0
Frequency (kHz)
2
4
6
8
10
12
14
16
18
Frequency (kHz)
®
5
PCM1739
TYPICAL PERFORMANCE CURVES (cont.)
All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE vs VCC
(VDD = 3.3V)
10
110
192kHz, 128fS
108
1
–60dB
Dynamic Range (dB)
THD+N (%)
DYNAMIC RANGE vs VCC
(VDD = 3.3V)
44.1kHz, 384fS
0.1
0.01
192kHz, 128fS
0dB
0.001
44.1kHz, 384fS
106
104
102
192kHz, 128fS
100
98
44.1kHz, 384fS
0.0001
96
4.0
4.5
5.0
5.5
6.0
4.0
4.5
5.0
VCC (V)
SIGNAL-TO-NOISE RATIO vs VCC
(VDD = 3.3V)
110
6.0
CHANNEL SEPARATION vs VCC
110
108
Channel Separation (dB)
108
44.1kHz, 384fS
106
SNR (dB)
5.5
VCC (V)
104
102
192kHz, 128fS
100
106
44.1kHz, 384fS
104
102
100
192kHz, 128fS
98
98
96
96
4.0
4.5
5.0
5.5
4.0
6.0
4.5
5.0
5.5
6.0
VCC (V)
VCC (V)
Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
110
10
192kHz, 128fS
108
1
–60dB
Dynamic Range (dB)
THD+N (%)
DYNAMIC RANGE vs TEMPERATURE
(VDD = 3.3V)
44.1kHz, 384fS
0.1
192kHz, 128fS
0.01
0dB
44.1kHz, 384fS
106
104
102
192kHz, 128fS
100
0.001
98
44.1kHz, 384fS
0.0001
96
4.0
4.5
5.0
5.5
6.0
–25
VCC (V)
25
50
Temperature (°C)
®
PCM1739
0
6
75
100
TYPICAL PERFORMANCE CURVES (cont.)
All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.
Temperature Characteristics (cont.)
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
(VDD = 3.3V)
110
110
108
108
Channel Separation (dB)
44.1kHz, 384fS
106
SNR (dB)
CHANNEL SEPARATION vs TEMPERATURE
(VDD = 3.3V)
104
192kHz, 128fS
102
100
98
106
44.1kHz, 384fS
104
102
100
192kHz, 128fS
98
96
96
–25
0
25
50
75
100
–25
Temperature (°C)
0
25
50
75
100
Temperature (°C)
®
7
PCM1739
POWER-ON AND EXTERNAL RESET FUNCTIONS
SYSTEM CLOCK AND RESET
FUNCTIONS
The PCM1739 includes a power-on reset function. Figure 2
shows the operation of this function. The system clock input
at SCLK should be active for at least one clock period prior
to VDD = 2.0V. With the system clock active and VDD >
2.0V, the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time VDD > 2.0V. The PCM1739 also includes an external
reset capability using the RSTB input (pin 22). This allows
an external controller or master reset circuit to force the
PCM1739 to initialize to its reset default state. For normal
operation, RSTB should be set to a logic ‘1’.
SYSTEM CLOCK INPUT
The PCM1739 requires a system clock for operating the
digital interpolation filters and multi-level delta-sigma modulators. The system clock is applied at the SCLK input (pin
5). Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1739 system clock.
Figure 3 shows the external reset operation and timing. The
RSTB pin is set to logic ‘0’ for a minimum of 20ns. The
RSTB pin is then set to a logic ‘1’ state, which starts the
initialization sequence, which lasts for 1024 system clock
periods.
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the CLKO output (pin 4). CLKO operates at the same
frequency as the system clock, SCLK.
The external reset is especially useful in applications where
there is a delay between PCM1739 power up and system
clock activation. In this case, the RSTB pin should be held
at a logic ‘0’ level until the system clock has been activated.
SYSTEM CLOCK FREQUENCY, fSCLK, (MHZ)
SAMPLING
FREQUENCY (fS)
128fS
192fS
256fS
384fS
512fS
768fS
16kHz
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192kHz
—
—
—
—
—
12.2880
24.5792
24.5760
—
—
—
—
—
18.4320
33.8688
36.8640
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
See Note 2
See Note 2
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
See Note 2
See Note 2
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
See Note 2
See Note 2
12.2880
24.5760
33.8688
36.8640
See Note 1
See Note 1
See Note 2
See Note 2
NOTES: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock rate is not supported for the given sampling frequencies.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
tSCLK
2.0V
“H”
SCLK
0.8V
“L”
fSCLK
tSCLK
System Clock Pulse Width High tSCLKH
System Clock Pulse Width Low tSCLKL
FIGURE 1. System Clock Input Timing.
®
PCM1739
8
: 7ns min
: 7ns min
2.4V
VCC = VDD
2.0V
1.6V
Reset
Reset Removal
Internal Reset
1024 system clocks
System Clock
(SCLK)
FIGURE 2. Power-On Reset Timing.
RSTB
tRST(1)
Reset
Reset Removal
Internal Reset
1024 system clocks
System Clock
(SCLK)
NOTE: (1) tRST = 20ns min.
FIGURE 3. External Reset Timing.
AUDIO SERIAL INTERFACE
MODE CONTROLS
The audio serial interface for the PCM1739 is comprised
of a 3-wire synchronous serial port. It includes LRCK (pin
1), BCLK (pin 3), and DATA (pin 2). BCLK is the serial
audio bit clock, and is used to clock the serial data present
on DATA into the audio interface’s serial shift registers.
Serial data is clocked into the PCM1739 on the rising edge
of BCLK. LRCK is the serial audio left/right word clock.
It is used to latch serial data into the serial audio interface’s
internal registers.
This section describes the mode control pins used to configure
the operating mode of the PCM1739.
AUDIO DATA FORMAT
The data format used by the audio serial interface is selected
using the FORM input (pin 28). The formats available
include Standard and I2S. Table II shows the FORM pin
configuration.
Both LRCK and BCLK must be synchronous to the system
clock. Ideally, it is recommended that LRCK and BCLK
be derived from the system clock input or output, SCLK or
CLKO. The left/right clock, LRCK, is operated at the
sampling frequency (fS). The bit clock, BCK, may be
operated at 48 or 64 times the sampling frequency.
FORM
DATA FORMAT
L
H
Standard
I2S
TABLE II. Audio Data Format Selection.
AUDIO DATA WORD LENGTH
The data word length used by the audio serial interface is
selected using the IBIT input (pin 9). The word length may
be either 24 or 16 bits. Table III shows the IBIT pin
configuration.
AUDIO DATA FORMATS AND TIMING
The PCM1739 supports industry-standard audio data formats, including Standard and I2S. The audio data word
length may be either 24 or 16 bits. Data format and word
length are selected using the FORM and IBIT pins, as
described in the Mode Controls section of this data sheet.
All formats require Binary Two’s Complement, MSB-first
audio data. The data formats are shown in Figure 4, while
Figure 5 shows a detailed timing diagram for the serial
audio interface.
IBIT
DATA WORD LENGTH
L
H
24 Bits
16 Bits
TABLE III. Audio Data Word Length Selection.
®
9
PCM1739
FIGURE 4. Audio Data Input Formats.
®
PCM1739
10
22 23 24
24-Bit Right-Justified
DATA
MSB
1
2
3
4
5
DATA
BCLK
(= 48fS or 64fS)
LRCK
MSB
1
2
3
Lch
22
MSB
1
LSB
23 24
Lch
(2) 16- or 24-Bit I2S Data Format; Lch = LOW, Rch = HIGH
14 15 16
16-Bit Right-Justified
DATA
BCLK
(= 48fS or 64fS)
LRCK
(1) Standard Data Format; Lch = HIGH, Rch = LOW
2
3
1/fS
MSB
1
2
3
LSB
22 23 24
LSB
14 15 16
MSB
1
1/fS
Rch
2
3
22
4
LSB
23 24
5
Rch
MSB
1
1
2
2
3
LSB
22 23 24
LSB
14 15 16
LRCK
50% of VDD
tBCH
tBCL
tLB
BCLK
50% of VDD
tBCY
tBL
50% of VDD
DATA
tDS
SYMBOL
tDH
PARAMETER
MIN
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
BCK Rising Edge to LRCK Edge
LRCK Falling Edge to BCK Rising Edge
DIN Set Up Time
DIN Hold Time
tBCY
tBCH
tBCL
tBL
tLB
tDS
tDH
MAX
48 or 64fS
35
35
10
10
10
10
UNITS
(1)
ns
ns
ns
ns
ns
ns
NOTE: (1) fS is the sampling frequency.
FIGURE 5. Audio Interface Timing.
4x/8x DIGITAL INTERPOLATION
sis function is required for proper playback of early audio
compact disks (CDs), which were mastered with signal
emphasis for higher frequencies in the audio band. This was
done to improve the poor high frequency performance of
early CD players. Plots of the de-emphasis filter and error
functions for 32kHz, 44.1kHz, and 48kHz are shown in the
Typical Performance Curves section of this data sheet.
The PCM1739’s digital filter may be configured for either
4x or 8x oversampling. The 8x oversampling setting is
utilized for sampling frequencies up to 96kHz, while 4x
oversampling is utilized for 192kHz operation. The FILT
input (pin 20) is used to select the oversampling rate of the
digital filter. Table IV shows the FILT pin configuration.
FILT
OVERSAMPLING RATE
L
H
8x
4x ( Required for 192kHz operation)
The DEM0 (pin 26) and DEM1 (pin 27) inputs of the
PCM1739 are used to enable and disable the digital deemphasis function. Table VI shows the DEM0 and DEM1
pin configurations.
TABLE IV. Digital Filter Oversampling Rate Selection.
SOFT MUTE
The Soft Mute function provides for quiet muting of the
DAC outputs, VOUTL (pin 16) and VOUTR (pin 13). This is
done by ramping an internal digital attenuator from unity
gain to digital mute (all 0’s input to the digital filter). The
MUTE input (pin 21) is used to enable and disable the Soft
Mute function. Table V shows the MUTE pin configuration.
MUTE
SOFT MUTE STATUS
L
H
Disabled
Enabled
DEM1
DEM0
DE-EMPHASIS FUNCTION
L
L
H
H
L
H
L
H
OFF
32kHz De-Emphasis Filter
44.1kHz De-Emphasis Filter
48kHz De-Emphasis Filter
TABLE VI. Digital De-Emphasis.
ANALOG OUTPUTS
The PCM1739 includes two independent output channels;
VOUTL (pin 16) and VOUTR (pin 13). These are unbalanced
outputs, each capable of driving 3.1Vp-p typical into a 5kΩ,
AC-coupled load (VCC = +5V). The internal output amplifiers for VOUTL and VOUTR are DC biased to a DC commonmode (or bipolar zero) voltage, equal to VCC/2.
TABLE V. Soft Mute Selection.
DIGITAL DE-EMPHASIS
The PCM1739 provides a De-emphasis function for sampling rates equal to 32kHz, 44.1kHz or 48kHz. It is incorporated into the digital filter of the PCM1739. The De-empha-
The output amplifiers include an RC continuous time filter,
which helps to reduce the out-of-band noise energy present
at the DAC outputs due to the noise shaping characteristics
of the PCM1739’s delta-sigma D/A converters. The fre-
®
11
PCM1739
quency response of this filter is shown in Figure 6. By itself,
this filter is not enough to attenuate the out-of-band noise to
an acceptable level for most applications. An external lowpass filter is required to provide sufficient out-of-band noise
rejection. Further discussion of DAC post filter circuits is
provided in the Applications Information section of this data
sheet.
VCOML AND VCOMR OUTPUTS
Two unbuffered, DC common-mode voltage output pins,
VCOML (pin 17) and VCOMR (pin 12), are brought out for
decoupling purposes. These pins are normally biased to a
DC voltage level equal to VCC/2. These pins may be used to
bias external circuits, but they must be connected to high
impedance nodes. Figure 7 shows examples of the proper use
of the VCOML and VCOMR pins for external biasing applications.
20
ZERO FLAG OUTPUTS
Level (dB)
0
The PCM1739 includes circuitry for detecting an all zero
data condition for the data input pin, DATA. Zero detection
for each output channel is independent from the other. If the
data for a given channel remains at a ‘0’ level for 1024
sample periods (or LRCK clock periods), a Zero Detect
condition exists for the that channel. Given that a Zero
Detect condition exists, the Zero Flag pin(s) for the corresponding channel(s) will be set to a logic ‘1’ state. The zero
flag outputs include ZEROL (pin 23) and ZEROR (pin 24).
These pins can be used to operate external mute circuits, or
used as status indicators for audio signal processor,
microcontroller, or other digitally-controlled functions.
–20
–40
–60
–80
–100
1
10
100
1k
10k
100k
1M
10M
Log Frequency (Hz)
FIGURE 6. Output Filter Frequency Response.
PCM1739
VOUTx
R1
10µF
+
C1
R2
VCC
R3
1/2
OPA2353
C2
Filtered
Output
VCOMx
+
10µF
VCC
PCM1739
x = L or R
OPA337
VCOMx
(a) Using VCOM To Bias A Single-Supply Filter Stage
+
Buffered
VCOM
10µF
x = L or R
(b) Using a Voltage Follower to Buffer VCOM when Biasing Multiple Nodes
VCC
49.9kΩ
1%
PCM1739
VOUTx
–IN
+
Sense
25kΩ
INA134
+IN
VCOMx
x = L or R
25kΩ
V+
Out
To Low-Pass
Filter Stage
25kΩ
10µF
25kΩ
V–
Ref
(c) Using INA134 for DC-Coupled Output
FIGURE 7. Biasing External Circuits Using the VCOML and VCOMR Pins.
®
PCM1739
12
APPLICATIONS INFORMATION
Proper power supply bypassing is shown in Figure 8. The
bypass capacitors should be located as close as possible to
the PCM1739 package. The 1µF and 10µF capacitors should
be tantalum or aluminum electrolytic, while the 0.1µF capacitors are ceramic (X7R type is recommended for surface
mount applications).
CONNECTION DIAGRAM
A basic connection diagram with the necessary power supply bypassing and decoupling components is shown in
Figure 8. Burr-Brown recommends using the component
values shown in Figure 8 for all designs.
D/A OUTPUT CIRCUITS
The use of series resistors (22Ω to 100Ω) is recommended
for the SCLK, LRCK, BCLK, and DATA inputs. The series
resistor combines with the stray PCB and device input
capacitance to form a low-pass filter, which reduces high
frequency noise emissions and helps to dampen glitches and
ringing present on clock and data lines.
Delta-sigma D/A converters utilize noise-shaping techniques
to improve in-band Signal-to-Noise (SNR) performance at
the expense of generating increased out-of-band noise above
the Nyquist Frequency, or fS/2. The out-of-band noise must
be low-pass filtered in order to provide optimal converter
performance. This is accomplished by a combination of onchip and external low pass filtering.
POWER SUPPLIES AND GROUNDING
Figures 7a and 9 show the recommended external low pass
active filter circuits for dual and single-supply applications.
These circuits are 2nd-order filters using the Multiple Feedback (MFB) circuit arrangement, which reduces sensitivity to
passive component variations over frequency and temperature. For more information regarding MFB active filter design,
please refer to Burr-Brown Applications Bulletin AB-034.
The PCM1739 requires a +5V analog supply and a +3.3V
digital supply. The +5V supply is used to power the DAC
analog and output filter circuitry, while the +3.3V supply is
used to power the digital filter and logic circuitry. For best
performance, the +3.3V supply should be derived from the
+5V supply using a linear regulator, shown in Figure 8.
Burr-Brown’s REG1117-3.3 is an ideal choice for this application.
PCM1739
RS(1)
From/To
Audio
Source
+
C1
C2
From
Mode Control
Logic
+
+
LRCK
FORM
DATA
DEM1
BCLK
DEM0
CLKO
NC
SCLK
ZEROR
VSS
ZEROL
VDD
RSTB
TEST1
MUTE
IBIT
FILT
VCCR
VCCL
GNDR
GNDL
VCOMR
VCOML
VOUTR
VOUTL
GNDA
VCCA
C3
C4
From
Mode Control
Logic
Zero Flag
Outputs
From Host Or
Master Reset
From
Mode Control
Logic
+
+
C10
C9
+
C8
C5
+3.3V
Regulator
To
Output
Filter
Circuits
C6
+
+5V
Analog
C7
+
C1, C4, C6, C9 = 10µF Tantalum or Aluminum Electrolytic
C2, C5 = 0.1µF Ceramic
C3, C10 = 1µF Tanatlum or Aluminum Electrolytic
C7, C8 = 1-10µF Aluminum Electrolytic
NOTE: (1) RS = 20Ω to 100Ω.
FIGURE 8. Basic Connection Diagram.
®
13
PCM1739
Since the overall system performance is defined by the
quality of the D/A converters and their associated analog
output circuitry, high quality audio op amps are recommended for the active filters. Burr-Brown’s OPA2134 and
OPA2353 dual op amps are shown in Figures 7a and 9, and
are recommended for use with the PCM1739.
R2
R1
AV ≈ –
C1
R3
VIN
2
1
C2
3
PCB LAYOUT GUIDELINES
A typical PCB floor plan for the PCM1739 is shown in
Figure 10. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a
split or cut in the circuit board. The PCM1739 should be
oriented with the digital I/O pins facing the ground plane
split/cut, allowing for direct connection of the digital audio
interface and control signals originating from the digital
section of the board.
R2
R1
Separate power supplies are recommended for the digital
and analog sections of the board. This prevents the switching
noise present on the digital supply from contaminating the
analog power supply and degrading the dynamic performance of the PCM1739. In cases where a common +5V
supply must be used for the analog and digital sections, an
R4
OPA2134
VOUT
FIGURE 9. Dual Supply Filter Circuit.
Digital Power
+VD
Analog Power
DGND
AGND +5VA
+VS –VS
REG
VCC
VDD
Digital Logic
and
Audio
Processor
DGND
PCM1739
Output
Circuits
Digital
Ground
AGND
DIGITAL SECTION
Analog
Ground
ANALOG SECTION
Return Path for Digital Signals
FIGURE 10. Recommended PCB Layout.
Power Supplies
RF Choke or Ferrite Bead
AGND
+5V
+VS –VS
REG
VCC
VDD
VDD
DGND
Output
Circuits
PCM1739
AGND
Common
Ground
DIGITAL SECTION
ANALOG SECTION
FIGURE 11. Single-Supply PCB Layout.
®
PCM1739
14
inductance (RF choke, ferrite bead) should be placed between the analog and digital +5V supply connections to
avoid coupling of the digital switching noise into the analog
circuitry. Figure 11 shows the recommended approach for
single-supply applications
enhanced multi-level delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, with the simulated jitter sensitivity shown in
Figure 14.
KEY PERFORMANCE
PARAMETERS AND MEASUREMENT
THEORY OF OPERATION
The delta-sigma section of PCM1739 is based on a 8-level
amplitude quantizer and a 4th-order noise shaper. This
section converts the oversampled input data to 8-level deltasigma format.
This section provides information on how to measure key
dynamic performance parameters for the PCM1739. In all
cases, an Audio Precision System Two Cascade or equivalent audio measurement system is utilized to perform the
testing.
A block diagram of the 8-level delta-sigma modulator is
shown in Figure 12. This 8-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64fS for all system clock
combinations (128, 192, 256, 384, 512, 768fS).
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion + Noise (THD+N) is a significant figure of merit for audio D/A converters since it takes
into account both harmonic distortion and all noise sources
within a specified measurement bandwidth. The true rms
value of the distortion and noise is referred to as THD+N.
The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 13. The
–
+
4fS or 8fS
Z–1
+
Z–1
+
Z–1
+
Z–1
+
+
8-Level Quantizer
64fS
CLOCK JITTER
0
125
–20
120
–40
115
Dynamic Range (dB)
Amplitude (dB)
FIGURE 12. Eight-Level Delta-Sigma Modulator.
–60
–80
–100
–120
–140
110
105
100
95
90
–160
85
–180
0
1
2
3
4
5
6
7
80
8
0
Frequency (fS)
100
200
300
400
500
600
Jitter (ps)
FIGURE 13. Quantization Noise Spectrum.
FIGURE 14. Jitter Sensitivity.
®
15
PCM1739
signed to give a good indicator of how the DAC will perform
given a low-level input signal.
For the PCM1739, THD+N is measured with a full scale,
1kHz digital sine wave as the test stimulus at the input of
the DAC. The digital generator is set to 24-bit audio word
length and a sampling frequency of 44.1kHz, 96kHz, or
192kHz. The digital generator output is taken from the
unbalanced S/PDIF connector of the measurement system.
The S/PDIF data is transmitted via a coaxial cable to the
digital audio receiver on the DEM-DAI1739 demo board.
The receiver is then configured to output 24-bit data in
either I2S or left-justified data format. The DAC audio
interface format is programmed to match the receiver
output format. The analog output is then taken from the
DAC post filter and connected to the analog analyzer input
of the measurment system. The analog input is band limited using filters resident in the analyzer. The resulting
THD+N is measured by the analyzer and displayed by the
measurement system.
The measurement setup for the dynamic range measurement
is shown in Figure 15, and is similar to the THD+N test
setup discussed previously. The differences include the
bandlimit filter selection, the additional A-Weighting filter,
and the –60dBFS input level.
IDLE CHANNEL SIGNAL-TO-NOISE RATIO
The SNR test provides a measure of the noise floor of the
D/A converter. The input to the D/A is all 0’s data, and the
D/A converter’s Infinite Zero Detect Mute function must
be disabled (default condition at power up for the PCM1739).
This ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if
present) can be observed and effect the SNR measurement.
The dither function of the digital generator must also be
disabled to ensure an all ‘0’s data stream at the input of the
D/A converter.
DYNAMIC RANGE
Dynamic range is specified as A-Weighted, THD+N measured with a –60dBFS, 1kHz digital sine wave stimulus at
the input of the D/A converter. This measurement is de-
The measurement setup for SNR is identical to that used for
dynamic range, with the exception of the input signal level.
(see the notes provided in Figure 16).
Evaluation Board
DEM-DAI1739
S/PDIF
Receiver
2nd-Order
Low-Pass
Filter
PCM1739
f–3dB = 54kHz or 108kHz
Digital
Generator
Analyzer
and
Display
0dBFS,
1kHz Sine Wave
RMS Mode
S/PDIF
Output
20kHz
Apogee
Filter
Band Limit
HPF = 22Hz
LPF = 30kHz
Notch Filter
fC = 1kHz
FIGURE 15. Test Setup for THD+N Measurement.
Evaluation Board
DEM-DAI1739
S/PDIF
Receiver
PCM1739(1)
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz or 108kHz
S/PDIF
Output
NOTES: (1) Infinite Zero Detect Mute disabled.
(2) Results without A-Weighting will be
approximately 3dB worse.
Digital
Generator
0% Full Scale,
Dither Off (SNR) or
–60dBFS,
1kHz Sine Wave
(Dynamic Range)
Analyzer
and
Display
RMS Mode
FIGURE 16. Test Set-Up for Dynamic Range and SNR Measurements.
®
PCM1739
16
A-Weight
Filter(2)
Band Limit
HPF = 22Hz
LPF = 22kHz
Notch Filter
fC = 1kHz
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCM1739E
ACTIVE
SSOP
DB
28
47
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM1739E
Samples
PCM1739E/2K
ACTIVE
SSOP
DB
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM1739E
Samples
PCM1739E/2KG4
ACTIVE
SSOP
DB
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM1739E
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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