PCM1741
PCM
174
1
www.ti.com
+3.3V Single-Supply, 24-Bit, 96kHz Sampling
Enhanced Multilevel, Delta-Sigma, Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● 24-BIT RESOLUTION
● AV RECEIVERS
● ANALOG PERFORMANCE (VCC = +3.3V):
Dynamic Range: 98dB typ
SNR: 98dB typ
THD+N: 0.005% typ
Full-Scale Output: 2.05Vp-p typ
● DVD MOVIE PLAYERS
● DVD ADD-ON CARDS FOR HIGH-END PCs
● HDTV RECEIVERS
● CAR AUDIO SYSTEMS
● OTHER APPLICATIONS REQUIRING 24-BIT
AUDIO
● 8x OVERSAMPLING DIGITAL FILTER:
Stopband Attenuation: –55dB
Passband Ripple: ±0.03dB
DESCRIPTION
● SAMPLING FREQUENCY: 5kHz to 100kHz
● SYSTEM CLOCK: 256, 384, 512, 768fS with
Auto Detect
● ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO
DATA
● DATA FORMATS: Standard, I2S, and LeftJustified
● USER-PROGRAMMABLE MODE CONTROLS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
Soft Mute
Zero Flags for Each Output
The PCM1741 is a CMOS, monolithic, integrated circuit
which includes stereo Digital-to-Analog Converters
(DACs) and support circuitry in a small SSOP-16 package.
The data converters utilize Texas Instrument’s enhanced
multilevel delta-sigma architecture that employs fourthorder noise shaping and 8-level amplitude quantization to
achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1741 accepts industry standard
audio data formats with 16- to 24-bit data, providing easy
interfacing to audio DSP and decoder chips. Sampling rates
up to 100kHz are supported. A full set of user-programmable functions are accessible through a 3-wire serial
control port that supports register write functions.
● 3.3V SINGLE POWER SUPPLY
● 5V TOLERANT DIGITAL INPUTS
● SMALL SSOP-16 PACKAGE
Copyright © 2000, Texas Instruments Incorporated
SBAS175
Printed in U.S.A. December, 2000
SPECIFICATIONS
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, fS = 44.1kHz, system clock = 384fS, and 24-bit data, unless otherwise noted.
PCM1741E
PARAMETER
CONDITIONS
MIN
RESOLUTION
DYNAMIC PERFORMANCE(4)
PCM1741E
THD+N at VOUT = 0dB
THD+N at VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1, Sharp Roll-Off
Passband
Passband
Stopband
Passband Ripple
Stopband Attenuation
Stopband Attenuation
Filter Characteristics 2, Slow Roll-Off
Passband
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
De-Emphasis Error
2
MAX
24
DATA FORMAT
Audio Data Interface Formats
Audio Data Bit Length
Audio Data Format
Sampling Frequency (fS)
System Clock Frequency
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level
VIH
VIL
Input Logic Current
IIH(1)
IIL(1)
IIH(2)
IIL(2)
Output Logic Level
VOH(3)
VOL(3)
TYP
UNITS
Bits
Standard, I2S, Left-Justified
16-, 18-, 20-, 24-Bits Selectable
MSB-First, Binary Two’s Complement
5
100
256, 384, 512, 768fS
kHz
TTL-Compatible
2.0
VIN = VDD
VIN = 0V
VIN = VDD
VIN = 0V
IOH = –2mA
IOL = +2mA
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
fS = 44.1kHz
fS = 96kHz
VOUT = –90dB
65
92
92
90
Full Scale (0dB)
µA
µA
µA
µA
1.0
VDC
VDC
0.01
%
%
%
%
dB
dB
dB
dB
dB
dB
dB
±1.0
±1.0
±30
±6
±3
±60
% of FSR
% of FSR
mV
62% of VCC
50% of VCC
Vp-p
VDC
kΩ
5
0.454fS
0.487fS
0.546fS
±0.03
–50
–55
±0.5dB
–3dB
dB
dB
dB
0.198fS
0.390fS
0.884fS
Stopband = 0.884fS
10
–10
100
–10
0.005
0.007
1.6
2.0
98
96
98
96
96
94
±0.5
±0.03dB
–3dB
Stopband = 0.546fS
Stopband = 0.567fS
VDC
VDC
2.4
VOUT = 0.5 VCC at Bipolar Zero
AC Load
0.8
±0.5
–40
20/fS
±0.1
dB
dB
sec
dB
PCM1741
SBAS175
SPECIFICATIONS (Cont.)
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit data, unless otherwise noted.
PCM1741E
PARAMETER
CONDITIONS
ANALOG FILTER PERFORMANCE
Frequency Response
TYP
f = 20kHz
f = 44kHz
POWER SUPPLY REQUIREMENTS(4)
Voltage Range, VDD
VCC
Supply Current, IDD
+3.3
+3.0
6.0
13.0
7.0
7.0
43
66
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
Power Dissipation
MAX
–0.03
–0.20
+2.7
+2.7
ICC
TEMPERATURE RANGE
Operation Temperature
Thermal Resistance
MIN
–25
θJA
dB
dB
+3.6
+3.6
10
11
88
+85
SSOP-16
115
UNITS
VDC
VDC
mA
mA
mA
mA
mW
mW
°C
°C/W
NOTES: (1) Pins 1, 2, 3, 16 (SCK, BCK, LRCK, DATA). (2) Pins 13-15 (MD, MC, ML). (3) Pins 11, 12 (ZEROR, ZEROL). (4) Analog performance specifications
are tested with a Shibasoku #725 THD Meter with 400Hz HPF on, 30kHz LPF on, and an average mode with 20kHz bandwidth limiting. The load connected
to the analog output is 5kΩ or larger, via capacitive coupling.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage, VDD .............................................................. +4.0V
VCC .............................................................. +6.5V
Ground Voltage Differences .............................................................. ±0.1V
Digital Input Voltage ................................................ –0.3V to (6.5V + 0.3V)
Input Current (except power supply) ............................................... ±10mA
Ambient Temperature Under Bias .................................. –40°C to +125°C
Storage Temperature ...................................................... –55°C to +150°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM1741E
SSOP-16
322
–25°C to +85°C
PCM1741E
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PCM1741E
PCM1741E/2K
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1741E/2K” will yield a single 2000-piece Tape and Reel.
PCM1741
SBAS175
3
BLOCK DIAGRAM
BCK
Audio
Serial
Port
LRCK
8x
Oversampling
Digital Filter
with
Function
Controller
DATA
ML
VOUTL
Low-Pass Filter
Enhanced
Multilevel
Delta-Sigma
Modulator
VCOM
Serial
Control
Port
MC
Output Amp and
DAC
Output Amp and
DAC
Low-Pass Filter
VOUTR
MD
System Clock
VCC
AGND
PIN ASSIGNMENTS
TOP VIEW
SSOP
BCK
1
16
SCK
DATA
2
15
ML
LRCK
3
14
MC
4
VDD
ZEROR
ZEROL
PIN CONFIGURATION
DGND
Power Supply
Zero Detect
DGND
System Clock
Manager
SCK
13
MD
PCM1741
VDD
5
12
ZEROL/NA
VCC
6
11
ZEROR/ZEROA
VOUTL
7
10
VCOM
VOUTR
8
9
AGND
PIN
NAME
TYPE
1
BCK
IN
Audio Data Bit Clock Input.(1)
FUNCTION
2
DATA
IN
Audio Data Digital Input.(1)
3
LRCK
IN
L-Channel and R-Channel Audio Data Latch Enable Input.(1)
4
DGND
–
Digital Ground
5
VDD
–
Digital Power Supply, +3.3V
6
VCC
–
Analog Power Supply, +3.3V
7
VOUTL
OUT
Analog Output for L-Channel.
8
VOUTR
OUT
9
AGND
–
Analog Ground
–
Common Voltage Decoupling.
10
VCOM
11
ZEROR/
ZEROA
OUT
Analog Output for R-Channel.
Zero Flag Output for R-Channel/Zero Flag Output
for L/R-Channel.
12
ZEROL/NA
OUT
13
MD
IN
Mode Control Data Input.(2)
14
MC
IN
Mode Control Clock Input.(2)
15
ML
IN
Mode Control Latch Input.(2)
16
SCK
IN
System Clock Input.
Zero Flag Output for L-Channel/No Assign.
NOTES: (1) Schmitt-trigger input, 5V tolerant. (2) Schmitt-trigger with internal
pull-down, 5V tolerant.
4
PCM1741
SBAS175
TYPICAL PERFORMANCE CURVES
All specifications at TA = +25°C, VCC = VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off
FREQUENCY RESPONSE PASSBAND
(Sharp Roll-Off)
FREQUENCY RESPONSE (Sharp Roll-Off)
0
0.05
0.04
–20
0.03
0.02
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
0.01
0
–0.01
–0.02
–0.03
–120
–0.04
–0.05
–140
0
1
2
3
4
0
0.1
0.2
Frequency (x fS)
0.3
0.4
0.5
Frequency (x fS)
FREQUENCY RESPONSE (Slow Roll-Off)
TRANSITION CHARACTERISTICS (Slow Roll-Off)
0
5
4
–20
3
2
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
1
0
–1
–2
–3
–120
–4
–5
–140
0
1
2
3
0
4
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
De-Emphasis
DE-EMPHASIS ERROR (fS = 32kHz)
0.5
–1.0
0.4
–2.0
0.3
–3.0
0.2
–4.0
0.1
Error (dB)
Level (dB)
DE-EMPHASIS (fS = 32kHz)
0.0
–5.0
–6.0
0.0
–0.1
–7.0
–0.2
–8.0
–0.3
–9.0
–0.4
–0.5
–10.0
0
2
4
6
8
Frequency (kHz)
PCM1741
SBAS175
10
12
14
0
2
4
6
8
10
12
14
Frequency (kHz)
5
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25°C, VCC = VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
De-Emphasis (Cont.)
DE-EMPHASIS ERROR (fS = 44.1kHz)
0.5
–1.0
0.4
–2.0
0.3
–3.0
0.2
–4.0
0.1
Error (dB)
Level (dB)
DE-EMPHASIS (fS = 44.1kHz)
0.0
–5.0
–6.0
0.0
–0.1
–7.0
–0.2
–8.0
–0.3
–9.0
–0.4
–0.5
–10.0
0
2
4
6
8
10
12
14
16
18
0
20
2
4
6
DE-EMPHASIS (fS = 48kHz)
10
12
14
16
18
20
18
22
DE-EMPHASIS ERROR (fS = 48kHz)
0.0
0.5
–1.0
0.4
–2.0
0.3
–3.0
0.2
–4.0
0.1
Error (dB)
Level (dB)
8
Frequency (kHz)
Frequency (kHz)
–5.0
–6.0
0.0
–0.1
–7.0
–0.2
–8.0
–0.3
–9.0
–0.4
–10.0
–0.5
0
2
4
6
8
10
12
14
16
18
22
0
2
4
Frequency (kHz)
6
8
10
12
14
16
Frequency (kHz)
ANALOG DYNAMIC PERFORMANCE
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, and 24-bit input data, unless otherwise noted.
Supply-Voltage Characteristics
THD+N vs VCC
DYNAMIC RANGE vs VCC
106
10
–60dB/96kHz, 384fS
104
102
Dynamic Range (dB)
1
THD+N (%)
–60dB/44.1kHz, 384fS
0.1
0dB/96kHz, 384fS
0.01
2.4
2.7
3
3.3
VCC (V)
6
44.1kHz, 384fS
98
96
94
96kHz, 384fS
92
90
88
0dB/44.1kHz, 384fS
0.001
100
86
3.6
3.9
2.4
2.7
3
3.3
3.6
3.9
VCC (V)
PCM1741
SBAS175
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25°C, VCC = VDD = 3.3V, and 24-bit input data, unless otherwise noted.
Supply-Voltage Characteristics (Cont.)
SNR vs VCC
106
CHANNEL SEPARATION vs VCC
106
104
104
44.1kHz, 384fS
100
SNR (dB)
Channel Separation (dB)
102
98
96
94
96kHz, 384fS
92
90
102
100
98
44.1kHz, 384fS
96
94
92
96kHz, 384fS
90
88
88
86
86
2.4
2.7
3
3.3
3.6
3.9
4.2
2.4
2.7
3
VCC (V)
3.3
3.6
3.9
VCC (V)
Temperature Characteristics
THD+N vs TA
10
DYNAMIC RANGE vs TA
106
–60dB/96kHz, 384fS
104
102
Dynamic Range (dB)
THD+N (%)
1
–60dB/44.1kHz, 384fS
0.1
0dB/96kHz, 384fS
0.01
98
96
94
96kHz, 384fS
92
90
88
0dB/44.1kHz, 384fS
0.001
–50
44.1kHz, 384fS
100
86
–25
0
25
50
75
100
–50
–25
0
Temperature (°C)
SNR vs TA
106
50
75
100
75
100
CHANNEL SEPARATION vs TA
106
104
104
Channel Separation (dB)
102
44.1kHz, 384fS
100
SNR (dB)
25
Temperature (°C)
98
96
94
96kHz, 384fS
92
90
88
102
100
44.1kHz, 384fS
98
96
94
92
96kHz, 384fS
90
88
86
86
–50
–25
0
25
Temperature (°C)
PCM1741
SBAS175
50
75
100
–50
–25
0
25
50
Temperature (°C)
7
SYSTEM CLOCK AND RESET
FUNCTIONS
POWER-ON RESET FUNCTIONS
The PCM1741 includes a power-on reset function, as shown in
Figure 2. With the system clock active, and VDD > 2.0V (typical
1.6V to 2.4V), the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time VDD > 2.0V. After the initialization period, the PCM1741
will be set to its reset default state, as described in the Mode
Control Register section of this data sheet.
SYSTEM CLOCK INPUT
The PCM1741 requires a system clock for operating the
digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK input (pin 16).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multiclock generator from Texas Instruments is an excellent choice
for providing the PCM1741 system clock.
During the reset period (1024 system clocks), the analog
outputs are forced to the bipolar zero level, or VCC/2. After
the reset period, the internal register is initialized in the next
1/fS period and, if SCK, BCK, and LRCK are provided
continuously, the PCM1741 provides proper analog output
with unit group delay against the input data.
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING
FREQUENCY
256fS
8kHz
2.0480
3.0720
4.0960
6.1440
16kHz
4.0960
6.1440
8.1920
12.2880
24.5760
384fS
512fS
768fS
32kHz
8.1920
12.2880
16.3840
44.1kHz
11.2896
16.9344
22.5792
33.8688
48kHz
12.2880
18.4320
24.5760
36.8640
88.2kHz
22.5792
33.8688
45.1584
See Note (1)
96kHz
24.5760
36.8640
49.1520
See Note (1)
NOTE: (1) The 768fS system clock rate is not supported for fS > 64kHz.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
tSCKH
“H”
2.0V
“L”
0.8V
System Clock
tSCKL
System clock pulse
cycle time(1)
System Clock Pulse Width HIGH tSCKH: 7ns (min)
System Clock Pulse Width LOW tSCKL: 7ns (min)
NOTE: (1) 1/256fS, 1/384fS, 1/512fS, and 1/768fS.
FIGURE 1. System Clock Input Timing.
2.4V
VDD
2.0V
1.6V
0V
Reset
Reset Removal
Internal Reset
Don't Care
1024 System Clocks
System Clock
FIGURE 2. Power-On Reset Timing.
8
PCM1741
SBAS175
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1741 is comprised of
a 3-wire synchronous serial port. It includes LRCK (pin 3),
BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit
clock, and is used to clock the serial data present on DATA
into the audio interface’s serial shift register. Serial data is
clocked into the PCM1741 on the rising edge of BCK.
LRCK is the serial audio left/right word clock used to latch
serial data into the serial audio interface’s internal registers.
Both LRCK and BCK should be synchronous to the
system clock. Ideally, it is recommended that LRCK and
BCK be derived from the system clock input, SCK. LRCK
is operated at the sampling frequency, fS. BCK may be
operated at 32, 48, or 64 times the sampling frequency (I2S
format except BCK = 32fS). Internal operation of the
PCM1741 is synchronized with LRCK. Accordingly, it is
held when the sampling rate clock of LRCK is changed or
SCK and/or BCK is broken at least for one clock cycle. If
SCK, BCK, and LRCK are provided continuously after this
hold condition, the internal operation will be resynchronized
automatically, less than 3/fS period. In this resynchronize
period, and following 3/fS, analog output is forced to the
bipolar zero level, or VCC/2. External resetting is not required.
AUDIO DATA FORMATS AND TIMING
The PCM1741 supports industry-standard audio data formats,
including Standard, I2S, and Left-Justified, as shown in
Figure 3. Data formats are selected using the format bits,
FMT[2:0], in Control Register 20. The default data format is
24-bit left justified. All formats require Binary Two’s Complement, MSB-first audio data. See Figure 4 for a detailed timing
diagram of the serial audio interface.
(1) Standard Data Format: L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
R-Channel
L-Channel
BCK
(= 32, 48 or 64fS)
16-Bit Right-Justified, BCK = 48fS or 64fS
DATA
14 15 16
1
14 15 16
3
MSB
16-Bit Right-Justified, BCK = 32fS
DATA
2
1
2
3
14 15 16
1
LSB
14 15 16
MSB
3
14 15 16
MSB
1
LSB
2
2
3
LSB
14 15 16
MSB
LSB
18-Bit Right-Justified
DATA
16 17 18
1
2
3
MSB
16 17 18
1
LSB
2
17 18
MSB
LSB
20-Bit Right-Justified
DATA
18 19 20
1
2
3
18 19 20
MSB
24-Bit Right-Justified
DATA
22 23 24
1
2
1
LSB
3
22 23 24
MSB
3
18 19 20
MSB
1
LSB
2
2
LSB
3
22 23 24
MSB
LSB
(2) I2S Data Format: L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48 or 64fS)
DATA
1
2
N-2 N-1 N
3
MSB
1
LSB
(3) Left-Justified Data Format: L-Channel = HIGH, R-Channel = LOW
2
N-2 N-1 N
3
MSB
1
2
1
2
LSB
1/fS
L-Channel
LRCK
R-Channel
BCK
(= 32, 48 or 64fS)
DATA
1
2
3
MSB
N-2 N-1 N
LSB
1
MSB
2
3
N-2 N-1 N
LSB
FIGURE 3. Audio Data Input Formats.
PCM1741
SBAS175
9
LRCK
50% of VDD
tBCH
tBCL
tLB
BCK
50% of VDD
tBCY
tBL
50% of VDD
DATA
tDS
SYMBOL
tBCY
tBCH
tBCL
tBL
tLB
tDS
tDH
tDH
PARAMETER
MIN
MAX
UNITS
32, 48, or 64fS(1)
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
BCK Rising Edge to LRCK Edge
LRCK Falling Edge to BCK Rising Edge
DATA Set Up Time
DATA Hold Time
35
35
10
10
10
10
ns
ns
ns
ns
ns
ns
NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
FIGURE 4. Audio Interface Timing.
SERIAL CONTROL INTERFACE
The serial control interface is a 3-wire serial port that
operates asynchronously to the serial audio interface. The
serial control interface is utilized to program the on-chip
mode registers. The control interface includes MD (pin 13),
MC (pin 14), and ML (pin 15). MD is the serial data input,
used to program the mode registers, MC is the serial bit
clock, used to shift data into the control port, and ML is the
control port latch clock.
REGISTER WRITE OPERATION
All write operations for the serial control port use 16-bit data
words. Figure 5 shows the control data word format. The
most significant bit must be a “0”. There are seven bits,
labeled IDX[6:0], that set the register index (or address) for
the write operation. The least significant eight bits, D[7:0],
contain the data to be written to the register specified by
IDX[6:0].
Figure 6 shows the functional timing diagram for writing the
serial control port. ML is held at a logic “1 ” state until a
register needs to be written. To start the register write cycle,
ML is set to logic “0”. Sixteen clocks are then provided on
MC, corresponding to the 16 bits of the control data word on
MD. After the sixteenth clock cycle has completed, ML is set
to logic “1” to latch the data into the indexed mode control
register.
CONTROL INTERFACE TIMING REQUIREMENTS
See Figure 7 for a detailed timing diagram of the serial
control interface. These timing parameters are critical for
proper control port operation.
MSB
0
LSB
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
Register Index (or Address)
D5
D4
D3
D2
D1
D0
D1
D0
X
Register Data
FIGURE 5. Control Data Word Format for MDI.
ML
MC
MD
X
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7
D6
D5
D4
D3
D2
X
0
IDX6
FIGURE 6. Register Write Operation.
10
PCM1741
SBAS175
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1741 includes a number of user-programmable
functions that are accessed via control registers. The registers are programmed using the Serial Control Interface that
was previously discussed in the “Serial Control Interface”
section of this data sheet. Table II lists the available mode
control functions, along with their reset default conditions
and associated register index.
Register Map
The mode control register map is shown in Table III. Each
register includes an index (or address) indicated by the
IDX[6:0] bits.
tMHH
50% of VDD
ML
tMCH
tMLS
tMCL
tMLH
50% of VDD
MC
tMCY
LSB
MD
50% of VDD
tMDS
tMCH
SYMBOL
tMCY
tMCL
tMCH
tMHH
tMLS
tMLH
tMDH
tMDS
PARAMETER
MIN
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
ML Falling Edge to MC Rising Edge
ML Hold Time(1)
MD Hold Time
MD Set Up Time
100
50
50
Note (2)
20
20
15
20
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
3
NOTES: (1) MC rising edge for LSB to ML rising edge. (2) 256 • f sec (min), fS = Sampling Rate.
S
FIGURE 7. Control Interface Timing.
FUNCTION
Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps
Soft Mute Control
Oversampling Rate Control (64 or 128fS)
DAC Operation Control
De-Emphasis Function Control
De-Emphasis Sample Rate Selection
Audio Data Format Control
Digital Filter Roll-Off Control
Zero Flag Function Select
Output Phase Select
Zero Flag Polarity Select
RESET DEFAULT
CONTROL REGISTER
INDEX, IDX[6:0]
0dB, No Attenuation
Mute Disabled
64fS Oversampling
DAC1 and DAC2 Enabled
De-Emphasis Disabled
44.1kHz
24-Bit Left Justified
Sharp Roll-Off
L-/R-Channel Independent
Normal Phase
High
16 and 17
18
18
19
19
19
20
20
22
22
22
AT1[7:0], AT2[7:0]
MUT[2:0]
OVER
DAC[2:1]
DM12
DMF[1:0]
FMT[2:0]
FLT
AZRO
DREV
ZREV
TABLE II. User-Programmable Mode Controls.
IDX
(B8-B14) REGISTER
10H
11H
12H
13H
14H
15H
16H
16
17
18
19
20
21
22
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
0
0
0
0
0
0
0
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
AT17
AT27
RSV(1)
RSV(1)
RSV(1)
RSV(1)
RSV(1)
AT16
AT26
OVER
DMF1
RSV(1)
RSV(1)
RSV(1)
AT15
AT25
RSV(1)
DMF0
FLT
RSV(1)
RSV(1)
AT14
AT24
RSV(1)
DM12
RSV(1)
RSV(1)
RSV(1)
AT13
AT23
RSV(1)
RSV(1)
RSV(1)
RSV(1)
RSV(1)
B2
B1
B0
AT12 AT11 AT10
AT22 AT21 AT20
RSV(1) MUT2 MUT1
RSV(1) DAC2 DAC1
FMT2 FMT1 FMT0
RSV(1) RSV(1) RSV(1)
AZRO ZREV DREV
NOTE: (1) RSV = Reserved for test operation. It should be set to “0” when in regular operation.
TABLE III. Mode Control Register Map.
PCM1741
SBAS175
11
REGISTER DEFINITIONS
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
Register 17
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
ATx[7:0]
Digital Attenuation Level Setting
where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default Value: 1111 1111B
Each DAC channel (VOUTL and VOUTR) includes a digital attenuator function. The attenuation level may be
set from 0dB to –63dB, in 0.5dB steps. Changes in attentuator levels are made by incrementing or
decrementing, by one step (0.5dB), for every 8/fS time interval until the programmed attenuator setting is
reached. Alternatively, the attenuator level may be set to infinite attenuation (or mute). The attenuation data
for each channel can be set individually.
The attenuation level may be set using the formula below.
Attenuation Level (dB) = 0.5 (ATx[7:0]DEC – 255)
where: ATx[7:0]DEC = 0 through 255
for: ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.
ATx[7:0]
Decimal Value
Attenuator Level Setting
255
254
253
131
130
129
128
•
•
•
0
0dB, No Attenuation (default)
–0.5dB
–1.0dB
–62.0dB
–62.5dB
–63.0dB
Mute
•
•
•
Mute
1111
1111
1111
1000
1000
1000
1000
1111B
1110B
1101B
0011B
0010B
0001B
0000B
•
•
•
0000 0000B
Register 18
MUTx
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
OVER
RSV
RSV
RSV
RSV
B1
B0
MUT2 MUT1
Soft Mute Control
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default Value: 0
MUTx = 0
MUTx = 1
Mute Disabled (default)
Mute Enabled
The mute bits, MUT1 and MUT2, are used to enable or disable the Soft Mute function for the corresponding
DAC outputs, VOUTL and VOUTR. The Soft Mute function is incorporated into the digital attenuators. When
Mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute is enabled by setting
MUTx = 1, the digital attenuator for the corresponding output will be decreased from the current setting to
the infinite attenuation setting, one attenuator step (0.5dB) at a time. This provides a “pop”-free muting of the
DAC output. By setting MUTx = 0, the attenuator will be increased one step at a time to a previously
programmed attenuation level.
OVER
Oversampling Rate Control
Default Value: 0
OVER = 0
OVER = 1
64x Oversampling (default)
128x Oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs.
12
PCM1741
SBAS175
REGISTER 19
DACx
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
DMF1
DMF0
DM12
RSV
RSV
B1
B0
DAC2 DAC1
DAC Operation Control
where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).
Default Value: 0
DACx = 0
DACx = 1
DAC Operation Enabled (default)
DAC Operation Disabled
The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. When
DACx = 0, the corresponding output will generate the audio waveform dictated by the data present on the
DATA pin. When DACx = 1, the corresponding output will be set to the bipolar zero level, or VCC/2.
DM12
Digital De-Emphasis Function Control
Default Value: 0
DM12 = 0
DM12 = 1
De-Emphasis Disabled (default)
De-Emphasis Enabled
The DM12 bit is used to enable or disable the Digital De-Emphasis function. Refer to the Typical Performance
Curves of this data sheet for more information.
DMF[1:0]
Sampling Frequency Selection for the De-Emphasis Function
Default Value: 00
DMF[1:0]
00
01
10
11
De-Emphasis Same Rate Selection
44.1kHz (default)
48kHz
32kHz
Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when
it is enabled.
REGISTER 20
FMT[2:0]
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
FLT
RSV
RSV
FMT2
FMT1
FMT0
Audio Interface Data Format
Default Value: 101
The FMT[2:0] bits are used to select the data format for the serial audio interface. The following table shows
the available format options.
FMT[2:0]
000
001
010
011
100
101
110
111
PCM1741
SBAS175
Audio Data Format Selection
24-Bit Standard Format, Right-Justified Data
20-Bit Standard Format, Right-Justified Data
18-Bit Standard Format, Right-Justified Data
16-Bit Standard Format, Right-Justified Data
I2S Format, 16- to 24-bits
Left-Justified Format, 16- to 24-Bits (default)
Reserved
Reserved
13
Register 20 (Cont.)
FLT
Digital Filter Roll-Off Control
Default Value: 0
FLT = 0
FLT = 1
Sharp Roll-Off (default)
Slow Roll-Off
The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Two
filter roll-off sections are available: Sharp or Slow. The filter responses for these selections are shown in
the Typical Performance Curves section of this data sheet.
REGISTER 22
DREV
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
RSV
RSV
AZRO
B1
B0
ZREV DREV
Output Phase Select
Default Value: 0
DREV = 0
DREV = 1
Normal Output (default)
Inverted Output
The DREV bit is used to set the output phase of VOUTL and VOUTR.
ZREV
Zero Flag Polarity Select
Default Value: 0
ZREV = 0
ZREV = 1
Zero Flag Pins HIGH at a Zero Detect (default)
Zero Flag Pins LOW at a Zero Detect
The ZREV bit allows the user to select the active polarity of Zero Flag pins.
AZRO
Zero Flag Function Select
Default Value: 0
AZRO = 0
AZRO = 1
L-/R-Channel Independent Zero Flag (default)
L-/R-Channel Common Zero Flag
Register22 (Cont.)
The AZRO bit allows the user to select the function of Zero Flag pins.
AZRO = 0:
Pin11: ZEROR; Zero Flag Output for R-Channel
Pin12: ZEROL; Zero Flag Output for L-Channel
AZRO = 1:
Pin11: ZEROA; Zero Flag Output for L-/R-Channel
Pin12: NA; No Assign
14
PCM1741
SBAS175
ANALOG OUTPUTS
ANALOG FILTER PERFORMANCE
(100Hz-10MHz)
The PCM1741 includes two independent output channels:
VOUTL and VOUTR. These are unbalanced outputs, each capable
of driving 2.05Vp-p typical into a 5kΩ AC-coupled load. The
internal output amplifiers for VOUTL and VOUTR are biased to the
DC common-mode (or bipolar zero) voltage, equal to VCC/2.
The output amplifiers include an RC continuous-time filter that
helps to reduce the out-of-band noise energy present at the
DAC outputs, due to the noise shaping characteristics of the
PCM1741’s delta-sigma DACs. The frequency response of this
filter is shown in Figure 8. By itself, this filter is not enough to
attenuate the out-of-band noise to an acceptable level for many
applications, therefore, an external low-pass filter is required to
provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Applications
Information section of this data sheet.
VCOM OUTPUT
0
Response (dB)
–10
–50
–60
0.1
VOUTx
R1
1
10
100
1K
10K
Frequency (kHz)
FIGURE 8. Output Filter Frequency Response.
nominally biased to a DC voltage level equal to VCC/2. This
pin may be used to bias external circuits. Figure 9 shows an
example of using the VCOM pin for external biasing applications.
R2
10µF
–30
–40
One unbuffered common-mode voltage output pin, VCOM
(pin 10), is brought out for decoupling purposes. This pin is
PCM1741
–20
AV = –1, where AV = –
C1
R3
VCC
R1
2
+
C2
R2
3
1/2
OPA2342
1
Filtered
Output
VCOM
+
x = L or R
10µF
(a) Using VCOM to Bias a Single-Supply Filter Stage
VCC
PCM1741
OPA342
VCOM
+
Buffered
VCOM
10µF
(b) Using a Voltage Follower to Buffer VCOM when Biasing Multiple Nodes
FIGURE 9. Biasing External Circuits Using the VCOM Pin.
PCM1741
SBAS175
15
ZERO FLAGS
Zero Detect Condition
Zero Detection for each output channel is independent from
the other. If the data for a given channel remains at a “0”
level for 1024 sample periods (or LRCK clock periods), a
Zero Detect condition exists for that channel.
Zero Output Flags
Given that a Zero Detect condition exists for one or more
channels, the Zero Flag pins for those channels will be set to
a logic “1” state. There are Zero Flag pins for each channel:
ZEROL (pin 12) and ZEROR (pin 11). These pins can be used
to operate external mute circuits, or used as status indicators
for a microcontroller, audio signal processor, or other digitally
controlled functions.
The active polarity of Zero Flag output can be inverted by
setting the ZREV bit of Control Register 22 to “1”. The reset
default is active high output, or ZREV = 0.
POWER SUPPLIES AND GROUNDING
The PCM1741 requires a +3.3V analog supply (VCC) and a
+3.3V digital supply (VDD). The +3.3V supply (VCC) is used to
power the DAC analog and output filter circuitry, while the
+3.3V (VDD) supply is used to power the digital filter and serial
interface circuitry. For best performance, the +3.3V (VDD)
supply should be derived from the +3.3V (VCC) supply using a
linear regulator, as shown in Figure 11.
Proper power-supply bypassing is shown in Figure 10. The
10µF capacitors should be tantalum or aluminum electrolytic,
while the 0.1µF capacitors are ceramic (X7R type is recommended for surface-mount applications).
AV ≈ –
C1
R2
R1
R3
2
VIN
1
The L-channel and R-channel common Zero Flag can be
selected by setting the AZRO bit of Control Register 22 to “1”.
The reset default is L-channel and R-channel independent
Zero Flag, or AZRO = 0.
3
C2
OPA2134
R2
R1
R4
VOUT
FIGURE 10. Dual-Supply Filter Circuit.
APPLICATIONS INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram is shown in Figure 11, with the
necessary power-supply bypassing and decoupling components. Texas Instruments recommends using the component
values shown in Figure 11 for all designs.
The use of series resistors (22Ω to 100Ω) are recommended
for the SCK, LRCK, BCK, and DATA inputs. The series
resistor combines with stray PCB and device input capacitance to form a low-pass filter that reduces high-frequency
noise emissions and helps to dampen glitches and ringing
present on clock and data lines.
PCM
Audio Data
Input
BCK
2
DATA
ML 15
3
LRCK
MC 14
4
DGND
5
VDD
ZEROL/NA 12
6
VCC
ZEROR/ZEROA 11
7
VOUTL
8
VOUTR
System Clock
SCK 16
Mode
Control
MD 13
10µF
+3.3V
Regulator
+
1
10µF
Zero Mute
Control
VCOM 10
+
+
DAC OUTPUT FILTER CIRCUITS
Delta-sigma DACs utilize noise-shaping techniques to improve in-band Signal-to-Noise Ratio (SNR) performance at
the expense of generating increased out-of-band noise above
the Nyquist Frequency, or fS/2. The out-of-band noise must
be low-pass filtered in order to provide the optimal converter
performance. This is accomplished by a combination of
on-chip and external low-pass filtering.
Figures 9(a) and 10 show the recommended external lowpass active filter circuits for single- and dual-supply applications. These circuits are second-order Butterworth filters
10µF
AGND
9
+3.3V
Post LPF
Post LPF
L-Chan OUT
R-Chan OUT
FIGURE 11. Basic Connection Diagram.
16
PCM1741
SBAS175
using a Multiple FeedBack (MFB) circuit arrangement that
reduces sensitivity to passive component variations over
frequency and temperature. For more information regarding
MFB active filter design, please refer to Burr-Brown Applications Bulletin #34 AB-034 (SBFA001), available from our
web site at http://www.ti.com.
Since the overall system performance is defined by the
quality of the DACs and their associated analog output
circuitry, high-quality audio op amps are recommended for
the active filters. The OPA2353 and OPA2134 dual op amps
from Texas Instruments are recommended for use with the
PCM1741, see Figures 9(a) and 10.
Digital Power
+VD
DGND
PCB LAYOUT GUIDELINES
A typical PCB floor plan for the PCM1741 is shown in
Figure 12. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a
split or cut in the circuit board. The PCM1741 should be
oriented with the digital I/O pins facing the ground plane
split/cut to allow for short, direct connections to the digital
audio interface and control signals originating from the
digital section of the board.
Analog Power
AGND +3.3V
+VS –VS
REG
VCC
Digital Logic
and
Audio
Processor
VDD
DGND
PCM1741
Output
Circuits
Digital
Ground
AGND
DIGITAL SECTION
ANALOG SECTION
Analog
Ground
Return Path for Digital Signals
FIGURE 12. Recommended PCB Layout.
PCM1741
SBAS175
17
THEORY OF OPERATION
Separate power supplies are recommended for the digital
and analog sections of the board. This prevents the switching
noise present on the digital supply from contaminating the
analog power supply and degrading the dynamic performance of the PCM1741. In cases where a common +3.3V
supply must be used for the analog and digital sections, an
inductance (RF choke, ferrite bead) should be placed between the analog and digital +3.3V supply connections to
avoid coupling of the digital switching noise into the analog
circuitry. Figure 13 shows the recommended approach for
single-supply applications.
The delta-sigma section of the PCM1741 is based on an
8-level amplitude quantizer and a fourth-order noise shaper. This
section converts the oversampled input data to 8-level delta-sigma
format. A block diagram of the 8-level delta-sigma modulator is
shown in Figure 14. This 8-level delta-sigma modulator has the
advantage of stability and clock jitter sensitivity over the typical
one-bit (2-level) delta-sigma modulator. The combined
oversampling rate of the delta-sigma modulator and the interpolation filter is 64fS.
Power Supplies
RF Choke or Ferrite Bead
+3.3V
AGND
+VS –VS
REG
VCC
VDD
VDD
Output
Circuits
DGND
PCM1741
AGND
Common
Ground
DIGITAL SECTION
ANALOG SECTION
FIGURE 13. Single-Supply PCB Layout.
–
+
8fS
+
Z–1
+
Z–1
Z–1
+
+
Z–1
+
8-Level Quantizer
64fS
FIGURE 14. 8-Level Delta-Sigma Modulator.
18
PCM1741
SBAS175
QUANTIZATION NOISE SPECTRUM
(128x Oversampling)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
QUANTIZATION NOISE SPECTRUM
(64x Oversampling)
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
–180
0
1
2
3
4
5
6
7
8
0
1
Frequency (fS)
2
3
4
5
6
7
8
Frequency (fS)
FIGURE 15. Quantization Noise Spectrum.
The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 15. The enhanced multilevel delta-sigma architecture also has advantages
for input clock jitter sensitivity due to the multilevel quantizer,
with the simulated jitter sensitivity, as shown in Figure 16.
JITTER DEPENDENCE (64x Oversampling)
125
Dynamic Range (dB)
120
115
110
105
100
95
90
0
100
200
300
400
500
Jitter (ps)
600
KEY PERFORMANCE PARAMETERS
AND MEASUREMENT
This section provides information on how to measure key
dynamic performance parameters for the PCM1741. In all
cases, an Audio Precision System Two Cascade or equivalent
audio measurement system is utilized to perform the testing.
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion + Noise (THD+N) is a significant
figure of merit for audio DACs, since it takes into account
both harmonic distortion and all noise sources within a
specified measurement bandwidth. The true rms value of the
distortion and noise is referred to as THD+N. Figure 17
shows the test setup for THD+N measurements.
For the PCM1741, THD+N is measured with a full-scale,
1kHz digital sine wave as the test stimulus at the input of the
DAC. The digital generator is set to a 24-bit audio word
length and a sampling frequency of 44.1kHz or 96kHz. The
digital generator output is taken from the unbalanced
S/PDIF connector of the measurement system. The S/PDIF
FIGURE 16. Jitter Sensitivity.
Evaluation Board
DEM-DAI1741
S/PDIF
Receiver
PCM1741
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz or 108kHz
S/PDIF
Output
Digital
Generator
Analyzer
and
Display
0dBFS,
1kHz Sine Wave
rms Mode
20kHz
Apogee
Filter
Band Limit
HPF = 22Hz
LPF = 30kHz
Notch Filter
fC = 1kHz
FIGURE 17. Test Setup for THD+N Measurements.
PCM1741
SBAS175
19
data is transmitted via a coaxial cable to the digital audio
receiver on the DEM-DAI1741 demo board. The receiver is
then configured to output 24-bit data in either I2S or leftjustified data format. The DAC audio interface format is
programmed to match the receiver output format. The analog output is then taken from the DAC post filter and
connected to the analog analyzer input of the measurement
system. The analog input is band limited using filters resident in the analyzer. The resulting THD+N is measured by
the analyzer and displayed by the measurement system.
DYNAMIC RANGE
Dynamic range is specified as A-Weighted, THD+N measured with a –60dBFS, 1kHz digital sine wave stimulus at
the input of the DAC. This measurement is designed to give
a good indicator of how the DAC will perform given a lowlevel input signal.
The measurement setup for the dynamic range measurement
is shown in Figure 18, and is similar to the THD+N test
setup discussed previously. The differences include the band
limit filter selection, the additional A-Weighting filter, and
the –60dBFS input level.
IDLE CHANNEL SIGNAL-TO-NOISE RATIO
The SNR test provides a measure of the noise floor of the
DAC. The input to the DAC is all “0”s data, and the DAC’s
Infinite Zero Detect Mute function must be disabled (default
condition at power up for the PCM1741). This ensures that
the delta-sigma modulator output is connected to the output
amplifier circuit so that idle tones (if present) can be observed and effect the SNR measurement. The dither function
of the digital generator must also be disabled to ensure an all
“0”s data stream at the input of the DAC. The measurement
setup for SNR is identical to that used for dynamic range,
with the exception of the input signal level (see the notes
provided in Figure 18).
Evaluation Board
DEM-DAI1741
S/PDIF
Receiver
PCM1741(1)
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz
S/PDIF
Output
Digital
Generator
Analyzer
and
Display
0% Full-Scale,
Dither Off (SNR)
–60dBFS,
1kHz Sine Wave
(Dynamic Range)
rms Mode
A-Weight
Filter(1)
Band Limit
HPF = 22Hz
LPF = 22kHz
Option = A-Weighting(2)
Notch Filter
fC = 1kHz
NOTES: (1) Infinite Zero Detect Mute disabled.
(2) Results without A-Weighting will be approximately 3dB worse.
FIGURE 18. Test Setup for Dynamic Range and SNR Measurements.
20
PCM1741
SBAS175
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1741E
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM
1741E
PCM1741E/2K
ACTIVE
SSOP
DBQ
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM
1741E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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