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PCM1753, PCM1754, PCM1755
SLES092E – APRIL 2003 – REVISED JULY 2019
PCM175x 24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma, Audio,
Digital-to-Analog Converter
1 Features
3 Description
•
•
The PCM1753, PCM1754, and PCM1755 (PCM175x)
devices are stereo digital-to-analog converters
(DACs) based on TI's enhanced delta-sigma
architecture. This enhanced architecture employs 4thorder noise shaping and 8-level amplitude
quantization
to
achieve
excellent
dynamic
performance and improved clock jitter tolerance. The
PCM175x devices easily interface with audio DSP
and decoder chips because of the devices support of
industry-standard audio data formats with 16-bit and
24-bit data. The PCM175x devices can be controlled
in a hardware mode, or through a full set of userprogrammable functions that are accessible through a
three-wire serial control port that supports registerwrite functions.
1
•
•
•
•
•
•
24-bit resolution
Analog performance (VCC = 5 V)
– Dynamic range: 106 dB
– SNR: 106 dB, typical
– THD+N: 0.002%, typical
– Full-scale output: 4 VPP, typical
4× or 8× oversampling digital filter
– Stop-band attenuation: –50 dB
– Pass-band ripple: ±0.04 dB
Sampling frequency: 5 kHz to 200 kHz
System clock: 128 fS, 192 fS, 256 fS, 384 fS, 512
fS, 768 fS, 1152 fS with auto detect
Hardware control (PCM1754)
– I2S and 16-bit word, right-justified
– 44.1 kHz digital de-emphasis
– Soft mute
– Zero flag for L-, R-channel common output
Power supply: 5-V single supply
Small 16-lead SSOP package, lead-free
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
PCM1753
PCM1754
SSOP (16)
3.90 mm × 4.90 mm
PCM1755
(1) For all available packages, see the package option addendum
at the end of the data sheet.
2 Applications
•
•
•
•
The PCM1753 is pin compatible with the PCM1748,
PCM1742, and PCM1741, except for pin 5.
A/V receivers
HDTV receivers
Car audio systems
Applications requiring 24-bit audio
Functional Block Diagram
BCK
LRCK
DA TA
Audio
Serial
Port
FMT
MUTE
Serial
Control
Port
Output Amp
And
Low-Pass Filter
DAC
4x/8x
Oversampling
Digital Filter
and Function
Control
Enhanced
Multilevel
Delta-Sigma
Modulator
V COM
Output Amp
And
Low-Pass Filter
DAC
DEMP
V OUTL
V OUTR
TEST
System C lock
AGND
V CC
Power Supply
Zero Detect
DGND
System
Clock Manager
ZEROA
SCK
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM1753, PCM1754, PCM1755
SLES092E – APRIL 2003 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
4
4
5
6
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions......................
Thermal Information ..................................................
Electrical Characteristics...........................................
System Clock Input Timing .......................................
Audio Interface Timing ..............................................
Control Interface Timing Requirements ....................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 18
8.6 Register Maps ......................................................... 19
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Related Documentation .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2015) to Revision E
Page
•
Added text to pin 11 description to clarify operation for PCM1755 ........................................................................................ 3
•
Added text to pin 12 description to clarify operation for PCM1755 ....................................................................................... 3
•
Added new row for PCM1755 temperature range to Absolute Maximum Ratings table ....................................................... 4
•
Changed location of operating temperature from Electrical Characteristics table to Recommended Operating
Conditions table ...................................................................................................................................................................... 4
•
Changed operating temperature MAX value for PCM1753 and PCM1754 from 105°C to 85°C in the Recommended
Operating Conditions table ..................................................................................................................................................... 4
•
Added new row for PCM1755 temperature range to the Recommended Operating Conditions table ................................. 4
•
Changed output voltage value from MIN to TYP in the Electrical Characteristics table ....................................................... 6
•
Changed center voltage value from MIN to TYP in the Electrical Characteristics table ........................................................ 6
Changes from Revision C (February 2009) to Revision D
•
2
Page
Added ESD Ratings table, Recommended Operating Conditions table,Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
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SLES092E – APRIL 2003 – REVISED JULY 2019
5 Device Comparison Table
FEATURE
PCM1753, PCM1755
PCM1754
Audio data interface format
I2S, standard, left-justified
I2S, standard
Audio data bit length
16-bit, 18-bit, 20-bit, and 24-bit selectable
16-bit and 24-bit I2S, 16-bit standard
Audio data format
MSB first, 2's complement
6 Pin Configuration and Functions
PCM1753, PCM1755 DBQ Package
16-Pin SSOP
Top View
PCM1754 DBQ Package
16-Pin SSOP
Top View
BCK
1
16
SCK
DATA
2
15
LRCK
3
DGND
4
NC
BCK
1
16
SCK
ML
DATA
2
15
FMT
14
MC
LRCK
3
14
MUTE
13
MD
DGND
4
13
DEMP
5
12
ZEROL/NA
NC
5
12
TEST
VCC
6
11
ZEROR/ZEROA
VCC
6
11
ZEROA
VOUTL
7
10
VCOM
VOUTL
7
10
VCOM
AGND
VOUTR
8
9
AGND
VOUTR
9
8
Pin Functions
PIN
I/O
DESCRIPTION
NAME
PCM1753,
PCM1755
PCM1754
AGND
9
9
—
BCK
1
1
I
Audio-data bit-clock input
DATA
2
2
I
Audio-data digital input
DEMP
-
13
I
De-emphasis control
DGND
4
4
—
FMT
-
15
I
Data format select
LRCK
3
3
I
L-channel and R-channel audio data latch enable input
MC
14
-
I
Mode control clock input
MD
13
-
I
Mode control data input
ML
Analog ground
Digital ground
15
-
I
Mode control latch input
MUTE
-
14
I
Analog mixing control
NC
5
5
—
SCK
16
16
I
System clock input
TEST
-
12
I
Test pin, ground or open
VCC
6
6
—
Analog power supply, 5 V
VCOM
10
10
—
Common voltage decoupling
VOUTL
7
7
O
Analog output for L-channel
VOUTR
8
8
O
Analog output for R-channel
ZEROR/ZEROA
11
11
O
Zero flag output for R-channel / Zero flag output for L-/R-channel.
Open-drain output for PCM1755.
ZEROL/NA
12
-
O
Zero flag output for L-channel / Not assigned.
Open-drain output for PCM1755.
No connection
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage
VCC
Ground voltage differences
AGND, DGND
Input voltage
MIN
MAX
–0.3
6.5
V
±0.1
V
–0.3
Input current (any pins except supplies)
Ambient temperature under bias
V
±10
mA
–40
85
PCM1755
–25
85
Storage temperature, Tstg
(1)
6.5
PCM1753, PCM1754
Junction temperature
–55
UNIT
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
TA
Operating temperature
MIN
NOM
MAX
4.5
5
5.5
PCM1753, PCM1754
–40
85
PCM1755
–25
85
UNIT
V
°C
7.4 Thermal Information
PCM175x
THERMAL METRIC (1)
DBQ (SSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
104.1
°C/W
53
RθJB
°C/W
Junction-to-board thermal resistance
46.9
°C/W
ψJT
Junction-to-top characterization parameter
10.3
°C/W
ψJB
Junction-to-board characterization parameter
46.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLES092E – APRIL 2003 – REVISED JULY 2019
7.5 Electrical Characteristics
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
24
UNIT
Bits
DATA FORMAT
fS
Sampling frequency
5
200
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1152 fS
System clock frequency
kHz
kHz
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
VIH
Input logic level, high
2
VIL
Input logic level, low
0.8
VDC
VDC
IIH
Input logic current, high (SCK, BCK, DATA,
VIN = VCC
and LRCK pins)
10
µA
IIL
Input logic current, low (SCK, BCK, DATA,
and LRCK pins)
VIN = 0 V
-10
µA
IIH
Input logic current, high (TEST, DEMP,
MUTE, and FMT pins)
VIN = VCC
100
µA
IIL
Input logic current, low (TEST, DEMP,
MUTE, and FMT pins)
VIN = 0 V
-10
µA
VOH
Output logic level, high (ZEROA pin)
IOH = –1 mA
VOL
Output logic level, low (ZEROA pin)
IOL = 1 mA
65
2.4
VDC
0.4
VDC
DYNAMIC PERFORMANCE (1) (2)
THD+N at VOUT = 0 dB
THD+N at VOUT = -60 dB
fS = 44.1 kHz
0%
fS = 96 kHz
0%
fS = 192 kHz
0%
fS = 44.1 kHz
0.65%
fS = 96 kHz
0.80%
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Dynamic range
Signal-to-noise ratio
104
102
100
104
A-weighted, fS = 192 kHz
102
97
dB
106
A-weighted, fS = 96 kHz
fS = 96 kHz
Level linearity error
106
A-weighted, fS = 192 kHz
fS = 44.1 kHz
Channel separation
0.95%
100
A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 44.1 kHz
0.01%
dB
103
101
fS = 192 kHz
100
VOUT = -90 dB
±0.5
dB
dB
DC ACCURACY
Gain error
±1
±6
% of
FSR
Gain mismatch, channel-to-channel
±1
±3
% of
FSR
±30
±60
mV
Bipolar zero error
(1)
(2)
VOUT = 0.5 VCC at BPZ
Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in
the averaging mode.
Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18.
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Electrical Characteristics (continued)
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
Output voltage
Full scale (0 dB)
Center voltage
Load impedance
AC-coupled load
80% of
VCC
VPP
50% of
VCC
VDC
5
kΩ
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS (SHARP ROLLOFF)
Pass band
±0.04 dB
0.454 fS
Stop band
0.546 fs
Pass-band ripple
±0.04
Stop-band attenuation
Stop band = 0.546 fS
–50
dB
dB
ANALOG FILTER PERFORMANCE
Frequency response
At 20 kHz
–0.03
At 44 kHz
–0.2
dB
POWER SUPPLY REQUIREMENTS (2)
ICC
Supply current
fS = 44.1 kHz
16
fS = 96 kHz
25
fS = 192 kHz
30
fS = 44.1 kHz
Power dissipation
21
mA
80
fS = 96 kHz
125
fS = 192 kHz
150
105
mW
TEMPERATURE
RθJA
Thermal Resistance
16-pin DBQ
104.1
°C/W
7.6 System Clock Input Timing
for more information, see the System Clock Input section
MIN
t(SCKH)
System clock pulse duration, high
t(SCKL)
System clock pulse duration, low
t(SCY)
System clock pulse cycle time
(1)
NOM
MAX
7
See Figure 20.
UNIT
ns
7
ns
See
(1)
ns
1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS.
7.7 Audio Interface Timing
for more information, see the Audio Data Formats and Timing section
MIN
MAX
UNIT
1/(32 fS)
1/(48 fS)
1/(64 fS) (1)
t(BCY)
BCK pulse cycle time
t(BCH)
BCK high–level time
t(BCL)
BCK low–level time
t(BL)
BCK rising edge to LRCK edge
35
ns
35
ns
10
ns
t(LB)
LRCK falling edge to BCK rising
edge
10
ns
t(DS)
DATA setup time
10
ns
t(DH)
DATA hold time
10
ns
(1)
6
See Figure 22.
fS is the sampling frequency (for example, 44.1 kHz, 48 kHz, 96 kHz, and so on).
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7.8 Control Interface Timing Requirements
these timing parameters are critical for proper control port operation
MIN
NOM
MAX
UNIT
t(MCY)
MC pulse cycle time
100
ns
t(MCL)
MC low-level time
50
ns
t(MCH)
MC high-level time
50
ns
t(MCH)
ML high-level time
(1)
ns
t(MLS)
ML falling edge to MC rising edge
20
ns
t(MLH)
ML hold time (2)
20
ns
t(MDH)
MD hold time
15
ns
t(MCS)
MD setup time
20
ns
(1)
(2)
See
See Figure 1.
3
256 ´ fS
seconds (min); fS: sampling rate.
MC rising edge for LSB to ML rising edge.
t(MHH)
ML
t(MCL)
t(MLS)
t(MCH)
t(MLH)
MC
t(MCY)
LSB
MD
t(MDS)
t(MDH)
Figure 1. Control Interface Timing
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7.9 Typical Characteristics
7.9.1 Digital Filter (De-Emphasis Off)
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
0
0.05
0.04
–20
0.03
0.02
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
0.01
0.00
–0.01
–0.02
–100
–0.03
–120
–0.04
–140
0
1
2
3
–0.05
0.0
4
0.1
0.2
Frequency [× f S]
0.3
0.4
0.5
Frequency [× f S]
Figure 2. Frequency Response, Sharp Rolloff
Figure 3. Pass-Band Ripple, Sharp Rolloff
5
0
4
–20
3
2
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
1
0
–1
–2
–100
–3
–120
–4
–5
0.0
–140
0
1
2
3
4
0.1
0.2
0.4
0.5
Figure 5. Transition Characteristics, Slow Rolloff
0
0.5
–1
0.4
–2
0.3
–3
0.2
De-emphasis Error (dB)
De-emphasis Level (dB)
Figure 4. Frequency Response, Slow Rolloff
–4
–5
–6
–7
0.1
0.0
–0.1
–0.2
–8
–0.3
–9
–0.4
–10
–0.5
0
2
4
6
8
10
12
14
0
2
Frequency (kHz)
Figure 6. De-Emphasis Level vs Frequency
8
0.3
Frequency [× f S]
Frequency [ × f S]
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4
6
8
Frequency (kHz)
10
12
14
Figure 7. De-Emphasis Error vs Frequency
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Digital Filter (De-Emphasis Off) (continued)
0
0.5
–1
0.4
–2
0.3
–3
0.2
De-emphasis Error (dB)
De-emphasis Level (dB)
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
–4
–5
–6
–7
0.1
0.0
–0.1
–0.2
–8
–0.3
–9
–0.4
–10
–0.5
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
Frequency (kHz)
Figure 8. De-Emphasis Level vs Frequency
10
12
14
16
18
20
Figure 9. De-Emphasis Error vs Frequency
0
0.5
–1
0.4
–2
0.3
–3
0.2
De-emphasis Error (dB)
De-emphasis Level (dB)
8
Frequency (kHz)
–4
–5
–6
–7
0.1
0.0
–0.1
–0.2
–8
–0.3
–9
–0.4
–10
–0.5
0
2
4
6
8
10
12
14
16
18
20
22
0
2
4
Frequency (kHz)
Figure 10. De-Emphasis Level vs Frequency
6
8 10 12 14
Frequency (kHz)
16
18
20
22
Figure 11. De-Emphasis Error vs Frequency
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7.9.2 Analog Dynamic Performance (Supply Voltage Characteristics)
All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
110
10
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
–60 dB
106
Dynamic Range (dB)
Total Harmonic Distortion + Noise (%)
108
1
0.1
0.01
0 dB
0.001
0.0001
4.0
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
4.5
5.0
5.5
104
102
100
98
96
4.0
6.0
4.5
Supply Voltage (V)
Figure 12. Total Harmonic Distortion + Noise vs Supply
Voltage
106
104
102
100
98
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
108
Channel Separation (dB)
Signal-to-Noise Ratio (dB)
6.0
110
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
108
10
5.5
Figure 13. Dynamic Range vs Supply Voltage
110
96
4.0
5.0
Supply Voltage (V)
106
104
102
100
98
4.5
5.0
5.5
6.0
96
4.0
Supply Voltage (V)
5.0
Supply Voltage (V)
Figure 14. Signal-to-Noise Ratio vs Supply Voltage
Figure 15. Channel Separation vs Supply Voltage
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4.5
5.5
6.0
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7.9.3 Analog Dynamic Performance (Temperature Characteristics)
All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
110
108
–60 dB
106
0.1
0.01
0 dB
0.001
0.0001
–50
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
–25
0
25
50
Free-Air Temperature (°C)
75
102
100
96
–50
–25
0
25
50
Free-Air Temperature (°C)
75
100
Figure 17. Dynamic Range vs Free-Air Temperature
110
110
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
108
104
102
100
98
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
108
Channel Separation (dB)
106
96
–50
104
98
100
Figure 16. Total Harmonic Distortion + Noise vs Free-Air
Temperature
Signal-to-Noise Ratio (dB)
44.1 kHz, 384 f S
96 kHz, 384 f S
192 kHz, 128 f S
1
Dynamic Range (dB)
Total Harmonic Distortion + Noise (%)
10
106
104
102
100
98
–25
0
25
50
Free-Air Temperature (°C)
75
100
Figure 18. Signal-to-Noise Ratio vs Free-Air Temperature
96
–50
–25
0
25
50
Free-Air Temperature (°C)
75
100
Figure 19. Channel Separation vs Free-Air Temperature
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8 Detailed Description
8.1 Overview
The PCM175x devices are stereo digital-to-analog converters (DACs) based on TI's enhanced delta-sigma
architecture which employ 4th-order noise shaping and 8-level amplitude quantization to achieve excellent
dynamic performance and improved clock jitter tolerance. The PCM175x devices easily interface with audio DSP
and decoder chips because of the devices' support of industry-standard audio data formats with 16- and 24-bit
data. The PCM175x devices can be controlled in a hardware mode, or a full set of user-programmable functions
is accessible through a three-wire serial control port, which supports register-write functions.
8.2 Functional Block Diagram
BCK
LRCK
DATA
Audio
Serial
Port
4x/8x
Oversampling
Digital
Filter
and
Function
Control
FMT
MUTE
Serial
Control
Port
Enhanced
Multilevel
Delta-Sigma
Modulator
TEST
VOUTL
VCOM
Output Amp
and
Low-Pass Filter
DAC
DEMP
VOUTR
System Clock
Zero Detect
AGND
VCC
Power Supply
DGND
System
Clock
Manager
ZEROA
SCK
Output Amp
and
Low-Pass Filter
DAC
8.3 Feature Description
8.3.1 System Clock and Reset Functions
8.3.1.1 System Clock Input
The PCM175x devices require a system clock for operating the digital interpolation filters and multilevel deltasigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 lists examples of system clock
frequencies for common audio sampling rates.
Figure 20 shows and the System Clock Input Timing table lists he timing requirements for the system clock input.
For optimal performance, use a clock source with low phase-jitter and noise. TI's PLL170x family of multiclock
generators is an excellent choice for providing the PCM175x system clock.
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Feature Description (continued)
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING
FREQUENCY
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1152 fS
8 kHz
1.024
1.536
2.048
3.072
4.096
6.144
9.216
16 kHz
2.048
3.072
4.096
6.144
8.192
12.288
18.432
32 kHz
4.096
6.144
8.192
12.288
16.384
24.576
36.864
44.1 kHz
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
(1)
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
(1)
88.2 kHz
(1)
11.2896
16.9344
96 kHz
12.288
18.432
192 kHz
24.576
36.864
22.5792
24.576
33.8688
36.864
(1)
45.1584
(1)
(1)
49.152
(1)
(1)
(1)
(1)
(1)
(1)
This system clock rate is not supported for the given sampling frequency.
t(SCKH)
H
2.0 V
System Clock (SCK)
0.8 V
L
t(SCKL)
t(SCY)
Figure 20. System Clock Input Timing
8.3.1.2 Power-On Reset Functions
The PCM175x devices include a power-on reset function. Figure 21 shows the operation of this function. With the
system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The
initialization sequence requires 1024 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V).
During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or VCC/2. After
the reset period, an internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK are provided
continuously, the PCM175x devices provide proper analog output with unit group delay against the input data.
VCC
3.7 V (Max)
3.0 V (Typ)
2.2 V (Min)
Reset
Reset Removal
Internal Reset
Don’t Care
1024 System Clocks
System Clock
Figure 21. Power-On Reset Timing
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8.3.2 Audio Serial Interface
The audio serial interface for the PCM175x devices consists of a 3-wire synchronous serial port. The interface
includes LRCK (pin 3), BCK (pin 1), and DATA (pin 2). The BCK pin is the serial audio bit clock, and it is used to
clock the serial data present on the DATA pin into the serial shift register of the audio interface. Serial data is
clocked into the PCM175x on the rising edge of the BCK pin. The LRCK pin is the serial audio left and right word
clock. This pin is used to latch serial data into the internal registers of the serial audio interface.
Both the LRCK and BCK pins should be synchronous to the system clock. Ideally, TI recommendeds that the
LRCK and BCK pins be derived from the system clock input, SCK. The LRCK pin is operated at the sampling
frequency, fS. The BCK pin can be operated at 32, 48, or 64 times the sampling frequency for standard (rightjustified) format, and 32 times the sampling frequency of the BCK pin is limited to 16-bit right-justified format only.
The BCK pin can be operated at 48 or 64 times the sampling frequency for the I2S and left-justified formats. 48
times the sampling frequency of BCK is limited to 192/384/768 fS SCKI.
Internal operation of the PCM175x devices is synchronized with the LRCK pin. Accordingly, internal operation is
held when the sampling rate clock of the LRCK pin is changed or when the SCK pin and/or BCK pin is
interrupted for a 3-bit clock cycle or longer. If th SCK, BCK, and LRCK pins are provided continuously after this
held condition, the internal operation is re-synchronized automatically in a period of less than 3/fS. External
resetting is not required.
8.3.2.1 Audio Data Formats and Timing
The PCM1753 device supports industry-standard audio data formats, including right-justified, I2S, and leftjustified. The PCM1754 device supports I2S and 16-bit-word right-justified audio data formats. Figure 23 shows
the data formats. Data formats are selected using the format bits, FMT[2:0], located in control register 20 of the
PCM1753 device, and are selected using the FMT pin on the PCM1754 device. The default data format is 24-bit
left-justified. All formats require binary 2s-complement MSB-first audio data. The Audio Interface Timing table
shows a detailed timing diagram for the serial audio interface.
1.4 V
LRCK
t(BCH)
t(BCL)
t(LB)
1.4 V
BCK
t(BCY)
t(BL)
1.4 V
DATA
t(DS)
t(DH)
Figure 22. Audio Interface Timing
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(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LR C K
L-Channel
R-Channel
BCK
(= 32 fS , 48 f S, or 64 fS)
16-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
14 15 16
1
2
3
14 15 16
MSB
1
LSB
2
3
14 15 16
MSB
LSB
16-Bit Right-Justified, BCK = 32 f S
DATA
14 15 16
1
2
3
14 15 16
MSB
1
LSB
2
3
14 15 16
MSB
LSB
18-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
16 17 18
1
2
3
16 17 18
MSB
1
LSB
2
3
16 17 18
MSB
LSB
20-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
18 19 20
1
2
3
18 19 20
MSB
1
2
LSB
3
18 19 20
MSB
LSB
24-Bit Right-Justified, BCK = 48 f S or 64 fS
DATA
22 23 24
1
2
3
22 23 24
MSB
1
2
3
22 23 24
MSB
LSB
LSB
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48 fS or 64 fS)
DATA
1
2
3
N–2
MSB
N–1
N
1
LSB
2
3
N–2
MSB
N–1
N
12
LSB
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48 fS, or 64 fS)
DATA
1
2
3
N–2
MSB
N–1
LSB
N
1
2
3
MSB
N–2
N–1
N
1
2
LSB
Figure 23. Audio Data Input Formats
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8.3.3 Zero Flag (PCM1754)
The PCM1754 device has a ZERO flag pin, ZEROA (pin 11). ZEROA is the L-channel and R-channel common
zero flag pin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK
clock periods), ZEROA is set to a logic 1 state.
8.3.4 Zero Flag (PCM1753)
Zero-Detect Condition
Zero detection for either output channel is independent from the other channel. If the data for a given channel
remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that
channel.
8.3.5 Zero Flag Outputs
If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic
1 state. There are zero flag pins for each channel, ZEROL (pin 12) and ZEROR (pin 11). These pins can be used
to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or
other digitally controlled function. The active polarity of zero flag outputs can be inverted by setting the ZREV bit
of control register 22 to 1. The reset default is active-high output, or ZREV = 0. The L-channel and R-channel
common zero flag can be selected by setting the AZRO bit of control register 22 to 1. The reset default is
independent zero flags for L-channel and R-channel, or AZRO = 0.
8.3.6 Analog Outputs
The PCM1753 device includes two independent output channels, VOUTL and VOUTR. These are unbalanced
outputs, each capable of driving 4 VPP typical into a 5-kΩ ac-coupled load. The internal output amplifiers for
VOUTL and VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 VCC.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the PCM1754 delta-sigma D/A converters.
The frequency response of this filter is shown in Figure 24. By itself, this filter is not enough to attenuate the outof-band noise to an acceptable level for many applications. An external low-pass filter is required to provide
sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Applications
Information section of this data sheet.
10
0
–10
Level (dB)
–20
–30
–40
–50
–60
0.1
1
100
10
Frequency (kHz)
1k
10k
Figure 24. Output Filter Frequency Response
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8.3.6.1 VCOM Output
One unbuffered common-mode voltage output pin, VCOM (pin 10) is brought out for decoupling purposes. This pin
is nominally biased to a dc voltage level equal to 0.5 VCC. This pin can be used to bias external circuits.
Figure 25 shows an example of using the VCOM pin for external biasing applications.
AV = –1, where AV = –
R2
R1
PCM1754
VCC
R1
R3
2
VOUTX(1)
3
C2
10 µF
–
1/2
OPA2353
1
+
C1
R2
+
Filtered
Output
VCOM
+
(1) X
10 µF
= L or R
(a) Using VCOM to Bias a Single-Supply Filter Stage
VCC
PCM1754
–
OPA337
Buffered VCOM
+
VCOM
+
10 µF
(b) Using a Voltage Follower to Buffer VCOM When Biasing Multiple Nodes
Figure 25. Biasing External Circuits Using the VCOM Pin
8.4 Device Functional Modes
8.4.1 Hardware Control (PCM1754)
The digital functions of the PCM1754 are capable of hardware control. Table 2 lists selectable formats, Table 3
shows de-emphasis control, and Table 4 lists mute control.
Table 2. Data Format Select
FMT (PIN 15)
DATA FORMAT
LOW
16– to 24–bit, I2S format
HIGH
16–bit right–justified
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Table 3. De-Emphasis Control
DEMP (PIN 13)
DE–EMPHASIS FUNCTION
LOW
44.1 kHz de–emphasis OFF
HIGH
44.1 kHz de–emphasis ON
Table 4. Mute Control
MUTE (PIN 14)
MUTE
LOW
Mute OFF
HIGH
Mute ON
8.4.2 Oversampling Rate Control (PCM1754)
The PCM1754 automatically controls the oversampling rate of the delta-sigma DACs with the system clock rate.
The oversampling rate is set to 64× oversampling with every system clock and sampling frequency.
8.5 Programming
8.5.1 Software Control (PCM1753/55)
The PCM1753 and PCM1755 devices have many programmable functions which can be controlled in the
software control mode. The functions are controlled by programming the internal registers using the ML, MC, and
MD pins.
The serial control interface is a 3-wire serial port, which operates asynchronously to the audio serial interface.
The serial control interface is used to program the on-chip mode registers. The control interface includes MD (pin
13), MC (pin 14), and ML (pin 15). The MD pin is the serial data input, used to program the mode registers. The
MC pin is the serial bit clock, used to shift data into the control port. The ML pin is the control port latch clock.
8.5.1.1 Register Write Operation
All write operations for the serial control port use 16-bit data words. Figure 26 lists the control data word format.
The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (or
address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the
register specified by IDX[6:0].
Figure 27 lists the functional timing diagram for writing to the serial control port. ML is held at a logic 1 state until
a register needs to be written. To start the register write cycle, ML is set to logic 0. Sixteen clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has
completed, ML is set to logic 1 to latch the data into the indexed mode control register.
Figure 26. Control Data Word Format for MD
Figure 27. Register Write Operation
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8.6 Register Maps
8.6.1 Mode Control Registers (PCM1753/55)
8.6.1.1 User-Programmable Mode Controls
The PCM1753/55 devices include a number of user-programmable functions, which are accessed via control
registers. The registers are programmed using the serial control interface, which was previously discussed in this
data sheet. Table 5 lists the available mode control functions, along with their reset default conditions and
associated register index.
Table 5. User-Programmable Mode Controls
FUNCTION
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps
Soft mute control
RESET DEFAULT
REGISTER
BIT(s)
0 dB, no attenuation
16 and 17
AT1[7:0], AT2[7:0]
Mute disabled
18
MUT[2:0]
64 fS oversampling
18
OVER
Reset disabled
18
SRST
DAC1 and DAC2 enabled
19
DAC[2:1]
De-emphasis disabled
19
DM12
44.1 kHz
19
DMF[1:0]
24-bit left-justified
20
FMT[2:0]
Digital filter rolloff control
Sharp rolloff
20
FLT
Zero flag function select
L-, R-channel independent
22
AZRO
Normal phase
22
DREV
High
22
ZREV
Oversampling rate control (64 fS or 128 fS)
Soft reset control
DAC operation control
De-emphasis function control
De-emphasis sample rate selection
Audio data format control
Output phase select
Zero flag polarity select
The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by the
IDX[6:0] bits.
Table 6. Mode Control Register Map (1)
IDX
(B8–B
14)
REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
10h
Register 16
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
11h
Register 17
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
12h
Register 18
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
SRST
OVER
RSV
RSV
RSV
RSV
MUT2
MUT1
13h
Register 19
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
DMF1
DMF0
DM12
RSV
RSV
DAC2
DAC1
14h
Register 20
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
FLT
RSV
RSV
FMT2
FMT1
FMT0
16h
Register 22
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
RSV
RSV
AZRO
ZREV
DREV
(1)
RSV: Reserved for test operation. It should be set to 0 for regular operation.
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8.6.1.2 Register Definitions
8.6.1.2.1 ATx[7:0]: Digital Attenuation Level Setting
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default value: 1111 1111b
Each DAC channel (VOUTL and VOUTR) includes a digital attenuation function. The attenuation level can be set
from 0 dB to –63 dB in 0.5-dB steps. Changes in attenuator levels are made by incrementing or decrementing
one step (0.5 dB) for every 8/fS time internal until the programmed attenuator setting is reached. Alternatively,
the attenuation level can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. The attenuation level is set using the following
formula:
Attenuation level (dB) = 0.5 × (ATx[7:0]DEC – 255)
where ATx[7:0]DEC = 0 through 255.
For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation.
The table in Figure 28 shows the attenuation levels for various settings:
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Figure 28. ATx[7:0]: Digital Attenuation Level Setting Table
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8.6.1.2.2 MUTx: Soft Mute Control
where x = 1 or 2, corresponding to the DAC outputs VOUTL (x = 1) and VOUTR (x = 2).
Default value: 0
The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC
outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is
disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the
digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one
attenuator step (0.5 dB) for every 8/fS seconds. This provides pop-free muting of the DAC output.
By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed
attenuation level.
8.6.1.2.3 OVER: Oversampling Rate Control
Default value: 0
System clock rate = 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS:
System clock rate = 128 fS or 192 fS:
The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters. The OVER = 1 setting
is recommended when the sampling rate is 192 kHz (system clock rate is 128 fS or 192 fS).
8.6.1.2.4 SRST: Reset
Default value: 0
The SRST bit is used to enable or disable the soft reset function. The operation is the same as power-on reset.
All registers are initialized.
8.6.1.2.5 DACx: DAC Operation Control
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).
Default value: 0
The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. When DACx =
0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When
DACx = 1, the corresponding output is set to the bipolar zero level, or 0.5 VCC.
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8.6.1.2.6 DM12: Digital De-Emphasis Function Control
Default value: 0
The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical
Characteristics section of this data sheet.
8.6.1.2.7 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
Default value: 00
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is
enabled.
8.6.1.2.8 FMT[2:0]: Audio Interface Data Format
Default value: 101
The FMT[2:0] bits are used to select the data format for the serial audio interface. The table in Figure 29 shows
the available format options.
Figure 29. FMT[2:0]: Audio Interface Data Format Table
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8.6.1.2.9 FLT: Digital Filter Rolloff Control
Default value: 0
The FLT bit allows the user to select the digital filter rolloff that is best suited to the application. Two filter rolloff
selections are available, sharp and slow. The filter responses for these selections are shown in the Typical
Characteristics section of this data sheet.
8.6.1.2.10 DREV: Output Phase Select
Default value: 0
The DREV bit is the output analog signal phase control.
8.6.1.2.11 ZREV: Zero Flag Polarity Select
Default value: 01h
The ZREV bit allows the user to select the polarity of zero flag pins.
8.6.1.2.12 AZRO: Zero Flag Function Select
Default value: 0
The AZRO bit allows the user to select the function of zero flag pins.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The delta-sigma section of the PCM175x device is based on an 8-level amplitude quantizer and a 4th-order noise
shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the advantage of
stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64 fS.
The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 35 and
Figure 36. The enhanced multilevel delta-sigma architecture also has advantages for input clock jitter sensitivity
due to the multilevel quantizer, with the simulated jitter sensitivity shown in Figure 37.
The PCM175X devices are suitable for a wide variety of cost-sensitive consumer applications requiring good
performance and operation with a single 5-V supply.
9.2 Typical Application
A basic connection diagram is shown in Figure 30, with the necessary power supply bypassing and decoupling
components. TI recommends using the component values shown in Figure 30 for all designs.
The use of series resistors (22 Ω to 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. The
series resistor combines with the stray PCB and device input capacitance to form a low-pass filter, which reduces
high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.
For this design example, use the parameters listed in Table 7.
+5 V
+
DATA
FMT
15
Format
3
LRCK
MUTE
14
MUTE On/Off
4
DGND
DEMP
13
DEMP On/Off
5
NC
TEST
12
6
VCC
ZEROA
11
7
VOUTL
VCOM
10
8
VOUTR
AGND
9
10 µF
2
+
10 µF
System Clock
BCK
+
10 µF
16
+
PCM Audio Data
PCM1754
SCK
1
Zero Mute Control
10 µF
Post LPF
Post LPF
L-Ch Out
R-Ch Out
Figure 30. Basic Connection Diagram
24
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Design Parameters
Table 7 lists the design parameters and example values for the PCM175x devices.
Table 7. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Audio input
PCM audio data
Analog output
0 VPP - 4 VPP
Part configuration
Hardware
9.2.1.2 Power Supplies and Grounding
The PCM1754 device requires 5 V for VCC.
Proper power supply bypassing is shown in Figure 30. The 10-μF capacitors should be tantalum or aluminum
electrolytic.
9.2.1.3 D/A Output Filter Circuits
Delta-sigma D/A converters use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR)
performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The
out-of-band noise must be low-pass filtered in order to provide the optimal converter performance. This is
accomplished by a combination of on-chip and external low-pass filtering.
Figure 25(a) and Figure 31 show the recommended external low-pass active filter circuits for single- and dualsupply applications. These circuits are 2nd-order Butterworth filters using the multiple feedback (MFB) circuit
arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For
more information regarding MFB active filter design, see Burr-Brown applications bulletin (SBAA055), available
from the TI Web site at http://www.ti.com.
Because the overall system performance is defined by the quality of the D/A converters and their associated
analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. TI's
OPA2353 and OPA2134 dual operational amplifiers are shown in Figure 25(a) and Figure 31, and are
recommended for use with the PCM1754 device.
R2
R1
C1
R3
VIN
2
R4
–
1
OPA2134
C2
AV = –
3
VOUT
+
R2
R1
Figure 31. Dual-Supply Filter Circuit
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9.2.2 Detailed Design Procedure
9.2.2.1 Total Harmonic Distortion + Noise
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio D/A converters because it
takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth.
The average value of the distortion and noise is referred to as THD+N.
For the PCM175x, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at the input
of the DAC (see Figure 33). The digital generator is set to 24-bit audio word length and a sampling frequency of
44.1 kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the
measurement system. The S/PDIF data is transmitted via a coaxial cable to the digital audio receiver on the
DEM-DAI1753 demonstration board. The receiver is then configured to output 24-bit data in either I2S or leftjustified data format. The DAC audio interface format is programmed to match the receiver output format. The
analog output is then taken from the DAC post filter and connected to the analog analyzer input of the
measurement system. The analog input is band limited using filters resident in the analyzer. The resulting
THD+N is measured by the analyzer and displayed by the measurement system.
+
IN
8 fS
+
+
+
+
Z–1
+
Z–1
+
+
Z–1
+
Z–1
+ +
+
+
8-Level Quantizer
OUT
64 fS
Figure 32. Eight-Level Delta-Sigma Modulator
26
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9.2.2.2 Dynamic Range
Dynamic range is specified as A-weighted THD+N measured with a –60-dB full-scale, 1-kHz digital sine wave
stimulus at the input of the D/A converter. This measurement is designed to give a good indicator of how the
DAC performs given a low-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 34, and is similar to the THD+N
test setup discussed previously. The differences include the band limit filter selection, the additional A-weighting
filter, and the –60-dB full-scale input level.
Evaluation Board
DEM-DAI1753
S/PDIF
Receiver
2nd-Order
Low-Pass
Filter
PCM1754
f–3 dB = 54 kHz or 108 kHz
Audio Precision System Two
Analyzer
and
Display
Digital
Generator
S/PDIF
Output
0 dB FS
(100% Full-Scale),
24-Bit,
1-kHz Sine Wave
Averaging
Mode
AES17 Filter
Band Limit
HPF = 400 Hz
LPF = 30 kHz
f–3 dB = 20.9 kHz
Figure 33. Test Setup for THD+N Measurement
9.2.2.3 Idle Channel Signal-to-Noise Ratio (SNR)
The SNR test provides a measure of the noise floor of the D/A converter. The input to the D/A is all-0s data, and
the dither function of the digital generator must be disabled to ensure an all-0s data stream at the input of the
D/A converter.
The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input
signal level.
(See the note provided in Figure 34).
Evaluation Board
DEM-DAI1753
S/PDIF
Receiver
2nd-Order
Low-Pass
Filter
PCM1754
f–3 dB = 54 kHz or 108 kHz
Audio Precision System Two
S/PDIF
Output
Analyzer
and
Display
Digital
Generator
0% Full-Scale,
Dither Off (SNR)
or –60 dB FS,
1 kHz Sine Wave
(Dynamic Range)
(1) Results
Averaging
Mode
A-Weighting
Filter(1)
AES17 Filter
Band Limit
HPF = 400 Hz
LPF = 30 kHz
f–3 dB = 20.9 kHz
without A-Weighting are approximately 3 dB worse.
Figure 34. Test Setup for Dynamic Range and SNR Measurement
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9.2.3 Application Curves
0
20
20
40
40
60
60
Amplitude (dB)
Amplitude (dB)
0
80
100
120
80
100
120
140
140
160
160
180
180
0
1
2
3
4
5
6
7
8
0
Frequency [× fS]
Figure 35. Quantization Noise Spectrum (×64
Oversampling)
1
2
3
4
5
6
7
8
Frequency [× fS]
Figure 36. Quantization Noise Spectrum (×128
Oversampling)
125
120
Dynamic Range (dB)
115
110
105
100
95
90
0
100
200
300
400
500
600
Jitter (psp-p)
Figure 37. Jitter Dependence (×64 Oversampling)
28
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10 Power Supply Recommendations
The PCM175x devices are designed to operate from a 4.5-V to 5.5-V power supply. Ensure that the power
supply is clean and use high-quality decoupling capacitors to reduce noise. The bulk capacitances can be from
either tantalum or aluminum capacitors.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the PCM175x devices. In cases where a common 5-V supply must be used for the
analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and
digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 39
shows the recommended approach for single-supply applications.
11 Layout
11.1 Layout Guidelines
Figure 38 shows a typical PCB floor plan for the PCM175x devices. A ground plane is recommended, with the
analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM175x
should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections
to the digital audio interface and control signals originating from the digital section of the board.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the PCM175x. In cases where a common 5-V supply must be used for the analog and
digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V
supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 39 shows the
recommended approach for single-supply applications.
11.2 Layout Example
Analog Power
Digital Power
+VD
AGND +5VA
DGND
+VS –VS
VCC
Digital Logic
and
Audio
Processor
DGND
PCM1754
Output
Circuits
Digital
Ground
AGND
Digital Section
Analog Section
Analog
Ground
Return Path for Digital Signals
Figure 38. Recommended PCB Layout
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Layout Example (continued)
Power Supplies
RF Choke or Ferrite Bead
+5V
VDD
AGND
+VS
–V S
VCC
Output
Circuits
DGND
PCM1754
AGND
Digital Section
Analog Section
Common
Ground
Figure 39. Single-Supply PCB Layout
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12 Device and Documentation Support
12.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Dynamic Performance Testing of Digital Audio D/A Converters application bulletin
• Texas Instruments, OPA2353 High-Speed, Single-Supply, Rail-to-Rail Operational Amplifiers MicroAmplifier™
Series data sheet
• Texas Instruments, OPA2134 SoundPlus™ High Performance Audio Operational Amplifiers data sheet
• Texas Instruments, , PLL170x 3.3-V Dual PLL Multiclock Generator data sheet
• Texas Instruments, PCM175x-Q1 24-Bit 192-kHz Sampling Enhanced Multi-Level Delta-Sigma Audio Digitalto-Analog Converter data sheet
12.2 Related Links
Table 8 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 8. Related Links
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS & SOFTWARE
SUPPORT &
COMMUNITY
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1753DBQ
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1753
PCM1753DBQR
ACTIVE
SSOP
DBQ
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1753
PCM1754DBQ
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1754
PCM1754DBQG4
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1754
PCM1754DBQR
ACTIVE
SSOP
DBQ
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1754
PCM1754DBQRG4
ACTIVE
SSOP
DBQ
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1754
PCM1755DBQ
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1755
PCM1755DBQR
ACTIVE
SSOP
DBQ
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1755
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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