PCM1796DB

Burr Brown Products from Texas Instruments PCM1796 SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 24 BIT, 192 kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL TO ANALOG CONVERTER FEATURES D 24-Bit Resolution D Analog Performance: D D D D D D − Dynamic Range: 123 dB − THD+N: 0.0005% Differential Current Output: 4 mA p-p 8× Oversampling Digital Filter: − Stop-Band Attenuation: –98 dB − Pass-Band Ripple: ±0.0002 dB Sampling Frequency: 10 kHz to 200 kHz System Clock: 128, 192, 256, 384, 512, or 768 fS With Autodetect Accepts 16-, 20-, and 24-Bit Audio Data PCM Data Formats: Standard, I2S, and Left-Justified DSD Format Interface Available Digital Filter or DSP D 5-V Tolerant Digital Inputs D Small 28-Lead SSOP Package APPLICATIONS D D D D D D D A/V Receivers SACD Players DVD Players HDTV Receivers Car Audio Systems Digital Multitrack Recorders Other Applications Requiring 24-Bit Audio DESCRIPTION The PCM1796 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1796 provides balanced current outputs, allowing the user to optimize analog performance externally. The PCM1796 accepts PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The PCM1796 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an SPI or I2C serial control port, which supports register write and readback functions. The PCM1796 also supports the time division multiplexed command and audio (TDMCA) data format. D D Interface Available for Optional External D TDMCA or Serial Port (SPI/I2C) D User-Programmable Mode Controls: D D − Digital Attenuation: 0 dB to –120 dB, 0.5 dB/Step − Digital De-Emphasis − Digital Filter Rolloff: Sharp or Slow − Soft Mute − Zero Flag for Each Output Compatible With PCM1792 (Pins and Mode Controls) Dual Supply Operation: − 5-V Analog, 3.3-V Digital This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2006, Texas Instruments Incorporated PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE –25°C to 85°C PACKAGE MARKING PCM1796 ORDERING NUMBER PCM1796DB PCM1796DBR TRANSPORT MEDIA Tube Tape and reel PCM1796DB 28-lead SSOP 28DB ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1796 Supply voltage VCC1, VCC2L, VCC2R VDD –0.3 V to 6.5 V –0.3 V to 4 V ±0.1 V ±0.1 V –0.3 V to 6.5 V –0.3 V to (VDD + 0.3 V) < 4 V –0.3 V to (VCC + 0.3 V) < 6.5 V ±10 mA –40°C to 125°C –55°C to 150°C 150°C 260°C, 5 s 260°C Supply voltage differences: VCC1, VCC2L, VCC2R Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND LRCK, DATA, BCK, SCK, MSEL, RST, MS(2), MDI, MC, MDO(2), ZEROL(2), ZEROR(2) Digital input voltage Analog input voltage Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (IR reflow, peak) ZEROL(3), ZEROR(3), MDO(3), MS(3) (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input mode or I2C mode (3) Output mode except for I2C mode ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PCM1796DB PARAMETER RESOLUTION DATA FORMAT (PCM Mode) Audio data interface format Audio data bit length Audio data format fS Sampling frequency System clock frequency DATA FORMAT (DSD Mode) Audio data interface format Audio data bit length fS Sampling frequency System clock frequency 2.8224 DSD (direct stream digital) 1 Bit 2.8224 11.2896 MHz MHz Standard, I2S, left-justified 16-, 20-, 24-bit selectable MSB first, twos complement 10 200 kHz 128, 192, 256, 384, 512, 768 fS TEST CONDITIONS MIN TYP 24 MAX UNIT Bits 2 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PCM1796DB PARAMETER DIGITAL INPUT/OUTPUT Logic family VIH VIL IIH IIL VOH VOL Input logic level Input logic current Output logic level VIN = VDD VIN = 0 V IOH = –2 mA IOL = 2 mA fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz Channel separation Level Linearity Error DYNAMIC PERFORMANCE (MONO MODE) (1)(2)(3) THD+N at VOUT = 0 dB dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz 0.0005% 0.001% 0.0015% 126 126 126 126 126 126 dB dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz VOUT = –120 dB 116 120 120 2.4 0.4 0.0005% 0.001% 0.0015% 123 123 123 123 123 123 119 118 117 ±1 dB dB dB dB 0.001% TTL compatible 2 0.8 10 –10 VDC µA VDC TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE (PCM MODE) (1)(2) THD+N at VOUT = 0 dB dB (1) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precision in the averaging mode. (2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 36. (3) Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 38. Audio Precision and System Two are trademarks of Audio Precision, Inc. Other trademarks are the property of their respective owners. 3 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PCM1796DB PARAMETER TEST CONDITIONS MIN TYP 0.0007% 122 122 –7 –3 At BPZ Full scale (0 dB) At BPZ –2 ±2 ±0.5 ±0.5 4 –3.5 ±0.1 ±0.0002 dB –3 dB 0.546 fS ±0.0002 Stop band = 0.546 fS –98 38/fS ±0.001 dB –3 dB 0.79 fS ±0.001 Stop band = 0.732 fS –80 38/fS dB dB 0.21 fS 0.448 fS dB dB s 0.454 fS 0.49 fS 7 3 2 dB dB % of FSR % of FSR % of FSR mA p-p mA dB MAX UNIT DSD MODE DYNAMIC PERFORMANCE (1) (2) (44.1 kHZ, 64 fS) THD+N at FS Dynamic range Signal-to-noise ratio ANALOG OUTPUT Gain error Gain mismatch, channel-to-channel Bipolar zero error Output current Center current DIGITAL FILTER PERFORMANCE De-emphasis error FILTER CHARACTERISTICS–1: SHARP ROLLOFF Pass band Stop band Pass-band ripple Stop-band attenuation Delay time FILTER CHARACTERISTICS–2: SLOW ROLLOFF Pass band Stop band Pass-band ripple Stop-band attenuation Delay time 2 V rms –60 dB, EIAJ, A-weighted EIAJ, A-weighted s (1) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging mode. (2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 37. 4 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PCM1796DB PARAMETER POWER SUPPLY REQUIREMENTS VDD VCC1 VCC2L VCC2R IDD Supply current (1) ICC 3 Voltage range 4.75 fS = 44.1 kHz fS = 96 kHz fS = 192 kHz fS = 44.1 kHz fS = 96 kHz fS = 192 kHz (1) Power dissipation (1) TEMPERATURE RANGE Operation temperature θJA Thermal resistance (1) Input is BPZ data. 28-pin SSOP –25 100 85 °C °C/W fS = 44.1 kHz fS = 96 kHz fS = 192 kHz 3.3 5 7 13 25 18 19 20 115 140 180 150 mW 23 mA 3.6 5.25 9 mA VDC VDC TEST CONDITIONS MIN TYP MAX UNIT PIN ASSIGNMENTS PCM1796 (TOP VIEW) ZEROL ZEROR MSEL LRCK DATA BCK SCK DGND VDD MS MDI MC MDO RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC2L AGND3L IOUTL– IOUTL+ AGND2 VCC1 VCOML VCOMR IREF AGND1 IOUTR– IOUTR+ AGND3R VCC2R 5 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Terminal Functions TERMINAL NAME AGND1 AGND2 AGND3L AGND3R BCK DATA DGND IOUTL+ IOUTL– IOUTR+ IOUTR– IREF LRCK MC MDI MDO MS MSEL RST SCK VCC1 VCC2L VCC2R VCOML VCOMR VDD ZEROL PIN 19 24 27 16 6 5 8 25 26 17 18 20 4 12 11 13 10 3 14 7 23 28 15 22 21 9 1 I/O – – – – I I – O O O O – I I I I/O I/O I I I – – – – – – I/O Analog ground (internal bias) Analog ground (internal bias) Analog ground (L-channel DACFF) Analog ground (R-channel DACFF) Bit clock input(1) Serial audio data input(1) Digital ground L-channel analog current output+ L-channel analog current output– R-channel analog current output+ R-channel analog current output– Output current reference bias pin Left and right clock (fS) input(1) Mode control clock input(1) Mode control data input(1) Mode control readback data output(3) Mode control chip-select input(2) I2C/SPI select(1) Reset(1) System clock input(1) Analog power supply, 5 V Analog power supply (L-channel DACFF), 5 V Analog power supply (R-channel DACFF), 5 V L-channel internal bias decoupling pin R-channel internal bias decoupling pin Digital power supply, 3.3 V Zero flag for L-channel(2) DESCRIPTIONS ZEROR 2 I/O Zero flag for R-channel(2) (1) Schmitt-trigger input, 5-V tolerant (2) Schmitt-trigger input and output. 5-V tolerant input and CMOS output (3) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS output. 6 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 FUNCTIONAL BLOCK DIAGRAM LRCK BCK DATA Audio Data Input I/F 8 Oversampling Digital Filter and Function Control Function Control I/F Current Segment DAC IOUTL+ IOUTL– VOUTL RST VCOML Advanced Segment DAC Modulator Bias and Vref IREF VCOMR I/V and Filter MDO MDI MC MS IOUTR– Current Segment DAC IOUTR+ I/V and Filter VOUTR MSEL ZEROL ZEROR Zero Detect System Clock Manager Power Supply AGND3L AGND3R AGND1 AGND2 VCC2L VCC2R DGND VCC1 SCK VDD 7 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY 0 −20 −40 2 0.0002 Amplitude – dB −60 −80 −100 −120 −3 –0.0003 −140 −160 0 1 2 Frequency [× fS] 3 4 −4 –0.0004 −5 –0.0005 0.0 0.1 0.2 0.3 0.4 0.5 Amplitude – dB 1 0.0001 0 −1 –0.0001 −2 –0.0002 5 0.0005 0.0004 4 3 0.0003 AMPLITUDE vs FREQUENCY Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff AMPLITUDE vs FREQUENCY 0 −20 −40 Figure 2. Pass-Band Ripple, Sharp Rolloff AMPLITUDE vs FREQUENCY 0 −2 −4 −6 Amplitude – dB −60 −80 −100 −120 Amplitude – dB 0 1 2 Frequency [× fS] 3 4 −8 −10 −12 −14 −16 −140 −160 −18 −20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [× fS] Figure 3. Frequency Response, Slow Rolloff 8 Figure 4. Transition Characteristics, Slow Rolloff PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY 0 −1 −2 De-Emphasis Level – dB −3 −4 −5 −6 −7 −8 −9 −10 0 2 4 6 8 10 12 14 f – Frequency – kHz De-Emphasis Error – dB fS = 32 kHz 0.5 0.4 0.3 0.2 0.1 −0.0 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 2 4 6 8 10 12 14 f – Frequency – kHz fS = 32 kHz DE-EMPHASIS ERROR vs FREQUENCY Figure 5 DE-EMPHASIS LEVEL vs FREQUENCY 0 −1 −2 De-Emphasis Level – dB −3 −4 −5 −6 −7 −8 −9 −10 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz De-Emphasis Error – dB fS = 44.1 kHz 0.5 0.4 0.3 0.2 0.1 −0.0 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 2 4 Figure 6 DE-EMPHASIS ERROR vs FREQUENCY fS = 44.1 kHz 6 8 10 12 14 16 18 20 f – Frequency – kHz Figure 7 Figure 8 9 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 De-Emphasis Filter (Continued) DE-EMPHASIS LEVEL vs FREQUENCY 0 −1 −2 De-Emphasis Level – dB −3 −4 −5 −6 −7 −8 −9 −10 0 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz De-Emphasis Error – dB fS = 48 kHz 0.5 0.4 0.3 0.2 0.1 −0.0 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz fS = 48 kHz DE-EMPHASIS ERROR vs FREQUENCY Figure 9 Figure 10 10 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE 0.01 THD+N – Total Harmonic Distortion + Noise – % 126 DYNAMIC RANGE vs SUPPLY VOLTAGE 124 fS = 96 kHz Dynamic Range – dB 122 fS = 192 kHz 120 fS = 48 kHz 0.001 fS = 192 kHz fS = 48 kHz fS = 96 kHz 118 0.0001 4.50 4.75 5.00 5.25 5.50 116 4.50 4.75 5.00 5.25 5.50 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 11 SIGNAL-to-NOISE RATIO vs SUPPLY VOLTAGE 126 122 Figure 12 CHANNEL SEPARATION vs SUPPLY VOLTAGE SNR – Signal-to-Noise Ratio – dB 124 fS = 96 kHz Channel Separation – dB 120 fS = 96 kHz 122 fS = 48 kHz 120 fS = 192 kHz 118 fS = 48 kHz fS = 192 kHz 116 118 114 116 4.50 4.75 5.00 5.25 5.50 112 4.50 4.75 5.00 5.25 5.50 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 13 NOTE: PCM mode, TA = 25°C, VDD = 3.3 V, measurement circuit is Figure 36. Figure 14 11 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE 0.01 THD+N – Total Harmonic Distortion + Noise – % 126 DYNAMIC RANGE vs FREE-AIR TEMPERATURE 124 Dynamic Range – dB fS = 96 kHz fS = 48 kHz fS = 192 kHz 122 0.001 fS = 96 kHz fS = 192 kHz fS = 48 kHz 120 118 0.0001 −50 −25 0 25 50 75 100 116 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 15 SIGNAL-to-NOISE RATIO vs FREE-AIR TEMPERATURE 126 122 Figure 16 CHANNEL SEPARATION vs FREE-AIR TEMPERATURE SNR – Signal-to-Noise Ratio – dB 124 Channel Separation – dB fS = 96 kHz 122 fS = 192 kHz 120 120 fS = 96 kHz fS = 48 kHz 118 fS = 192 kHz fS = 48 kHz 116 118 114 116 −50 −25 0 25 50 75 100 112 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 17 Figure 18 NOTE: PCM mode, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 36. 12 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY 0 −20 −40 Amplitude – dB −60 −80 −100 −120 −140 −160 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz NOTE: PCM mode, fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V VCC = 5 V, measurement circuit is Figure 36. Amplitude – dB 0 −20 −40 −60 −80 −100 −120 −140 −160 0 10 20 30 AMPLITUDE vs FREQUENCY 40 50 60 70 80 90 100 f – Frequency – kHz NOTE: PCM mode, fS = 96 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V VCC = 5 V, measurement circuit is Figure 36. Figure 19. –60-dB Output Spectrum, BW = 20 kHz TOTAL HARMONIC DISTORTION + NOISE vs INPUT LEVEL 10 THD+N – Total Harmonic Distortion + Noise – % Figure 20. –60-dB Output Spectrum, BW = 100 kHz AMPLITUDE vs FREQUENCY 0 −20 1 −40 Amplitude – dB −60 −80 −100 −120 0.1 0.01 0.001 −140 0.0001 −90 −80 −70 −60 −50 −40 −30 −20 −10 Input Level – dBFS −160 0 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz NOTE: PCM mode, fS = 48 kHz, TA = 25°C, VDD = 3.3 V, VCC = 5 V, NOTE: DSD mode (FIR-2), 32768 point 8 average, TA = 25°C, measurement circuit is Figure 36. VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 37. Figure 21. THD+N vs Input Level, PCM Mode Figure 22. –60-dB Output Spectrum, DSD Mode 13 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1796 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1796 has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 fS, the system clock frequency is required to be over 256 fS. Figure 23 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators is an excellent choice for providing the PCM1796 system clock. Table 1. System Clock Rates for Common Audio Sampling Frequencies SAMPLING FREQUENCY 32 kHz 44.1 kHz 48 kHz 96 kHz SYSTEM CLOCK FREQUENCY (fSCK) (MHz) 128 fS 4.096(1) 5.6488(1) 6.144(1) 12.288 192 fS 6.144(1) 8.4672 9.216 18.432 256 fS 8.192 11.2896 12.288 24.576 49.152(1) 384 fS 12.288 16.9344 18.432 36.864 73.728(1) 512 fS 16.384 22.5792 24.576 49.152(1) —(2) 768 fS 24.576 33.8688 36.864 73.728(1) —(2) 192 kHz 24.576 36.864 (1) This system clock rate is not supported in I2C fast mode. (2) This system clock rate is not supported for the given sampling frequency. t(SCKH) H System Clock (SCK) L t(SCKL) PARAMETERS t(SCY) System clock pulse cycle time t(SCKH) System clock pulse duration, HIGH t(SCKL) System clock pulse duration, LOW t(SCY) MIN 13 0.4t (SCY) 0.4t (SCY) MAX UNITS ns ns ns 0.8 V 2V Figure 23. System Clock Input Timing 14 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Power-On and External Reset Functions The PCM1796 includes a power-on reset function. Figure 24 shows the operation of this function. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. After the initialization period, the PCM1796 is set to its default reset state, as described in the MODE CONTROL REGISTERS section of this data sheet. The PCM1796 also includes an external reset capability using the RST input (pin 14). This allows an external controller or master reset circuit to force the PCM1796 to initialize to its default reset state. Figure 25 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between the PCM1796 power up and system clock activation. VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Internal Reset Reset Removal 1024 System Clocks System Clock Figure 24. Power-On Reset Timing RST (Pin 14) 1.4 V t(RST) Reset Internal Reset 1024 System Clocks System Clock PARAMETERS t(RST) Reset pulse duration, LOW MIN 20 MAX UNITS ns Reset Removal Figure 25. External Reset Timing 15 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1796 on the rising edge of BCK. LRCK is the serial audio left/right word clock. The PCM1796 requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock. If the relationship between LRCK and system clock changes more than ±6 BCK, internal operation is initialized within 1/fS and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed. PCM Audio Data Formats and Timing The PCM1796 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0], in control register 18. The default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio data. Figure 26 shows a detailed timing diagram for the serial audio interface. LRCK t(BCH) BCK t(BCY) DATA t(DS) PARAMETERS t(BCY) t(BCL) t(BCH) t(BL) t(LB) t(DS) t(DH) — BCK pulse cycle time BCK pulse duration, LOW BCK pulse duration, HIGH BCK rising edge to LRCK edge LRCK edge to BCK rising edge DATA setup time DATA hold time LRCK clock data t(DH) MIN 70 30 30 10 10 10 10 MAX UNITS ns ns ns ns ns ns ns t(BL) 1.4 V t(BCL) t(LB) 1.4 V 1.4 V 50% ± 2 bit clocks Figure 26. Timing of Audio Interface 16 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 (1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK Audio Data Word = 16-Bit DATA 14 15 16 1 2 MSB Audio Data Word = 20-Bit DATA 18 19 20 1 2 MSB Audio Data Word = 24-Bit DATA 22 23 24 1 2 MSB 23 24 LSB 1 2 23 24 19 20 LSB 1 2 19 20 15 16 LSB 1 2 15 16 (2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK Audio Data Word = 24-Bit DATA 1 2 MSB 23 24 LSB 1 2 23 24 1 2 (3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH LRCK L-Channel 1/fS R-Channel BCK Audio Data Word = 16-Bit DATA 1 2 MSB Audio Data Word = 24-Bit DATA 1 2 MSB 23 24 LSB 1 2 23 24 1 2 15 16 LSB 1 2 15 16 1 2 Figure 27. Audio Data Input Formats 17 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 External Digital Filter Interface and Timing The PCM1796 supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which allows the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor. In the external DF mode, LRCK (pin 4), BCK (pin 6) and DATA (pin 5) are defined as WDCK, the word clock; BCK, the bit clock; and DATA, the monaural data. The external digital filter interface is selected by using the DFTH bit of control register 20, which functions to bypass the internal digital filter of the PCM1796. When the DFMS bit of control register 19 is set, the PCM1796 can process stereo data. In this case, ZEROL (pin 1) and ZEROR (pin 2) are defined as L-channel data and R-channel data input, respectively. Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet. Direct Stream Digital (DSD) Format Interface and Timing The PCM1796 supports the DSD format interface operation, which includes out-of-band noise filtering using an internal analog FIR filter. For DSD operation, SCK (pin 7) is redefined as BCK, DATA (pin 5) as DATAL (left channel audio data), and LRCK (pin 4) as DATAR (right channel audio data). BCK (pin 6) must be forced low in the DSD mode. The DSD format interface is activated by setting the DSD bit of control register 20. Detailed information for the DSD mode is provided in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet. TDMCA Interface The PCM1796 supports the time-division-multiplexed command and audio (TDMCA) data format to enable control of and communication with a number of external devices over a single serial interface. Detailed information for the TDMCA format is provided in the TDMCA INTERFACE FORMAT section of this data sheet. FUNCTION DESCRIPTIONS Zero Detect The PCM1796 has a zero-detect function. When the PCM1796 detects the zero conditions as shown in Table 2, the PCM1796 sets ZEROL (pin 1) and ZEROR (pin 2) to HIGH. Table 2. Zero Conditions MODE PCM External DF Mode DZ0 DSD DZ1 DETECTING CONDITION AND TIME DATA is continuously LOW for 1024 LRCKs. DATA is continuously LOW for 1024 WDCKs. There are an equal number of 1s and 0s in every 8 bits of DSD input data for 23 ms. The input data is 1001 0110 continuously for 23 ms. 18 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 SERIAL CONTROL INTERFACE The PCM1796 supports SPI and I2C that sets mode control registers as shown in Table 4. This serial control interface is selected by MSEL (pin 3), SPI is activated when MSEL is set to LOW, and I2C is activated when MSEL is set to HIGH. SPI Interface The SPI interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output, used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers; MC is the serial bit clock, used to shift data in and out of the control port, and MS is the mode control enable, used to enable the internal mode register access. Register Read/Write Operation All read/write operations for the serial control port use 16-bit data words. Figure 28 shows the control data word format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to, or the data that was read from, the register specified by IDX[6:0]. Figure 29 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1 state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on MDO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to 1 once. MSB R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 LSB D0 Register Index (or Address) Register Data Figure 28. Control Data Word Format for MDI MS MC MDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MDO High Impedance D7 D6 D5 D4 D3 D2 D1 D0 When Read Mode is Instructed NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14–8 are used for the register address. Bits 7–0 are used for register data. Figure 29. Serial Control Format 19 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 t(MHH) MS t(MSS) t(MCH) MC t(MCY) MDI t(MDS) t(MDH) MDO 50% of VDD LSB 1.4 V t(MCL) t(MSH) 1.4 V 1.4 V t(MOS) PARAMETER t(MCY) t(MCL) t(MCH) t(MHH) t(MSS) t(MSH) t(MDH) t(MDS) MC pulse cycle time MC low-level time MC high-level time MS high-level time MS falling edge to MC rising edge MS hold time(1) MDI hold time MDI setup time MIN 100 40 40 80 15 15 15 15 MAX UNITS ns ns ns ns ns ns ns ns t(MOS) MC falling edge to MDO stable (1) MC rising edge for LSB to MS rising edge 30 ns Figure 30. Control Interface Timing 20 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 I2C INTERFACE The PCM1796 supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave device. This protocol is explained in I2C specification 2.0. In I2C mode, the control terminals are changed as follows. TERMINAL NAME MS MDI MC MDO TDMCA NAME ADR0 ADR1 SCL SDA PROPERTY Input Input Input Input/output DESCRIPTION I2C address 0 I2C address 1 I2C clock I2C data Slave Address MSB 1 0 0 1 1 ADR1 ADR0 LSB R/W The PCM1796 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset to 10011. The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0 terminals. A maximum of four PCM1796s can be connected on the same bus at one time. Each PCM1796 responds when it receives its own slave address. Packet Protocol A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The PCM1796 supports only slave receivers and slave transmitters. SDA SCL St 1−7 Slave Address 8 R/W 9 ACK 1−8 DATA 9 ACK 1−8 DATA 9 ACK 9 ACK Sp Start Condition Write Operation Transmitter Data Type R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 NACK: Not Acknowledgement if 1 DATA: 8 Bits (Byte) M Slave Address M W S ACK M DATA S ACK M DATA S ACK S ACK Stop Condition M St M Sp Read Operation Transmitter Data Type M St M Slave Address M R S ACK S DATA M ACK S DATA M ACK M NACK M Sp M: Master Device St: Start Condition NACK: Not Acknowledge S: Slave Device Sp: Stop Condition W: Write R: Read ACK: Acknowledge Figure 31. Basic I2C Framework 21 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Write Register A master can write to any PCM1796 registers using single or multiple accesses. The master sends a PCM1796 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x00. When undefined registers are accessed, the PCM1796 does not send an acknowledgement. Figure 32 is a diagram of the write operation. Transmitter Data Type M St M Slave Address M W S ACK M Reg Address S ACK M Write Data 1 S ACK M Write Data 2 S ACK S ACK M Sp M: Master Device St: Start Condition S: Slave Device Sp: Stop Condition ACK: Acknowledge W: Write Figure 32. Write Operation Read Register A master can read the PCM1796 register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM1796 slave address with a read bit after storing the register address. Then the PCM1796 transfers the data which the index register points to. When the data are transferred during a multiple access, the index register is incremented by 1 automatically. (When first going into read mode immediately following a write, the index register is not incremented. The master can read the register that was previously written.) When the index register reaches 0x7F, the next value is 0x00. The PCM1796 outputs some data when the index register is 0x10 to 0x1F, even if it is not defined in Table 4. Figure 33 is a diagram of the read operation. Transmitter Data Type M St M Slave Address M W S M S M Sr M Slave Address M R S ACK S Data M ACK M NACK M Sp ACK Reg Address ACK M: Master Device St: Start Condition W: Write S: Slave Device Sr: Repeated Start Condition Sp: Stop Condition R: Read ACK: Acknowledge NACK: Not Acknowledge Figure 33. Read Operation 22 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Noise Suppression The PCM1796 incorporates noise suppression using the system clock (SCK). However, there must be no more than two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast mode. However, it works incorrectly in the following conditions. Case 1: 1. t(SCK) > 120 ns (t(SCK): period of SCK) 2. t(HI) + t(D–HD) < t(SCK) × 5 3. Spike noise exists on the first half of the SCL HIGH pulse. 4. Spike noise exists on the SDA HIGH pulse just before SDA goes LOW. SCL Noise SDA When these conditions occur at the same time, the data is recognized as LOW. Case 2: 1. t(SCK) > 120 ns 2. t(S–HD) or t(RS–HD) < t(SCK) × 5 3. Spike noise exists on both SCL and SDA during the hold time. SCL Noise SDA When these conditions occur at the same time, the PCM1796 fails to detect a start condition. Case 3: 1. t(SCK) < 50 ns 2. t(SP) > t(SCK) 3. Spike noise exists on SCL just after SCL goes LOW. 4. Spike noise exists on SDA just before SCL goes LOW. SCL SDA Noise When these conditions occur at the same time, the PCM1796 erroneously detects a start or stop condition. 23 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 TIMING DIAGRAM Start Repeated Start t(D-HD) t(BUF) SDA t(D-SU) t(SDA-R) t(SDA-F) t(P-SU) Stop t(SCL-R) t(LOW) SCL t(RS-HD) t(SP) t(S-HD) t(SCL-F) t(HI) t(RS-SU) TIMING CHARACTERISTICS PARAMETER f(SCL) t(BUF) t(LOW) t(HI) t(RS-SU) (RS-SU) t(S-HD) t(RS-HD) t(D-SU) t(D-HD) t(SCL-R) SCL clock frequency Bus free time between stop and start conditions Low period of the SCL clock High period of the SCL clock Setup time for (repeated) start condition Hold time for (repeated) start condition Data setup time Data hold time Rise time of SCL signal CONDITIONS Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Standard Fast Fast 0.2 VDD 4.7 1.3 4.7 1.3 4 600 4.7 600 4 600 250 100 0 0 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 4 600 400 50 900 900 1000 300 1000 300 1000 300 1000 300 1000 300 MIN MAX 100 400 UNIT kHz µs µs µs ns µs ns µs ns ns ns ns ns ns ns ns µs ns pF ns V Rise time of SCL signal after a repeated start condition and after an t(SCL-R1) (SCL-R1) acknowledge bit t(SCL-F) t(SDA-R) (SDA-R) t(SDA-F) t(P-SU) C(B) t(SP) VNH Fall time of SCL signal Rise time of SDA signal Fall time of SDA signal Setup time for stop condition Capacitive load for SDA and SCL line Pulse duration of suppressed spike Noise margin at high level for each connected device (including hysteresis) Figure 34. Timing Definition on the I2C Bus 24 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1796 includes a number of user-programmable functions which are accessed via mode control registers. The registers are programmed using the serial control interface, which is previously discussed in the SPI Interface and I2C INTERFACE sections of this data sheet. Table 3 lists the available mode-control functions, along with their default reset conditions and associated register index. Table 3. User-Programmable Function Controls FUNCTION Digital attenuation control 0 dB to –120 dB and mute, 0.5 dB step Attenuation load control Disabled, enabled Input audio data format selection 16-, 20-, 24-bit standard (right-justified) format 24-bit MSB-first left-justified format 16-/24-bit I2S format Sampling rate selection for de-emphasis Disabled,44.1 kHz, 48 kHz, 32 kHz De-emphasis control Disabled, enabled Soft mute control Soft mute disabled, enabled Output phase reversal Normal, reverse Attenuation speed selection ×1fS, ×(1/2)fS, ×(1/4)fS, ×(1/8)fS DAC operation control Enabled, disabled Stereo DF bypass mode select Monaural, stereo Digital filter rolloff selection Sharp rolloff, slow rolloff Infinite zero mute control Disabled, enabled System reset control Reset operation , normal operation DSD interface mode control DSD enabled, disabled Digital-filter bypass control DF enabled, DF bypass Monaural mode selection Stereo, monaural Channel selection for monaural mode data L-channel, R-channel Delta-sigma oversampling rate selection ×64 fS, ×128 fS, ×32 fS PCM zero output enable DSD zero output enable FUNCTION AVAILABLE ONLY FOR READ Zero detection flag Not zero, zero detected Not zero = 0 Zero detected = 1 Register 22 ZFGL (for L-ch) ZFGR (for R-ch) yes yes yes yes 0 dB Attenuation disabled 24-bit I2S format DEFAULT REGISTER Register 16 Register 17 Register 18 Register 18 BIT ATL[7:0] (for L-ch) ATR[7:0] (for R-ch) ATLD FMT[2:0] PCM yes yes yes yes DSD DF BYPASS De-emphasis disabled De-emphasis disabled Mute disabled Normal ×1 fS DAC operation enabled Monaural Sharp rolloff Disabled Normal operation Disabled DF enabled Stereo L-channel ×64 fS Enabled Disabled Register 18 Register 18 Register 18 Register 19 Register 19 Register 19 Register 19 Register 19 Register 19 Register 20 Register 20 Register 20 Register 20 Register 20 Register 20 Register 21 Register 21 DMF[1:0] DME MUTE REV ATS[1:0] OPE DFMS FLT INZD SRST DSD DFTH MONO CHSL OS[1:0] PCMZ DZ[1:0] yes yes yes yes yes yes yes(1) yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes(2) yes yes yes yes yes yes yes yes yes Device ID (at TDMCA) – Register 23 ID[4:0] (1) When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection. (2) When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection. 25 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Register Map The mode control register map is shown in Table 4. Registers 16–21 include an R/W bit, which determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only. Table 4. Mode Control Register Map B15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 Register 22 Register 23 R/W R/W R/W R/W R/W R/W R R B14 0 0 0 0 0 0 0 0 B13 0 0 0 0 0 0 0 0 B12 1 1 1 1 1 1 1 1 B11 0 0 0 0 0 0 0 0 B10 0 0 0 0 1 1 1 1 B9 0 0 1 1 0 0 1 1 B8 0 1 0 1 0 1 0 1 B7 ATL7 ATR7 ATLD REV RSV RSV RSV RSV B6 ATL6 ATR6 FMT2 ATS1 SRST RSV RSV RSV B5 ATL5 ATR5 FMT1 ATS0 DSD RSV RSV RSV B4 ATL4 ATR4 FMT0 OPE DFTH RSV RSV ID4 B3 ATL3 ATR3 DMF1 RSV MONO RSV RSV ID3 B2 ATL2 ATR2 DMF0 DFMS CHSL DZ1 RSV ID2 B1 ATL1 ATR1 DME FLT OS1 DZ0 ZFGR ID1 B0 ATL0 ATR0 MUTE INZD OS0 PCMZ ZFGL ID0 Register Definitions B15 Register 16 Register 17 R/W R/W B14 0 0 B13 0 0 B12 1 1 B11 0 0 B10 0 0 B9 0 0 B8 0 1 B7 ATL7 B6 ATL6 B5 ATL5 B4 ATL4 B3 ATL3 ATR3 B2 ATL2 ATR2 B1 ATL1 ATR1 B0 ATL0 ATR0 ATR7 ATR6 ATR5 ATR4 R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATx[7:0]: Digital Attenuation Level Setting These bits are available for read and write. Default value: 1111 1111b Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB steps. Alternatively, the attenuator can be set to infinite attenuation (or mute). The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control register 18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The attenuation level can be set using the following formula: Attenuation level (dB) = 0.5 dB • (ATx[7:0] DEC – 255) where ATx[7:0] DEC = 0 through 255 For ATx[7:0] DEC = 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation levels for various settings: ATx[7:0] 1111 1111b 1111 1110b 1111 1101b L 0001 0000b 0000 1111b 0000 1110b L 0000 0000b 26 Decimal Value 255 254 253 L 16 15 14 L 0 Attenuation Level Setting 0 dB, no attenuation (default) –0.5 dB –1.0 dB L –119.5 dB –120.0 dB Mute L Mute PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 B15 Register 18 R/W B14 0 B13 0 B12 1 B11 0 B10 0 B9 1 B8 0 B7 ATLD B6 FMT2 B5 FMT1 B4 FMT0 B3 B2 B1 DME B0 MUTE DMF1 DMF0 R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATLD: Attenuation Load Control This bit is available for read and write. Default value: 0 ATLD = 0 ATLD = 1 Attenuation control disabled (default) Attenuation control enabled The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0, the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally. FMT[2:0]: Audio Interface Data Format These bits are available for read and write. Default value: 101 FMT[2:0] 000 001 010 011 100 101 110 111 Audio Data Format Selection 16-bit standard format, right-justified data 20-bit standard format, right-justified data 24-bit standard format, right-justified data 24-bit MSB-first, left-justified format data 16-bit I2S format data 24-bit I2S format data (default) Reserved Reserved The FMT[2:0] bits are used to select the data format for the serial audio interface. For the external digital filter interface mode (DFTH mode), this register is operated as shown in the APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet. DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function These bits are available for read and write. Default value: 00 DMF[1:0] 00 01 10 11 De-Emphasis Sampling Frequency Selection Disabled (default) 48 kHz 44.1 kHz 32 kHz The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is enabled by setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter response plots are shown in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet. 27 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 DME: Digital De-Emphasis Control This bit is available for read and write. Default value: 0 DME = 0 DME = 1 De-emphasis disabled (default) De-emphasis enabled The DME bit is used to enable or disable the de-emphasis function for both channels. MUTE: Soft Mute Control This bit is available for read and write. Default value: 0 MUTE = 0 MUTE = 1 Soft mute disabled (default) Soft mute enabled The MUTE bit is used to enable or disable the soft mute function for both channels. Soft mute is operated as a 256-step attenuator. The speed for each step to – ∞ dB (mute) is determined by the attenuation rate selected in the ATS register. B15 Register 19 R/W B14 0 B13 0 B12 1 B11 0 B10 0 B9 1 B8 1 B7 REV B6 ATS1 B5 ATS0 B4 OPE B3 RSV B2 DFMS B1 FLT B0 INZD R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 REV: Output Phase Reversal This bit is available for read and write. Default value: 0 REV = 0 REV = 1 Normal output (default) Inverted output The REV bit is used to invert the output phase for both channels. ATS[1:0]: Attenuation Rate Select These bits are available for read and write. Default value: 00 ATS[1:0] 00 01 10 11 Attenuation Rate Selection Every LRCK (default) LRCK/2 LRCK/4 LRCK/8 The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level transitions. 28 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 OPE: DAC Operation Control This bit is available for read and write. Default value: 0 OPE = 0 OPE = 1 DAC operation enabled (default) DAC operation disabled The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ) even if audio data is present on the input. DFMS: Stereo DF Bypass Mode Select This bit is available for read and write. Default value: 0 DFMS = 0 DFMS = 1 Monaural (default) Stereo input enabled The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is set to 0, the pin for the input data is DATA (pin 5) only, therefore the PCM1796 operates as a monaural DAC. When DFMS is set to 1, the PCM1796 can operate as a stereo DAC with inputs of L-channel and R-channel data on ZEROL (pin 1) and ZEROR (pin 2), respectively. FLT: Digital Filter Rolloff Control This bit is available for read and write. Default value: 0 FLT = 0 FLT = 1 Sharp rolloff (default) Slow rolloff The FLT bit is used to select the digital filter rolloff characteristic. The filter responses for these selections are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. INZD: Infinite Zero Detect Mute Control This bit is available for read and write. Default value: 0 INZD = 0 INZD = 1 Infinite zero detect mute disabled (default) Infinite zero detect mute enabled The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to 1 forces muted analog outputs to hold a bipolar zero level when the PCM1796 detects a zero condition in both channels. The infinite zero detect mute function is not available in the DSD mode. B15 Register 20 R/W B14 0 B13 0 B12 1 B11 0 B10 1 B9 0 B8 0 B7 RSV B6 SRST B5 DSD B4 DFTH B3 MONO B2 CHSL B1 OS1 B0 OS0 R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 29 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 SRST: System Reset Control This bit is available for write only. Default value: 0 SRST = 0 SRST = 1 Normal operation (default) System reset operation (generate one reset pulse) The SRST bit is used to reset the PCM1796 to the initial system condition. DSD: DSD Interface Mode Control This bit is available for read and write. Default value: 0 DSD = 0 DSD = 1 DSD interface mode disabled (default) DSD interface mode enabled The DSD bit is used to enable or disable the DSD interface mode. DFTH: Digital Filter Bypass (or Through Mode) Control This bit is available for read and write. Default value: 0 DFTH = 0 DFTH = 1 Digital filter enabled (default) Digital filter bypassed for external digital filter The DFTH bit is used to enable or disable the external digital filter interface mode. MONO: Monaural Mode Selection This bit is available for read and write. Default value: 0 MONO = 0 MONO = 1 Stereo mode (default) Monaural mode The MONO function is used to change operation mode from the normal stereo mode to the monaural mode. When the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately following. CHSL: Channel Selection for Monaural Mode This bit is available for read and write. Default value: 0 CHSL = 0 CHSL = 1 L-channel selected (default) R-channel selected This bit is available when MONO = 1. The CHSL bit selects L-channel or R-channel data to be used in monaural mode. 30 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 OS[1:0]: Delta-Sigma Oversampling Rate Selection These bits are available for read and write. Default value: 00 OS[1:0] 00 01 10 11 Operation Speed Select 64 times fS (default) 32 times fS 128 times fS Reserved The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 fS oversampling rate is not available at sampling rates above 100 kHz. If the 128-fS oversampling rate is selected, a system clock of more than 256 fS is required. In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter. B15 Register 21 R/W B14 0 B13 0 B12 1 B11 0 B10 1 B9 0 B8 1 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 DZ1 B1 DZ0 B0 PCMZ R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 DZ[1:0]: DSD Zero Output Enable These bits are available for read and write. Default value: 00 DZ[1:0] 00 01 1x Zero Output Enable Disabled (default) Even pattern detect 96h pattern detect The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode. PCMZ: PCM Zero Output Enable These bits are available for read and write. Default value: 1 PCMZ = 0 PCMZ = 1 PCM zero output disabled PCM zero output enabled (default) The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode. B15 Register 22 R B14 0 B13 0 B12 1 B11 0 B10 1 B9 1 B8 0 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 RSV B1 ZFGR B0 ZFGL R: Read Mode Select Value is always 1, specifying the readback mode. 31 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ZFGx: Zero-Detection Flag Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Default value: 00 ZFGx = 0 ZFGx = 1 Not zero Zero detected These bits show zero conditions. Their status is the same as that of the zero flags at ZEROL (pin 1) and ZEROR (pin 2). See Zero Detect in the FUNCTION DESCRIPTIONS section. B15 Register 23 R B14 0 B13 0 B12 1 B11 0 B10 1 B9 1 B8 1 B7 RSV B6 RSV B5 RSV B4 ID4 B3 ID3 B2 ID2 B1 ID1 B0 ID0 R: Read Mode Select Value is always 1, specifying the readback mode. ID[4:0]: Device ID The ID[4:0] bits hold a device ID in the TDMCA mode. 32 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 APPLICATION INFORMATION TYPICAL CONNECTION DIAGRAM IN PCM MODE 5V 0.1 µF + 1 2 3 4 PCM Audio Data Source 5 6 7 0.1 µF 8 9 ZEROL ZEROR MSEL LRCK DATA BCK SCK DGND VDD PCM1796 VCC2L AGND3L IOUTL– IOUTL+ AGND2 VCC1 VCOML VCOMR IREF AGND1 IOUTR– IOUTR+ AGND3R VCC2R 28 27 26 25 24 23 10 µF 22 21 20 19 18 17 16 + 15 10 µF 0.1 µF 47 µF 10 kΩ – + Cf 5V – + Rf Differential to Single Converter With Low-Pass Filter + + 5V – + Cf Rf 10 µF – + Cf Rf Differential to Single Converter With Low-Pass Filter Cf Rf VOUT L-Channel 10 MS 11 MDI Controller 12 MC 13 MDO 14 RST 3.3 V + 10 µF VOUT R-Channel Figure 35. Typical Application Circuit for Standard PCM Audio Operation APPLICATION CIRCUIT The design of the application circuit is very important in order to actually realize the high S/N ratio of which the PCM1796 is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the third-order LPF circuit of Figure 36, the output level is 2.1 V rms and 123 dB S/N is achieved. Figure 37 shows a circuit for the DSD mode, which is a fourth-order LPF in order to reduce the out-of-band noise. I/V Section The current of the PCM1796 on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 4 mA p-p at 0 dB (full scale). The voltage output level of the I/V converter (Vi) is given by following equation: Vi = 4 mA p-p × Rf (Rf : feedback resistance of I/V converter) An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio dynamic performance of the I/V section. 33 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Differential Section The PCM1796 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function. The operational amplifier recommended for the differential circuit is the low-noise type. C1 2700 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 5 – + 4 8 6 U1 NE5534 C12 0.1 µF VEE C2 2700 pF R3 220 Ω C5 27000 pF R4 220 Ω R8 180 Ω C4 8200 pF VEE C3 8200 pF R5 200 Ω C15 0.1 µF C19 22 pF 5 – + 4 8 6 U3 NE5534 C16 0.1 µF R9 100 Ω 7 IOUT– 2 3 R7 180 Ω 7 2 3 R6 200 Ω R2 820 Ω VCC C13 0.1 µF C18 22 pF 5 – + 4 8 6 U2 NE5534 C14 0.1 µF VEE VCC = 15 V VEE = –15 V fc = 50 kHz 7 IOUT+ 2 3 Figure 36. Measurement Circuit for PCM 34 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 C1 2200 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 5 – + 4 8 6 U1 NE5534 C12 0.1 µF VEE C2 2200 pF R4 91 Ω R3 91 Ω R8 75 Ω C3 22000 pF R9 75 Ω C5 8200 pF R5 150 Ω C15 0.1 µF C19 22 pF 5 – + 4 8 6 U3 NE5534 C16 0.1 µF VEE R7 100 Ω 7 IOUT– 2 3 R10 120 Ω C4 27000 pF R11 120 Ω C6 8200 pF 7 2 3 R6 150 Ω R2 820 Ω VCC C13 0.1 µF C18 22 pF 5 – + 4 8 6 U2 NE5534 C14 0.1 µF VEE VCC = 15 V VEE = –15 V fc = 50 kHz 7 IOUT+ 2 3 Figure 37. Measurement Circuit for DSD 35 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 IOUTL– (Pin 26) IOUTL+ (Pin 25) IOUT– IOUT+ Figure 36 Circuit OUT+ 3 1 2 IOUTR– (Pin 18) IOUTR+ (Pin 17) IOUT– Figure 36 Circuit IOUT+ OUT– Balanced Out Figure 38. Measurement Circuit for Monaural Mode 36 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE DFMS = 0 External Filter Device 1 2 3 WDCK (Word Clock) DATA BCK SCK 4 5 6 7 ZEROL ZEROR MSEL LRCK DATA BCK SCK PCM1796 DFMS = 1 External Filter Device DATA_L DATA_R 1 2 3 WDCK (Word Clock) 4 5 BCK SCK 6 7 ZEROL ZEROR MSEL LRCK DATA BCK SCK PCM1796 Figure 39. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application 37 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1796. The PCM1796 supports several external digital filters, including: D Texas Instruments DF1704 and DF1706 D Pacific Microsonics PMD200 HDCD filter/decoder IC D Programmable digital signal processors The external digital filter application mode is accessed by programming the following bits in the corresponding control register: D DFTH = 1 (register 20) The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of Figure 39. The word clock (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, fS. Pin Assignment When Using the External Digital Filter Interface D D D D D LRCK (pin 4): BCK (pin 6): DATA (pin 5): WDCK as word clock input Bit clock for audio data Monaural audio data input when the DFMS bit is not set to 1 ZEROL (pin 1): DATAL as L-channel audio data input when the DFMS bit is set to 1 ZEROR (pin 2): DATAR as R-channel audio data input when the DFMS bit is set to 1 38 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Audio Format The PCM1796 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit, and 24-bit audio data, as shown in Figure 40. The audio format is selected by the FMT[2:0] bits of control register18. 1/4 fS or 1/8 fS WDCK BCK Audio Data Word = 16-Bit DATA, DATAL, DATAR 15 16 1 2 3 MSB Audio Data Word = 20-Bit DATA, DATAL, DATAR 19 20 1 2 3 MSB Audio Data Word = 24-Bit DATA, DATAL, DATAR 23 24 1 2 3 MSB 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LSB 4 5 6 7 8 9 10 11 12 13 14 15 16 LSB Figure 40. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application System Clock (SCK) and Interface Timing The PCM1796 in an application using an external digital filter requires the synchronization of WDCK and the system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL, and DATAR is shown in Figure 41. WDCK t(BCH) BCK t(BCY) DATA DATAL DATAR t(DS) PARAMETER t(BCY) BCK pulse cycle time t(BCL) BCK pulse duration, LOW t(BCH) BCK pulse duration, HIGH t(BL) BCK rising edge to WDCK falling edge t(LB) t(DS) t(DH) WDCK falling edge to BCK rising edge DATA, DATAL, DATAR setup time DATA, DATAL, DATAR hold time t(DH) MIN 20 7 7 5 5 5 5 MAX UNITS ns ns ns ns ns ns ns t(BL) t(BCL) t(LB) 1.4 V 1.4 V 1.4 V Figure 41. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application 39 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL FILTER MODE The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20. B4). The external digital filter mode allows access to the majority of the PCM1796 mode control functions. The following table shows the register mapping available when the external digital filter mode is selected, along with descriptions of functions which are modified when using this mode selection. B15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 Register 22 R/W R/W R/W R/W R/W R/W R B14 0 0 0 0 0 0 0 B13 0 0 0 0 0 0 0 B12 1 1 1 1 1 1 1 B11 0 0 0 0 0 0 0 B10 0 0 0 0 1 1 1 B9 0 0 1 1 0 0 1 B8 0 1 0 1 0 1 0 B7 – – – REV – – – B6 – – FMT2 – SRST – – B5 – – FMT1 – 0 – – B4 – – FMT0 OPE 1 – – B3 – – – – MONO – – B2 – – – DFMS CHSL – – B1 – – – – OS1 – ZFGR B0 – – – INZD OS0 PCMZ ZFGL NOTE: –: Function is disabled. No operation even if data bit is set FMT[2:0]: Audio Data Format Selection Default value: 000 FMT[2:0] 000 001 010 Other Audio Data Format Select 16-bit right-justified format (default) 20-bit right-justified format 24-bit right-justified format N/A OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection Default value: 00 OS[1:0] 00 01 10 11 Operation Speed Select 8 times WDCK (default) 4 times WDCK 16 times WDCK Reserved The effective oversampling rate is determined by the oversampling performed by both the external digital filter and the delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×. The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected is 16× WDCK, the system clock frequency must be over 256 fS. 40 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE DSD Decoder ZEROL ZEROR MSEL LRCK DATA BCK SCK PCM1796 1 2 3 DATA_R DATA_L 4 5 6 Bit Clock 7 Figure 42. Connection Diagram in DSD Mode Feature This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications. The DSD mode is accessed by programming the following bit in the corresponding control register. DSD = 1 (register 20) The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure. Four FIR responses are available, and are selected by the DMF[1:0] bits of control register 18. The DSD bit must be set before inputting DSD data; otherwise, the PCM1796 erroneously detects the TDMCA mode, and commands are not accepted through the serial control interface. Pin Assignment When Using DSD Format Interface Several pins are redefined for DSD mode operation. These include: D D D D DATA (pin 5): DSDL as L-channel DSD data input LRCK (pin 4): DSDR as R-channel DSD data input SCK (pin 7): DBCK as bit clock for DSD data BCK (pin 6): Set LOW (N/A) Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan. 41 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Requirements for System Clock For operation in the DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1796. The frequency of the bit clock can be N times the sampling frequency. Generally, N is 64 in DSD applications. The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time specifications shown in Figure 44. t = 1/(64 × 44.1 kHz) DBCK DSDL DSDR D0 D1 D2 D3 D4 Figure 43. Normal Data Output Form From DSD Decoder t(BCH) DBCK t(BCY) DSDL DSDR t(DS) PARAMETER t(BCY) DBCK pulse cycle time t(BCH) DBCK high-level time t(BCL) DBCK low-level time t(DS) DSDL, DSDR setup time t(DH) MIN 85(1) 30 30 10 MAX UNITS ns ns ns ns 1.4 V t(BCL) 1.4 V t(DH) DSDL, DSDR hold time 10 ns (1) 2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a sampling rate of DSD.) Figure 44. Timing for DSD Audio Interface 42 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ANALOG FIR FILTER PERFORMANCE IN DSD MODE GAIN vs FREQUENCY 0 0 fc = 185 kHz Gain(1) = –6.6 dB −1 −10 GAIN vs FREQUENCY −2 Gain – dB Gain – dB 0 50 100 f – Frequency – kHz 150 200 −20 −3 −30 −4 −40 −5 −50 −6 −60 0 500 1000 1500 f – Frequency – kHz Figure 45. DSD Filter-1, Low BW GAIN vs FREQUENCY 0 0 Figure 46. DSD Filter-1, High BW GAIN vs FREQUENCY fc = 90 kHz Gain(1) = 0.3 dB −1 −10 −2 Gain – dB Gain – dB 0 50 100 f – Frequency – kHz 150 200 −20 −3 −30 −4 −40 −5 −50 −6 −60 0 500 1000 1500 f – Frequency – kHz Figure 47. DSD Filter-2, Low BW Figure 48. DSD Filter-2, High BW (1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%. All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted. 43 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ANALOG FIR FILTER PERFORMANCE IN DSD MODE (CONTINUED) GAIN vs FREQUENCY 0 0 fc = 85 kHz Gain(1) = –1.5 dB −1 −10 GAIN vs FREQUENCY −2 Gain – dB Gain – dB 0 50 100 f – Frequency – kHz 150 200 −20 −3 −30 −4 −40 −5 −50 −6 −60 0 500 1000 1500 f – Frequency – kHz Figure 49. DSD Filter-3, Low BW GAIN vs FREQUENCY 0 0 Figure 50. DSD Filter-3, High BW GAIN vs FREQUENCY fc = 94 kHz Gain(1) = –3.3 dB −1 −10 −2 Gain – dB Gain – dB 0 50 100 f – Frequency – kHz 150 200 −20 −3 −30 −4 −40 −5 −50 −6 −60 0 500 1000 1500 f – Frequency – kHz Figure 51. DSD Filter-4, Low BW Figure 52. DSD Filter-4, High BW (1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%. All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted. 44 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 DSD MODE CONFIGURATION AND FUNCTION CONTROLS Configuration for the DSD Interface Mode The DSD interface mode is selected by setting DSD = 1 (register 20, B5). B15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 Register 22 R/W R/W R/W R/W R/W R R B14 0 0 0 0 0 0 0 B13 0 0 0 0 0 0 0 B12 1 1 1 1 1 1 1 B11 0 0 0 0 0 0 0 B10 0 0 0 0 1 1 1 B9 0 0 1 1 0 0 1 B8 0 1 0 1 0 1 0 B7 – – – REV – – – B6 – – – – SRST – – B5 – – – – 1 – – B4 – – – OPE – – – B3 – – DMF1 – MONO – – B2 – – DMF0 – CHSL DZ1 – B1 – – – – OS1 DZ0 ZFGR B0 – – – – OS0 – ZFGL NOTE: –: Function is disabled. No operation even if data bit is set DMF[1:0]: Analog-FIR Performance Selection Default value: 00 DMF[1:0] 00 01 10 11 Analog-FIR Performance Select FIR-1 (default) FIR-2 FIR-3 FIR-4 Plots for the four analog FIR filter responses are shown in the ANALOG FIR FILTER PERFORMANCE IN DSD MODE section of this data sheet. OS[1:0]: Analog-FIR Operation-Speed Selection Default value: 00 OS[1:0] 00 01 10 11 Operation-Speed Select fDBCK (default) fDBCK /2 Reserved fDBCK/4 The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before setting the DSD bit to1. 45 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 TDMCA INTERFACE FORMAT The PCM1796 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the host control serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any programmable devices. The TDMCA format can transfer not only audio data but also command data, so that it can be used together with any kind of device that supports the TDMCA format. The TDMCA frame consists of a command field, extended command field, and some audio data fields. Those audio data are transported to IN devices (such as a DAC) and/or from OUT devices (such as an ADC). The PCM1796 is an IN device. LRCK and BCK are used with both IN and OUT devices so that the sample frequency of all devices in a system must be the same. The TDMCA mode supports a maximum of 30 device IDs. The maximum number of audio channels depends on the BCK frequency. TDMCA Mode Determination The PCM1796 recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%. Figure 53 shows the LRCK and BCK timing that determines the TDMCA mode. The PCM1796 enters the TDMCA mode after two continuous TDMCA frames. Any TDMCA commands can be issued during the next TDMCA frame after the TDMCA mode is entered. Pre-TDMCA Frame LRCK TDMCA Frame Command Accept 2 BCKs BCK Figure 53. LRCK and BCK Timing for Determination of TDMCA Mode TDMCA Terminals TDMCA requires six signals, of which four signals are for command and audio data interface, and one pair for daisy chaining. Those signals can be shared as in the following table. The DO signal has a 3-state output so that it can be connected directly to other devices. TERMINAL NAME LRCK BCK DATA MDO MC MS TDMCA NAME LRCK BCK DI DO DCI DCO PROPERTY input input input output input output DESCRIPTION TDMCA frame start signal. It must be the same as the sampling frequency. TDMCA clock. Its frequency must be high enough to communicate a TDMCA frame within an LRCK cycle. TDMCA command and audio data input signal TDMCA command data 3-state output signal TDMCA daisy-chain input signal TDMCA daisy-chain output signal 46 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Device ID Determination The TDMCA mode also supports a multichip implementation in one system. This means a host controller (DSP) can simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM devices. The PCM devices are categorized as IN device, OUT device, IN/OUT device, and NO device. The IN device has an input port to receive audio data, the OUT device has an output port to supply audio data, the IN/OUT device has both input and output ports for audio data, and the NO device has no port for audio data but needs command data from the host. A DAC is an IN device, an ADC is an OUT device, a codec is an IN/OUT device, and a PLL is a NO device. The PCM1796 is an IN device. For the host controller to distinguish the devices, each device is assigned its own device ID by the daisy chain. The devices obtain their own device IDs automatically by connecting their DCI to the DCO of the preceding device and their DCO to the DCI of the following device in the daisy chain. The daisy chains are categorized as the IN chain and the OUT chain, which are completely independent and equivalent. Figure 54 shows an example daisy chain connection. If a system needs to chain the PCM1796 and a NO device in the same IN or OUT chain, the NO device must be chained at the back end of the chain because it does not require any audio data. Figure 55 shows an example of TDMCA system including an IN chain and an OUT chain with a TI DSP. For a device to get its own device ID, the DID signal must be set to 1 (see the Command Field section for details), and LRCK and BCK must be driven in the TDMCA mode for all PCM devices that are chained. The device at the top of the chain knows its device ID is 1 because its DCI is fixed HIGH. Other devices count the BCK pulses and observe their own DCI signal to determine their position and ID. Figure 56 shows the initialization of each device ID. IN Chain DCI DCI DCI DCOi DCOi DCO DCO DCO DCI ••• IN Device IN Device IN IN/OUT Device IN ••• NO Device NO Device ••• DCOo IN/OUT Device OUT DCOo DCIo NO Device DCO DCI NO Device DCO 47 DCI OUT Device DCO DCI OUT Device DCIo DCO DCI ••• OUT ••• OUT Chain Figure 54. Daisy Chain Connection DCO DCIi DCIi PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 DCII LRCK BCK DI DCIO DO DCOO Device ID = 1 IN/OUT Device (DIX1700) DCOI LRCK BCK DI DO IN Device (PCM1796) DCI DCO Device ID = 2 LRCK BCK DI DO NO Device DCI DCO Device ID = 3 • • • FSX FSR CLKX CLKR DX DR TI DSP LRCK BCK DI DO DCO Device ID = 3 OUT Device DCI LRCK BCK DI DO DCO Device ID = 2 OUT Device DCI • • • Figure 55. IN Daisy Chain and OUT Daisy Chain Connection for a Multichip System 48 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 LRCK BCK DI DID Command Field Device ID = 1 Device ID = 2 DCO1 DCO1 DCI2 DCO2 DCI3 • • • • • • Device ID = 30 DCO29 DCI30 Device ID = 3 58 BCKs Figure 56. Device ID Determination Sequence TDMCA Frame In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields. All of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field. The command field is always transferred as the first packet of the frame. The EMD field is transferred if the EMD flag of the command field is HIGH. If any EMD packets are transferred, no audio data follows the EMD packets. This frame is for quick system initialization. All devices of a daisy chain should respond to the command field and extended command field. The PCM1796 has two audio channels that can be selected by OPE (register 19). If the OPE bit is not set to HIGH, those audio channels are transferred. Figure 57 shows the general TDMCA frame. If some DACs are enabled, but corresponding audio data packets are not transferred, the analog outputs are unpredictable. 1/fS LRCK BCK [For Initialization] DI CMD 32 Bits DO [For Operation] DI CMD Ch1 Ch2 Ch3 Ch4 Ch(n) Don’t Care EMD EMD EMD EMD EMD Don’t Care CMD CMD CMD CMD CMD CMD CMD CMD DO CMD Ch1 Ch2 Ch3 Ch4 Ch(m) Figure 57. General TDMCA Frame 49 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 1/fS (256 BCK Clocks) 7 Packets × 32 Bits LRCK BCK DI CMD Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Don’t Care CMD IN and OUT Channel Orders are Completely Independent DO CMD Ch1 Ch2 Figure 58. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read Command Field The normal command field is defined as follows. When the DID bit (MSB) is 1, this frame is used only for device ID determination, and all remaining bits in the field are ignored. 31 command DID 30 EMD 29 DCS 28 24 23 R/W 22 register ID 16 15 data 8 7 not used 0 device ID Bit 31: Device ID enable flag The PCM1796 operates to get its own device ID for TDMCA initialization if this bit is HIGH. Bit 30: Extended command enable flag The EMD packet is transferred if this bit is HIGH, otherwise skipped. Once this bit is HIGH, this frame does not contain any audio data. This is for system initialization. Bit 29: Daisy chain selection flag HIGH designates OUT-chain devices, LOW designates IN-chain devices. The PCM1796 is an IN device, so the DCS bit must be set to LOW. Bits[28:24]: Device ID The device ID is 5 bits length, and it can be defined. These bits identify the order of a device in the IN or OUT daisy chain. The top of the daisy chain defines device ID 1 and successive devices are numbered 2, 3, 4, etc. All devices for which the DCI is fixed HIGH are also defined as ID 1. The maximum device ID is 30 each in the IN and OUT chains. If a device ID of 0x1F is used, all devices are selected as broadcast when in the write mode. If a device ID of 0x00 is used, no device is selected. Bit 23: Command Read/Write flag If this bit is HIGH, the command is a read operation. Bits[22:16]: Register ID It is 7 bits in length. Bits[15:8]: Command data It is 8 bits in length. Any valid data can be chosen for each register. Bits[7:0]: Not used These bits are never transported when a read operation is performed. Extended command field The extended command field is the same as the command field, except that it does not have a DID flag. 31 extended command rsvd 30 EMD 29 DCS 28 24 23 R/W 22 register ID 16 15 data 8 7 not used 0 device ID 50 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Audio Fields The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with 0s as shown in the following example. 31 audio data MSB 16 24 bits 12 8 LSB 7 43 All 0s 0 TDMCA Register Requirements TDMCA mode requires device ID and audio channel information, previously described. The OPE bit in register 19 indicates audio channel availability and register 23 indicates the device ID. Register 23 is used only in the TDMCA mode. See the mode control register map (Table 4). Register Write/Read Operation The command supports register write and read operations. If the command requests to read one register, the read data is transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the positive edge of BCK, and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle early to compensate for the output delay caused by high impedance. Figure 59 shows the TDMCA write and read timing. Register ID Phase Data Phase BCK DI Read Mode and Proper Register ID Write Data Retrieved, if Write Mode DO Read Data Driven, if Read Mode 1 BCK Early DOEN (Internal) Figure 59. TDMCA Write and Read Operation Timing TDMCA-Mode Operation DCO specifies the owner of the next audio channel in TDMCA-mode operation. When a device retrieves its own audio channel data, DCO goes HIGH during the last audio channel period. Figure 60 shows the DCO output timing in TDMCA-mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates the last audio channel of each device. Therefore, DCI means the next audio channel is allocated. If some devices are skipped due to no active audio channel, the skipped devices must notify the next device that the DCO will be passed through the next DCI. Figure 61 and Figure 62 show DCO timing with skip operation. Figure 63 shows the ac timing of the daisy chain signals. 51 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 1/fS (384 BCK Clocks) 9 Packets y 32 Bits LRCK BCK IN Daisy Chain DI DCI1 DID = 1 DID = 2 DID = 3 DID = 4 DCO1 DCI2 DCO2 DCI3 DCO3 DCI4 DCO4 CMD Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Don’t Care CMD Figure 60. DCO Output Timing of TDMCA Mode Operation 1/fS (256 BCK Clocks) 5 Packets × 32 Bits LRCK BCK DI CMD Ch1 Ch2 Ch15 Ch16 Don’t Care CMD DCI DID = 1 DCO DCI DID = 2 • • • • • • DID = 8 DCO DCO • • • DCI 14 BCK Delay 2 BCK Delay Figure 61. DCO Output Timing With Skip Operation 52 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 Command Packet LRCK BCK DID EMD DI DCO1 DCO2 • • • Figure 62. DCO Output Timing With Skip Operation (for Command Packet 1) 53 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 LRCK t(LB) BCK t(BL) t(BCY) DI t(DS) t(DH) t(DOE) DO t(DS) DCI t(DH) t(COE) DCO PARAMETER t(BCY) BCK pulse cycle time t(LB) LRCK setup time t(BL) t(DS) t(DH) t(DS) LRCK hold time DI setup time DI hold time DCI setup time MIN 20 0 3 0 3 0 3 8 6 MAX UNITS ns ns ns ns ns ns ns ns ns t(DH) DCI hold time t(DOE) DO output delay(1) t(COE) DCO output delay(1) (1) Load capacitance is 10 pF. Figure 63. AC Timing of Daisy Chain Signals 54 PCM1796 www.ti.com SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006 ANALOG OUTPUT Table 5 and Figure 64 show the relationship between the digital input code and analog output. Table 5. Analog Output Current and Voltage 800000 (–FS) IOUTN [mA] IOUTP [mA] VOUTN [V] VOUTP [V] –1.5 –5.5 –1.23 –4.51 000000 (BPZ) –3.5 –3.5 –2.87 –2.87 7FFFFF (+FS) –5.5 –1.5 –4.51 –1.23 VOUT [V] –2.98 0 2.98 NOTE: VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the measurement circuit of Figure 36. OUTPUT CURRENT vs INPUT CODE 0 −1 IO – Output Current – mA IOUTN −2 −3 −4 IOUTP −5 −6 800000(–FS) 000000(BPZ) Input Code – Hex 7FFFFF(+FS) Figure 64. The Relationship Between Digital Input and Analog Output 55 PACKAGE OPTION ADDENDUM www.ti.com 30-Oct-2006 PACKAGING INFORMATION Orderable Device PCM1796DB PCM1796DBG4 PCM1796DBR PCM1796DBRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type SSOP SSOP SSOP SSOP Package Drawing DB DB DB DB Pins Package Eco Plan (2) Qty 28 28 28 28 47 47 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 17.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 12.0 W Pin1 (mm) Quadrant 16.0 Q1 PCM1796DBR 2000 8.5 10.8 2.4 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device PCM1796DBR Package Type SSOP Package Drawing DB Pins 28 SPQ 2000 Length (mm) 336.6 Width (mm) 336.6 Height (mm) 28.6 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M PLASTIC SMALL-OUTLINE 0,25 0,09 5,60 5,00 8,20 7,40 Gage Plane 1 A 14 0°– 8° 0,25 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** DIM A MAX 14 16 20 24 28 30 38 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 /E 12/01 NOTES: A. B. C. D. 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